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pmassolino/hw-goppa-mceliece
|
mceliece/backup/controller_syndrome_calculator_2_pipe.vhd
| 1 | 19,184 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Syndrome_Calculator_2_pipe
-- Module Name: Controller_Syndrome_Calculator_2_pipe
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st step in Goppa Code Decoding.
--
-- This circuit is the state machine that controls the syndrome_calculator_n_pipe
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_syndrome_calculator_2_pipe is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
almost_units_ready : in STD_LOGIC;
empty_units : in STD_LOGIC;
limit_ctr_codeword_q : in STD_LOGIC;
limit_ctr_syndrome_q : in STD_LOGIC;
reg_first_syndrome_q : in STD_LOGIC_VECTOR(0 downto 0);
reg_codeword_q : in STD_LOGIC_VECTOR(0 downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
control_units_ce : out STD_LOGIC;
control_units_rst : out STD_LOGIC;
int_reg_L_ce : out STD_LOGIC;
int_square_h : out STD_LOGIC;
int_reg_h_ce : out STD_LOGIC;
int_reg_h_rst : out STD_LOGIC;
int_sel_reg_h : out STD_LOGIC;
reg_load_syndrome_ce : out STD_LOGIC;
reg_load_syndrome_rst : out STD_LOGIC;
reg_new_value_syndrome_ce : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_first_syndrome_ce : out STD_LOGIC;
reg_first_syndrome_rst : out STD_LOGIC;
ctr_load_address_syndrome_ce : out STD_LOGIC;
ctr_load_address_syndrome_rst : out STD_LOGIC;
reg_bus_address_syndrome_ce : out STD_LOGIC;
reg_calc_address_syndrome_ce : out STD_LOGIC;
reg_store_address_syndrome_ce : out STD_LOGIC;
ctr_load_address_codeword_ce : out STD_LOGIC;
ctr_load_address_codeword_rst : out STD_LOGIC
);
end controller_syndrome_calculator_2_pipe;
architecture Behavioral of controller_syndrome_calculator_2_pipe is
type State is (reset, load_counters, prepare_values, load_values, jump_codeword, clear_remaining_units, prepare_synd, prepare_synd_2, prepare_synd_3, load_store_synd, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, limit_ctr_codeword_q, limit_ctr_syndrome_q, reg_first_syndrome_q, reg_codeword_q, almost_units_ready, empty_units)
begin
case (actual_state) is
when reset =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
when load_counters =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
when prepare_values =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
when load_values =>
if(reg_first_syndrome_q(0) = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '1';
int_square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '1';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '1';
int_square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_syndrome_ce <= '1';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '1';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
end if;
when jump_codeword =>
if(reg_codeword_q(0) = '1') then
if(almost_units_ready = '1' or limit_ctr_codeword_q = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '1';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '1';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
end if;
elsif(limit_ctr_codeword_q = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '1';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '1';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
end if;
when clear_remaining_units =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '1';
int_sel_reg_h <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
when prepare_synd =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '1';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
when prepare_synd_2 =>
if(reg_first_syndrome_q(0) = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '1';
reg_calc_address_syndrome_ce <= '1';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_syndrome_ce <= '1';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '1';
reg_calc_address_syndrome_ce <= '1';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
end if;
when prepare_synd_3 =>
if(reg_first_syndrome_q(0) = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '1';
reg_calc_address_syndrome_ce <= '1';
reg_store_address_syndrome_ce <= '1';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_syndrome_ce <= '1';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '1';
reg_calc_address_syndrome_ce <= '1';
reg_store_address_syndrome_ce <= '1';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
end if;
when load_store_synd =>
if(limit_ctr_syndrome_q = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '1';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_syndrome_ce <= '1';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '1';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '1';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_syndrome_ce <= '1';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '1';
reg_calc_address_syndrome_ce <= '1';
reg_store_address_syndrome_ce <= '1';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
end if;
when final =>
syndrome_finalized <= '1';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
when others =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
end case;
end process;
NewState: process (actual_state, limit_ctr_codeword_q, limit_ctr_syndrome_q, reg_first_syndrome_q, reg_codeword_q, almost_units_ready, empty_units)
begin
case (actual_state) is
when reset =>
next_state <= load_counters;
when load_counters =>
next_state <= prepare_values;
when prepare_values =>
next_state <= load_values;
when load_values =>
next_state <= jump_codeword;
when jump_codeword =>
if(reg_codeword_q(0) = '1') then
if(almost_units_ready = '1') then
next_state <= prepare_synd;
elsif(limit_ctr_codeword_q = '1') then
next_state <= clear_remaining_units;
else
next_state <= prepare_values;
end if;
elsif(limit_ctr_codeword_q = '1') then
if(empty_units = '1') then
next_state <= final;
else
next_state <= clear_remaining_units;
end if;
else
next_state <= prepare_values;
end if;
when clear_remaining_units =>
if(almost_units_ready = '1') then
next_state <= prepare_synd;
else
next_state <= clear_remaining_units;
end if;
when prepare_synd =>
next_state <= prepare_synd_2;
when prepare_synd_2 =>
next_state <= prepare_synd_3;
when prepare_synd_3 =>
next_state <= load_store_synd;
when load_store_synd =>
if(limit_ctr_syndrome_q = '1') then
if(limit_ctr_codeword_q = '1') then
next_state <= final;
else
next_state <= prepare_values;
end if;
else
next_state <= load_store_synd;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
9c8f3e9e7dd8b60a74f2fc539347bba3
| 0.581631 | 2.659642 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/mceliece_qd_goppa_decrypt_v3.vhd
| 1 | 26,261 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: McEliece_QD-Goppa_Decrypt_v3
-- Module Name: McEliece_QD-Goppa_Decrypt_v3
-- Project Name: McEliece Goppa Decryption
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit implements McEliece decryption algorithm fo binary Goppa codes.
-- The circuit is divided into 3 phases : Syndrome computation, Solving Key Equation and
-- Finding Roots.
-- Each circuits waits for the next one to begin computation. All circuits share some
-- input and output memories, therefore is not possible to make a pipeline of this 3 phases.
-- First circuit, polynomial_syndrome_computing_n_v2, computes the syndrome from the ciphertext
-- and private keys, support L and polynomial g(x) (In this case g(L)^-1).
-- Second circuit, solving_key_equation_4, computes polynomial sigma through
-- the syndrome computed by first circuit.
-- Third circuit, polynomial_syndrome_computing_n_v2, find the roots of polynomial sigma
-- and correct respective errors in the ciphertext and obtains plaintext array.
-- Inversion circuit, inv_gf_2_m_pipeline, is only used during solving_key_equation_4.
-- This circuit was made outside of solving_key_equation_4 so it can be used by other circuits.
--
-- The circuits parameters
--
-- number_of_polynomial_evaluator_syndrome_pipelines :
--
-- The number of pipelines in polynomial_syndrome_computing_n_v2 circuit.
-- This number can be 1 or greater.
--
-- polynomial_evaluator_syndrome_pipeline_size :
--
-- This is the number of stages on polynomial_syndrome_computing_n_v2 circuit.
-- This number can be 2 or greater.
--
-- polynomial_evaluator_syndrome_size_pipeline_size :
--
-- The number of bits necessary to hold the number of stages on the pipeline.
-- This is ceil(log2(polynomial_evaluator_syndrome_pipeline_size))
--
-- gf_2_m :
--
-- The size of the finite field extension used in this circuit.
-- This values depends of the Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword in this Goppa code.
-- This values depends of the Goppa code used.
--
-- size_codeword :
--
-- The number of bits necessary to store an array of codeword lengths.
-- This is ceil(log2(length_codeword))
--
-- number_of_errors :
--
-- The number of errors the Goppa code is able to decode.
-- This values depends of the Goppa code used.
--
-- size_number_of_errors :
--
-- The number of bits necessary to store an array of number of errors + 1 length.
-- This is ceil(log2(number_of_errors + 1))
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- polynomial_syndrome_computing_n_v2 Rev 1.0
-- solving_key_equation_4 Rev 1.0
-- inv_gf_2_m_pipeline Rev 1.0
-- register_rst_nbits Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mceliece_qd_goppa_decrypt_v3 is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 4;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 28;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 27;
-- size_number_of_errors : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 50;
-- size_number_of_errors : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3307;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 66;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [2528, 2144, 32, 12] --
number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
polynomial_evaluator_syndrome_pipeline_size : integer := 2;
polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
gf_2_m : integer range 1 to 20 := 12;
length_codeword : integer := 2528;
size_codeword : integer := 12;
number_of_errors : integer := 32;
size_number_of_errors : integer := 6
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 4;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 7;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 3;
-- gf_2_m : integer range 1 to 20 := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- number_of_errors : integer := 128;
-- size_number_of_errors : integer := 8
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_L : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
value_G : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_B : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma_evaluated : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
syndrome_generation_finalized : out STD_LOGIC;
key_equation_finalized : out STD_LOGIC;
decryption_finalized : out STD_LOGIC;
address_value_h : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_L : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_codeword : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_G : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_B : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_G : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_B : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_sigma : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_error : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_G : out STD_LOGIC;
write_enable_new_value_B : out STD_LOGIC;
write_enable_new_value_sigma : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_new_value_error : out STD_LOGIC;
write_enable_new_value_sigma_evaluated : out STD_LOGIC;
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_G : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_B : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_error : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0)
);
end mceliece_qd_goppa_decrypt_v3;
architecture Behavioral of mceliece_qd_goppa_decrypt_v3 is
component polynomial_syndrome_computing_n_v2
Generic (
number_of_pipelines : integer := 1;
pipeline_size : integer := 2;
size_pipeline_size : integer := 2;
gf_2_m : integer range 1 to 20 := 13;
number_of_errors : integer := 128;
size_number_of_errors : integer := 8;
number_of_support_elements: integer := 7296;
size_number_of_support_elements : integer := 13
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_message : in STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_h : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
computation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
address_value_error : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_value_error : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR(((gf_2_m) - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_error : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0)
);
end component;
component solving_key_equation_4
Generic(
gf_2_m : integer range 1 to 20;
final_degree : integer;
size_final_degree : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_F : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_G : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_B : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_C : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_F : out STD_LOGIC;
write_enable_G : out STD_LOGIC;
write_enable_B : out STD_LOGIC;
write_enable_C : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_F : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_B : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_G : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_C : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_value_F : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_G : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_B : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_C : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_F : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_G : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_B : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_C : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end component;
component inv_gf_2_m_pipeline
Generic(gf_2_m : integer range 1 to 20 := 13);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
flag : in STD_LOGIC;
clk : in STD_LOGIC;
oflag : out STD_LOGIC;
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component register_rst_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
signal polynomial_evaluator_syndrome_value_x : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_value_polynomial : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal polynomial_evaluator_syndrome_value_message : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal polynomial_evaluator_syndrome_value_h : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_mode_polynomial_syndrome : STD_LOGIC;
signal polynomial_evaluator_syndrome_rst : STD_LOGIC;
signal polynomial_evaluator_syndrome_computation_finalized : STD_LOGIC;
signal polynomial_evaluator_syndrome_address_value_polynomial : STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
signal polynomial_evaluator_syndrome_address_value_x : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_value_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_value_message : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_new_value_message : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_new_value_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_new_value_syndrome : STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
signal polynomial_evaluator_syndrome_address_value_error : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_write_enable_new_value_acc : STD_LOGIC;
signal polynomial_evaluator_syndrome_write_enable_new_value_syndrome : STD_LOGIC;
signal polynomial_evaluator_syndrome_write_enable_new_value_message : STD_LOGIC;
signal polynomial_evaluator_syndrome_write_enable_value_error : STD_LOGIC;
signal polynomial_evaluator_syndrome_new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal polynomial_evaluator_syndrome_new_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_new_value_message : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal polynomial_evaluator_syndrome_value_error : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal syndrome_finalized : STD_LOGIC;
signal solving_key_equation_rst : STD_LOGIC;
signal solving_key_equation_value_F : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_C : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_key_equation_found : STD_LOGIC;
signal solving_key_equation_write_enable_F : STD_LOGIC;
signal solving_key_equation_write_enable_G : STD_LOGIC;
signal solving_key_equation_write_enable_B : STD_LOGIC;
signal solving_key_equation_write_enable_C : STD_LOGIC;
signal solving_key_equation_new_value_F : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_C : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_address_value_F : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_C : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_F : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_C : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal inv_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal inv_flag : STD_LOGIC;
signal inv_oflag : STD_LOGIC;
signal inv_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
begin
polynomial_evaluator_syndrome : polynomial_syndrome_computing_n_v2
Generic Map(
number_of_pipelines => number_of_polynomial_evaluator_syndrome_pipelines,
pipeline_size => polynomial_evaluator_syndrome_pipeline_size,
size_pipeline_size => polynomial_evaluator_syndrome_size_pipeline_size,
gf_2_m => gf_2_m,
number_of_errors => number_of_errors,
size_number_of_errors => size_number_of_errors,
number_of_support_elements => length_codeword,
size_number_of_support_elements => size_codeword
)
Port Map(
value_x => polynomial_evaluator_syndrome_value_x,
value_acc => polynomial_evaluator_syndrome_value_acc,
value_polynomial => polynomial_evaluator_syndrome_value_polynomial,
value_message => polynomial_evaluator_syndrome_value_message,
value_h => polynomial_evaluator_syndrome_value_h,
mode_polynomial_syndrome => polynomial_evaluator_syndrome_mode_polynomial_syndrome,
clk => clk,
rst => polynomial_evaluator_syndrome_rst,
computation_finalized => polynomial_evaluator_syndrome_computation_finalized,
address_value_polynomial => polynomial_evaluator_syndrome_address_value_polynomial,
address_value_x => polynomial_evaluator_syndrome_address_value_x,
address_value_acc => polynomial_evaluator_syndrome_address_value_acc,
address_value_message => polynomial_evaluator_syndrome_address_value_message,
address_new_value_message => polynomial_evaluator_syndrome_address_new_value_message,
address_new_value_acc => polynomial_evaluator_syndrome_address_new_value_acc,
address_new_value_syndrome => polynomial_evaluator_syndrome_address_new_value_syndrome,
address_value_error => polynomial_evaluator_syndrome_address_value_error,
write_enable_new_value_acc => polynomial_evaluator_syndrome_write_enable_new_value_acc,
write_enable_new_value_syndrome => polynomial_evaluator_syndrome_write_enable_new_value_syndrome,
write_enable_new_value_message => polynomial_evaluator_syndrome_write_enable_new_value_message,
write_enable_value_error => polynomial_evaluator_syndrome_write_enable_value_error,
new_value_syndrome => polynomial_evaluator_syndrome_new_value_syndrome,
new_value_acc => polynomial_evaluator_syndrome_new_value_acc,
new_value_message => polynomial_evaluator_syndrome_new_value_message,
value_error => polynomial_evaluator_syndrome_value_error
);
solving_key_equation : solving_key_equation_4
Generic Map(
gf_2_m => gf_2_m,
final_degree => number_of_errors,
size_final_degree => size_number_of_errors
)
Port Map(
clk => clk,
rst => solving_key_equation_rst,
ready_inv => inv_oflag,
value_F => solving_key_equation_value_F,
value_G => solving_key_equation_value_G,
value_B => solving_key_equation_value_B,
value_C => solving_key_equation_value_C,
value_inv => inv_o,
signal_inv => inv_flag,
key_equation_found => solving_key_equation_key_equation_found,
write_enable_F => solving_key_equation_write_enable_F,
write_enable_G => solving_key_equation_write_enable_G,
write_enable_B => solving_key_equation_write_enable_B,
write_enable_C => solving_key_equation_write_enable_C,
new_value_inv => inv_a,
new_value_F => solving_key_equation_new_value_F,
new_value_B => solving_key_equation_new_value_B,
new_value_G => solving_key_equation_new_value_G,
new_value_C => solving_key_equation_new_value_C,
address_value_F => solving_key_equation_address_value_F,
address_value_G => solving_key_equation_address_value_G,
address_value_B => solving_key_equation_address_value_B,
address_value_C => solving_key_equation_address_value_C,
address_new_value_F => solving_key_equation_address_new_value_F,
address_new_value_G => solving_key_equation_address_new_value_G,
address_new_value_B => solving_key_equation_address_new_value_B,
address_new_value_C => solving_key_equation_address_new_value_C
);
inverter : inv_gf_2_m_pipeline
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => inv_a,
flag => inv_flag,
clk => clk,
oflag => inv_oflag,
o => inv_o
);
reg_syndrome_finalized : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => "1",
clk => clk,
ce => polynomial_evaluator_syndrome_computation_finalized,
rst => rst,
rst_value => "0",
q(0) => syndrome_finalized
);
polynomial_evaluator_syndrome_value_x <= value_L;
polynomial_evaluator_syndrome_value_acc <= value_sigma_evaluated;
polynomial_evaluator_syndrome_value_polynomial <= value_sigma;
polynomial_evaluator_syndrome_value_message <= value_codeword;
polynomial_evaluator_syndrome_value_h <= value_h;
polynomial_evaluator_syndrome_mode_polynomial_syndrome <= not syndrome_finalized;
polynomial_evaluator_syndrome_rst <= ( (rst) or (syndrome_finalized and (not solving_key_equation_key_equation_found)));
solving_key_equation_rst <= not syndrome_finalized;
solving_key_equation_value_F <= value_syndrome;
solving_key_equation_value_G <= value_G;
solving_key_equation_value_B <= value_B;
solving_key_equation_value_C <= value_sigma;
syndrome_generation_finalized <= syndrome_finalized or polynomial_evaluator_syndrome_computation_finalized;
key_equation_finalized <= solving_key_equation_key_equation_found;
decryption_finalized <= polynomial_evaluator_syndrome_computation_finalized and solving_key_equation_key_equation_found;
address_value_h <= polynomial_evaluator_syndrome_address_value_acc;
address_value_L <= polynomial_evaluator_syndrome_address_value_x;
address_value_syndrome <= solving_key_equation_address_value_F when syndrome_finalized = '1' else
"0" & polynomial_evaluator_syndrome_address_new_value_syndrome;
address_value_codeword <= polynomial_evaluator_syndrome_address_value_message;
address_value_G <= solving_key_equation_address_value_G;
address_value_B <= solving_key_equation_address_value_B;
address_value_sigma <= "00" & polynomial_evaluator_syndrome_address_value_polynomial when solving_key_equation_key_equation_found = '1' else
solving_key_equation_address_value_C;
address_value_sigma_evaluated <= polynomial_evaluator_syndrome_address_value_acc;
new_value_syndrome <= solving_key_equation_new_value_F when syndrome_finalized = '1' else
polynomial_evaluator_syndrome_new_value_syndrome;
new_value_G <= solving_key_equation_new_value_G;
new_value_B <= solving_key_equation_new_value_B;
new_value_sigma <= solving_key_equation_new_value_C;
new_value_message <= polynomial_evaluator_syndrome_new_value_message;
new_value_error <= polynomial_evaluator_syndrome_value_error;
new_value_sigma_evaluated <= polynomial_evaluator_syndrome_new_value_acc;
write_enable_new_value_syndrome <= solving_key_equation_write_enable_F when syndrome_finalized = '1' else
polynomial_evaluator_syndrome_write_enable_new_value_syndrome;
write_enable_new_value_G <= solving_key_equation_write_enable_G;
write_enable_new_value_B <= solving_key_equation_write_enable_B;
write_enable_new_value_sigma <= solving_key_equation_write_enable_C;
write_enable_new_value_message <= polynomial_evaluator_syndrome_write_enable_new_value_message;
write_enable_new_value_error <= polynomial_evaluator_syndrome_write_enable_value_error;
write_enable_new_value_sigma_evaluated <= polynomial_evaluator_syndrome_write_enable_new_value_acc;
address_new_value_syndrome <= solving_key_equation_address_new_value_F when syndrome_finalized = '1' else
"0" & polynomial_evaluator_syndrome_address_new_value_syndrome;
address_new_value_G <= solving_key_equation_address_new_value_G;
address_new_value_B <= solving_key_equation_address_new_value_B;
address_new_value_sigma <= solving_key_equation_address_new_value_C;
address_new_value_message <= polynomial_evaluator_syndrome_address_new_value_message;
address_new_value_error <= polynomial_evaluator_syndrome_address_value_error;
address_new_value_sigma_evaluated <= polynomial_evaluator_syndrome_address_new_value_acc;
end Behavioral;
|
bsd-2-clause
|
8c82f6d4d7b9de6f02d828a97e62d79b
| 0.721222 | 3.14503 | false | false | false | false |
kharazi/ALU
|
ALU/ALU4.vhd
| 1 | 2,187 |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.2
-- \ \ Application :
-- / / Filename : xil_34000_21
-- /___/ /\ Timestamp : 01/16/2014 18:28:31
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity AlU4 is
port( Cl : in std_logic; -- Clock
A,B : in signed(3 downto 0); --input operands
Operation : in signed(3 downto 0); --select operation
Result : out signed(3 downto 0); --Reg3
Co : out std_logic --carry output
);
end ALU4;
architecture BEHAVIORAL of ALU4 is
signal Reg1,Reg2,Reg3 : signed(3 downto 0) := "0000";
begin
Reg1 <= A;
Reg2 <= B;
Result <= Reg3;
Co:= 0;
process(Cl)
begin
if(rising_edge(Cl)) then
case Operation is
when "0000" =>
Reg3 <= Reg1 + Reg2; --ADD
when "0001" =>
Reg3 <= Reg1 - Reg2; --SUB
when "0010" =>
Reg3 <= Reg1 * Reg2; --MUl
when "0011" =>
Reg3 <= Reg1 / Reg2; --DIV
when "0100" =>
Reg3 <= Reg1 nor Reg2; --NOR
when "0101" =>
Reg3 <= Reg1 nand Reg2; --NAND
when "0110" =>
Reg3 <= Reg1 or Reg2; --OR
when "0111" =>
Reg3 <= Reg1 and Reg2; --AND
when "1000" =>
Reg3 <= Reg1 xor Reg2; --xor
when "1001" =>
Reg3 <= Reg1 srl 1; --shift right logical
when "1010" =>
Reg3 <= Reg1 sll 1; --shift left logical
when "1011" =>
Reg3 <= Reg1 ror 1; -- right rotate
when "1100" =>
Reg3 <= Reg1 rol 1; -- left rotate
when others =>
NULL;
end case;
end if;
end process;
end BEHAVIORAL;
|
gpl-3.0
|
f4b42eee3b404a747bd8a5bb923e6d29
| 0.426155 | 3.651085 | false | false | false | false |
ruygargar/LCSE_lab
|
doc/PIC/bram64.vhd
| 1 | 2,008 |
-------------------------------------------------------------------------------
-- Author: Aragonés Orellana, Silvia
-- García Garcia, Ruy
-- Project Name: PIC
-- Design Name: ram.vhd
-- Module Name: bram64.vhd
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
ENTITY bram64 IS
PORT (
Clk : in std_logic;
WriteEnable : in std_logic;
OutputEnable : in std_logic;
Address : in std_logic_vector(5 downto 0);
Databus : inout std_logic_vector(7 downto 0) := (others => 'Z')
);
END bram64;
ARCHITECTURE behavior OF bram64 IS
-- RAM:
-- + Ancho de palabra: 8 bits (Bus de Datos de 8 bits)
-- + Longitud de la memoria: 64 (Bus de Direcciones de 6 bits)
-- + Tamaño: 64 bytes
SIGNAL contents_ram : array8_ram(63 downto 0);
BEGIN
-- Proceso secuencial utilizado para la actualización del valor almacenado
-- en cada dirección de memoria.
-- No dispone de Reset. Es necesaria la inicialización, mediante software,
-- de cada posición de memoria tras iniciar el sistema antes de su lectura.
process (Clk)
begin
if Clk'event and Clk = '1' then
if WriteEnable = '1' then
contents_ram(Conv_Integer(address)) <= Databus;
end if;
end if;
end process;
-- Lógica combinacional necesaria para multiplexar la salida de las
-- posiciones de memoria hacia el bus de datos en función de la dirección
-- indicada en el bus de direcciones.
-- Únicamente cuando la señal de control WriteEnable esté activada,
-- almacenará el valor del bus de datos en la posición de memoria cuya
-- dirección esté seleccionada en el bus de direcciones.
-- La salida al bus de datos se mantendrá a alta impedancia siempre que la
-- señal de control OutputEnable este desactivada.
Databus <= contents_ram(Conv_integer(address)) when OutputEnable= '1'
else (others => 'Z');
END behavior;
|
gpl-3.0
|
8949dddab5568c630d874e898ad7bf22
| 0.645916 | 3.541446 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
USB_TEST/FIFO_TO_USB.vhd
| 1 | 8,138 |
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo_mixed_widths
-- ============================================================
-- File Name: FIFO_TO_USB.vhd
-- Megafunction Name(s):
-- dcfifo_mixed_widths
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY FIFO_TO_USB IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
END FIFO_TO_USB;
ARCHITECTURE SYN OF fifo_to_usb IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (10 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (10 DOWNTO 0);
COMPONENT dcfifo_mixed_widths
GENERIC (
add_usedw_msb_bit : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
lpm_widthu_r : NATURAL;
lpm_width_r : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0);
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdreq : IN STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(15 DOWNTO 0);
wrusedw <= sub_wire1(10 DOWNTO 0);
rdusedw <= sub_wire2(10 DOWNTO 0);
dcfifo_mixed_widths_component : dcfifo_mixed_widths
GENERIC MAP (
add_usedw_msb_bit => "ON",
intended_device_family => "Cyclone IV E",
lpm_hint => "MAXIMUM_DEPTH=512",
lpm_numwords => 1024,
lpm_showahead => "OFF",
lpm_type => "dcfifo_mixed_widths",
lpm_width => 16,
lpm_widthu => 11,
lpm_widthu_r => 11,
lpm_width_r => 16,
overflow_checking => "ON",
rdsync_delaypipe => 5,
read_aclr_synch => "OFF",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 5
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
q => sub_wire0,
wrusedw => sub_wire1,
rdusedw => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "1024"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "16"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "1"
-- Retrieval info: PRIVATE: output_width NUMERIC "16"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_USEDW_MSB_BIT STRING "ON"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMUM_DEPTH=512"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "11"
-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL "rdusedw[10..0]"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL "wrusedw[10..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-- Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
-- Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_USB.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_USB.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_USB.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_USB.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_USB_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
36751fe642611201e04c987bbaa71787
| 0.669083 | 3.445385 | false | false | false | false |
ruygargar/LCSE_lab
|
dma/tb_dma_tx.vhd
| 1 | 3,437 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:54:09 01/07/2014
-- Design Name:
-- Module Name: C:/Users/Ruy/Desktop/LCSE_lab-master/dma/tb_dma_tx.vhd
-- Project Name: dma
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dma_tx
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_dma_tx IS
END tb_dma_tx;
ARCHITECTURE behavior OF tb_dma_tx IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dma_tx
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
Databus : IN std_logic_vector(7 downto 0);
Address : OUT std_logic_vector(7 downto 0);
ChipSelect : OUT std_logic;
WriteEnable : OUT std_logic;
OutputEnable : OUT std_logic;
Start_TX : IN std_logic;
Ready_TX : OUT std_logic;
End_TX : OUT std_logic;
DataOut : OUT std_logic_vector(7 downto 0);
Valid_DO : OUT std_logic;
Ack_DO : IN std_logic
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal Databus : std_logic_vector(7 downto 0) := (others => '0');
signal Start_TX : std_logic := '0';
signal Ack_DO : std_logic := '1';
--Outputs
signal Address : std_logic_vector(7 downto 0);
signal ChipSelect : std_logic;
signal WriteEnable : std_logic;
signal OutputEnable : std_logic;
signal Ready_TX : std_logic;
signal End_TX : std_logic;
signal DataOut : std_logic_vector(7 downto 0);
signal Valid_DO : std_logic;
-- Clock period definitions
constant Clk_period : time := 25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dma_tx PORT MAP (
Clk => Clk,
Reset => Reset,
Databus => Databus,
Address => Address,
ChipSelect => ChipSelect,
WriteEnable => WriteEnable,
OutputEnable => OutputEnable,
Start_TX => Start_TX,
Ready_TX => Ready_TX,
End_TX => End_TX,
DataOut => DataOut,
Valid_DO => Valid_DO,
Ack_DO => Ack_DO
);
-- Clock process definitions
Clk <= not Clk after Clk_period;
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
Reset <= '1';
wait for 50 ns;
Start_TX <= '1';
wait for 25 ns;
Start_TX <= '0';
Databus <= X"AA";
wait for 50 ns;
Databus <= X"55";
wait for 50 ns;
Databus <= X"00";
wait for 50 ns;
Ack_DO <= '0';
wait for 50 ns;
Ack_DO <= '1';
wait for 500 ns;
Ack_DO <= '0';
wait for 50 ns;
Ack_DO <= '1';
wait;
end process;
END;
|
gpl-3.0
|
1196af48279c3ace149f9e1ab6d52df4
| 0.570265 | 3.691729 | false | false | false | false |
hitomi2500/wasca
|
fpga_firmware/buff_spi_ram.vhd
| 1 | 9,916 |
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: buff_spi_ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2018 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY buff_spi_ram IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END buff_spi_ram;
ARCHITECTURE SYN OF buff_spi_ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
q_a <= sub_wire0(15 DOWNTO 0);
q_b <= sub_wire1(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
intended_device_family => "MAX 10",
lpm_type => "altsyncram",
numwords_a => 512,
numwords_b => 512,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "DONT_CARE",
read_during_write_mode_port_a => "NEW_DATA_WITH_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_WITH_NBE_READ",
widthad_a => 9,
widthad_b => 9,
width_a => 16,
width_b => 16,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
address_a => address_a,
address_b => address_b,
clock0 => clock,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_WITH_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
-- Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
-- Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
-- Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
-- Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
-- Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
-- Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL buff_spi_ram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL buff_spi_ram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL buff_spi_ram.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL buff_spi_ram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL buff_spi_ram_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
20f392a2551086eadd526880dffa8651
| 0.682937 | 3.381992 | false | false | false | false |
laurivosandi/hdl
|
zynq/src/ov7670_axi_stream_capture/ov7670_axi_stream_capture.vhd
| 1 | 3,774 |
----------------------------------------------------------------------------------
-- Authors: Mike Field <[email protected]>
-- Lauir Vosandi <[email protected]>
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ov7670_axi_stream_capture is
port (
pclk : in std_logic;
vsync : in std_logic;
href : in std_logic;
d : in std_logic_vector (7 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tlast : out std_logic;
m_axis_tdata : out std_logic_vector ( 31 downto 0 );
m_axis_tuser : out std_logic;
aclk : out std_logic
);
end ov7670_axi_stream_capture;
architecture behavioral of ov7670_axi_stream_capture is
signal d_latch : std_logic_vector(15 downto 0) := (others => '0');
signal address : std_logic_vector(18 downto 0) := (others => '0');
signal line : std_logic_vector(1 downto 0) := (others => '0');
signal href_last : std_logic_vector(6 downto 0) := (others => '0');
signal we_reg : std_logic := '0';
signal href_hold : std_logic := '0';
signal latched_vsync : std_logic := '0';
signal latched_href : std_logic := '0';
signal latched_d : std_logic_vector (7 downto 0) := (others => '0');
signal sof : std_logic := '0';
signal eol : std_logic := '0';
begin
-- Expand 16-bit RGB (5:6:5) to 32-bit RGBA (8:8:8:8)
m_axis_tdata <= "11111111" & d_latch(4 downto 0) & d_latch(0) & d_latch(0) & d_latch(0) & d_latch(10 downto 5) & d_latch(5) & d_latch(5) & d_latch(15 downto 11) & d_latch(11) & d_latch(11) & d_latch(11);
m_axis_tvalid <= we_reg;
m_axis_tlast <= eol;
m_axis_tuser <= sof;
aclk <= not pclk;
capture_process: process(pclk)
begin
if rising_edge(pclk) then
if we_reg = '1' then
address <= std_logic_vector(unsigned(address)+1);
end if;
if href_hold = '0' and latched_href = '1' then
case line is
when "00" => line <= "01";
when "01" => line <= "10";
when "10" => line <= "11";
when others => line <= "00";
end case;
end if;
href_hold <= latched_href;
-- Capturing the data from the camera
if latched_href = '1' then
d_latch <= d_latch( 7 downto 0) & latched_d;
end if;
we_reg <= '0';
-- Is a new screen about to start (i.e. we have to restart capturing)
if latched_vsync = '1' then
address <= (others => '0');
href_last <= (others => '0');
line <= (others => '0');
else
-- If not, set the write enable whenever we need to capture a pixel
if href_last(0) = '1' then
we_reg <= '1';
href_last <= (others => '0');
else
href_last <= href_last(href_last'high-1 downto 0) & latched_href;
end if;
end if;
case unsigned(address) mod 640 = 639 is
when true => eol <= '1';
when others => eol <= '0';
end case;
case unsigned(address) = 0 is
when true => sof <= '1';
when others => sof <= '0';
end case;
end if;
if falling_edge(pclk) then
latched_d <= d;
latched_href <= href;
latched_vsync <= vsync;
end if;
end process;
end behavioral;
|
mit
|
50e926e03029473a752924e02f9a3b0e
| 0.468998 | 3.656977 | false | false | false | false |
KenKeeley/My68k-system
|
CircuitBoards/MainBoard/SupportCPLD/Clock_Div_5.vhd
| 1 | 1,773 |
----------------------------------------------------------------------------------------------------
--
-- FileName: Clock_Div_5.vhd
-- Description: Clock Divide by 5.
--
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY work;
ENTITY Clock_Div_5 IS
PORT
(
nReset : IN STD_LOGIC; -- Reset
ClkIn : IN STD_LOGIC; -- Incoming Clock
ClkOut : OUT STD_LOGIC -- Outgoing Clock
);
END Clock_Div_5;
ARCHITECTURE Behavioral OF Clock_Div_5 IS
SIGNAL Div_1 : STD_LOGIC;
SIGNAL Div_2 : STD_LOGIC;
SIGNAL Counter_1 : UNSIGNED(2 DOWNTO 0);
SIGNAL Counter_2 : UNSIGNED(2 DOWNTO 0);
BEGIN
PROCESS(ClkIn, nReset)
BEGIN
IF (nReset = '0') THEN
Div_1 <= '0';
Counter_1 <= "000";
ELSIF RISING_EDGE(ClkIn) THEN
IF Counter_1 = 5 THEN
Counter_1 <= "001";
Div_1 <= '1';
ELSIF Counter_1 >= 2 THEN
Div_1 <= '0';
Counter_1 <= Counter_1 + 1;
ELSE
Div_1 <= '1';
Counter_1 <= Counter_1 + 1;
END IF;
END IF;
END PROCESS;
PROCESS(ClkIn, nReset)
BEGIN
IF (nReset = '0') THEN
Div_2 <= '0';
Counter_2 <= "000";
ELSIF FALLING_EDGE(ClkIn) THEN
IF Counter_2 = 5 THEN
Counter_2 <= "001";
Div_2 <= '1';
ELSIF Counter_2 >= 2 THEN
Div_2 <= '0';
Counter_2 <= Counter_2 + 1;
ELSE
Div_2 <= '1';
Counter_2 <= Counter_2 + 1;
END IF;
END IF;
END PROCESS;
ClkOut <= Div_1 OR Div_2;
END Behavioral;
|
gpl-3.0
|
8d500abb54ba3cc062b41e50af4f1b53
| 0.435984 | 3.957589 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/normalizer/normalizer.vhd
| 1 | 2,848 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--This component normalizes the vector components according to the steps used in cordic algorithm
entity normalizer is
generic(TOTAL_BITS: integer := 32; FRACTIONAL_BITS: integer := 16);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
steps_applied : in integer := 0;
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end normalizer;
architecture normalizer_arq of normalizer is
signal lut_index : integer := 0;
signal scaling_values_lut_value : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
component scaling_values_lut is
generic(TOTAL_BITS: integer := 32);
port(
steps: in integer := 0;
scaling_value: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
begin
scaling_values_lut_0 : scaling_values_lut
generic map(TOTAL_BITS => 32)
port map(
steps => lut_index,
scaling_value => scaling_values_lut_value
);
process (x_in, y_in, steps_applied, lut_index, scaling_values_lut_value) is
variable x_signed : signed(TOTAL_BITS - 1 downto 0) := (others => '0');
variable y_signed : signed(TOTAL_BITS - 1 downto 0) := (others => '0');
variable scaling_value_signed : signed(TOTAL_BITS - 1 downto 0) := (others => '0');
variable scaled_x : signed(TOTAL_BITS * 2 - 1 downto 0) := (others => '0');
variable scaled_y : signed(TOTAL_BITS * 2 - 1 downto 0) := (others => '0');
variable shifted_x : signed(TOTAL_BITS * 2 - 1 downto 0) := (others => '0');
variable shifted_y : signed(TOTAL_BITS * 2 - 1 downto 0) := (others => '0');
begin
lut_index <= steps_applied;
x_signed := signed(x_in);
y_signed := signed(y_in);
scaling_value_signed := signed(scaling_values_lut_value);
--report "X: " & integer'image(x_integer);
--report "Y: " & integer'image(y_integer);
--report "SV: " & integer'image(scaling_value_integer);
scaled_x := x_signed * scaling_value_signed;
scaled_y := y_signed * scaling_value_signed;
shifted_x := shift_right(scaled_x,FRACTIONAL_BITS);
shifted_y := shift_right(scaled_y,FRACTIONAL_BITS);
x_out <= std_logic_vector(shifted_x(TOTAL_BITS - 1 downto 0));
y_out <= std_logic_vector(shifted_y(TOTAL_BITS - 1 downto 0));
end process;
end architecture;
|
gpl-3.0
|
90ba95c15a1d328a43064dffb5bb17b2
| 0.570927 | 3.651282 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/number_shifter/number_shifter_tb.vhd
| 1 | 3,110 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity number_shifter_tb is
end entity;
architecture number_shifter_tb_arq of number_shifter_tb is
signal man_in : std_logic_vector(31 downto 0) := (others => '0');
signal sign_1_in : std_logic := '0';
signal sign_2_in : std_logic := '0';
signal greater_exp : std_logic_vector(5 downto 0) := (others => '0');
signal smaller_exp : std_logic_vector(5 downto 0) := (others => '0');
signal man_out : std_logic_vector(31 downto 0) := (others => '0');
signal rounding_bit : std_logic := '0';
component number_shifter is
generic(
BITS : natural := 32;
EXP_BITS : natural := 6
);
port(
sign_1_in : in std_logic;
sign_2_in : in std_logic;
greater_exp : in std_logic_vector(EXP_BITS - 1 downto 0);
smaller_exp : in std_logic_vector(EXP_BITS - 1 downto 0);
man_in : in std_logic_vector(BITS - 1 downto 0);
man_out : out std_logic_vector(BITS - 1 downto 0);
rounding_bit : out std_logic
);
end component;
for number_shifter_0 : number_shifter use entity work.number_shifter;
begin
number_shifter_0 : number_shifter
generic map(BITS => 32, EXP_BITS => 6)
port map(
man_in => man_in,
sign_1_in => sign_1_in,
sign_2_in => sign_2_in,
greater_exp => greater_exp,
smaller_exp => smaller_exp,
man_out => man_out,
rounding_bit => rounding_bit
);
process
type pattern_type is record
mi : std_logic_vector(31 downto 0);
s1 : std_logic;
s2 : std_logic;
ge : std_logic_vector(5 downto 0);
se : std_logic_vector(5 downto 0);
mo : std_logic_vector(31 downto 0);
rb : std_logic;
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("00000000000000000000000000000000",'0','0',"000000","000000","00000000000000000000000000000000",'0'),
("11000000000000000000000000000000",'0','0',"000001","000000","01100000000000000000000000000000",'0'),
("11000000000000000000000000000000",'1','0',"000001","000000","11100000000000000000000000000000",'0'),
("11000000000000000000000000000000",'1','1',"000001","000000","01100000000000000000000000000000",'0'),
("11000000000000000000000000000000",'0','1',"000001","000000","11100000000000000000000000000000",'0'),
("11000000000000000000000000000000",'0','0',"111111","000000","00000000000000000000000000000000",'0'),
("11000000000000000000000000000000",'0','1',"111111","000000","11111111111111111111111111111111",'1')
);
begin
for i in patterns'range loop
-- Set the inputs.
man_in <= patterns(i).mi;
sign_1_in <= patterns(i).s1;
sign_2_in <= patterns(i).s2;
greater_exp <= patterns(i).ge;
smaller_exp <= patterns(i).se;
wait for 1 ns;
assert patterns(i).mo = man_out report "BAD SHIFTING, GOT: " & integer'image(to_integer(unsigned(man_out)));
assert patterns(i).rb = rounding_bit report "BAD ROUNDING BIT, GOT " & std_logic'image(rounding_bit);
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
4e5e0b2af4756d2959c05847bf1075cd
| 0.667846 | 3.266807 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/Contador_td.vhd
| 2 | 762 |
library IEEE;
use IEEE.std_logic_1164.all;
entity contador_tb is
end;
architecture contador_sim of contador_tb is
signal rst_in: std_logic:='1';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal q0_out: std_logic:='0';
signal q1_out: std_logic:='0';
component contador is
port(
rst_c: in std_logic;
clk_c: in std_logic;
enable_c: in std_logic;
q1_c: out std_logic;
q0_c: out std_logic
);
end component;
begin
clk_in <= not clk_in after 20 ns;
enable_in <= '1' after 100 ns;
rst_in <= '0' after 50 ns;
ContadorMap: contador port map(
clk_c => clk_in,
rst_c => rst_in,
enable_c => enable_in,
q1_c => q1_out,
q0_c => q0_out
);
end architecture;
|
gpl-3.0
|
b60b35c8c567274ceba572e470957cea
| 0.594488 | 2.609589 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/controller_solving_key_equation_1_v2.vhd
| 1 | 62,386 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Solving_Key_Equation_1_v2
-- Module Name: Controller_Solving_Key_Equation_1_v2
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 2nd step in Goppa Code Decoding.
--
-- This is a state machine circuit that controls solving_key_equation_1_v2.
-- This state machine have 3 phases: first phase variable initialization,
-- second computation of polynomial sigma, third step writing the polynomial sigma
-- on a specific memory position.
--
-- This is the second circuit version. It is a non pipeline version of the algorithm,
-- each coefficient takes more than 1 cycle to be computed.
-- A more optimized pipelined version was made called solving_key_equation_2
--
-- Dependencies:
--
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_solving_key_equation_1_v2 is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
FB_equal_zero : in STD_LOGIC;
i_equal_zero : in STD_LOGIC;
i_minus_j_less_than_zero : in STD_LOGIC;
degree_G_less_equal_final_degree : in STD_LOGIC;
degree_F_less_than_degree_G : in STD_LOGIC;
degree_B_equal_degree_C_plus_j : in STD_LOGIC;
degree_B_less_than_degree_C_plus_j : in STD_LOGIC;
reg_looking_degree_q : in STD_LOGIC_VECTOR(0 downto 0);
key_equation_found : out STD_LOGIC;
signal_inv : out STD_LOGIC;
sel_new_value_inv : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
sel_base_mul : out STD_LOGIC;
reg_h_ce : out STD_LOGIC;
ctr_i_ce : out STD_LOGIC;
ctr_i_load : out STD_LOGIC;
ctr_i_rst : out STD_LOGIC;
sel_ctr_i_rst_value : out STD_LOGIC;
sel_ctr_i_d : out STD_LOGIC;
reg_j_ce : out STD_LOGIC;
reg_j_rst : out STD_LOGIC;
reg_FB_ce : out STD_LOGIC;
reg_FB_rst : out STD_LOGIC;
sel_reg_FB : out STD_LOGIC;
sel_load_new_value_FB : out STD_LOGIC;
reg_GC_ce : out STD_LOGIC;
reg_GC_rst : out STD_LOGIC;
sel_reg_GC : out STD_LOGIC;
ctr_degree_F_ce : out STD_LOGIC;
ctr_degree_F_load : out STD_LOGIC;
ctr_degree_F_rst : out STD_LOGIC;
reg_degree_G_ce : out STD_LOGIC;
reg_degree_G_rst : out STD_LOGIC;
ctr_degree_B_ce : out STD_LOGIC;
ctr_degree_B_load : out STD_LOGIC;
ctr_degree_B_rst : out STD_LOGIC;
sel_ctr_degree_B : out STD_LOGIC;
reg_degree_C_ce : out STD_LOGIC;
reg_degree_C_rst : out STD_LOGIC;
reg_looking_degree_d : out STD_LOGIC_VECTOR(0 downto 0);
reg_looking_degree_ce : out STD_LOGIC;
reg_swap_ce : out STD_LOGIC;
reg_swap_rst : out STD_LOGIC;
sel_address_FB : out STD_LOGIC;
sel_address_GC : out STD_LOGIC;
ctr_address_FB_ce : out STD_LOGIC;
ctr_address_FB_load : out STD_LOGIC;
ctr_address_GC_ce : out STD_LOGIC;
ctr_address_GC_load : out STD_LOGIC;
BC_calculation : out STD_LOGIC;
enable_external_swap : out STD_LOGIC
);
end controller_solving_key_equation_1_v2;
architecture Behavioral of controller_solving_key_equation_1_v2 is
type State is (reset, load_counter, store_G2t, load_first_inv, send_first_inv, prepare_load_F_store_G, load_F_store_G, wait_F, prepare_store_B_C, store_B_C, last_store_B_C, swap_F_G_B_C, prepare_load_j, load_j, load_first_G_first_F, load_h, prepare_load_F_G, load_F_G, mult_add_F_G, store_F, finalize_i, prepare_i, prepare_load_B_C, load_B_C, mult_add_B_C, store_B, prepare_final_swap, preparel_swap_address, prepare_load_sigma, load_sigma, store_sigma, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process(actual_state, FB_equal_zero, i_equal_zero, i_minus_j_less_than_zero, degree_G_less_equal_final_degree, degree_F_less_than_degree_G, degree_B_equal_degree_C_plus_j, degree_B_less_than_degree_C_plus_j, reg_looking_degree_q)
begin
case (actual_state) is
when reset =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '1';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '1';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when load_counter =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '1';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '1';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
sel_reg_GC <= '1';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
sel_address_FB <= '0';
sel_address_GC <= '1';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '1';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '1';
BC_calculation <= '0';
enable_external_swap <= '1';
when store_G2t =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '1';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "1";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '1';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '1';
BC_calculation <= '0';
enable_external_swap <= '1';
when load_first_inv =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when send_first_inv =>
key_equation_found <= '0';
signal_inv <= '1';
sel_new_value_inv <= '1';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when prepare_load_F_store_G =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when load_F_store_G =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when wait_F =>
if(i_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
elsif(reg_looking_degree_q(0) = '1' and FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
end if;
when prepare_store_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '1';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '1';
BC_calculation <= '1';
enable_external_swap <= '1';
when store_B_C =>
if(i_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '1';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
end if;
when last_store_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '1';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
BC_calculation <= '1';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
enable_external_swap <= '1';
when swap_F_G_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '1';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '1';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '1';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '1';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '1';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when prepare_load_j =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_rst <= '0';
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '1';
sel_address_GC <= '1';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '1';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '1';
BC_calculation <= '0';
enable_external_swap <= '1';
when load_j =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '1';
reg_j_ce <= '1';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '1';
sel_address_GC <= '1';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when load_first_G_first_F =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '1';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when load_h =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '1';
reg_h_ce <= '1';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "1";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when prepare_load_F_G =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when load_F_G =>
if(i_minus_j_less_than_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
end if;
when mult_add_F_G =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
when store_F =>
if(i_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_load_new_value_FB <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
elsif(reg_looking_degree_q(0) = '1') then
if(FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
elsif(degree_F_less_than_degree_G = '1') then
key_equation_found <= '0';
signal_inv <= '1';
sel_new_value_inv <= '1';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
end if;
else
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '1';
end if;
when prepare_i =>
if(degree_B_equal_degree_C_plus_j = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "1";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
elsif(degree_B_less_than_degree_C_plus_j = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '1';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '1';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
end if;
when finalize_i =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '1';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '1';
BC_calculation <= '1';
enable_external_swap <= '1';
when prepare_load_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
when load_B_C =>
if(i_minus_j_less_than_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
end if;
when mult_add_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
when store_B =>
if(i_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
elsif(reg_looking_degree_q(0) = '1' and FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
end if;
when prepare_final_swap =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
when preparel_swap_address =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '1';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '1';
BC_calculation <= '1';
enable_external_swap <= '1';
when prepare_load_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '1';
enable_external_swap <= '1';
when load_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '1';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '1';
BC_calculation <= '0';
enable_external_swap <= '1';
when store_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '1';
ctr_address_FB_load <= '1';
ctr_address_GC_ce <= '1';
ctr_address_GC_load <= '1';
BC_calculation <= '0';
enable_external_swap <= '0';
when final =>
key_equation_found <= '1';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '0';
when others =>
key_equation_found <= '0';
signal_inv <= '0';
sel_new_value_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_address_FB_ce <= '0';
ctr_address_FB_load <= '0';
ctr_address_GC_ce <= '0';
ctr_address_GC_load <= '0';
BC_calculation <= '0';
enable_external_swap <= '0';
end case;
end process;
New_State : process(actual_state, FB_equal_zero, i_equal_zero, i_minus_j_less_than_zero, degree_G_less_equal_final_degree, degree_F_less_than_degree_G, degree_B_equal_degree_C_plus_j, degree_B_less_than_degree_C_plus_j, reg_looking_degree_q)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= store_G2t;
when store_G2t =>
next_state <= load_first_inv;
when load_first_inv =>
next_state <= send_first_inv;
when send_first_inv =>
next_state <= prepare_load_F_store_G;
when prepare_load_F_store_G =>
next_state <= load_F_store_G;
when load_F_store_G =>
next_state <= wait_F;
when wait_F =>
if(i_equal_zero = '1') then
next_state <= prepare_store_B_C;
else
next_state <= prepare_load_F_store_G;
end if;
when prepare_store_B_C =>
next_state <= store_B_C;
when store_B_C =>
if(i_equal_zero = '1') then
next_state <= last_store_B_C;
else
next_state <= store_B_C;
end if;
when last_store_B_C =>
next_state <= swap_F_G_B_C;
when swap_F_G_B_C =>
next_state <= prepare_load_j;
when prepare_load_j =>
next_state <= load_j;
when load_j =>
next_state <= load_first_G_first_F;
when load_first_G_first_F =>
next_state <= load_h;
when load_h =>
next_state <= prepare_load_F_G;
when prepare_load_F_G =>
next_state <= load_F_G;
when load_F_G =>
next_state <= mult_add_F_G;
when mult_add_F_G =>
next_state <= store_F;
when store_F =>
if(i_equal_zero = '1') then
next_state <= prepare_i;
else
next_state <= prepare_load_F_G;
end if;
when prepare_i =>
next_state <= finalize_i;
when finalize_i =>
next_state <= prepare_load_B_C;
when prepare_load_B_C =>
next_state <= load_B_C;
when load_B_C =>
next_state <= mult_add_B_C;
when mult_add_B_C =>
next_state <= store_B;
when store_B =>
if(i_equal_zero = '1') then
if(degree_G_less_equal_final_degree = '1') then
next_state <= prepare_final_swap;
elsif(degree_F_less_than_degree_G = '1') then
next_state <= swap_F_G_B_C;
else
next_state <= prepare_load_j;
end if;
else
next_state <= prepare_load_B_C;
end if;
when prepare_final_swap =>
next_state <= preparel_swap_address;
when preparel_swap_address =>
next_state <= prepare_load_sigma;
when prepare_load_sigma =>
next_state <= load_sigma;
when load_sigma =>
next_state <= store_sigma;
when store_sigma =>
if(i_equal_zero = '1') then
next_state <= final;
else
next_state <= preparel_swap_address;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
d13d0f993b3a314aa8bb6e0ba20a1902
| 0.496425 | 2.277609 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/display/display.vhd
| 1 | 5,619 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity display is
port(
clk: in std_logic := '0';
rst: in std_logic := '0';
ena: in std_logic := '0';
hs: out std_logic := '0';
vs: out std_logic := '0';
red_o: out std_logic;
grn_o: out std_logic;
blu_o: out std_logic
);
attribute loc : string;
attribute loc of clk: signal is "C9";
attribute loc of rst: signal is "H13";
attribute loc of ena: signal is "D18";
attribute loc of hs: signal is "F15";
attribute loc of vs: signal is "F14";
attribute loc of red_o: signal is "H14";
attribute loc of grn_o: signal is "H15";
attribute loc of blu_o: signal is "G15";
end display;
architecture display_arq of display is
constant MIN_X : integer := 145;
constant MAX_X : integer := 145 + 350;
constant MIN_Y : integer := 65;
constant MAX_Y : integer := 65 + 350;
component memory_matrix is
generic(ROWS: integer := 350; COLUMNS: integer := 350; CLK_DELAY_COUNT: integer := 9);
port(
x_write: in std_logic_vector(9 downto 0) := (others => '0');
y_write: in std_logic_vector(9 downto 0) := (others => '0');
write_data: in std_logic_vector(0 downto 0) := (others => '0');
write_enable: in std_logic := '0';
clk: in std_logic := '0';
enable: in std_logic := '0';
reset: in std_logic := '0';
x_read: in std_logic_vector(9 downto 0) := (others => '0');
y_read: in std_logic_vector(9 downto 0) := (others => '0');
read_data : out std_logic_vector(0 downto 0) := (others => '0')
);
end component;
component vga_ctrl is
port (
mclk: in std_logic;
red_i: in std_logic;
grn_i: in std_logic;
blu_i: in std_logic;
hs: out std_logic;
vs: out std_logic;
red_o: out std_logic;
grn_o: out std_logic;
blu_o: out std_logic;
pixel_row: out std_logic_vector(9 downto 0);
pixel_col: out std_logic_vector(9 downto 0)
);
end component;
component memory_writer is
generic(ROWS : integer := 350; COLUMNS : integer := 350; BITS : integer := 32);
port(
clk : in std_logic := '0';
enable : in std_logic := '0';
rst : in std_logic := '0';
pixel_x : out std_logic_vector(9 downto 0) := (others => '0');
pixel_y : out std_logic_vector(9 downto 0) := (others => '0');
pixel_on : out std_logic_vector(0 downto 0) := (others => '0')
);
end component;
component memory_read_proxy is
generic(STARTING_X: integer := 0; STARTING_Y: integer := 0);
port(
x_in: in std_logic_vector(9 downto 0) := (others => '0');
y_in: in std_logic_vector(9 downto 0) := (others => '0');
memory_value: in std_logic_vector(0 downto 0) := (others => '0');
x_out: out std_logic_vector(9 downto 0) := (others => '0');
y_out: out std_logic_vector(9 downto 0) := (others => '0');
proxy_value: out std_logic_vector(0 downto 0) := (others => '0')
);
end component;
signal x_vga_to_proxy : std_logic_vector(9 downto 0) := (others => '0');
signal y_vga_to_proxy : std_logic_vector(9 downto 0) := (others => '0');
signal x_proxy_to_ram : std_logic_vector(9 downto 0) := (others => '0');
signal y_proxy_to_ram : std_logic_vector(9 downto 0) := (others => '0');
signal x_cordic_to_ram : std_logic_vector(9 downto 0) := (others => '0');
signal y_cordic_to_ram : std_logic_vector(9 downto 0) := (others => '0');
signal writer_to_memory_x : std_logic_vector(9 downto 0) := (others => '0');
signal writer_to_memory_y : std_logic_vector(9 downto 0) := (others => '0');
signal pixel_to_vga : std_logic_vector(0 downto 0) := (others => '0');
signal pixel_to_proxy : std_logic_vector(0 downto 0) := (others => '0');
signal pixel_to_matrix : std_logic_vector(0 downto 0) := (others => '0');
signal red : std_logic := '0';
signal green : std_logic := '0';
signal blue : std_logic := '0';
--For cordic--
signal vsync : std_logic := '0';
signal memory_values_rst : std_logic := '0';
begin
memory_matrix_0 : memory_matrix
generic map(CLK_DELAY_COUNT => 0)
port map(
x_write => writer_to_memory_x,
y_write => writer_to_memory_y,
write_data => pixel_to_matrix,
write_enable => '1',
clk => clk,
enable => ena,
reset => rst,
x_read => x_proxy_to_ram,
y_read => y_proxy_to_ram,
read_data => pixel_to_proxy
);
vga_controller_0: vga_ctrl
port map(
mclk => clk,
red_i => pixel_to_vga(0),
grn_i => pixel_to_vga(0),
blu_i => ena,
hs => hs,
vs => vsync,
red_o => red,
grn_o => green,
blu_o => blue,
pixel_row => y_vga_to_proxy,
pixel_col => x_vga_to_proxy
);
memory_writer_0 : memory_writer
port map(
clk => clk,
enable => ena,
rst => memory_values_rst,
pixel_x => writer_to_memory_x,
pixel_y => writer_to_memory_y,
pixel_on => pixel_to_matrix
);
memory_read_proxy_0 : memory_read_proxy
generic map(STARTING_X => 145, STARTING_Y => 65)
port map(
x_in => x_vga_to_proxy,
x_out => x_proxy_to_ram,
y_in => y_vga_to_proxy,
y_out => y_proxy_to_ram,
memory_value => pixel_to_proxy,
proxy_value => pixel_to_vga
);
vs <= vsync;
red_o <= red;
grn_o <= green;
blu_o <= blue;
memory_values_rst <= '0' when (
to_integer(unsigned(y_vga_to_proxy)) > MIN_Y and
to_integer(unsigned(y_vga_to_proxy)) < MAX_Y)
else '1';
end architecture;
|
gpl-3.0
|
d119d2d851f059612e9a5372b356e349
| 0.563979 | 3.083974 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
VHDL/USB/USB_RAM_BUFFER.vhd
| 1 | 16,531 |
--FPGA application for this system.
--copyright(c) 2014 dtysky
--This program is free software; you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation; either version 2 of the License, or
--(at your option) any later version.
--This program is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License along
--with this program; if not, write to the Free Software Foundation, Inc.,
--51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
------------------------------------------------------------------------
--数据传输结束确定后进入LOCK状态，usb_end置1
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity USB_RAM_BUFFER is
port
(
clk_usb_lock,clk_ram_lock:in std_logic;
clk_usb_p,clk_usb_o_p:in std_logic;
clk_ram_p:in std_logic;
usb_clk:out std_logic;
usb_full,usb_empty:in std_logic;
sloe:out std_logic:='0';
slrd,pktend:out std_logic:='0';
slwr:out std_logic:='0';
fifoadr:out std_logic_vector(1 downto 0);
usb_data_in:in std_logic_vector(15 downto 0);
usb_data_out:out std_logic_vector(15 downto 0):=x"0000";
usb_data_en:out std_logic:='0';
pc_rqu:in std_logic;
usb_in:in std_logic;
w_rqu,r_rqu:out std_logic;
w_ready,r_ready:in std_logic;
w_end,r_end:in std_logic;
ram_dm:out std_logic_vector(3 downto 0):="0011";
w_num,r_num:out std_logic_vector(15 downto 0);
ram_bank:out std_logic_vector(2 downto 0);
ram_addr_row:out std_logic_vector(12 downto 0);
ram_addr_col:out std_logic_vector(9 downto 0);
ram_data_in:in std_logic_vector(15 downto 0);
ram_data_out:out std_logic_vector(15 downto 0);
ram_reset:out std_logic:='0';
usb_end:out std_logic:='0'
);
end entity;
architecture bufferx of usb_RAM_BUFFER is
component FIFO_TO_OTHER is
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end component;
component FIFO_TO_USB is
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
end component;
component COUNTER_TIMEOUT IS
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
end component;
----------------fifo例化----------------
signal data_from_ram,data_to_ram:std_logic_vector(15 downto 0);
signal fifo_utr_write,fifo_utr_read:std_logic:='0';
signal fifo_utr_aclr:std_logic:='0';
signal data_from_usb:std_logic_vector(7 downto 0);
signal data_to_usb:std_logic_vector(7 downto 0);
signal clk_from_ram,clk_to_usb:std_logic:='0';
signal fifo_rtu_write,fifo_rtu_read:std_logic:='0';
signal fifo_rtu_aclr:std_logic:='0';
--------------fifo已写/可读数据-----------
signal fifo_utr_num_w:std_logic_vector(9 downto 0);
signal fifo_utr_num_r:std_logic_vector(8 downto 0);
signal fifo_utr_num_w_buffer:std_logic_vector(9 downto 0);
signal fifo_utr_num_r_buffer:std_logic_vector(8 downto 0);
signal fifo_rtu_num_w:std_logic_vector(10 downto 0);
signal fifo_rtu_num_w_buffer:std_logic_vector(10 downto 0);
signal fifo_rtu_num_r:std_logic_vector(11 downto 0);
----------------pc cmd------------------
signal command:std_logic_vector(15 downto 0);
------------------usb-------------------
signal usb_in_rqu,usb_out_rqu:std_logic:='0';
signal usb_in_rqu_last:std_logic:='0';
signal usb_in_ready,usb_out_ready:std_logic:='0';
signal usb_in_ready_last,usb_out_ready_last:std_logic:='0';
signal usb_in_allow:std_logic:='0';
signal usb_out_allow:std_logic:='0';
signal usb_check:std_logic_vector(15 downto 0);
signal usb_check_o:std_logic_vector(7 downto 0);
-------------------ram-------------------
signal w_num_s:std_logic_vector(15 downto 0):=x"0000";
signal ram_bank_s:std_logic_vector(2 downto 0):="000";
signal ram_addr_row_s:std_logic_vector(12 downto 0):="0000000000000";
signal ram_addr_col_s:std_logic_vector(9 downto 0):="0000000000";
signal r_num_s:std_logic_vector(15 downto 0):=x"0000";
signal trans_no:std_logic_vector(31 downto 0):=x"00000000";
signal r_ready_s:std_logic;
------------------timeout----------------
signal timeout_aclr:std_logic:='1';
signal timeout_clken:std_logic:='0';
signal timeout_q:std_logic_vector(11 downto 0);
signal timeout_buffer:std_logic_vector(11 downto 0);
-----------------flags-------------------
type ustates is (free,trans,collect,full,judge,ack,reset,lock);
type rstates is (free,trans,collect,judge,ack,reset,lock);
signal usb_state,usb_state_buffer:ustates:=free;
signal ram_state:rstates:=free;
begin
usb_clk<=clk_usb_o_p;
buffer_usb:FIFO_TO_OTHER
port map
(
aclr=>fifo_utr_aclr,
data=>data_from_usb,q(7 downto 0)=>data_to_ram(15 downto 8),q(15 downto 8)=>data_to_ram(7 downto 0),
wrclk=>clk_usb_p,rdclk=>clk_ram_p,
wrreq=>fifo_utr_write,rdreq=>fifo_utr_read,
wrusedw=>fifo_utr_num_w,rdusedw=>fifo_utr_num_r
);
buffer_ram:FIFO_TO_USB
port map
(
aclr=>fifo_rtu_aclr,
data=>data_from_ram,q=>data_to_usb,
wrclk=>clk_ram_p,rdclk=>clk_usb_p,
wrreq=>fifo_rtu_write,rdreq=>fifo_rtu_read,
wrusedw=>fifo_rtu_num_w,rdusedw=>fifo_rtu_num_r
);
timeout:COUNTER_TIMEOUT
port map
(
aclr=>timeout_aclr,
clk_en=>timeout_clken,
clock=>clk_ram_p,
q=>timeout_q
);
--------------USB------------
usb_control:process(clk_usb_p,clk_usb_lock)
variable con_full:integer range 0 to 7:=0;
variable con_collect:integer range 0 to 3:=0;
variable con_ack:integer range 0 to 7:=0;
begin
if clk_usb_p'event and clk_usb_p='1' and clk_usb_lock='1' then
case usb_state is
-----------IDLE------------
when free =>
fifo_rtu_aclr<='0';
pktend<='0';
if usb_full='1' then
usb_state<=full;
else
usb_state<=free;
end if;
-----------FULL------------
when full =>
case con_full is
when 0 =>
usb_data_en<='0';
fifo_utr_write<='0';
sloe<='0';
slrd<='0';
fifoadr<="00";
con_full:=con_full+1;
when 1 =>
sloe<='1';
con_full:=con_full+1;
when 2 =>
con_full:=con_full+1;
when 3 =>
slrd<='1';
fifo_utr_write<='1';
con_full:=con_full+1;
when others =>
case fifo_utr_num_w_buffer is
when "0111111100" =>
usb_check(7 downto 0)<=usb_data_in(7 downto 0);
when "0111111101" =>
usb_check(15 downto 8)<=usb_data_in(7 downto 0);
sloe<='0';
slrd<='0';
fifo_utr_write<='0';
when "1000000000" =>
usb_state<=judge;
con_full:=0;
when others =>
fifo_utr_write<=fifo_utr_write;
end case;
end case;
-------------JUDGE------------
when judge =>
case ram_state is
when collect =>
if fifo_rtu_num_w_buffer="10000000000" then
usb_state<=collect;
else
usb_state<=judge;
end if;
when trans =>
usb_state<=trans;
when judge =>
usb_state<=judge;
when others =>
usb_state<=reset;
end case;
-----------TRANS------------
when trans =>
case ram_state is
when ack =>
usb_state<=ack;
when trans =>
usb_state<=trans;
when others =>
usb_state<=reset;
end case;
-------------ACK------------
when ack =>
case con_ack is
when 0 =>
usb_data_en<='1';
fifoadr<="10";
slwr<='0';
pktend<='0';
con_ack:=con_ack+1;
when 2 =>
usb_check_o<=usb_check(7 downto 0);
slwr<='1';
con_ack:=con_ack+1;
when 3=>
usb_check_o<=usb_check(15 downto 8);
con_ack:=con_ack+1;
when 4 =>
slwr<='0';
pktend<='1';
con_ack:=con_ack+1;
when 5 =>
usb_data_en<='0';
pktend<='0';
usb_state<=free;
con_ack:=0;
when others =>
con_ack:=con_ack+1;
end case;
-----------COLLECT----------
when collect =>
if ram_state=reset or usb_full='1' then
usb_state<=reset;
else
case con_collect is
when 0 =>
usb_data_en<='1';
fifoadr<="10";
con_collect:=con_collect+1;
when 1 =>
fifo_rtu_read<='1';
con_collect:=con_collect+1;
when 2 =>
slwr<='1';
con_collect:=con_collect+1;
when others =>
if usb_in='0' and fifo_rtu_num_r(7 downto 0)=x"01" then
usb_data_en<='0';
fifo_rtu_read<='0';
elsif usb_in='0' and fifo_rtu_num_r(7 downto 0)=x"00" then
slwr<='0';
elsif usb_in='1' and fifo_rtu_num_r(11)='0' then
case fifo_rtu_num_r(10 downto 9) is
when "00" =>
usb_state<=free;
when others =>
usb_data_en<='1';
fifo_rtu_read<='1';
slwr<='1';
end case;
else
fifo_rtu_read<=fifo_rtu_read;
end if;
-- if fifo_rtu_num_r="0000000000" then
-- usb_data_en<='0';
-- fifo_rtu_read<='0';
-- slwr<='0';
-- usb_state<=free;
-- con_collect:=0;
-- else
-- fifo_rtu_read<='1';
-- end if;
end case;
end if;
-----------RESET-----------
when reset =>
con_full:=0;
con_ack:=0;
con_collect:=0;
fifo_rtu_aclr<='1';
usb_data_en<='0';
fifo_rtu_read<='0';
slwr<='0';
usb_state<=free;
-----------LOCK------------
when lock =>
fifo_rtu_aclr<='1';
-----------ERROR-----------
when others =>
usb_state<=reset;
end case;
fifo_utr_num_w_buffer<=fifo_utr_num_w;
end if;
end process;
data_from_usb<=usb_data_in(7 downto 0);
--data_from_usb(15 downto 8)<=usb_data_in(7 downto 0);
with usb_state select
usb_data_out(7 downto 0)<=usb_check_o when ack,
data_to_usb when collect,
x"00" when others;
--------------RAM------------
ram_control:process(clk_ram_p,clk_ram_lock)
variable con_judge:integer range 0 to 7:=0;
variable con_collect:integer range 0 to 3:=0;
variable con_trans:integer range 0 to 3:=0;
begin
if clk_ram_p'event and clk_ram_p='1' and clk_ram_lock='1' then
case ram_state is
-------------IDLE-------------
when free =>
fifo_utr_aclr<='0';
ram_reset<='0';
if usb_state_buffer=judge then
ram_state<=judge;
else
ram_state<=free;
end if;
-------------JUDGE------------
when judge =>
case con_judge is
when 0 =>
fifo_utr_read<='1';
con_judge:=con_judge+1;
when 1 =>
con_judge:=con_judge+1;
when 2 =>
command<=data_to_ram;
con_judge:=con_judge+1;
when 3 =>
w_num_s<=data_to_ram;
r_num_s<=data_to_ram;
con_judge:=con_judge+1;
when 4 =>
trans_no(15 downto 8)<=data_to_ram(7 downto 0);
trans_no(7 downto 0)<=data_to_ram(15 downto 8);
con_judge:=con_judge+1;
when 5 =>
fifo_utr_read<='0';
trans_no(31 downto 24)<=data_to_ram(7 downto 0);
trans_no(23 downto 16)<=data_to_ram(15 downto 8);
con_judge:=con_judge+1;
when 6 =>
con_judge:=0;
case command is
when "1000011110000110" => --UTF8-采集-8786
ram_state<=collect;
fifo_utr_aclr<='1';
when "1010000010000001" => --UTF8-传送-A081
ram_state<=trans;
when "1001010101011101" => --UTF8-锁定-955B
--ram_state<=lock;
null;
when others =>
ram_state<=reset;
end case;
when others =>
ram_state<=reset;
end case;
-----------TRANS------------
when trans =>
if timeout_buffer=2500 then
ram_reset<='1';
fifo_utr_read<='0';
w_rqu<='0';
ram_state<=reset;
else
case con_trans is
when 0 =>
case trans_no(1 downto 0) is
when "00" =>
ram_addr_col_s<="0000000000";
when "01" =>
ram_addr_col_s<="0011111011"; --251
when "10" =>
ram_addr_col_s<="0111110110"; --502
when "11" =>
ram_addr_col_s<="1011110001"; --753
when others =>
null;
end case;
ram_addr_row_s<=trans_no(14 downto 2);
ram_bank_s<=trans_no(17 downto 15);
if trans_no(18)='1' then
ram_dm<="0011";
else
ram_dm<="1100";
end if;
con_trans:=con_trans+1;
when 1 =>
timeout_clken<='1';
timeout_aclr<='0';
w_rqu<='1';
w_num<=w_num_s;
ram_bank<=ram_bank_s;
ram_addr_col<=ram_addr_col_s;
ram_addr_row<=ram_addr_row_s;
con_trans:=con_trans+1;
when others =>
if w_ready='1' then
fifo_utr_read<='1';
elsif fifo_utr_num_r_buffer<"000100000" then
timeout_clken<='0';
timeout_aclr<='1';
fifo_utr_read<='0';
w_rqu<='0';
fifo_utr_aclr<='1';
ram_state<=ack;
con_trans:=0;
else
ram_state<=trans;
end if;
end case;
end if;
-------------ACK------------
when ack =>
case usb_state_buffer is
when free =>
ram_state<=free;
when ack =>
ram_state<=ack;
when trans =>
ram_state<=ack;
when others =>
ram_state<=reset;
end case;
-----------COLLECT----------
when collect =>
if timeout_buffer=4090 then
ram_reset<='1';
fifo_rtu_write<='0';
r_rqu<='0';
ram_state<=reset;
else
case con_collect is
when 0 =>
ram_addr_col_s<="0000000000";
ram_addr_row_s<=trans_no(12 downto 0);
ram_bank_s<=trans_no(15 downto 13);
if trans_no(16)='1' then
ram_dm<="0011";
else
ram_dm<="1100";
end if;
con_trans:=con_trans+1;
con_collect:=con_collect+1;
when 1 =>
timeout_clken<='1';
timeout_aclr<='0';
r_rqu<='1';
r_num<=r_num_s;
ram_bank<=ram_bank_s;
ram_addr_col<=ram_addr_col_s;
ram_addr_row<=ram_addr_row_s;
con_collect:=con_collect+1;
when others =>
case r_ready_s is
when '1' =>
fifo_rtu_write<='1';
when others =>
--if fifo_rtu_num_w_buffer(9 downto 2)=r_num_s(7 downto 0) then
if usb_state_buffer=collect then
timeout_clken<='0';
timeout_aclr<='1';
ram_state<=free;
con_collect:=0;
else
con_collect:=con_collect;
end if;
end case;
if fifo_rtu_num_w_buffer="10000000000" then
fifo_rtu_write<='0';
r_rqu<='0';
else
r_rqu<='1';
end if;
end case;
end if;
-----------RESET------------
when reset =>
fifo_utr_aclr<='1';
ram_reset<='1';
con_judge:=0;
con_trans:=0;
con_collect:=0;
if usb_state_buffer=free then
ram_state<=free;
else
null;
end if;
------------LOCK------------
when lock =>
fifo_utr_aclr<='1';
usb_end<='1';
------------ERROR-----------
when others =>
ram_state<=reset;
end case;
fifo_utr_num_r_buffer<=fifo_utr_num_r;
fifo_rtu_num_w_buffer<=fifo_rtu_num_w;
timeout_buffer<=timeout_q;
usb_state_buffer<=usb_state;
r_ready_s<=r_ready;
end if;
end process;
ram_data_out<=data_to_ram;
data_from_ram<=ram_data_in;
end bufferx;
|
gpl-2.0
|
f1b0a3c60dc9f2e7c6494baaba6db0be
| 0.533843 | 2.990198 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/finite_field/product_generator_gf_2_m.vhd
| 1 | 57,326 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Product_Generator_GF_2_M
-- Module Name: Product_Generator_GF_2_M
-- Project Name: GF_2_M Arithmetic
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit is part of the GF(2^m) multiplier.
-- This circuit generates the partial product to be latter used in the multiplier.
-- This version is for primitive polynomials present on IEEE 13009 cryptographic standard.
--
-- The circuits parameters
--
-- m :
--
-- The size of the field used in this circuit.
--
-- value :
--
-- Used to select the partial product generated by this circuit of
-- o = a * x^(value)
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity product_generator_gf_2_m is
Generic(
value : integer;
m : integer range 2 to 20
);
Port (
a : in STD_LOGIC_VECTOR ((m - 1) downto 0);
o : out STD_LOGIC_VECTOR ((m - 1) downto 0)
);
end product_generator_gf_2_m;
architecture IEEE_POLYNOMIALS of product_generator_gf_2_m is
constant final_value : integer := value mod m;
begin
GF_2_2 : if m = 2 generate -- x^2 + x^1 + 1
GF_2_2_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_2_P_1 : if final_value = 1 generate
o <= ( (a(0) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_3 : if m = 3 generate -- x^3 + x^1 + 1
GF_2_3_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_3_P_1 : if final_value = 1 generate
o <= ( a(1) & (a(0) xor a(2)) & a(2) );
end generate;
GF_2_3_P_2 : if final_value = 2 generate
o <= ( (a(0) xor a(2)) & (a(2) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_4 : if m = 4 generate -- x^4 + x^1 + 1
GF_2_4_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_4_P_1 : if final_value = 1 generate
o <= ( a(2 downto 1) & (a(0) xor a(3)) & a(3) );
end generate;
GF_2_4_P_2 : if final_value = 2 generate
o <= ( a(1) & (a(0) xor a(3)) & (a(3) xor a(2)) & a(2) );
end generate;
GF_2_4_P_3 : if final_value = 3 generate
o <= ( (a(0) xor a(3)) & (a(3) xor a(2)) & (a(2) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_5 : if m = 5 generate -- x^5 + x^2 + 1
GF_2_5_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_5_P_1 : if final_value = 1 generate
o <= ( a(3) & a(2) & (a(1) xor a(4)) & a(0) & a(4) );
end generate;
GF_2_5_P_2 : if final_value = 2 generate
o <= ( a(2) & (a(1) xor a(4)) & (a(0) xor a(3)) & a(4) & a(3) );
end generate;
GF_2_5_P_3 : if final_value = 3 generate
o <= ( (a(1) xor a(4)) & (a(0) xor a(3)) & (a(4) xor a(2)) & a(3) & a(2) );
end generate;
GF_2_5_P_4 : if final_value = 4 generate
o <= ( (a(0) xor a(3)) & (a(4) xor a(2)) & (a(3) xor a(1) xor a(4)) & a(2) & (a(1) xor a(4)) );
end generate;
end generate;
GF_2_6 : if m = 6 generate -- x^6 + x^1 + 1
GF_2_6_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_6_P_1 : if final_value = 1 generate
o <= ( a(4) & a(3) & a(2) & a(1) & (a(0) xor a(5)) & a(5) );
end generate;
GF_2_6_P_2 : if final_value = 2 generate
o <= ( a(3) & a(2) & a(1) & (a(0) xor a(5)) & (a(5) xor a(4)) & a(4) );
end generate;
GF_2_6_P_3 : if final_value = 3 generate
o <= ( a(2) & a(1) & (a(0) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & a(3) );
end generate;
GF_2_6_P_4 : if final_value = 4 generate
o <= ( a(1) & (a(0) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & a(2) );
end generate;
GF_2_6_P_5 : if final_value = 5 generate
o <= ( (a(0) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & (a(2) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_7 : if m = 7 generate -- x^7 + x^1 + 1
GF_2_7_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_7_P_1 : if final_value = 1 generate
o <= ( a(5) & a(4) & a(3) & a(2) & a(1) & (a(0) xor a(6)) & a(6) );
end generate;
GF_2_7_P_2 : if final_value = 2 generate
o <= ( a(4) & a(3) & a(2) & a(1) & (a(0) xor a(6)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_7_P_3 : if final_value = 3 generate
o <= ( a(3) & a(2) & a(1) & (a(0) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & a(4) );
end generate;
GF_2_7_P_4 : if final_value = 4 generate
o <= ( a(2) & a(1) & (a(0) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & a(3) );
end generate;
GF_2_7_P_5 : if final_value = 5 generate
o <= ( a(1) & (a(0) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & a(2) );
end generate;
GF_2_7_P_6 : if final_value = 6 generate
o <= ( (a(0) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & (a(2) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_8 : if m = 8 generate -- x^8 + x^4 + x^3 + x^1 + 1
GF_2_8_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_8_P_1 : if final_value = 1 generate
o <= ( a(6) & a(5) & a(4) & (a(3) xor a(7)) & (a(2) xor a(7)) & a(1) & (a(0) xor a(7)) & a(7) );
end generate;
GF_2_8_P_2 : if final_value = 2 generate
o <= ( a(5) & a(4) & (a(3) xor a(7)) & ((a(2) xor a(7)) xor a(6)) & (a(1) xor a(6)) & (a(0) xor a(7)) & (a(7) xor a(6)) & a(6) );
end generate;
GF_2_8_P_3 : if final_value = 3 generate
o <= ( a(4) & (a(3) xor a(7)) & (a(2) xor a(7) xor a(6)) & (a(1) xor a(6) xor a(5)) & (a(0) xor a(7) xor a(5)) & (a(7) xor a(6)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_8_P_4 : if final_value = 4 generate
o <= ( (a(3) xor a(7)) & (a(2) xor a(7) xor a(6)) & (a(1) xor a(6) xor a(5)) & (a(0) xor a(7) xor a(5) xor a(4)) & (a(7) xor a(6) xor a(4)) & (a(6) xor a(5)) & (a(5) xor a(4)) & a(4) );
end generate;
GF_2_8_P_5 : if final_value = 5 generate
o <= ( (a(2) xor a(7) xor a(6)) & (a(1) xor a(6) xor a(5)) & (a(0) xor a(7) xor a(5) xor a(4)) & (a(6) xor a(4) xor a(3)) & (a(6) xor a(5) xor a(3) xor a(7)) & (a(5) xor a(4)) & (a(4) xor a(3) xor a(7)) & (a(3) xor a(7)) );
end generate;
GF_2_8_P_6 : if final_value = 6 generate
o <= ( (a(1) xor a(6) xor a(5)) & (a(0) xor a(7) xor a(5) xor a(4)) & (a(6) xor a(4) xor a(3)) & (a(5) xor a(3) xor a(2)) & (a(5) xor a(4) xor a(2) xor a(7) xor a(6)) & (a(4) xor a(3) xor a(7)) & (a(3) xor a(2) xor a(6)) & (a(2) xor a(7) xor a(6)) );
end generate;
GF_2_8_P_7 : if final_value = 7 generate
o <= ( (a(0) xor a(7) xor a(5) xor a(4)) & (a(6) xor a(4) xor a(3)) & (a(5) xor a(3) xor a(2)) & (a(4) xor a(2) xor a(7) xor a(1)) & (a(4) xor a(3) xor a(7) xor a(1) xor a(6) xor a(5)) & (a(3) xor a(2) xor a(6)) & (a(2) xor a(7) xor a(1) xor a(5)) & (a(1) xor a(6) xor a(5)) );
end generate;
end generate;
GF_2_9 : if m = 9 generate -- x^9 + x^1 + 1
GF_2_9_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_9_P_1 : if final_value = 1 generate
o <= ( a(7) & a(6) & a(5) & a(4) & a(3) & a(2) & a(1) & (a(0) xor a(8)) & a(8) );
end generate;
GF_2_9_P_2 : if final_value = 2 generate
o <= ( a(6) & a(5) & a(4) & a(3) & a(2) & a(1) & (a(0) xor a(8)) & (a(8) xor a(7)) & a(7) );
end generate;
GF_2_9_P_3 : if final_value = 3 generate
o <= ( a(5) & a(4) & a(3) & a(2) & a(1) & (a(0) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & a(6) );
end generate;
GF_2_9_P_4 : if final_value = 4 generate
o <= ( a(4) & a(3) & a(2) & a(1) & (a(0) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_9_P_5 : if final_value = 5 generate
o <= ( a(3) & a(2) & a(1) & (a(0) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & a(4) );
end generate;
GF_2_9_P_6 : if final_value = 6 generate
o <= ( a(2) & a(1) & (a(0) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & a(3) );
end generate;
GF_2_9_P_7 : if final_value = 7 generate
o <= ( a(1) & (a(0) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & a(2) );
end generate;
GF_2_9_P_8 : if final_value = 8 generate
o <= ( (a(0) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & (a(2) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_10 : if m = 10 generate -- x^10 + x^3 + 1
GF_2_10_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_10_P_1 : if final_value = 1 generate
o <= ( a(8) & a(7) & a(6) & a(5) & a(4) & a(3) & (a(2) xor a(9)) & a(1) & a(0) & a(9) );
end generate;
GF_2_10_P_2 : if final_value = 2 generate
o <= ( a(7) & a(6) & a(5) & a(4) & a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) & a(0) & a(9) & a(8) );
end generate;
GF_2_10_P_3 : if final_value = 3 generate
o <= ( a(6) & a(5) & a(4) & a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) & (a(0) xor a(7)) & a(9) & a(8) & a(7) );
end generate;
GF_2_10_P_4 : if final_value = 4 generate
o <= ( a(5) & a(4) & a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) & (a(0) xor a(7)) & (a(9) xor a(6)) & a(8) & a(7) & a(6) );
end generate;
GF_2_10_P_5 : if final_value = 5 generate
o <= ( a(4) & a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) & (a(0) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & a(7) & a(6) & a(5) );
end generate;
GF_2_10_P_6 : if final_value = 6 generate
o <= ( a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) & (a(0) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & a(6) & a(5) & a(4) );
end generate;
GF_2_10_P_7 : if final_value = 7 generate
o <= ( (a(2) xor a(9)) & (a(1) xor a(8)) & (a(0) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & a(5) & a(4) & a(3) );
end generate;
GF_2_10_P_8 : if final_value = 8 generate
o <= ( (a(1) xor a(8)) & (a(0) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(9)) & a(4) & a(3) & (a(2) xor a(9)) );
end generate;
GF_2_10_P_9 : if final_value = 9 generate
o <= ( (a(0) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(9)) & (a(4) xor a(1) xor a(8)) & a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) );
end generate;
end generate;
GF_2_11 : if m = 11 generate -- x^11 + x^2 + 1
GF_2_11_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_11_P_1 : if final_value = 1 generate
o <= ( a(9 downto 2) & (a(1) xor a(10)) & a(0) & a(10) );
end generate;
GF_2_11_P_2 : if final_value = 2 generate
o <= ( a(8 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & a(10) & a(9) );
end generate;
GF_2_11_P_3 : if final_value = 3 generate
o <= ( a(7 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & a(9) & a(8) );
end generate;
GF_2_11_P_4 : if final_value = 4 generate
o <= ( a(6 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & a(8) & a(7) );
end generate;
GF_2_11_P_5 : if final_value = 5 generate
o <= ( a(5 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & a(7) & a(6) );
end generate;
GF_2_11_P_6 : if final_value = 6 generate
o <= ( a(4 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & (a(7) xor a(5)) & a(6) & a(5) );
end generate;
GF_2_11_P_7 : if final_value = 7 generate
o <= ( a(3 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & (a(7) xor a(5)) & (a(6) xor a(4)) & a(5) & a(4) );
end generate;
GF_2_11_P_8 : if final_value = 8 generate
o <= ( a(2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & (a(7) xor a(5)) & (a(6) xor a(4)) & (a(5) xor a(3)) & a(4) & a(3) );
end generate;
GF_2_11_P_9 : if final_value = 9 generate
o <= ( (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & (a(7) xor a(5)) & (a(6) xor a(4)) & (a(5) xor a(3)) & (a(4) xor a(2)) & a(3) & a(2) );
end generate;
GF_2_11_P_10 : if final_value = 10 generate
o <= ( (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & (a(7) xor a(5)) & (a(6) xor a(4)) & (a(5) xor a(3)) & (a(4) xor a(2)) & (a(3) xor a(1) xor a(10)) & a(2) & (a(1) xor a(10)) );
end generate;
end generate;
GF_2_12 : if m = 12 generate -- x^12 + x^3 + 1
GF_2_12_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_12_P_1 : if final_value = 1 generate
o <= ( a(10 downto 3) & (a(2) xor a(11)) & a(1) & a(0) & a(11) );
end generate;
GF_2_12_P_2 : if final_value = 2 generate
o <= ( a(9 downto 3) & (a(2) xor a(11)) & (a(1) xor a(10)) & a(0) & a(11) & a(10) );
end generate;
GF_2_12_P_3 : if final_value = 3 generate
o <= ( a(8 downto 3) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & a(11) & a(10) & a(9) );
end generate;
GF_2_12_P_4 : if final_value = 4 generate
o <= ( a(7 downto 3) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(11) xor a(8)) & a(10) & a(9) & a(8) );
end generate;
GF_2_12_P_5 : if final_value = 5 generate
o <= ( a(6 downto 3) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & a(9) & a(8) & a(7) );
end generate;
GF_2_12_P_6 : if final_value = 6 generate
o <= ( a(5 downto 3) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & a(8) & a(7) & a(6) );
end generate;
GF_2_12_P_7 : if final_value = 7 generate
o <= ( a(4 downto 3) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & a(7) & a(6) & a(5) );
end generate;
GF_2_12_P_8 : if final_value = 8 generate
o <= ( a(3) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & a(6) & a(5) & a(4) );
end generate;
GF_2_12_P_9 : if final_value = 9 generate
o <= ( (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & a(5) & a(4) & a(3) );
end generate;
GF_2_12_P_10 : if final_value = 10 generate
o <= ( (a(1) xor a(10)) & (a(0) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(11)) & a(4) & a(3) & (a(2) xor a(11)) );
end generate;
GF_2_12_P_11 : if final_value = 11 generate
o <= ( (a(0) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(11)) & (a(4) xor a(1) xor a(10)) & a(3) & (a(2) xor a(11)) & (a(1) xor a(10)) );
end generate;
end generate;
GF_2_13 : if m = 13 generate -- x^13 + x^4 + x^3 + x^1 + 1
GF_2_13_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_13_P_1 : if final_value = 1 generate
o <= ( a(11 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12)) & a(1) & (a(0) xor a(12)) & a(12) );
end generate;
GF_2_13_P_2 : if final_value = 2 generate
o <= ( a(10 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11)) & (a(0) xor a(12)) & (a(12) xor a(11)) & a(11) );
end generate;
GF_2_13_P_3 : if final_value = 3 generate
o <= ( a(9 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10)) & (a(12) xor a(11)) & (a(11) xor a(10)) & a(10) );
end generate;
GF_2_13_P_4 : if final_value = 4 generate
o <= ( a(8 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9)) & (a(11) xor a(10)) & (a(10) xor a(9)) & a(9) );
end generate;
GF_2_13_P_5 : if final_value = 5 generate
o <= ( a(7 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8)) & (a(10) xor a(9)) & (a(9) xor a(8)) & a(8) );
end generate;
GF_2_13_P_6 : if final_value = 6 generate
o <= ( a(6 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7)) & (a(9) xor a(8)) & (a(8) xor a(7)) & a(7) );
end generate;
GF_2_13_P_7 : if final_value = 7 generate
o <= ( a(5 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6)) & (a(8) xor a(7)) & (a(7) xor a(6)) & a(6) );
end generate;
GF_2_13_P_8 : if final_value = 8 generate
o <= ( a(4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6) xor a(5)) & (a(8) xor a(7) xor a(5)) & (a(7) xor a(6)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_13_P_9 : if final_value = 9 generate
o <= ( (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6) xor a(5)) & (a(8) xor a(7) xor a(5) xor a(4)) & (a(7) xor a(6) xor a(4)) & (a(6) xor a(5)) & (a(5) xor a(4)) & a(4) );
end generate;
GF_2_13_P_10 : if final_value = 10 generate
o <= ( (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6) xor a(5)) & (a(8) xor a(7) xor a(5) xor a(4)) & (a(7) xor a(6) xor a(4) xor a(3) xor a(12)) & (a(6) xor a(5) xor a(3) xor a(12)) & (a(5) xor a(4)) & (a(4) xor a(3) xor a(12)) & (a(3) xor a(12)) );
end generate;
GF_2_13_P_11 : if final_value = 11 generate
o <= ( (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6) xor a(5)) & (a(8) xor a(7) xor a(5) xor a(4)) & (a(7) xor a(6) xor a(4) xor a(3) xor a(12)) & (a(6) xor a(5) xor a(3) xor a(2) xor a(11)) & (a(5) xor a(4) xor a(2) xor a(12) xor a(11)) & (a(4) xor a(3) xor a(12)) & (a(3) xor a(2) xor a(11)) & (a(2) xor a(12) xor a(11)) );
end generate;
GF_2_13_P_12 : if final_value = 12 generate
o <= ( (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6) xor a(5)) & (a(8) xor a(7) xor a(5) xor a(4)) & (a(7) xor a(6) xor a(4) xor a(3) xor a(12)) & (a(6) xor a(5) xor a(3) xor a(2) xor a(11)) & (a(5) xor a(4) xor a(2) xor a(12) xor a(1) xor a(10)) & (a(4) xor a(3) xor a(12) xor a(1) xor a(11) xor a(10)) & (a(3) xor a(2) xor a(11)) & (a(2) xor a(12) xor a(1) xor a(10)) & (a(1) xor a(11) xor a(10)) );
end generate;
end generate;
GF_2_14 : if m = 14 generate -- x^14 + x^5 + 1
GF_2_14_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_14_P_1 : if final_value = 1 generate
o <= ( a(12 downto 5) & (a(4) xor a(13)) & a(3) & a(2) & a(1) & a(0) & a(13) );
end generate;
GF_2_14_P_2 : if final_value = 2 generate
o <= ( a(11 downto 5) & (a(4) xor a(13)) & (a(3) xor a(12)) & a(2) & a(1) & a(0) & a(13) & a(12) );
end generate;
GF_2_14_P_3 : if final_value = 3 generate
o <= ( a(10 downto 5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) & a(1) & a(0) & a(13) & a(12) & a(11) );
end generate;
GF_2_14_P_4 : if final_value = 4 generate
o <= ( a(9 downto 5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) & (a(1) xor a(10)) & a(0) & a(13) & a(12) & a(11) & a(10) );
end generate;
GF_2_14_P_5 : if final_value = 5 generate
o <= ( a(8 downto 5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & a(13) & a(12) & a(11) & a(10) & a(9) );
end generate;
GF_2_14_P_6 : if final_value = 6 generate
o <= ( a(7 downto 5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(13) xor a(8)) & a(12) & a(11) & a(10) & a(9) & a(8) );
end generate;
GF_2_14_P_7 : if final_value = 7 generate
o <= ( a(6 downto 5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(13) xor a(8)) & (a(12) xor a(7)) & a(11) & a(10) & a(9) & a(8) & a(7) );
end generate;
GF_2_14_P_8 : if final_value = 8 generate
o <= ( a(5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(13) xor a(8)) & (a(12) xor a(7)) & (a(11) xor a(6)) & a(10) & a(9) & a(8) & a(7) & a(6) );
end generate;
GF_2_14_P_9 : if final_value = 9 generate
o <= ( (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(13) xor a(8)) & (a(12) xor a(7)) & (a(11) xor a(6)) & (a(10) xor a(5)) & a(9) & a(8) & a(7) & a(6) & a(5) );
end generate;
GF_2_14_P_10 : if final_value = 10 generate
o <= ( (a(3) xor a(12)) & (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(13) xor a(8)) & (a(12) xor a(7)) & (a(11) xor a(6)) & (a(10) xor a(5)) & (a(9) xor a(4) xor a(13)) & a(8) & a(7) & a(6) & a(5) & (a(4) xor a(13)) );
end generate;
GF_2_14_P_11 : if final_value = 11 generate
o <= ( (a(2) xor a(11)) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(13) xor a(8)) & (a(12) xor a(7)) & (a(11) xor a(6)) & (a(10) xor a(5)) & (a(9) xor a(4) xor a(13)) & (a(8) xor a(3) xor a(12)) & a(7) & a(6) & a(5) & (a(4) xor a(13)) & (a(3) xor a(12)) );
end generate;
GF_2_14_P_12 : if final_value = 12 generate
o <= ( (a(1) xor a(10)) & (a(0) xor a(9)) & (a(13) xor a(8)) & (a(12) xor a(7)) & (a(11) xor a(6)) & (a(10) xor a(5)) & (a(9) xor a(4) xor a(13)) & (a(8) xor a(3) xor a(12)) & (a(7) xor a(2) xor a(11)) & a(6) & a(5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) );
end generate;
GF_2_14_P_13 : if final_value = 13 generate
o <= ( (a(0) xor a(9)) & (a(13) xor a(8)) & (a(12) xor a(7)) & (a(11) xor a(6)) & (a(10) xor a(5)) & (a(9) xor a(4) xor a(13)) & (a(8) xor a(3) xor a(12)) & (a(7) xor a(2) xor a(11)) & (a(6) xor a(1) xor a(10)) & a(5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(11)) & (a(1) xor a(10)) );
end generate;
end generate;
GF_2_15 : if m = 15 generate -- x^15 + x^1 + 1
GF_2_15_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_15_P_1 : if final_value = 1 generate
o <= ( a(13 downto 1) & (a(0) xor a(14)) & a(14) );
end generate;
GF_2_15_P_2 : if final_value = 2 generate
o <= ( a(12 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & a(13) );
end generate;
GF_2_15_P_3 : if final_value = 3 generate
o <= ( a(11 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & a(12) );
end generate;
GF_2_15_P_4 : if final_value = 4 generate
o <= ( a(10 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & a(11) );
end generate;
GF_2_15_P_5 : if final_value = 5 generate
o <= ( a(9 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & a(10) );
end generate;
GF_2_15_P_6 : if final_value = 6 generate
o <= ( a(8 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & a(9) );
end generate;
GF_2_15_P_7 : if final_value = 7 generate
o <= ( a(7 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & a(8) );
end generate;
GF_2_15_P_8 : if final_value = 8 generate
o <= ( a(6 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & a(7) );
end generate;
GF_2_15_P_9 : if final_value = 9 generate
o <= ( a(5 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & a(6) );
end generate;
GF_2_15_P_10 : if final_value = 10 generate
o <= ( a(4 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_15_P_11 : if final_value = 11 generate
o <= ( a(3 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & a(4) );
end generate;
GF_2_15_P_12 : if final_value = 12 generate
o <= ( a(2 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & a(3) );
end generate;
GF_2_15_P_13 : if final_value = 13 generate
o <= ( a(1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & a(2) );
end generate;
GF_2_15_P_14 : if final_value = 14 generate
o <= ( (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & (a(2) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_16 : if m = 16 generate -- x^16 + x^5 + x^3 + x^1 + 1
GF_2_16_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_16_P_1 : if final_value = 1 generate
o <= ( a(14 downto 5) & (a(4) xor a(15)) & a(3) & (a(2) xor a(15)) & a(1) & (a(0) xor a(15)) & a(15) );
end generate;
GF_2_16_P_2 : if final_value = 2 generate
o <= ( a(13 downto 5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15)) & (a(1) xor a(14)) & (a(0) xor a(15)) & (a(15) xor a(14)) & a(14) );
end generate;
GF_2_16_P_3 : if final_value = 3 generate
o <= ( a(12 downto 5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14)) & (a(0) xor a(15) xor a(13)) & (a(15) xor a(14)) & (a(14) xor a(13)) & a(13) );
end generate;
GF_2_16_P_4 : if final_value = 4 generate
o <= ( a(11 downto 5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13)) & (a(15) xor a(14) xor a(12)) & (a(14) xor a(13)) & (a(13) xor a(12)) & a(12) );
end generate;
GF_2_16_P_5 : if final_value = 5 generate
o <= ( a(10 downto 5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12)) & (a(14) xor a(13) xor a(11)) & (a(13) xor a(12)) & (a(12) xor a(11)) & a(11) );
end generate;
GF_2_16_P_6 : if final_value = 6 generate
o <= ( a(9 downto 5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11)) & (a(13) xor a(12) xor a(10)) & (a(12) xor a(11)) & (a(11) xor a(10)) & a(10) );
end generate;
GF_2_16_P_7 : if final_value = 7 generate
o <= ( a(8 downto 5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10)) & (a(12) xor a(11) xor a(9)) & (a(11) xor a(10)) & (a(10) xor a(9)) & a(9) );
end generate;
GF_2_16_P_8 : if final_value = 8 generate
o <= ( a(7 downto 5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9)) & (a(11) xor a(10) xor a(8)) & (a(10) xor a(9)) & (a(9) xor a(8)) & a(8) );
end generate;
GF_2_16_P_9 : if final_value = 9 generate
o <= ( a(6 downto 5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8)) & (a(10) xor a(9) xor a(7)) & (a(9) xor a(8)) & (a(8) xor a(7)) & a(7) );
end generate;
GF_2_16_P_10 : if final_value = 10 generate
o <= ( a(5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7)) & (a(9) xor a(8) xor a(6)) & (a(8) xor a(7)) & (a(7) xor a(6)) & a(6) );
end generate;
GF_2_16_P_11 : if final_value = 11 generate
o <= ( (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7) xor a(5)) & (a(9) xor a(8) xor a(6)) & (a(8) xor a(7) xor a(5)) & (a(7) xor a(6)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_16_P_12 : if final_value = 12 generate
o <= ( (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7) xor a(5)) & (a(9) xor a(8) xor a(6) xor a(4) xor a(15)) & (a(8) xor a(7) xor a(5)) & (a(7) xor a(6) xor a(4) xor a(15)) & (a(6) xor a(5)) & (a(5) xor a(4) xor a(15)) & (a(4) xor a(15)) );
end generate;
GF_2_16_P_13 : if final_value = 13 generate
o <= ( (a(2) xor a(15) xor a(13)) & (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7) xor a(5)) & (a(9) xor a(8) xor a(6) xor a(4) xor a(15)) & (a(8) xor a(7) xor a(5) xor a(3) xor a(14)) & (a(7) xor a(6) xor a(4) xor a(15)) & (a(6) xor a(5) xor a(3) xor a(14)) & (a(5) xor a(4) xor a(15)) & (a(4) xor a(15) xor a(3) xor a(14)) & (a(3) xor a(14)) );
end generate;
GF_2_16_P_14 : if final_value = 14 generate
o <= ( (a(1) xor a(14) xor a(12)) & (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7) xor a(5)) & (a(9) xor a(8) xor a(6) xor a(4) xor a(15)) & (a(8) xor a(7) xor a(5) xor a(3) xor a(14)) & (a(7) xor a(6) xor a(4) xor a(2) xor a(13)) & (a(6) xor a(5) xor a(3) xor a(14)) & (a(5) xor a(4) xor a(2) xor a(13)) & (a(4) xor a(15) xor a(3) xor a(14)) & (a(3) xor a(14) xor a(2) xor a(15) xor a(13)) & (a(2) xor a(15) xor a(13)) );
end generate;
GF_2_16_P_15 : if final_value = 15 generate
o <= ( (a(0) xor a(15) xor a(13) xor a(11)) & (a(15) xor a(14) xor a(12) xor a(10)) & (a(14) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7) xor a(5)) & (a(9) xor a(8) xor a(6) xor a(4) xor a(15)) & (a(8) xor a(7) xor a(5) xor a(3) xor a(14)) & (a(7) xor a(6) xor a(4) xor a(2) xor a(13)) & (a(6) xor a(5) xor a(3) xor a(1) xor a(12)) & (a(5) xor a(4) xor a(2) xor a(13)) & (a(4) xor a(15) xor a(3) xor a(1) xor a(12)) & (a(3) xor a(14) xor a(2) xor a(15) xor a(13)) & (a(2) xor a(15) xor a(13) xor a(1) xor a(14) xor a(12)) & (a(1) xor a(14) xor a(12)) );
end generate;
end generate;
GF_2_17 : if m = 17 generate -- x^17 + x^3 + 1
GF_2_17_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_17_P_1 : if final_value = 1 generate
o <= ( a(15 downto 3) & (a(2) xor a(16)) & a(1) & a(0) & a(16) );
end generate;
GF_2_17_P_2 : if final_value = 2 generate
o <= ( a(14 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & a(0) & a(16) & a(15) );
end generate;
GF_2_17_P_3 : if final_value = 3 generate
o <= ( a(13 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & a(16) & a(15) & a(14) );
end generate;
GF_2_17_P_4 : if final_value = 4 generate
o <= ( a(12 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & a(15) & a(14) & a(13) );
end generate;
GF_2_17_P_5 : if final_value = 5 generate
o <= ( a(11 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & a(14) & a(13) & a(12) );
end generate;
GF_2_17_P_6 : if final_value = 6 generate
o <= ( a(10 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & a(13) & a(12) & a(11) );
end generate;
GF_2_17_P_7 : if final_value = 7 generate
o <= ( a(9 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & a(12) & a(11) & a(10) );
end generate;
GF_2_17_P_8 : if final_value = 8 generate
o <= ( a(8 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & a(11) & a(10) & a(9) );
end generate;
GF_2_17_P_9 : if final_value = 9 generate
o <= ( a(7 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & a(10) & a(9) & a(8) );
end generate;
GF_2_17_P_10 : if final_value = 10 generate
o <= ( a(6 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & a(9) & a(8) & a(7) );
end generate;
GF_2_17_P_11 : if final_value = 11 generate
o <= ( a(5 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & a(8) & a(7) & a(6) );
end generate;
GF_2_17_P_12 : if final_value = 12 generate
o <= ( a(4 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & a(7) & a(6) & a(5) );
end generate;
GF_2_17_P_13 : if final_value = 13 generate
o <= ( a(3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & a(6) & a(5) & a(4) );
end generate;
GF_2_17_P_14 : if final_value = 14 generate
o <= ( (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & a(5) & a(4) & a(3) );
end generate;
GF_2_17_P_15 : if final_value = 15 generate
o <= ( (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(16)) & a(4) & a(3) & (a(2) xor a(16)) );
end generate;
GF_2_17_P_16 : if final_value = 16 generate
o <= ( (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(16)) & (a(4) xor a(1) xor a(15)) & a(3) & (a(2) xor a(16)) & (a(1) xor a(15)) );
end generate;
end generate;
GF_2_18 : if m = 18 generate -- x^18 + x^3 + 1
GF_2_18_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_18_P_1 : if final_value = 1 generate
o <= ( a(16 downto 3) & (a(2) xor a(17)) & a(1) & a(0) & a(17) );
end generate;
GF_2_18_P_2 : if final_value = 2 generate
o <= ( a(15 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & a(0) & a(17) & a(16) );
end generate;
GF_2_18_P_3 : if final_value = 3 generate
o <= ( a(14 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & a(17) & a(16) & a(15) );
end generate;
GF_2_18_P_4 : if final_value = 4 generate
o <= ( a(13 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & a(16) & a(15) & a(14) );
end generate;
GF_2_18_P_5 : if final_value = 5 generate
o <= ( a(12 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & a(15) & a(14) & a(13) );
end generate;
GF_2_18_P_6 : if final_value = 6 generate
o <= ( a(11 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & a(14) & a(13) & a(12) );
end generate;
GF_2_18_P_7 : if final_value = 7 generate
o <= ( a(10 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & a(13) & a(12) & a(11) );
end generate;
GF_2_18_P_8 : if final_value = 8 generate
o <= ( a(9 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & a(12) & a(11) & a(10) );
end generate;
GF_2_18_P_9 : if final_value = 9 generate
o <= ( a(8 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & a(11) & a(10) & a(9) );
end generate;
GF_2_18_P_10 : if final_value = 10 generate
o <= ( a(7 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & a(10) & a(9) & a(8) );
end generate;
GF_2_18_P_11 : if final_value = 11 generate
o <= ( a(6 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & a(9) & a(8) & a(7) );
end generate;
GF_2_18_P_12 : if final_value = 12 generate
o <= ( a(5 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & a(8) & a(7) & a(6) );
end generate;
GF_2_18_P_13 : if final_value = 13 generate
o <= ( a(4 downto 3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & a(7) & a(6) & a(5) );
end generate;
GF_2_18_P_14 : if final_value = 14 generate
o <= ( a(3) & (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & a(6) & a(5) & a(4) );
end generate;
GF_2_18_P_15 : if final_value = 15 generate
o <= ( (a(2) xor a(17)) & (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & a(5) & a(4) & a(3) );
end generate;
GF_2_18_P_16 : if final_value = 16 generate
o <= ( (a(1) xor a(16)) & (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(17)) & a(4) & a(3) & (a(2) xor a(17)) );
end generate;
GF_2_18_P_17 : if final_value = 17 generate
o <= ( (a(0) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(17)) & (a(4) xor a(1) xor a(16)) & a(3) & (a(2) xor a(17)) & (a(1) xor a(16)) );
end generate;
end generate;
GF_2_19 : if m = 19 generate -- x^19 + x^5 + x^2 + x^1 + 1
GF_2_19_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_19_P_1 : if final_value = 1 generate
o <= ( a(17 downto 5) & (a(4) xor a(18)) & a(3) & a(2) & (a(1) xor a(18)) & (a(0) xor a(18)) & a(18) );
end generate;
GF_2_19_P_2 : if final_value = 2 generate
o <= ( a(16 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & a(2) & (a(1) xor a(18)) & (a(0) xor a(18) xor a(17)) & (a(18) xor a(17)) & a(17) );
end generate;
GF_2_19_P_3 : if final_value = 3 generate
o <= ( a(15 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18)) & (a(0) xor a(18) xor a(17)) & (a(18) xor a(17) xor a(16)) & (a(17) xor a(16)) & a(16) );
end generate;
GF_2_19_P_4 : if final_value = 4 generate
o <= ( a(14 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17)) & (a(18) xor a(17) xor a(16)) & (a(17) xor a(16) xor a(15)) & (a(16) xor a(15)) & a(15) );
end generate;
GF_2_19_P_5 : if final_value = 5 generate
o <= ( a(13 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16)) & (a(17) xor a(16) xor a(15)) & (a(16) xor a(15) xor a(14)) & (a(15) xor a(14)) & a(14) );
end generate;
GF_2_19_P_6 : if final_value = 6 generate
o <= ( a(12 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15)) & (a(16) xor a(15) xor a(14)) & (a(15) xor a(14) xor a(13)) & (a(14) xor a(13)) & a(13) );
end generate;
GF_2_19_P_7 : if final_value = 7 generate
o <= ( a(11 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14)) & (a(15) xor a(14) xor a(13)) & (a(14) xor a(13) xor a(12)) & (a(13) xor a(12)) & a(12) );
end generate;
GF_2_19_P_8 : if final_value = 8 generate
o <= ( a(10 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13)) & (a(14) xor a(13) xor a(12)) & (a(13) xor a(12) xor a(11)) & (a(12) xor a(11)) & a(11) );
end generate;
GF_2_19_P_9 : if final_value = 9 generate
o <= ( a(9 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12)) & (a(13) xor a(12) xor a(11)) & (a(12) xor a(11) xor a(10)) & (a(11) xor a(10)) & a(10) );
end generate;
GF_2_19_P_10 : if final_value = 10 generate
o <= ( a(8 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11)) & (a(12) xor a(11) xor a(10)) & (a(11) xor a(10) xor a(9)) & (a(10) xor a(9)) & a(9) );
end generate;
GF_2_19_P_11 : if final_value = 11 generate
o <= ( a(7 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10)) & (a(11) xor a(10) xor a(9)) & (a(10) xor a(9) xor a(8)) & (a(9) xor a(8)) & a(8) );
end generate;
GF_2_19_P_12 : if final_value = 12 generate
o <= ( a(6 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9)) & (a(10) xor a(9) xor a(8)) & (a(9) xor a(8) xor a(7)) & (a(8) xor a(7)) & a(7) );
end generate;
GF_2_19_P_13 : if final_value = 13 generate
o <= ( a(5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8)) & (a(9) xor a(8) xor a(7)) & (a(8) xor a(7) xor a(6)) & (a(7) xor a(6)) & a(6) );
end generate;
GF_2_19_P_14 : if final_value = 14 generate
o <= ( (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8) xor a(5)) & (a(9) xor a(8) xor a(7)) & (a(8) xor a(7) xor a(6)) & (a(7) xor a(6) xor a(5)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_19_P_15 : if final_value = 15 generate
o <= ( (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8) xor a(5)) & (a(9) xor a(8) xor a(7) xor a(4) xor a(18)) & (a(8) xor a(7) xor a(6)) & (a(7) xor a(6) xor a(5)) & (a(6) xor a(5) xor a(4) xor a(18)) & (a(5) xor a(4) xor a(18)) & (a(4) xor a(18)) );
end generate;
GF_2_19_P_16 : if final_value = 16 generate
o <= ( (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8) xor a(5)) & (a(9) xor a(8) xor a(7) xor a(4) xor a(18)) & (a(8) xor a(7) xor a(6) xor a(3) xor a(17)) & (a(7) xor a(6) xor a(5)) & (a(6) xor a(5) xor a(4) xor a(18)) & (a(5) xor a(4) xor a(18) xor a(3) xor a(17)) & (a(4) xor a(18) xor a(3) xor a(17)) & (a(3) xor a(17)) );
end generate;
GF_2_19_P_17 : if final_value = 17 generate
o <= ( (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8) xor a(5)) & (a(9) xor a(8) xor a(7) xor a(4) xor a(18)) & (a(8) xor a(7) xor a(6) xor a(3) xor a(17)) & (a(7) xor a(6) xor a(5) xor a(2) xor a(16)) & (a(6) xor a(5) xor a(4) xor a(18)) & (a(5) xor a(4) xor a(18) xor a(3) xor a(17)) & (a(4) xor a(18) xor a(3) xor a(17) xor a(2) xor a(16)) & (a(3) xor a(17) xor a(2) xor a(16)) & (a(2) xor a(16)) );
end generate;
GF_2_19_P_18 : if final_value = 18 generate
o <= ( (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8) xor a(5)) & (a(9) xor a(8) xor a(7) xor a(4) xor a(18)) & (a(8) xor a(7) xor a(6) xor a(3) xor a(17)) & (a(7) xor a(6) xor a(5) xor a(2) xor a(16)) & (a(6) xor a(5) xor a(4) xor a(1) xor a(15)) & (a(5) xor a(4) xor a(18) xor a(3) xor a(17)) & (a(4) xor a(18) xor a(3) xor a(17) xor a(2) xor a(16)) & (a(3) xor a(17) xor a(2) xor a(16) xor a(1) xor a(18) xor a(15)) & (a(2) xor a(16) xor a(1) xor a(18) xor a(15)) & (a(1) xor a(18) xor a(15)) );
end generate;
end generate;
GF_2_20 : if m = 20 generate -- x^20 + x^3 + 1
GF_2_20_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_20_P_1 : if final_value = 1 generate
o <= ( a(18 downto 3) & (a(2) xor a(19)) & a(1) & a(0) & a(19) );
end generate;
GF_2_20_P_2 : if final_value = 2 generate
o <= ( a(17 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & a(0) & a(19) & a(18) );
end generate;
GF_2_20_P_3 : if final_value = 3 generate
o <= ( a(16 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & a(19) & a(18) & a(17) );
end generate;
GF_2_20_P_4 : if final_value = 4 generate
o <= ( a(15 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & a(18) & a(17) & a(16) );
end generate;
GF_2_20_P_5 : if final_value = 5 generate
o <= ( a(14 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & a(17) & a(16) & a(15) );
end generate;
GF_2_20_P_6 : if final_value = 6 generate
o <= ( a(13 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & a(16) & a(15) & a(14) );
end generate;
GF_2_20_P_7 : if final_value = 7 generate
o <= ( a(12 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & a(15) & a(14) & a(13) );
end generate;
GF_2_20_P_8 : if final_value = 8 generate
o <= ( a(11 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & a(14) & a(13) & a(12) );
end generate;
GF_2_20_P_9 : if final_value = 9 generate
o <= ( a(10 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & a(13) & a(12) & a(11) );
end generate;
GF_2_20_P_10 : if final_value = 10 generate
o <= ( a(9 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & a(12) & a(11) & a(10) );
end generate;
GF_2_20_P_11 : if final_value = 11 generate
o <= ( a(8 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & a(11) & a(10) & a(9) );
end generate;
GF_2_20_P_12 : if final_value = 12 generate
o <= ( a(7 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & a(10) & a(9) & a(8) );
end generate;
GF_2_20_P_13 : if final_value = 13 generate
o <= ( a(6 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & a(9) & a(8) & a(7) );
end generate;
GF_2_20_P_14 : if final_value = 14 generate
o <= ( a(5 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & a(8) & a(7) & a(6) );
end generate;
GF_2_20_P_15 : if final_value = 15 generate
o <= ( a(4 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & a(7) & a(6) & a(5) );
end generate;
GF_2_20_P_16 : if final_value = 16 generate
o <= ( a(3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & a(6) & a(5) & a(4) );
end generate;
GF_2_20_P_17 : if final_value = 17 generate
o <= ( (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & a(5) & a(4) & a(3) );
end generate;
GF_2_20_P_18 : if final_value = 18 generate
o <= ( (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(19)) & a(4) & a(3) & (a(2) xor a(19)) );
end generate;
GF_2_20_P_19 : if final_value = 19 generate
o <= ( (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(19)) & (a(4) xor a(1) xor a(18)) & a(3) & (a(2) xor a(19)) & (a(1) xor a(18)) );
end generate;
end generate;
end IEEE_POLYNOMIALS;
|
bsd-2-clause
|
cd8b7b9032ebc259c7f2c11002a4d0b2
| 0.488068 | 1.901865 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
VHDL/LED/FIFO_LED_TRANS.vhd
| 1 | 7,747 |
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
-- ============================================================
-- File Name: FIFO_LED_TRANS.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY FIFO_LED_TRANS IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
END FIFO_LED_TRANS;
ARCHITECTURE SYN OF fifo_led_trans IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (10 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (10 DOWNTO 0);
COMPONENT dcfifo
GENERIC (
add_usedw_msb_bit : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0);
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdreq : IN STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(15 DOWNTO 0);
wrusedw <= sub_wire1(10 DOWNTO 0);
rdusedw <= sub_wire2(10 DOWNTO 0);
dcfifo_component : dcfifo
GENERIC MAP (
add_usedw_msb_bit => "ON",
intended_device_family => "Cyclone IV E",
lpm_numwords => 1024,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 16,
lpm_widthu => 11,
overflow_checking => "ON",
rdsync_delaypipe => 5,
read_aclr_synch => "OFF",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 5
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
q => sub_wire0,
wrusedw => sub_wire1,
rdusedw => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "1024"
-- Retrieval info: PRIVATE: Empty NUMERIC "0"
-- Retrieval info: PRIVATE: Full NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "16"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "1"
-- Retrieval info: PRIVATE: output_width NUMERIC "16"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_USEDW_MSB_BIT STRING "ON"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL "rdusedw[10..0]"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL "wrusedw[10..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-- Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
-- Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_LED_TRANS.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_LED_TRANS.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_LED_TRANS.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_LED_TRANS.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_LED_TRANS_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
490fce16bbb70833c0472ee4b16b772b
| 0.66813 | 3.494362 | false | false | false | false |
pwuertz/digitizer2fw
|
src/rtl/application.vhd
| 1 | 14,163 |
-------------------------------------------------------------------------------
-- Application logic
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.communication_pkg.all;
use work.sampling_pkg.all;
use work.tdc_sample_prep_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity application is
port (
clk_main: in std_logic;
clk_samples: in std_logic;
LED1: out std_logic;
LED2: out std_logic;
device_temp: in std_logic_vector(11 downto 0);
-- usb communication
comm_addr: in unsigned(5 downto 0);
comm_port: in unsigned(5 downto 0);
comm_to_slave: in comm_to_slave_t;
comm_from_slave: out comm_from_slave_t;
comm_error: in std_logic;
-- ram interface
ram_calib_complete : in std_logic;
ram_rdy : in std_logic;
ram_addr : out std_logic_vector(27 downto 0);
ram_cmd : out std_logic_vector(2 downto 0);
ram_en : out std_logic;
ram_rd_data : in std_logic_vector(127 downto 0);
ram_rd_data_valid : in std_logic;
ram_wdf_rdy : in std_logic;
ram_wdf_data : out std_logic_vector(127 downto 0);
ram_wdf_wren : out std_logic;
ram_wdf_end : out std_logic;
-- analog pwr/enable/rst
APWR_EN: out std_logic;
ADC_ENABLE: out std_logic;
ADC_SRESETB: out std_logic;
-- adc program
adc_prog_start: out std_logic;
adc_prog_rd: out std_logic;
adc_prog_busy: in std_logic;
adc_prog_addr: out std_logic_vector(6 downto 0);
adc_prog_din: out std_logic_vector(15 downto 0);
adc_prog_dout: in std_logic_vector(15 downto 0);
-- analog/digital samples
sampling_rst: out std_logic;
samples_d: in din_samples_t(0 to 3);
samples_a: in adc_samples_t(0 to 1)
);
end application;
architecture application_arch of application is
-- clock domain crossing
component slow_cdc_bit
port (clk: in std_logic; din: in std_logic; dout: out std_logic);
end component;
component slow_cdc_bits
port (clk: in std_logic; din: in std_logic_vector; dout: out std_logic_vector);
end component;
component acquisition is
generic ( TDC_CNT_BITS: natural := 22 );
port (
-- acquisition domain
clk_samples: in std_logic;
samples_d_in: in din_samples_t(0 to 3);
samples_a_in: in adc_samples_t(0 to 1);
a_threshold: in a_sample_t;
a_invert: in std_logic;
a_average: in std_logic_vector(1 downto 0);
acq_mode: in std_logic_vector(1 downto 0);
acq_start_src: in std_logic_vector(2 downto 0);
acq_stop_src: in std_logic_vector(2 downto 0);
acq_reset: in std_logic;
acq_stop: in std_logic;
acq_state: out std_logic_vector(2 downto 0);
-- application domain
clk_rd: in std_logic;
rd_en: in std_logic;
rd_empty: out std_logic;
rd_data: out std_logic_vector(15 downto 0);
rd_2xcnt: out std_logic_vector(15 downto 0)
);
end component;
signal acq_buffer_dout: std_logic_vector(15 downto 0);
signal acq_buffer_2xcnt: std_logic_vector(15 downto 0);
signal acq_buffer_empty: std_logic;
signal acq_buffer_rd: std_logic;
signal a_threshold_in_main, a_threshold_in_acq : std_logic_vector(11 downto 0);
signal a_invert : std_logic;
signal a_average : std_logic_vector(1 downto 0);
signal acq_mode : std_logic_vector(1 downto 0) := (others => '0');
signal acq_start_src : std_logic_vector(2 downto 0) := (others => '0');
signal acq_stop_src : std_logic_vector(2 downto 0) := (others => '0');
signal acq_reset : std_logic := '0';
signal acq_stop : std_logic := '0';
signal acq_state_in_acq, acq_state_in_main : std_logic_vector(2 downto 0) := (others => '0');
-- communication signals/registers
signal comm_to_global, comm_to_ram, comm_to_adcprog, comm_to_acqbuf: comm_to_slave_t;
signal comm_from_global, comm_from_ram, comm_from_adcprog, comm_from_acqbuf: comm_from_slave_t;
-- global registers
signal usr_access_data: std_logic_vector(31 downto 0);
signal global_status: std_logic_vector(2 downto 0);
signal global_conf, global_conf_in_acq: std_logic_vector(15 downto 0) := (others => '0');
signal acq_conf_in_main, acq_conf_in_acq: std_logic_vector(15 downto 0) := (others => '0');
begin
LED1 <= '0';
LED2 <= '0';
-- read user logic version
USR_ACCESSE2_inst : USR_ACCESSE2
port map (
CFGCLK => open,
DATA => usr_access_data,
DATAVALID => open
);
-- communication slave select
slave_select: process(comm_addr, comm_to_slave, comm_from_global, comm_from_ram, comm_from_adcprog, comm_from_acqbuf)
constant not_selected: comm_to_slave_t := (rd_req => '0', wr_req => '0', data_wr => (others => '-'));
constant invalid_slave: comm_from_slave_t := (rd_ack => '1', wr_ack => '1', data_rd => (others => '1'));
begin
-- no read/write requests to unselected slaves
comm_to_global <= not_selected;
comm_to_ram <= not_selected;
comm_to_adcprog <= not_selected;
comm_to_acqbuf <= not_selected;
-- don't stall when reading from invalid slave address, no error reporting
comm_from_slave <= invalid_slave;
-- select communication slave based on comm_addr
case to_integer(comm_addr) is
when 0 =>
comm_to_global <= comm_to_slave;
comm_from_slave <= comm_from_global;
when 2 =>
comm_to_ram <= comm_to_slave;
comm_from_slave <= comm_from_ram;
when 3 =>
comm_to_adcprog <= comm_to_slave;
comm_from_slave <= comm_from_adcprog;
when 4 =>
comm_to_acqbuf <= comm_to_slave;
comm_from_slave <= comm_from_acqbuf;
when others =>
null;
end case;
end process;
-- read global registers
process(comm_port, global_conf, global_status, acq_conf_in_main, device_temp)
begin
comm_from_global <= (rd_ack => '1', wr_ack => '1', data_rd => (others => '0'));
case to_integer(comm_port) is
when 0 =>
-- read global configuration register
comm_from_global.data_rd(global_conf'range) <= global_conf;
when 1 =>
-- read global status register
comm_from_global.data_rd(global_status'range) <= global_status;
when 3 =>
-- read version (upper)
comm_from_global.data_rd <= usr_access_data(31 downto 16);
when 4 =>
-- read version (lower)
comm_from_global.data_rd <= usr_access_data(15 downto 0);
when 5 =>
-- read acquisition configuration register
comm_from_global.data_rd(acq_conf_in_main'range) <= acq_conf_in_main;
when 6 =>
-- read device temperature
comm_from_global.data_rd(device_temp'range) <= device_temp;
when others =>
null;
end case;
end process;
-- write global registers
global_registers: process(clk_main)
begin
if rising_edge(clk_main) then
-- update status registers
global_status <= acq_state_in_main; -- TODO: more to follow
-- write register 0 (global_conf)
if comm_to_global.wr_req = '1' and to_integer(comm_port) = 0 then
global_conf <= comm_to_global.data_wr(global_conf'range);
end if;
-- write register 4 (threshold)
if comm_to_global.wr_req = '1' and to_integer(comm_port) = 4 then
a_threshold_in_main <= comm_to_global.data_wr(a_threshold_in_main'range);
end if;
-- write register 5 (acquisition conf)
if comm_to_global.wr_req = '1' and to_integer(comm_port) = 5 then
acq_conf_in_main <= comm_to_global.data_wr(acq_conf_in_main'range);
end if;
end if;
end process;
-- application-acquisition domain crossing
sync_global_conf: slow_cdc_bits
port map (
clk => clk_samples,
din => global_conf,
dout => global_conf_in_acq
);
sync_acq_conf: slow_cdc_bits
port map (
clk => clk_samples,
din => acq_conf_in_main,
dout => acq_conf_in_acq
);
sync_a_threshold: slow_cdc_bits
port map (
clk => clk_samples,
din => a_threshold_in_main,
dout => a_threshold_in_acq
);
sync_acq_state: slow_cdc_bits
port map (
clk => clk_main,
din => acq_state_in_acq,
dout => acq_state_in_main
);
-- global conf mapping
APWR_EN <= global_conf(1);
ADC_SRESETB <= not global_conf(2);
ADC_ENABLE <= global_conf(3);
sampling_rst <= global_conf_in_acq(4);
a_average <= global_conf_in_acq(14 downto 13);
a_invert <= global_conf_in_acq(15);
-- acquisition conf mapping
acq_reset <= acq_conf_in_acq(0);
acq_stop <= acq_conf_in_acq(1);
acq_mode <= acq_conf_in_acq(3 downto 2);
acq_start_src <= acq_conf_in_acq(6 downto 4);
acq_stop_src <= acq_conf_in_acq(9 downto 7);
-- ram comm slave
process(clk_main)
constant RAM_CMD_WR: std_logic_vector(2 downto 0) := "000";
constant RAM_CMD_RD: std_logic_vector(2 downto 0) := "001";
variable n: integer;
variable ram_rd_data_last: std_logic_vector(ram_rd_data'range) := (others => '0');
variable ram_addr_reg: std_logic_vector(ram_addr'range) := (others => '0');
begin
if rising_edge(clk_main) then
-- default, no ram activity, no comm answer
comm_from_ram <= (rd_ack => '0', wr_ack => '0', data_rd => (others => '-'));
ram_en <= '0';
ram_addr <= ram_addr_reg;
ram_wdf_wren <= '0';
ram_wdf_end <= '0';
n := to_integer(comm_port);
if (n < 8) then
-- write to ram_wr buffer or read from last ram word
if comm_to_ram.wr_req = '1' then
-- write word to ram write buffer
ram_wdf_data(((n+1)*16-1) downto (n*16)) <= comm_to_ram.data_wr;
comm_from_ram.wr_ack <= '1';
elsif comm_to_ram.rd_req = '1' then
-- read word from ram read buffer
comm_from_ram.data_rd <= ram_rd_data_last(((n+1)*16-1) downto (n*16));
comm_from_ram.rd_ack <= '1';
end if;
elsif (n = 8) then
if comm_to_ram.wr_req = '1' then
-- write low address bits
ram_addr_reg(15 downto 0) := comm_to_ram.data_wr;
comm_from_ram.wr_ack <= '1';
end if;
elsif (n = 9) then
if comm_to_ram.wr_req = '1' then
-- write high address bits
ram_addr_reg(27 downto 16) := comm_to_ram.data_wr(11 downto 0);
comm_from_ram.wr_ack <= '1';
end if;
else
-- send read or write command to ram
if comm_to_ram.wr_req = '1' then
comm_from_ram.wr_ack <= '1';
if comm_to_ram.data_wr(0) = '0' then
-- ram write command
ram_wdf_wren <= '1';
ram_wdf_end <= '1';
ram_cmd <= RAM_CMD_WR;
ram_en <= '1';
else
-- ram read command
ram_cmd <= RAM_CMD_RD;
ram_en <= '1';
end if;
end if;
end if;
-- store last word from ram
if (ram_rd_data_valid = '1') then
ram_rd_data_last := ram_rd_data;
end if;
end if;
end process;
-- adc programming requests
adc_program_reg: process(clk_main)
variable read_cmd: std_logic;
begin
if rising_edge(clk_main) then
adc_prog_start <= '0';
-- write address for adc programming request
-- start adc read operation if address read bit is set
if to_integer(comm_port) = 0 and comm_to_adcprog.wr_req = '1' then
adc_prog_addr <= comm_to_adcprog.data_wr(adc_prog_addr'range);
read_cmd := comm_to_adcprog.data_wr(7);
adc_prog_rd <= read_cmd;
if read_cmd = '1' then
adc_prog_start <= '1';
end if;
end if;
-- write data for adc programming request
-- start adc write operation
if to_integer(comm_port) = 1 and comm_to_adcprog.wr_req = '1' then
adc_prog_din <= comm_to_adcprog.data_wr(adc_prog_din'range);
adc_prog_start <= '1';
end if;
end if;
end process;
comm_from_adcprog.wr_ack <= not adc_prog_busy;
comm_from_adcprog.rd_ack <= '1';
comm_from_adcprog.data_rd <= adc_prog_dout;
-- read acquisition buffer
adc_buffer_read: process(comm_port, comm_to_acqbuf, acq_buffer_empty, acq_buffer_dout, acq_buffer_2xcnt)
begin
comm_from_acqbuf <= (rd_ack => '1', wr_ack => '1', data_rd => (others => '0'));
acq_buffer_rd <= '0';
case to_integer(comm_port) is
when 0 =>
-- read fifo size
comm_from_acqbuf.data_rd(acq_buffer_2xcnt'range) <= acq_buffer_2xcnt;
when 1 =>
-- read fifo data word
acq_buffer_rd <= comm_to_acqbuf.rd_req;
comm_from_acqbuf.rd_ack <= not acq_buffer_empty;
comm_from_acqbuf.data_rd(acq_buffer_dout'range) <= acq_buffer_dout;
when others =>
null;
end case;
end process;
acquisition_inst: acquisition
port map(
-- acquisition domain
clk_samples => clk_samples,
samples_d_in => samples_d,
samples_a_in => samples_a,
a_threshold => signed(a_threshold_in_acq),
a_invert => a_invert,
a_average => a_average,
acq_mode => acq_mode,
acq_start_src => acq_start_src,
acq_stop_src => acq_stop_src,
acq_reset => acq_reset,
acq_stop => acq_stop,
acq_state => acq_state_in_acq,
-- application domain
clk_rd => clk_main,
rd_en => acq_buffer_rd,
rd_empty => acq_buffer_empty,
rd_data => acq_buffer_dout,
rd_2xcnt => acq_buffer_2xcnt
);
end application_arch;
|
gpl-3.0
|
01d7399ca7d03278176fdda13037d408
| 0.576331 | 3.329102 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/number_swapper/number_swapper_tb.vhd
| 1 | 3,865 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity number_swapper_tb is
end entity;
architecture number_swapper_tb_arq of number_swapper_tb is
signal man_1_in : std_logic_vector(15 downto 0) := (others => '0');
signal exp_1_in : std_logic_vector(5 downto 0) := (others => '0');
signal man_2_in : std_logic_vector(15 downto 0) := (others => '0');
signal exp_2_in : std_logic_vector(5 downto 0) := (others => '0');
signal man_greater_out : std_logic_vector(15 downto 0) := (others => '0');
signal man_smaller_out : std_logic_vector(15 downto 0) := (others => '0');
signal exp_greater_out : std_logic_vector(5 downto 0) := (others => '0');
signal exp_smaller_out : std_logic_vector(5 downto 0) := (others => '0');
component number_swapper is
generic(
TOTAL_BITS : natural := 23;
EXP_BITS : natural := 6
);
port(
man_1_in : in std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_1_in : in std_logic_vector(EXP_BITS - 1 downto 0);
man_2_in : in std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_2_in : in std_logic_vector(EXP_BITS - 1 downto 0);
man_greater_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
man_smaller_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_greater_out : out std_logic_vector(EXP_BITS - 1 downto 0);
exp_smaller_out : out std_logic_vector(EXP_BITS - 1 downto 0)
);
end component;
for number_swapper_0 : number_swapper use entity work.number_swapper;
begin
number_swapper_0 : number_swapper
generic map(TOTAL_BITS => 23, EXP_BITS => 6)
port map(
exp_1_in => exp_1_in,
exp_2_in => exp_2_in,
man_1_in => man_1_in,
man_2_in => man_2_in,
exp_greater_out => exp_greater_out,
exp_smaller_out => exp_smaller_out,
man_greater_out => man_greater_out,
man_smaller_out => man_smaller_out
);
process
type pattern_type is record
m1 : std_logic_vector(15 downto 0);
e1 : std_logic_vector(5 downto 0);
m2 : std_logic_vector(15 downto 0);
e2 : std_logic_vector(5 downto 0);
mg : std_logic_vector(15 downto 0);
ms : std_logic_vector(15 downto 0);
eg : std_logic_vector(5 downto 0);
es : std_logic_vector(5 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("0000000000000001", "000000", "0000000000000001", "000000", "0000000000000001", "0000000000000001", "000000","000000"),
("0000000000000001", "000100", "0000000000000001", "000000", "0000000000000001", "0000000000000001", "000100","000000"),
("0000000110000000", "000011", "0000000000000001", "000001", "0000000110000000", "0000000000000001", "000011","000001"),
("0000000000000001", "000001", "0000000011000000", "000011", "0000000011000000", "0000000000000001", "000011","000001"),
("1111111111111111", "111110", "0000000000000000", "111111", "0000000000000000", "1111111111111111", "111111","111110")
);
begin
for i in patterns'range loop
-- Set the inputs.
exp_1_in <= patterns(i).e1;
exp_2_in <= patterns(i).e2;
man_1_in <= patterns(i).m1;
man_2_in <= patterns(i).m2;
wait for 1 ns;
assert patterns(i).mg = man_greater_out report "BAD MANTISSA G, GOT: " & integer'image(to_integer(unsigned(man_greater_out)));
assert patterns(i).ms = man_smaller_out report "BAD MANTISSA S, GOT: " & integer'image(to_integer(unsigned(man_smaller_out)));
assert patterns(i).eg = exp_greater_out report "BAD EXP G, GOT: " & integer'image(to_integer(unsigned(exp_greater_out)));
assert patterns(i).es = exp_smaller_out report "BAD EXP S, GOT: " & integer'image(to_integer(unsigned(exp_smaller_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
571c9202f330cfaf1a3b665f4782850b
| 0.65718 | 2.979954 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/number_swapper/number_swapper.vhd
| 1 | 2,167 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--STEP 1
--This component takes 2 numbers written in scientific notation and returns the same 2 numbers specifying which has the biggest
--exponent and which has the smaller
entity number_swapper is
generic(
TOTAL_BITS : natural := 23;
EXP_BITS : natural := 6
);
port(
man_1_in : in std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_1_in : in std_logic_vector(EXP_BITS - 1 downto 0);
man_2_in : in std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_2_in : in std_logic_vector(EXP_BITS - 1 downto 0);
man_greater_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
man_smaller_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_greater_out : out std_logic_vector(EXP_BITS - 1 downto 0);
exp_smaller_out : out std_logic_vector(EXP_BITS - 1 downto 0)
);
end number_swapper;
architecture number_swapper_arq of number_swapper is
begin
process(man_1_in,exp_1_in,man_2_in,exp_2_in) is
variable man_1_integer : integer := 0;
variable man_2_integer : integer := 0;
variable exp_1_integer : integer := 0;
variable exp_2_integer : integer := 0;
begin
man_1_integer := to_integer(unsigned(man_1_in));
man_2_integer := to_integer(unsigned(man_2_in));
exp_1_integer := to_integer(unsigned(exp_1_in));
exp_2_integer := to_integer(unsigned(exp_2_in));
if(exp_1_integer = exp_2_integer) then --compare mantissas
if(man_1_integer > man_2_integer) then
man_greater_out <= man_1_in;
man_smaller_out <= man_2_in;
exp_greater_out <= exp_1_in;
exp_smaller_out <= exp_2_in;
else
man_greater_out <= man_2_in;
man_smaller_out <= man_1_in;
exp_greater_out <= exp_2_in;
exp_smaller_out <= exp_1_in;
end if;
else
if(exp_1_integer > exp_2_integer) then
man_greater_out <= man_1_in;
man_smaller_out <= man_2_in;
exp_greater_out <= exp_1_in;
exp_smaller_out <= exp_2_in;
else
man_greater_out <= man_2_in;
man_smaller_out <= man_1_in;
exp_greater_out <= exp_2_in;
exp_smaller_out <= exp_1_in;
end if;
end if;
end process;
end;
|
gpl-3.0
|
9f81600db4ef73a3697b81c8836dd21e
| 0.652515 | 2.658896 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/finite_field/pow2_gf_2_m.vhd
| 1 | 7,549 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Pow2_GF_2_M
-- Module Name: Pow2_GF_2_M
-- Project Name: GF_2_M Arithmetic
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit computes the power of 2 of a GF(2^m) element.
-- The strategy for this computation is pure combinatorial.
-- This version is for primitive polynomials present on IEEE 13009 cryptographic standard.
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit.
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pow2_gf_2_m is
Generic(gf_2_m : integer range 1 to 20);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end pow2_gf_2_m;
architecture IEEE_POLYNOMIAL of pow2_gf_2_m is
begin
GF_2_1 : if gf_2_m = 1 generate
o <= a;
end generate;
GF_2_2 : if gf_2_m = 2 generate -- x^2 + x^1 + 1
o(0) <= a(1) xor a(0);
o(1) <= a(1);
end generate;
GF_2_3 : if gf_2_m = 3 generate -- x^3 + x^1 + 1
o(0) <= a(0);
o(1) <= a(2);
o(2) <= a(1) xor a(2);
end generate;
GF_2_4 : if gf_2_m = 4 generate -- x^4 + x^1 + 1
o(0) <= a(0) xor a(2);
o(1) <= a(2);
o(2) <= a(1) xor a(3);
o(3) <= a(3);
end generate;
GF_2_5 : if gf_2_m = 5 generate -- x^5 + x^2 + 1
o(0) <= a(0) xor a(4);
o(1) <= a(3);
o(2) <= a(1) xor a(4);
o(3) <= a(4) xor a(3);
o(4) <= a(2);
end generate;
GF_2_6 : if gf_2_m = 6 generate -- x^6 + x^1 + 1
o(0) <= a(0) xor a(3);
o(1) <= a(3);
o(2) <= a(1) xor a(4);
o(3) <= a(4);
o(4) <= a(2) xor a(5);
o(5) <= a(5);
end generate;
GF_2_7 : if gf_2_m = 7 generate -- x^7 + x^1 + 1
o(0) <= a(0);
o(1) <= a(4);
o(2) <= a(1) xor a(4);
o(3) <= a(5);
o(4) <= a(2) xor a(5);
o(5) <= a(6);
o(6) <= a(3) xor a(6);
end generate;
GF_2_8 : if gf_2_m = 8 generate -- x^8 + x^4 + x^3 + x^1 + 1
o(0) <= a(0) xor a(4) xor a(6);
o(1) <= a(4) xor a(6) xor a(7);
o(2) <= a(1) xor a(5);
o(3) <= a(5) xor a(4) xor a(6) xor a(7);
o(4) <= a(2) xor a(4) xor a(7);
o(5) <= a(6) xor a(5);
o(6) <= a(3) xor a(5);
o(7) <= a(7) xor a(6);
end generate;
GF_2_9 : if gf_2_m = 9 generate -- x^9 + x^1 + 1
o(0) <= a(0);
o(1) <= a(5);
o(2) <= a(1) xor a(5);
o(3) <= a(6);
o(4) <= a(2) xor a(6);
o(5) <= a(7);
o(6) <= a(3) xor a(7);
o(7) <= a(8);
o(8) <= a(4) xor a(8);
end generate;
GF_2_10 : if gf_2_m = 10 generate -- x^10 + x^3 + 1
o(0) <= a(0) xor a(5);
o(1) <= a(9);
o(2) <= a(1) xor a(6);
o(3) <= a(5);
o(4) <= a(2) xor a(7) xor a(9);
o(5) <= a(6);
o(6) <= a(3) xor a(8);
o(7) <= a(7);
o(8) <= a(4) xor a(9);
o(9) <= a(8);
end generate;
GF_2_11 : if gf_2_m = 11 generate -- x^11 + x^2 + 1
o(0) <= a(0) xor a(10);
o(1) <= a(6);
o(2) <= a(1) xor a(10);
o(3) <= a(7) xor a(6);
o(4) <= a(2);
o(5) <= a(8) xor a(7);
o(6) <= a(3);
o(7) <= a(9) xor a(8);
o(8) <= a(4);
o(9) <= a(10) xor a(9);
o(10) <= a(5);
end generate;
GF_2_12 : if gf_2_m = 12 generate -- x^12 + x^3 + 1
o(0) <= a(0) xor a(6);
o(1) <= a(11);
o(2) <= a(1) xor a(7);
o(3) <= a(6);
o(4) <= a(2) xor a(8) xor a(11);
o(5) <= a(7);
o(6) <= a(3) xor a(9);
o(7) <= a(8);
o(8) <= a(4) xor a(10);
o(9) <= a(9);
o(10) <= a(5) xor a(11);
o(11) <= a(10);
end generate;
GF_2_13 : if gf_2_m = 13 generate -- x^13 + x^4 + x^3 + x^1 + 1
o(0) <= a(0) xor a(11);
o(1) <= a(7) xor a(11) xor a(12);
o(2) <= a(1) xor a(7);
o(3) <= a(8) xor a(11) xor a(12);
o(4) <= a(2) xor a(7) xor a(8) xor a(11) xor a(12);
o(5) <= a(7) xor a(9);
o(6) <= a(3) xor a(8) xor a(9) xor a(12);
o(7) <= a(8) xor a(10);
o(8) <= a(4) xor a(9) xor a(10);
o(9) <= a(11) xor a(9);
o(10) <= a(5) xor a(10) xor a(11);
o(11) <= a(10) xor a(12);
o(12) <= a(6) xor a(11) xor a(12);
end generate;
GF_2_14 : if gf_2_m = 14 generate -- x^14 + x^5 + 1
o(0) <= a(0) xor a(7);
o(1) <= a(12);
o(2) <= a(1) xor a(8);
o(3) <= a(13);
o(4) <= a(2) xor a(9);
o(5) <= a(7);
o(6) <= a(3) xor a(10) xor a(12);
o(7) <= a(8);
o(8) <= a(4) xor a(11) xor a(13);
o(9) <= a(9);
o(10) <= a(5) xor a(12);
o(11) <= a(10);
o(12) <= a(6) xor a(13);
o(13) <= a(11);
end generate;
GF_2_15 : if gf_2_m = 15 generate -- x^15 + x^1 + 1
o(0) <= a(0);
o(1) <= a(8);
o(2) <= a(1) xor a(8);
o(3) <= a(9);
o(4) <= a(2) xor a(9);
o(5) <= a(10);
o(6) <= a(3) xor a(10);
o(7) <= a(11);
o(8) <= a(4) xor a(11);
o(9) <= a(12);
o(10) <= a(5) xor a(12);
o(11) <= a(13);
o(12) <= a(6) xor a(13);
o(13) <= a(14);
o(14) <= a(7) xor a(14);
end generate;
GF_2_16 : if gf_2_m = 16 generate -- x^16 + x^5 + x^3 + x^1 + 1
o(0) <= a(0) xor a(8);
o(1) <= a(8) xor a(14) xor a(15);
o(2) <= a(1) xor a(9) xor a(14) xor a(15);
o(3) <= a(8) xor a(9) xor a(15);
o(4) <= a(2) xor a(10) xor a(14);
o(5) <= a(8) xor a(9) xor a(10);
o(6) <= a(3) xor a(11) xor a(14);
o(7) <= a(9) xor a(10) xor a(11);
o(8) <= a(4) xor a(12) xor a(15);
o(9) <= a(10) xor a(11) xor a(12);
o(10) <= a(5) xor a(13);
o(11) <= a(11) xor a(12) xor a(13);
o(12) <= a(6) xor a(14);
o(13) <= a(12) xor a(13) xor a(14);
o(14) <= a(7) xor a(15);
o(15) <= a(13) xor a(14) xor a(15);
end generate;
GF_2_17 : if gf_2_m = 17 generate -- x^17 + x^3 + 1
o(0) <= a(0);
o(1) <= a(9) xor a(16);
o(2) <= a(1);
o(3) <= a(10);
o(4) <= a(2) xor a(9) xor a(16);
o(5) <= a(11);
o(6) <= a(3) xor a(10);
o(7) <= a(12);
o(8) <= a(4) xor a(11);
o(9) <= a(13);
o(10) <= a(5) xor a(12);
o(11) <= a(14);
o(12) <= a(6) xor a(13);
o(13) <= a(15);
o(14) <= a(7) xor a(14);
o(15) <= a(16);
o(16) <= a(8) xor a(15);
end generate;
GF_2_18 : if gf_2_m = 18 generate -- x^18 + x^3 + 1
o(0) <= a(0) xor a(9);
o(1) <= a(17);
o(2) <= a(1) xor a(10);
o(3) <= a(9);
o(4) <= a(2) xor a(11) xor a(17);
o(5) <= a(10);
o(6) <= a(3) xor a(12);
o(7) <= a(11);
o(8) <= a(4) xor a(13);
o(9) <= a(12);
o(10) <= a(5) xor a(14);
o(11) <= a(13);
o(12) <= a(6) xor a(15);
o(13) <= a(14);
o(14) <= a(7) xor a(16);
o(15) <= a(15);
o(16) <= a(8) xor a(17);
o(17) <= a(16);
end generate;
GF_2_19 : if gf_2_m = 19 generate -- x^19 + x^5 + x^2 + x^1 + 1
o(0) <= a(0) xor a(18);
o(1) <= a(10) xor a(17) xor a(18);
o(2) <= a(1) xor a(10) xor a(17) xor a(18);
o(3) <= a(10) xor a(11) xor a(17) xor a(18);
o(4) <= a(2) xor a(11) xor a(18);
o(5) <= a(11) xor a(12);
o(6) <= a(3) xor a(10) xor a(12) xor a(17);
o(7) <= a(12) xor a(13);
o(8) <= a(4) xor a(11) xor a(13) xor a(18);
o(9) <= a(13) xor a(14);
o(10) <= a(5) xor a(12) xor a(14);
o(11) <= a(14) xor a(15);
o(12) <= a(6) xor a(13) xor a(15);
o(13) <= a(15) xor a(16);
o(14) <= a(7) xor a(14) xor a(16);
o(15) <= a(16) xor a(17);
o(16) <= a(8) xor a(15) xor a(17);
o(17) <= a(17) xor a(18);
o(18) <= a(9) xor a(16) xor a(18);
end generate;
GF_2_20 : if gf_2_m = 20 generate -- x^20 + x^3 + 1
o(0) <= a(0) xor a(10);
o(1) <= a(19);
o(2) <= a(1) xor a(11);
o(3) <= a(10);
o(4) <= a(2) xor a(12) xor a(19);
o(5) <= a(11);
o(6) <= a(3) xor a(13);
o(7) <= a(12);
o(8) <= a(4) xor a(14);
o(9) <= a(13);
o(10) <= a(5) xor a(15);
o(11) <= a(14);
o(12) <= a(6) xor a(16);
o(13) <= a(15);
o(14) <= a(7) xor a(17);
o(15) <= a(16);
o(16) <= a(8) xor a(18);
o(17) <= a(17);
o(18) <= a(9) xor a(19);
o(19) <= a(18);
end generate;
end IEEE_POLYNOMIAL;
|
bsd-2-clause
|
8bc29bf5763e7f204ea932de6cea8e90
| 0.452378 | 1.795671 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/TP1-Contador/led_display_controller_tb.vhd
| 1 | 1,294 |
library ieee;
use ieee.std_logic_1164.all;
entity led_display_controller_tb is
end;
architecture led_display_controller_tb_func of led_display_controller_tb is
signal bcd0_in : std_logic_vector(3 downto 0);
signal bcd1_in : std_logic_vector(3 downto 0);
signal bcd2_in : std_logic_vector(3 downto 0);
signal bcd3_in : std_logic_vector(3 downto 0);
signal anode_out: std_logic_vector(3 downto 0);
signal led_out : std_logic_vector(7 downto 0);
signal clk_in: std_logic:='0';
component led_display_controller is
port (
clk_in: in std_logic;
bcd0: in std_logic_vector(3 downto 0);
bcd1: in std_logic_vector(3 downto 0);
bcd2: in std_logic_vector(3 downto 0);
bcd3: in std_logic_vector(3 downto 0);
anode_output: out std_logic_vector(3 downto 0);
led_output : out std_logic_vector(7 downto 0)
);
end component;
begin
clk_in <= not(clk_in) after 1 ns;
bcd0_in <= b"1001";
bcd1_in <= b"0110";
bcd2_in <= b"0101";
bcd3_in <= b"1010";
led_display_controllerMap: led_display_controller
port map(
clk_in => clk_in,
bcd0 => bcd0_in,
bcd1 => bcd1_in,
bcd2 => bcd2_in,
bcd3 => bcd3_in,
anode_output => anode_out,
led_output => led_out
);
end architecture;
|
gpl-3.0
|
9a4c1d20444f7aa7cd2ae599440cd483
| 0.632921 | 2.770878 | false | false | false | false |
KenKeeley/My68k-system
|
CircuitBoards/MainBoard/DRAMControllerCPLD/DRAM.vhd
| 1 | 6,570 |
----------------------------------------------------------------------------------------------------
--
-- FileName: DRAM.vhd
-- Description: MainBoard DRAM Controller CPLD Top Level.
--
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY DRAMController IS
PORT
(
Clk : IN STD_LOGIC; -- Clock
nReset : IN STD_LOGIC; -- Reset
Address : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- Address Bus
nAS : IN STD_LOGIC; -- CPU Address signal
nSIZ0 : IN STD_LOGIC; -- CPU SIZ 0 signal
nSIZ1 : IN STD_LOGIC; -- CPU SIZ 1 signal
Func : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- CPU Function Signals
nWR : IN STD_LOGIC; -- CPU Read/Write signal
nCS_ROM : IN STD_LOGIC; -- ROM Chip Select
nDSACK0_OUT : OUT STD_LOGIC; -- CPU DSACK 0 signal
nDSACK1_OUT : OUT STD_LOGIC; -- CPU DSACK 1 signal
MA : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); -- Multiplexed Address Bus
nRAS_DRAM : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- Row Address Select
nCAS_DRAM : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- Column Address Select
nWE_DRAM : OUT STD_LOGIC -- DRAM Read/Write signal
);
END DRAMController;
ARCHITECTURE Behavioral OF DRAMController IS
-- Component Declaration for the State Machine
COMPONENT StateMachine
PORT (
Clk : IN STD_LOGIC; -- Clock
nReset : IN STD_LOGIC; -- Reset
nWR : IN STD_LOGIC; -- CPU Read/Write signal
nCS_DRAM : IN STD_LOGIC; -- DRAM Chip Select
nPage_Hit : IN STD_LOGIC; -- Request is in Same Page
nBank : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- DRAM Bank to Address
nByte : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- Byte/s Selected
nPreCharge : OUT STD_LOGIC; -- Flag to show when in PreCharge
nDSACK0 : OUT STD_LOGIC; -- Data size/ack signal 0 to CPU
nDSACK1 : OUT STD_LOGIC; -- Data size/ack signal 1 to CPU
nRAS : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- Row Address Select
nCAS : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- Column Address Select
nWE_DRAM : OUT STD_LOGIC -- DRAM Read/Write signal
);
END COMPONENT;
-- Component Declaration for the Decoder
COMPONENT Decoder
PORT (
nReset : IN STD_LOGIC; -- Reset
nAS : IN STD_LOGIC; -- CPU Address signal
nSIZ0 : IN STD_LOGIC; -- CPU SIZ 0 signal
nSIZ1 : IN STD_LOGIC; -- CPU SIZ 1 signal
nPreCharge : IN STD_LOGIC; -- Flag to show when in PreCharge
Func : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- CPU Function Signals
Address : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- Address Bus
nCS_ROM : IN STD_LOGIC; -- ROM Chip Select
nBank : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- DRAM Bank to Address
nByte : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- Byte/s Selected
nCS_DRAM : OUT STD_LOGIC; -- DRAM Chip Select
nPage_Hit : OUT STD_LOGIC -- Request is in Same Page
);
END COMPONENT;
-- Component Declaration for the Multiplexer
COMPONENT Multiplexer
PORT (
Address : IN STD_LOGIC_VECTOR (23 DOWNTO 0); -- Address Bus
nRAS : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- Row Address Select
MA : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) -- Multiplexed Address Bus
);
END COMPONENT;
-- Define internal signals.
SIGNAL nCS_DRAM : STD_LOGIC;
SIGNAL nPage_Hit : STD_LOGIC;
SIGNAL nPreCharge : STD_LOGIC;
SIGNAL nBank : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL nByte : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL nRAS : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL nDSACK0 : STD_LOGIC;
SIGNAL nDSACK1 : STD_LOGIC;
BEGIN
-- Instantiate the State Machine
State_Machine : StateMachine PORT MAP (
Clk => Clk,
nReset => nReset,
nWR => nWR,
nCS_DRAM => nCS_DRAM,
nPage_Hit => nPage_Hit,
nBank => nBank,
nByte => nByte,
nPreCharge => nPreCharge,
nDSACK0 => nDSACK0,
nDSACK1 => nDSACK1,
nRAS => nRAS,
nCAS => nCAS_DRAM,
nWE_DRAM => nWE_DRAM
);
-- Instantiate the Decoder
Address_Decoder : Decoder PORT MAP (
nReset => nReset,
nAS => nAS,
nSIZ0 => nSIZ0,
nSIZ1 => nSIZ1,
nPreCharge => nPreCharge,
Func => Func,
Address => Address,
nCS_ROM => nCS_ROM,
nBank => nBank,
nByte => nByte,
nCS_DRAM => nCS_DRAM,
nPage_Hit => nPage_Hit
);
-- Instantiate the Multiplexer
Address_Multiplexer : Multiplexer PORT MAP (
Address(23 DOWNTO 0) => Address(25 DOWNTO 2),
nRAS => nRAS,
MA => MA
);
-- Connect signals that also tie to external ports to those ports
nRAS_DRAM <= nRAS;
nDSACK0_OUT <= '0' WHEN nDSACK0 = '0' ELSE 'Z';
nDSACK1_OUT <= '0' WHEN nDSACK1 = '0' ELSE 'Z';
END Behavioral;
|
gpl-3.0
|
3ea5abca52088928b1945a1eddd0a7fa
| 0.434399 | 5.298387 | false | false | false | false |
ruygargar/LCSE_lab
|
doc/PIC/tb_PICtop.vhd
| 1 | 2,025 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
entity PICtop_tb is
end PICtop_tb;
architecture TestBench of PICtop_tb is
component PICtop
port (
Reset : in std_logic;
Clk : in std_logic;
RS232_RX : in std_logic;
RS232_TX : out std_logic;
switches : out std_logic_vector(7 downto 0);
Temp_L : out std_logic_vector(6 downto 0);
Temp_H : out std_logic_vector(6 downto 0));
end component;
-----------------------------------------------------------------------------
-- Internal signals
-----------------------------------------------------------------------------
signal Reset : std_logic;
signal Clk : std_logic;
signal RS232_RX : std_logic;
signal RS232_TX : std_logic;
signal switches : std_logic_vector(7 downto 0);
signal Temp_L : std_logic_vector(6 downto 0);
signal Temp_H : std_logic_vector(6 downto 0);
begin -- TestBench
UUT: PICtop
port map (
Reset => Reset,
Clk => Clk,
RS232_RX => RS232_RX,
RS232_TX => RS232_TX,
switches => switches,
Temp_L => Temp_L,
Temp_H => Temp_H);
-----------------------------------------------------------------------------
-- Reset & clock generator
-----------------------------------------------------------------------------
Reset <= '0', '1' after 75 ns;
p_clk : PROCESS
BEGIN
clk <= '1', '0' after 25 ns;
wait for 50 ns;
END PROCESS;
-------------------------------------------------------------------------------
-- Sending some stuff through RS232 port
-------------------------------------------------------------------------------
SEND_STUFF : process
begin
RS232_RX <= '1';
wait for 40 us;
Transmit(RS232_RX, X"49");
wait for 40 us;
Transmit(RS232_RX, X"34");
wait for 40 us;
Transmit(RS232_RX, X"31");
wait;
end process SEND_STUFF;
end TestBench;
|
gpl-3.0
|
d652b545cf8fc7720ecebf6053d82b9f
| 0.453827 | 4.05 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/multiplication/floating_point_multiplier/floating_point_multiplier.vhd
| 1 | 5,282 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity floating_point_multiplier is
generic(
TOTAL_BITS : natural := 23;
EXP_BITS : natural := 6
);
port(
number1_in : in std_logic_vector(TOTAL_BITS - 1 downto 0);
number2_in : in std_logic_vector(TOTAL_BITS - 1 downto 0);
multiplication_result : out std_logic_vector(TOTAL_BITS - 1 downto 0)
);
end floating_point_multiplier;
architecture floating_point_multiplier_arq of floating_point_multiplier is
signal number1 : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
signal number2 : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
signal man1 : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
signal man2 : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
signal exp1 : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '0');
signal exp2 : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '0');
signal sign1 : std_logic := '0';
signal sign2 : std_logic := '0';
signal added_exponents : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '0');
signal exponent_addition_cout: std_logic := '0';
signal multiplied_mantissas : std_logic_vector(TOTAL_BITS - EXP_BITS downto 0) := (others => '0');
signal result_man : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
signal result_exp : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '0');
signal result_sign : std_logic := '0';
component number_splitter is
generic(
TOTAL_BITS:natural := 23;
EXP_BITS:natural := 6);
port (
number_in: in std_logic_vector(TOTAL_BITS-1 downto 0);
sign_out: out std_logic;
exp_out: out std_logic_vector(EXP_BITS-1 downto 0);
mant_out: out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0)
);
end component;
component class_adder is
generic(N: integer:= 4);
port(
number1_in: in std_logic_vector(N-1 downto 0);
number2_in: in std_logic_vector(N-1 downto 0);
cin: in std_logic;
result: out std_logic_vector(N-1 downto 0);
cout: out std_logic
);
end component;
component mantissa_multiplier is
generic(
BITS:natural := 16
);
port (
man1_in: in std_logic_vector(BITS - 1 downto 0);
man2_in: in std_logic_vector(BITS - 1 downto 0);
result: out std_logic_vector(BITS + 1 downto 0) --Add one to shift if necessary
);
end component;
component rounder is
generic(
TOTAL_BITS:natural := 23;
EXP_BITS: natural := 6
);
port (
exponent_addition_cout: in std_logic;
man_in: in std_logic_vector(TOTAL_BITS - EXP_BITS downto 0);
exp_in: in std_logic_vector(EXP_BITS - 1 downto 0);
man_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_out : out std_logic_vector(EXP_BITS - 1 downto 0)
);
end component;
component sign_computer is
port(
sign1_in : in std_logic;
sign2_in : in std_logic;
sign_out : out std_logic
);
end component;
for sign_computer_0 : sign_computer use entity work.sign_computer;
for mantissa_multiplier_0: mantissa_multiplier use entity work.mantissa_multiplier;
for class_adder_0: class_adder use entity work.class_adder;
for rounder_0: rounder use entity work.rounder;
for number_splitter_1 : number_splitter use entity work.number_splitter;
for number_splitter_2 : number_splitter use entity work.number_splitter;
begin
number_splitter_1: number_splitter
generic map(TOTAL_BITS => TOTAL_BITS, EXP_BITS => EXP_BITS)
port map(
number_in => number1,
sign_out => sign1,
exp_out => exp1,
mant_out => man1
);
number_splitter_2: number_splitter
generic map(TOTAL_BITS => TOTAL_BITS, EXP_BITS => EXP_BITS)
port map(
number_in => number2,
sign_out => sign2,
exp_out => exp2,
mant_out => man2
);
class_adder_0: class_adder
generic map(N => EXP_BITS)
port map(
number1_in => exp1,
number2_in => exp2,
result => added_exponents,
cout => exponent_addition_cout,
cin => '0'
);
mantissa_multiplier_0: mantissa_multiplier
generic map(BITS => TOTAL_BITS - EXP_BITS - 1)
port map(
man1_in => man1,
man2_in => man2,
result => multiplied_mantissas
);
rounder_0: rounder
generic map(TOTAL_BITS => TOTAL_BITS, EXP_BITS => EXP_BITS)
port map(
exponent_addition_cout => exponent_addition_cout,
man_in => multiplied_mantissas,
exp_in => added_exponents,
man_out => result_man,
exp_out => result_exp
);
sign_computer_0: sign_computer
port map(
sign1_in => sign1,
sign2_in => sign2,
sign_out => result_sign
);
process(number1_in,
number2_in,
number1,
number2,
man1,
man2,
exp1,
exp2,
sign1,
sign2,
added_exponents,
exponent_addition_cout,
multiplied_mantissas,
result_man,
result_exp,
result_sign) is
variable int_1: integer := 0;
variable int_2 : integer := 0;
begin
int_1 := to_integer(unsigned(number1_in));
int_2 := to_integer(unsigned(number2_in));
number1 <= number1_in;
number2 <= number2_in;
if(int_1 = 0 or int_2 = 0) then
multiplication_result <= (others => '0');
else
multiplication_result <= result_sign & result_exp & result_man;
end if;
end process;
end;
|
gpl-3.0
|
fc5de8c6b423889aa41e4158498cfd75
| 0.649375 | 2.924695 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/Ejercicio1.vhd
| 4 | 973 |
library IEEE;
use IEEE.std_logic_1164.all;
entity contador is
port(
rst_c: in std_logic;
clk_c: in std_logic;
enable_c: in std_logic;
q1_c: out std_logic;
q0_c: out std_logic
);
end;
architecture contador_func of contador is
component FFD is
port(
enable: in std_logic;
reset: in std_logic;
clk: in std_logic;
Q: out std_logic;
D: in std_logic
);
end component;
signal q0_c_aux,q1_c_aux,d0_c_aux,d1_c_aux:std_logic;
begin
ffd0: FFD port map( --nombres del FFD : enable,reset,clk,Q,D
clk => clk_c,
enable => enable_c,
reset => rst_c, --Siempre van a la izquierda los puertos de los componentes
D => d0_c_aux,
Q => q0_c_aux
);
q0_c <= q0_c_aux;
ffd1: FFD port map(
clk=> clk_c,
enable => enable_c,
reset => rst_c,
D => d1_c_aux,
Q => q1_c_aux
);
q1_c <= q1_c_aux;
d0_c_aux <= not(q0_c_aux);
d1_c_aux <= q1_c_aux or q0_c_aux;
end architecture;
|
gpl-3.0
|
d7057810f5b9db9768e1818bb6f2f72e
| 0.579651 | 2.355932 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/multiplier/multiplier_tb.vhd
| 1 | 2,019 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiplier_tb is
end entity;
architecture multiplier_tb_arq of multiplier_tb is
signal op_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal op_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal result_out : std_logic_vector(63 downto 0) := (others => '0');
component multiplier is
port(
op_1_in: in std_logic_vector(31 downto 0) := (others => '0');
op_2_in: in std_logic_vector(31 downto 0) := (others => '0');
result_out: out std_logic_vector(63 downto 0) := (others => '0')
);
end component;
begin
multiplier_0 : multiplier
port map(
op_1_in => op_1_in,
op_2_in => op_2_in,
result_out => result_out
);
process
type pattern_type is record
o1 : std_logic_vector(31 downto 0);
o2 : std_logic_vector(31 downto 0);
r : std_logic_vector(63 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
( "00000000000000000000000000000000","00000000000000000000000000000000","0000000000000000000000000000000000000000000000000000000000000000"),
( "00000000000000000000000000000010","00000000000000000000000000000010","0000000000000000000000000000000000000000000000000000000000000100"),
( "00000000000000000000010000000000","00000000000000000000001000000000","0000000000000000000000000000000000000000000010000000000000000000"),
( "11111111111111111111111111111111","11111111111111111111111111111111","1111111111111111111111111111111000000000000000000000000000000001")
);
begin
for i in patterns'range loop
-- Set the inputs.
op_1_in <= patterns(i).o1;
op_2_in <= patterns(i).o2;
wait for 1 ns;
assert patterns(i).r = result_out report "BAD RESULT, GOT: " & integer'image(to_integer(unsigned(result_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
71474cc21ded564538af6e2c548a2625
| 0.710748 | 3.711397 | false | false | false | false |
laurivosandi/hdl
|
zynq/src/ov7670_controller/ov7670_controller.vhd
| 3 | 2,394 |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Controller for the OV760 camera - transferes registers to the
-- camera over an I2C like bus
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_controller is
Port ( clk : in STD_LOGIC;
resend :in STD_LOGIC;
config_finished : out std_logic;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end ov7670_controller;
architecture Behavioral of ov7670_controller is
COMPONENT ov7670_registers
PORT(
clk : IN std_logic;
advance : IN std_logic;
resend : in STD_LOGIC;
command : OUT std_logic_vector(15 downto 0);
finished : OUT std_logic
);
END COMPONENT;
COMPONENT i2c_sender
PORT(
clk : IN std_logic;
send : IN std_logic;
taken : out std_logic;
id : IN std_logic_vector(7 downto 0);
reg : IN std_logic_vector(7 downto 0);
value : IN std_logic_vector(7 downto 0);
siod : INOUT std_logic;
sioc : OUT std_logic
);
END COMPONENT;
signal sys_clk : std_logic := '0';
signal command : std_logic_vector(15 downto 0);
signal finished : std_logic := '0';
signal taken : std_logic := '0';
signal send : std_logic;
constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet
begin
config_finished <= finished;
send <= not finished;
Inst_i2c_sender: i2c_sender PORT MAP(
clk => clk,
taken => taken,
siod => siod,
sioc => sioc,
send => send,
id => camera_address,
reg => command(15 downto 8),
value => command(7 downto 0)
);
reset <= '1'; -- Normal mode
pwdn <= '0'; -- Power device up
xclk <= sys_clk;
Inst_ov7670_registers: ov7670_registers PORT MAP(
clk => clk,
advance => taken,
command => command,
finished => finished,
resend => resend
);
process(clk)
begin
if rising_edge(clk) then
sys_clk <= not sys_clk;
end if;
end process;
end Behavioral;
|
mit
|
989bb6854806919738fc912b38560ee6
| 0.547619 | 3.30663 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/controller_FG_solving_key_equation_4.vhd
| 1 | 50,321 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_FG_Solving_Key_Equation_4
-- Module Name: Controller_FG_Solving_Key_Equation_4
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 2nd step in Goppa Code Decoding.
--
-- This is a state machine circuit that controls the part of computing
-- polynomials FG in solving_key_equation_4. This state machine is synchronized
-- with the Controller_BC_Solving_Key_Equation_4, in some states it waits for the other
-- machine to finish.
-- This state machine have 3 phases: first phase variable initialization,
-- second computation of polynomial sigma, third step writing the polynomial sigma
-- on a specific memory position.
--
-- Dependencies:
--
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_FG_solving_key_equation_4 is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
F_equal_zero : in STD_LOGIC;
i_FG_equal_zero : in STD_LOGIC;
i_FG_minus_j_less_than_zero : in STD_LOGIC;
degree_G_less_equal_final_degree : in STD_LOGIC;
degree_F_less_than_degree_G : in STD_LOGIC;
reg_looking_degree_FG_q : in STD_LOGIC_VECTOR(0 downto 0);
ready_controller_BC : in STD_LOGIC;
ready_controller_FG : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
signal_inv : out STD_LOGIC;
write_enable_F : out STD_LOGIC;
write_enable_G : out STD_LOGIC;
sel_base_mul_FG : out STD_LOGIC;
reg_h_ce : out STD_LOGIC;
ctr_i_FG_ce : out STD_LOGIC;
ctr_i_FG_load : out STD_LOGIC;
ctr_i_FG_rst : out STD_LOGIC;
reg_j_ce : out STD_LOGIC;
reg_j_rst : out STD_LOGIC;
reg_F_ce : out STD_LOGIC;
reg_F_rst : out STD_LOGIC;
reg_new_value_F_ce : out STD_LOGIC;
reg_new_value_F_rst : out STD_LOGIC;
sel_load_new_value_F : out STD_LOGIC;
reg_G_ce : out STD_LOGIC;
reg_G_rst : out STD_LOGIC;
reg_new_value_G_ce : out STD_LOGIC;
reg_new_value_G_rst : out STD_LOGIC;
sel_reg_new_value_G : out STD_LOGIC;
ctr_degree_F_ce : out STD_LOGIC;
ctr_degree_F_load : out STD_LOGIC;
ctr_degree_F_rst : out STD_LOGIC;
reg_degree_G_ce : out STD_LOGIC;
reg_degree_G_rst : out STD_LOGIC;
reg_looking_degree_FG_d : out STD_LOGIC_VECTOR(0 downto 0);
reg_looking_degree_FG_ce : out STD_LOGIC;
reg_swap_ce : out STD_LOGIC;
reg_swap_rst : out STD_LOGIC;
ctr_load_address_F_ce : out STD_LOGIC;
ctr_load_address_F_load : out STD_LOGIC;
ctr_load_address_G_ce : out STD_LOGIC;
ctr_load_address_G_load : out STD_LOGIC;
reg_bus_address_F_ce : out STD_LOGIC;
reg_bus_address_G_ce : out STD_LOGIC;
reg_calc_address_F_ce : out STD_LOGIC;
reg_calc_address_G_ce : out STD_LOGIC;
reg_store_address_F_ce : out STD_LOGIC;
reg_store_address_F_rst : out STD_LOGIC;
reg_store_address_G_ce : out STD_LOGIC;
reg_store_address_G_rst : out STD_LOGIC;
enable_external_swap : out STD_LOGIC
);
end controller_FG_solving_key_equation_4;
architecture Behavioral of controller_FG_solving_key_equation_4 is
type State is (reset, load_counter, load_counter_2, load_counter_3, load_first_inv, send_first_inv_store_G2t, load_F_store_G, last_store_G, swap_F_G_B_C, prepare_load_j, load_j, load_first_G_first_F, load_h, prepare_load_F_G, load_store_F_G, wait_finalize_BC_controller, prepare_final_swap, prepare_swap_address, prepare_load_sigma, prepare_load_sigma_2, load_sigma, load_store_sigma, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process(actual_state, F_equal_zero, i_FG_equal_zero, i_FG_minus_j_less_than_zero, degree_G_less_equal_final_degree, degree_F_less_than_degree_G, reg_looking_degree_FG_q)
begin
case (actual_state) is
when reset =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '1';
reg_j_ce <= '0';
reg_j_rst <= '1';
reg_F_ce <= '0';
reg_F_rst <= '1';
reg_new_value_F_ce <= '0';
reg_new_value_F_rst <= '1';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '1';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '1';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
ctr_load_address_F_ce <= '0';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '0';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '0';
reg_bus_address_G_ce <= '0';
reg_calc_address_F_ce <= '0';
reg_calc_address_G_ce <= '0';
reg_store_address_F_ce <= '0';
reg_store_address_F_rst <= '1';
reg_store_address_G_ce <= '0';
reg_store_address_G_rst <= '1';
enable_external_swap <= '1';
ready_controller_FG <= '0';
when load_counter =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '1';
reg_j_ce <= '0';
reg_j_rst <= '1';
reg_F_ce <= '0';
reg_F_rst <= '0';
reg_new_value_F_ce <= '0';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '0';
reg_new_value_G_ce <= '1';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '1';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '1';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '1';
reg_bus_address_F_ce <= '0';
reg_bus_address_G_ce <= '0';
reg_calc_address_F_ce <= '0';
reg_calc_address_G_ce <= '0';
reg_store_address_F_ce <= '0';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '0';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '0';
when load_counter_2 =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '1';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '0';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '0';
reg_new_value_G_ce <= '1';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '1';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '0';
reg_calc_address_G_ce <= '0';
reg_store_address_F_ce <= '0';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '0';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '0';
when load_counter_3 =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '1';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '0';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '0';
reg_new_value_G_ce <= '1';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '1';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '0';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '0';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '0';
when load_first_inv =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '1';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '0';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "1";
reg_looking_degree_FG_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '1';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '1';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '0';
when send_first_inv_store_G2t =>
key_equation_found <= '0';
signal_inv <= '1';
write_enable_F <= '0';
write_enable_G <= '1';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '1';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '1';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '0';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '1';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '1';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '1';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '0';
when load_F_store_G =>
if(i_FG_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '1';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '1';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '1';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '1';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '0';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '0';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '0';
reg_bus_address_G_ce <= '0';
reg_calc_address_F_ce <= '0';
reg_calc_address_G_ce <= '0';
reg_store_address_F_ce <= '1';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '1';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '0';
elsif(reg_looking_degree_FG_q(0) = '1' and F_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '1';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '1';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '1';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '0';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '1';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '1';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '0';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '1';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '1';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '1';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '0';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '1';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '1';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '0';
end if;
when last_store_G =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '1';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '0';
reg_F_rst <= '0';
reg_new_value_F_ce <= '0';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '0';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '0';
reg_calc_address_G_ce <= '0';
reg_store_address_F_ce <= '0';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '0';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '0';
when swap_F_G_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '0';
reg_F_rst <= '0';
reg_new_value_F_ce <= '0';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '0';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '1';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '1';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '1';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '0';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '0';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '0';
reg_bus_address_G_ce <= '0';
reg_calc_address_F_ce <= '0';
reg_calc_address_G_ce <= '0';
reg_store_address_F_ce <= '0';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '0';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '0';
when prepare_load_j =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_rst <= '0';
reg_j_ce <= '0';
reg_F_ce <= '0';
reg_F_rst <= '0';
reg_new_value_F_ce <= '0';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '0';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '1';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '1';
reg_bus_address_F_ce <= '0';
reg_bus_address_G_ce <= '0';
reg_calc_address_F_ce <= '0';
reg_calc_address_G_ce <= '0';
reg_store_address_F_ce <= '0';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '0';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '0';
when load_j =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '1';
ctr_i_FG_load <= '1';
ctr_i_FG_rst <= '0';
reg_j_ce <= '1';
reg_j_rst <= '0';
reg_F_ce <= '0';
reg_F_rst <= '0';
reg_new_value_F_ce <= '0';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '0';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '0';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '0';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '0';
reg_bus_address_G_ce <= '0';
reg_calc_address_F_ce <= '0';
reg_calc_address_G_ce <= '0';
reg_store_address_F_ce <= '0';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '0';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '1';
when load_first_G_first_F =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '0';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '1';
reg_G_rst <= '0';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '0';
reg_calc_address_G_ce <= '0';
reg_store_address_F_ce <= '0';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '0';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '1';
when load_h =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '1';
reg_h_ce <= '1';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '0';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '1';
reg_G_rst <= '0';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "1";
reg_looking_degree_FG_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '0';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '0';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '1';
when prepare_load_F_G =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '1';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '1';
reg_G_ce <= '1';
reg_G_rst <= '0';
reg_new_value_G_ce <= '1';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '1';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '1';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '0';
when load_store_F_G =>
if(i_FG_equal_zero = '1') then
ready_controller_FG <= '1';
else
ready_controller_FG <= '0';
end if;
if(i_FG_minus_j_less_than_zero = '1') then
if(reg_looking_degree_FG_q(0) = '1') then
if(F_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '1';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '1';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '1';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '1';
reg_G_ce <= '0';
reg_G_rst <= '1';
reg_new_value_G_ce <= '1';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '1';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '1';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
elsif(degree_F_less_than_degree_G = '1') then
key_equation_found <= '0';
signal_inv <= '1';
write_enable_F <= '1';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '1';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '1';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '1';
reg_G_ce <= '0';
reg_G_rst <= '1';
reg_new_value_G_ce <= '1';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '1';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '1';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '1';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '1';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '1';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '1';
reg_G_ce <= '0';
reg_G_rst <= '1';
reg_new_value_G_ce <= '1';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '1';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '1';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
end if;
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '1';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '1';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '1';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '1';
reg_G_ce <= '0';
reg_G_rst <= '1';
reg_new_value_G_ce <= '1';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '1';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '1';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
end if;
else
if(reg_looking_degree_FG_q(0) = '1') then
if(F_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '1';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '1';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '1';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '1';
reg_G_ce <= '1';
reg_G_rst <= '0';
reg_new_value_G_ce <= '1';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '1';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '1';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
elsif(degree_F_less_than_degree_G = '1') then
key_equation_found <= '0';
signal_inv <= '1';
write_enable_F <= '1';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '1';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '1';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '1';
reg_G_ce <= '1';
reg_G_rst <= '0';
reg_new_value_G_ce <= '1';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '1';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '1';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '1';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '1';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '1';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '1';
reg_G_ce <= '1';
reg_G_rst <= '0';
reg_new_value_G_ce <= '1';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '1';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '1';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
end if;
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '1';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '1';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '1';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '1';
reg_G_ce <= '1';
reg_G_rst <= '0';
reg_new_value_G_ce <= '1';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '1';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '1';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
end if;
end if;
when wait_finalize_BC_controller =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '1';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '0';
reg_F_rst <= '0';
reg_new_value_F_ce <= '0';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '0';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '0';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '0';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '0';
reg_bus_address_G_ce <= '0';
reg_calc_address_F_ce <= '0';
reg_calc_address_G_ce <= '0';
reg_store_address_F_ce <= '0';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '0';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '1';
when prepare_final_swap =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '1';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '0';
reg_F_rst <= '1';
reg_new_value_F_ce <= '0';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '1';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '0';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '0';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '0';
reg_bus_address_G_ce <= '0';
reg_calc_address_F_ce <= '0';
reg_calc_address_G_ce <= '0';
reg_store_address_F_ce <= '0';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '0';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '0';
when prepare_swap_address =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '0';
reg_F_rst <= '0';
reg_new_value_F_ce <= '0';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '0';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '1';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '1';
reg_bus_address_F_ce <= '0';
reg_bus_address_G_ce <= '0';
reg_calc_address_F_ce <= '0';
reg_calc_address_G_ce <= '0';
reg_store_address_F_ce <= '0';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '0';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '0';
when prepare_load_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '0';
reg_F_rst <= '0';
reg_new_value_F_ce <= '0';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '0';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '0';
reg_calc_address_G_ce <= '0';
reg_store_address_F_ce <= '0';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '0';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '0';
when prepare_load_sigma_2 =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '0';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '1';
reg_G_rst <= '0';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '0';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '0';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '0';
when load_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '1';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '1';
reg_G_rst <= '0';
reg_new_value_G_ce <= '1';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '1';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '1';
reg_store_address_G_rst <= '0';
enable_external_swap <= '1';
ready_controller_FG <= '0';
when load_store_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '1';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '1';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '1';
reg_F_rst <= '0';
reg_new_value_F_ce <= '1';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '1';
reg_G_rst <= '0';
reg_new_value_G_ce <= '1';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '1';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '1';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '1';
reg_bus_address_G_ce <= '1';
reg_calc_address_F_ce <= '1';
reg_calc_address_G_ce <= '1';
reg_store_address_F_ce <= '1';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '1';
reg_store_address_G_rst <= '0';
enable_external_swap <= '0';
ready_controller_FG <= '0';
when final =>
key_equation_found <= '1';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '1';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '0';
reg_F_rst <= '1';
reg_new_value_F_ce <= '0';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '1';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
ctr_load_address_F_ce <= '0';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '0';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '0';
reg_bus_address_G_ce <= '0';
reg_calc_address_F_ce <= '0';
reg_calc_address_G_ce <= '0';
reg_store_address_F_ce <= '0';
reg_store_address_F_rst <= '0';
reg_store_address_G_ce <= '0';
reg_store_address_G_rst <= '0';
enable_external_swap <= '0';
ready_controller_FG <= '0';
when others =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_F <= '0';
write_enable_G <= '0';
sel_base_mul_FG <= '0';
reg_h_ce <= '0';
ctr_i_FG_ce <= '0';
ctr_i_FG_load <= '0';
ctr_i_FG_rst <= '1';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_F_ce <= '0';
reg_F_rst <= '1';
reg_new_value_F_ce <= '0';
reg_new_value_F_rst <= '0';
sel_load_new_value_F <= '0';
reg_G_ce <= '0';
reg_G_rst <= '1';
reg_new_value_G_ce <= '0';
reg_new_value_G_rst <= '0';
sel_reg_new_value_G <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
reg_looking_degree_FG_d <= "0";
reg_looking_degree_FG_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
ctr_load_address_F_ce <= '0';
ctr_load_address_F_load <= '0';
ctr_load_address_G_ce <= '0';
ctr_load_address_G_load <= '0';
reg_bus_address_F_ce <= '0';
reg_bus_address_G_ce <= '0';
reg_calc_address_F_ce <= '0';
reg_calc_address_G_ce <= '0';
reg_store_address_F_ce <= '0';
reg_store_address_F_rst <= '1';
reg_store_address_G_ce <= '0';
reg_store_address_G_rst <= '1';
enable_external_swap <= '0';
ready_controller_FG <= '0';
end case;
end process;
New_State : process(actual_state, ready_controller_BC, F_equal_zero, i_FG_equal_zero, i_FG_minus_j_less_than_zero, degree_G_less_equal_final_degree, degree_F_less_than_degree_G, reg_looking_degree_FG_q)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= load_counter_2;
when load_counter_2 =>
next_state <= load_counter_3;
when load_counter_3 =>
next_state <= load_first_inv;
when load_first_inv =>
next_state <= send_first_inv_store_G2t;
when send_first_inv_store_G2t =>
next_state <= load_F_store_G;
when load_F_store_G =>
if(i_FG_equal_zero = '1') then
next_state <= last_store_G;
else
next_state <= load_F_store_G;
end if;
when last_store_G =>
next_state <= swap_F_G_B_C;
when swap_F_G_B_C =>
next_state <= prepare_load_j;
when prepare_load_j =>
if(degree_G_less_equal_final_degree = '1') then
next_state <= prepare_final_swap;
else
next_state <= load_j;
end if;
when load_j =>
next_state <= load_first_G_first_F;
when load_first_G_first_F =>
next_state <= load_h;
when load_h =>
next_state <= prepare_load_F_G;
when prepare_load_F_G =>
next_state <= load_store_F_G;
when load_store_F_G =>
if(i_FG_equal_zero = '1') then
if(ready_controller_BC = '0') then
next_state <= wait_finalize_BC_controller;
elsif(degree_G_less_equal_final_degree = '1') then
next_state <= prepare_final_swap;
elsif(degree_F_less_than_degree_G = '1') then
next_state <= swap_F_G_B_C;
else
next_state <= prepare_load_j;
end if;
else
next_state <= load_store_F_G;
end if;
when wait_finalize_BC_controller =>
if(ready_controller_BC = '0') then
next_state <= wait_finalize_BC_controller;
elsif(degree_G_less_equal_final_degree = '1') then
next_state <= prepare_final_swap;
elsif(degree_F_less_than_degree_G = '1') then
next_state <= swap_F_G_B_C;
else
next_state <= prepare_load_j;
end if;
when prepare_final_swap =>
next_state <= prepare_swap_address;
when prepare_swap_address =>
next_state <= prepare_load_sigma;
when prepare_load_sigma =>
next_state <= prepare_load_sigma_2;
when prepare_load_sigma_2 =>
next_state <= load_sigma;
when load_sigma =>
next_state <= load_store_sigma;
when load_store_sigma =>
if(i_FG_equal_zero = '1') then
next_state <= final;
else
next_state <= load_store_sigma;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
70d854d601dceadc651b9f27a80f2f9b
| 0.516961 | 2.288254 | false | false | false | false |
KenKeeley/My68k-system
|
CircuitBoards/MainBoard/SupportCPLD/DTACK.vhd
| 1 | 2,403 |
----------------------------------------------------------------------------------------------------
--
-- FileName: DTACK.vhd
-- Description: DTACK and WatchDog Timer.
--
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY work;
ENTITY DTACK IS
PORT
(
nReset : IN STD_LOGIC; -- Reset
ClkIn : IN STD_LOGIC; -- Incoming Clock
nAS : IN STD_LOGIC; -- Address Strobe
nCS_RTC : IN STD_LOGIC; -- RTC Chip Select
nCS_PS2 : IN STD_LOGIC; -- PS2 Chip Select
nPS_OFF : IN STD_LOGIC; -- Power Off
nCS_SRAM : IN STD_LOGIC; -- SRAM Chip Select
nCS_ROM : IN STD_LOGIC; -- ROM Chip Select
nDSACK0 : OUT STD_LOGIC; -- Data Transfer Acknowledge 0
nBERR : OUT STD_LOGIC -- Bus Error
);
END DTACK;
ARCHITECTURE Behavioral OF DTACK IS
SIGNAL Clk_Counter : UNSIGNED(5 DOWNTO 0);
BEGIN
PROCESS(ClkIn, nReset, nAS)
BEGIN
IF (nReset = '0' OR nAS = '1') THEN
nDSACK0 <= 'Z';
nBERR <= 'Z';
Clk_Counter <= "000000";
ELSIF RISING_EDGE(ClkIn) THEN
-- SRAM DTACK Delay = 40ns.
IF Clk_Counter = 2 AND nCS_SRAM = '0' THEN
nDSACK0 <= '0';
-- ROM DTACK Delay = 80ns.
ELSIF Clk_Counter = 4 AND nCS_ROM = '0' THEN
nDSACK0 <= '0';
-- PS/2 DTACK Delay = 160ns.
ELSIF Clk_Counter = 8 AND nCS_PS2 = '0' THEN
nDSACK0 <= '0';
-- RTC DTACK Delay = 200ns.
ELSIF Clk_Counter = 10 AND nCS_RTC = '0' THEN
nDSACK0 <= '0';
-- PS_OFF DTACK Delay = 400ns.
ELSIF Clk_Counter = 20 AND nPS_OFF = '0' THEN
nDSACK0 <= '0';
-- Watchdog Timer 1us.
ELSIF Clk_Counter = 50 THEN
nBERR <= '0';
ELSE
Clk_Counter <= Clk_Counter + 1;
END IF;
END IF;
END PROCESS;
END Behavioral;
|
gpl-3.0
|
fa76b6d39676e656bd063b6053bac180
| 0.403246 | 4.711765 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/UART/timing.vhd
| 1 | 3,502 |
-- --------------------------
-- TIMING
-- --------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- ----------------------------------------------------
Entity timing is
-- ----------------------------------------------------
generic (
F : natural;
min_baud: natural
);
port (
CLK : in std_logic;
RST : in std_logic;
divisor : in std_logic_vector;
ClrDiv : in std_logic;
Top16 : buffer std_logic;
TopTx : out std_logic;
TopRx : out std_logic
);
end timing;
-- ----------------------------------------------------
Architecture timing of timing is
-- ----------------------------------------------------
-- signal baud_value : natural;
constant max_div : natural := ((F*1000)/(16*min_baud));
subtype div16_type is natural range 0 to max_div-1;
signal Div16 : div16_type;
signal ClkDiv : integer;
signal RxDiv : integer;
begin
-- --------------------------
-- Baud rate selection
-- --------------------------
--
-- process (CLK) -- baud_value setting.
-- begin
-- if rising_edge(CLK) then
-- case Baud is
-- when "000" => baud_value <= 115200;
-- when "001" => baud_value <= 57600;
-- when "010" => baud_value <= 38400;
-- when "011" => baud_value <= 19200;
-- when "100" => baud_value <= 9600;
-- when "101" => baud_value <= 4800;
-- when "110" => baud_value <= 2400;
-- when "111" => baud_value <= 1200;
-- when others => baud_value <= 1200; -- n.u.
-- end case;
-- end if;
-- end process;
--
-- --------------------------
-- Clk16 Clock Generation
-- --------------------------
process (RST, CLK)
begin
if RST='1' then
Top16 <= '0';
Div16 <= 0;
elsif rising_edge(CLK) then
Top16 <= '0';
if Div16 = conv_integer(divisor) then
Div16 <= 0;
Top16 <= '1';
else
Div16 <= Div16 + 1;
end if;
end if;
end process;
-- --------------------------
-- Tx Clock Generation
-- --------------------------
process (RST, CLK)
begin
if RST='1' then
TopTx <= '0';
ClkDiv <= 0; --(others=>'0');
elsif rising_edge(CLK) then
TopTx <= '0';
if Top16='1' then
ClkDiv <= ClkDiv + 1;
if ClkDiv = 15 then
TopTx <= '1';
ClkDiv <= 0;
end if;
end if;
end if;
end process;
-- ------------------------------
-- Rx Sampling Clock Generation
-- ------------------------------
process (RST, CLK)
begin
if RST='1' then
TopRx <= '0';
RxDiv <= 0;
elsif rising_edge(CLK) then
TopRx <= '0';
if ClrDiv='1' then
RxDiv <= 0;
elsif Top16='1' then
if RxDiv = 7 then
RxDiv <= 0;
TopRx <= '1';
else
RxDiv <= RxDiv + 1;
end if;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
7c6a4bc9874f51044513c11138744042
| 0.363507 | 4.571802 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/floating_point_adder/floating_point_adder.vhd
| 1 | 21,655 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--This component takes 2 numbers written in scientific notation returns the sum of them, also in scientific notation.
entity floating_point_adder is
generic(
TOTAL_BITS : natural := 23;
EXP_BITS : natural := 6
);
port(
enable : in std_logic;
reset : in std_logic;
clk : in std_logic;
number_1_in : in std_logic_vector(TOTAL_BITS - 1 downto 0);
number_2_in : in std_logic_vector(TOTAL_BITS - 1 downto 0);
result: out std_logic_vector(TOTAL_BITS - 1 downto 0)
);
end floating_point_adder;
architecture floating_point_adder_arq of floating_point_adder is
signal enable_in : std_logic := '0';
signal reset_in : std_logic := '0';
signal clk_in : std_logic := '0';
signal number_1 : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
signal number_2 : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
--For registry shared values:
-- s{x} = generated in step x or for use in step x
-- br = before registry
-- ar = after registry
--STEP 1
signal man_1_s1 : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
signal man_2_s1 : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
signal exp_1 : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '0');
signal exp_2 : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '0');
signal sign_1_s1 : std_logic := '0';
signal sign_2_s1 : std_logic := '0';
signal man_greater_s1 : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
signal man_smaller_s1 : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
signal exp_greater_s1 : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '0');
signal exp_smaller_s1 : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '0');
--STEP 2
signal man_smaller_s2 : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
signal man_greater_s2 : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
signal sign_1_s2 : std_logic := '0';
signal sign_2_s2 : std_logic := '0';
signal expanded_man_smaller : std_logic_vector(TOTAL_BITS - EXP_BITS - 1 downto 0) := (others => '0');
signal expanded_man_greater_s2 : std_logic_vector(TOTAL_BITS - EXP_BITS - 1 downto 0) := (others => '0');
signal complemented_expanded_man_smaller_s2 : std_logic_vector(TOTAL_BITS - EXP_BITS - 1 downto 0) := (others => '0');
--STEP 3
signal sign_1_s3 : std_logic := '0';
signal sign_2_s3 : std_logic := '0';
signal exp_greater_s3 : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '0');
signal exp_smaller_s3 : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '0');
signal complemented_expanded_man_smaller_s3 : std_logic_vector(TOTAL_BITS - EXP_BITS - 1 downto 0) := (others => '0');
signal shifted_complemented_expanded_man_smaller_s3 : std_logic_vector(TOTAL_BITS - EXP_BITS - 1 downto 0) := (others => '0');
signal rounding_bit_s3 : std_logic := '0';
--STEP 4
signal shifted_complemented_expanded_man_smaller_s4 : std_logic_vector(TOTAL_BITS - EXP_BITS - 1 downto 0) := (others => '0');
signal expanded_man_greater_s4 : std_logic_vector(TOTAL_BITS - EXP_BITS - 1 downto 0) := (others => '0');
signal expanded_man_result_s4 : std_logic_vector(TOTAL_BITS - EXP_BITS - 1 downto 0) := (others => '0');
signal addition_cout_s4 : std_logic := '0';
--STEP 5
signal sign_1_s5 : std_logic := '0';
signal sign_2_s5 : std_logic := '0';
signal diff_signs : std_logic := '0';
signal rounding_bit_s5 : std_logic := '0';
signal exp_greater_s5 : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '0');
signal expanded_man_result_s5 : std_logic_vector(TOTAL_BITS - EXP_BITS - 1 downto 0) := (others => '0');
signal addition_cout_s5 : std_logic := '0';
signal complemented_expanded_man_result_s5 : std_logic_vector(TOTAL_BITS - EXP_BITS - 1 downto 0) := (others => '0');
signal man_result_s5 : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
signal exp_result_s5 : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '0');
--STEP 6
signal sign_1_s6 : std_logic := '0';
signal sign_2_s6 : std_logic := '0';
signal man_1_s6 : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
signal man_2_s6 : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
signal man_greater_s6 : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
signal expanded_man_result_s6 : std_logic_vector(TOTAL_BITS - EXP_BITS - 1 downto 0) := (others => '0');
signal complemented_expanded_man_result_s6 : std_logic_vector(TOTAL_BITS - EXP_BITS - 1 downto 0) := (others => '0');
signal sign_result_s6 : std_logic := '0';
signal man_result : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
signal exp_result : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '0');
signal sign_result : std_logic := '0';
--component for storing values for multiple clock cycles
component shift_register is
generic(REGISTRY_BITS : integer := 32;
STEPS : integer := 4);
port(
enable: in std_logic;
reset: in std_logic;
clk: in std_logic;
D: in std_logic_vector(REGISTRY_BITS - 1 downto 0);
Q: out std_logic_vector(REGISTRY_BITS - 1 downto 0)
);
end component;
--Component used for splitting numbers to add into their scientific notations parts: mantissa, exponent, sign.
component number_splitter is
generic(
TOTAL_BITS:natural := 23;
EXP_BITS:natural := 6);
port (
number_in: in std_logic_vector(TOTAL_BITS-1 downto 0);
sign_out: out std_logic;
exp_out: out std_logic_vector(EXP_BITS-1 downto 0);
mant_out: out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0)
);
end component;
--Component used to swap the inputs and recognise the bigger and the smaller to apply the adding algorithm correctly
component number_swapper is
generic(
TOTAL_BITS : natural := 23;
EXP_BITS : natural := 6
);
port(
man_1_in : in std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_1_in : in std_logic_vector(EXP_BITS - 1 downto 0);
man_2_in : in std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_2_in : in std_logic_vector(EXP_BITS - 1 downto 0);
man_greater_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
man_smaller_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_greater_out : out std_logic_vector(EXP_BITS - 1 downto 0);
exp_smaller_out : out std_logic_vector(EXP_BITS - 1 downto 0)
);
end component;
--Component used to expand the operands and work with double precision. It also adds the implicit 1
component number_expander is
generic(
BITS : natural := 16
);
port(
number_in : in std_logic_vector(BITS - 1 downto 0);
number_out : out std_logic_vector(BITS downto 0)
);
end component;
--Component used to complement the smaller mantissa to add the absolute values properly
component sign_based_complementer is
generic(
BITS : natural := 16
);
port(
sign_1_in : in std_logic;
sign_2_in : in std_logic;
man_in : in std_logic_vector(BITS - 1 downto 0);
man_out : out std_logic_vector(BITS -1 downto 0)
);
end component;
--Component to shift the samller mantissa in order to have the same exponents for correct addition
component number_shifter is
generic(
BITS : natural := 32;
EXP_BITS : natural := 6
);
port(
sign_1_in : in std_logic;
sign_2_in : in std_logic;
greater_exp : in std_logic_vector(EXP_BITS - 1 downto 0);
smaller_exp : in std_logic_vector(EXP_BITS - 1 downto 0);
man_in : in std_logic_vector(BITS - 1 downto 0);
man_out : out std_logic_vector(BITS - 1 downto 0);
rounding_bit : out std_logic
);
end component;
--Component used to add 2 expanded mantissas with the same exponents and correct the result according to sings
component expanded_mantissa_adder is
generic(
BITS : natural := 16
);
port(
man_1_in : in std_logic_vector(BITS - 1 downto 0);
man_2_in : in std_logic_vector(BITS - 1 downto 0);
result : out std_logic_vector(BITS - 1 downto 0);
cout : out std_logic
);
end component;
--Component used to complement the result in case is necessary
component result_complementer is
generic(
BITS : natural := 16
);
port(
in_result : in std_logic_vector(BITS - 1 downto 0) := (others => '0');
sign_1_in : in std_logic := '0';
sign_2_in : in std_logic := '0';
result_cout : in std_logic := '0';
out_result : out std_logic_vector(BITS - 1 downto 0) := (others => '0')
);
end component;
component bit_xor is
port (
bit1_in: in std_logic := '0';
bit2_in: in std_logic := '0';
result: out std_logic := '0'
);
end component;
component normalizer is
generic(
TOTAL_BITS : natural := 23;
EXP_BITS : natural := 6
);
port(
man_in : in std_logic_vector(TOTAL_BITS - EXP_BITS - 1 downto 0);
exp_in : in std_logic_vector(EXP_BITS - 1 downto 0);
cin : in std_logic; --To check if the sum had a carry
diff_signs : in std_logic;
rounding_bit : in std_logic;
man_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_out : out std_logic_vector(EXP_BITS - 1 downto 0)
);
end component;
component sign_computer is
generic(
BITS : natural := 16
);
port(
man_1_in: in std_logic_vector(BITS - 1 downto 0) := (others => '0');
man_2_in: in std_logic_vector(BITS - 1 downto 0) := (others => '0');
sign_1_in: in std_logic := '0';
sign_2_in: in std_logic := '0';
man_greater_in: in std_logic_vector(BITS - 1 downto 0) := (others => '0');
pre_complemented_result: in std_logic_vector(BITS downto 0) := (others => '0');
complemented_result: in std_logic_vector(BITS downto 0) := (others => '0');
sign_out: out std_logic := '0'
);
end component;
begin
--########################## STEP 1: SPLIT NUMBERS AND SWITCH SMALLER AND GREATER #################################
number_splitter_1: number_splitter
generic map(TOTAL_BITS => TOTAL_BITS, EXP_BITS => EXP_BITS)
port map(
number_in => number_1,
sign_out => sign_1_s1,
exp_out => exp_1,
mant_out => man_1_s1
);
number_splitter_2: number_splitter
generic map(TOTAL_BITS => TOTAL_BITS, EXP_BITS => EXP_BITS)
port map(
number_in => number_2,
sign_out => sign_2_s1,
exp_out => exp_2,
mant_out => man_2_s1
);
number_swapper_0 : number_swapper
generic map(TOTAL_BITS => TOTAL_BITS, EXP_BITS => EXP_BITS)
port map(
exp_1_in => exp_1,
exp_2_in => exp_2,
man_1_in => man_1_s1,
man_2_in => man_2_s1,
exp_greater_out => exp_greater_s1,
exp_smaller_out => exp_smaller_s1,
man_greater_out => man_greater_s1,
man_smaller_out => man_smaller_s1
);
step1_to_step2_man_greater : shift_register
generic map(REGISTRY_BITS => TOTAL_BITS - EXP_BITS - 1, STEPS => 1)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => man_greater_s1,
Q => man_greater_s2
);
step1_to_step2_man_smaller : shift_register
generic map(REGISTRY_BITS => TOTAL_BITS - EXP_BITS - 1, STEPS => 1)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => man_smaller_s1,
Q => man_smaller_s2
);
step1_to_step2_sign1: shift_register
generic map(REGISTRY_BITS => 1, STEPS => 1)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D(0) => sign_1_s1,
Q(0) => sign_1_s2
);
step1_to_step2_sign2: shift_register
generic map(REGISTRY_BITS => 1, STEPS => 1)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D(0) => sign_2_s1,
Q(0) => sign_2_s2
);
--#################### STEP 2: EXPAND MANTISSAS AND COMPLEMENT SMALLER IF NECESSARY #########################
number_expander_1 : number_expander
generic map(BITS => TOTAL_BITS - EXP_BITS - 1)
port map(
number_in => man_greater_s2,
number_out => expanded_man_greater_s2
);
number_expander_2 : number_expander
generic map(BITS => TOTAL_BITS - EXP_BITS - 1)
port map(
number_in => man_smaller_s2,
number_out => expanded_man_smaller
);
sign_based_complementer_0 : sign_based_complementer
generic map(BITS => TOTAL_BITS - EXP_BITS)
port map(
sign_1_in => sign_1_s2,
sign_2_in => sign_2_s2,
man_in => expanded_man_smaller,
man_out => complemented_expanded_man_smaller_s2
);
step2_to_step3_complemented_expanded_man_smaller: shift_register
generic map(REGISTRY_BITS => TOTAL_BITS - EXP_BITS, STEPS => 1)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => complemented_expanded_man_smaller_s2,
Q => complemented_expanded_man_smaller_s3
);
--################ STEP 3: EQUALIZE EXPONENTS #############################################
step1_to_step3_sign1: shift_register
generic map(REGISTRY_BITS => 1, STEPS => 2)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D(0) => sign_1_s1,
Q(0) => sign_1_s3
);
step1_to_step3_sign2: shift_register
generic map(REGISTRY_BITS => 1, STEPS => 2)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D(0) => sign_2_s1,
Q(0) => sign_2_s3
);
step1_to_step3_exp_smaller: shift_register
generic map(REGISTRY_BITS => EXP_BITS, STEPS => 2)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => exp_smaller_s1,
Q => exp_smaller_s3
);
step1_to_step3_exp_greater: shift_register
generic map(REGISTRY_BITS => EXP_BITS, STEPS => 2)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => exp_greater_s1,
Q => exp_greater_s3
);
number_shifter_0 : number_shifter
generic map(BITS => TOTAL_BITS - EXP_BITS, EXP_BITS => EXP_BITS)
port map(
man_in => complemented_expanded_man_smaller_s3,
sign_1_in => sign_1_s3,
sign_2_in => sign_2_s3,
greater_exp => exp_greater_s3,
smaller_exp => exp_smaller_s3,
man_out => shifted_complemented_expanded_man_smaller_s3,
rounding_bit => rounding_bit_s3
);
step3_to_step4_shifted_complemented_expanded_man_smaller: shift_register
generic map(REGISTRY_BITS => TOTAL_BITS - EXP_BITS, STEPS => 1)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => shifted_complemented_expanded_man_smaller_s3,
Q => shifted_complemented_expanded_man_smaller_s4
);
step3_to_step5_rounding_bit: shift_register
generic map(REGISTRY_BITS => 1, STEPS => 2)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D(0) => rounding_bit_s3,
Q(0) => rounding_bit_s5
);
-- ############## STEP 4: ADD MANTISSAS ##################################################
step2_to_step4_expanded_man_greater: shift_register
generic map(REGISTRY_BITS => TOTAL_BITS - EXP_BITS, STEPS => 2)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => expanded_man_greater_s2,
Q => expanded_man_greater_s4
);
expanded_mantissa_adder_0 : expanded_mantissa_adder
generic map(BITS => (TOTAL_BITS - EXP_BITS))
port map(
man_1_in => expanded_man_greater_s4,
man_2_in => shifted_complemented_expanded_man_smaller_s4,
result => expanded_man_result_s4,
cout => addition_cout_s4
);
step4_to_step5_expanded_man_result: shift_register
generic map(REGISTRY_BITS => TOTAL_BITS - EXP_BITS, STEPS => 1)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => expanded_man_result_s4,
Q => expanded_man_result_s5
);
step4_to_step6_expanded_man_result: shift_register
generic map(REGISTRY_BITS => TOTAL_BITS - EXP_BITS, STEPS => 2)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => expanded_man_result_s4,
Q => expanded_man_result_s6
);
step4_to_step5_addition_cout: shift_register
generic map(REGISTRY_BITS => 1, STEPS => 1)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D(0) => addition_cout_s4,
Q(0) => addition_cout_s5
);
-- ############# STEP 5: COMPLEMENT IF NECESARY AND NORMALIZE ############################
step1_to_step5_sign1: shift_register
generic map(REGISTRY_BITS => 1, STEPS => 4)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D(0) => sign_1_s1,
Q(0) => sign_1_s5
);
step1_to_step5_sign2: shift_register
generic map(REGISTRY_BITS => 1, STEPS => 4)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D(0) => sign_2_s1,
Q(0) => sign_2_s5
);
result_complementer_0 : result_complementer
generic map(BITS => (TOTAL_BITS - EXP_BITS))
port map(
in_result => expanded_man_result_s5,
sign_1_in => sign_1_s5,
sign_2_in => sign_2_s5,
result_cout => addition_cout_s5,
out_result => complemented_expanded_man_result_s5
);
step1_to_step5_exp_greater: shift_register
generic map(REGISTRY_BITS => EXP_BITS, STEPS => 4)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => exp_greater_s1,
Q => exp_greater_s5
);
step5_to_step6_complemented_expanded_man_result: shift_register
generic map(REGISTRY_BITS => TOTAL_BITS - EXP_BITS, STEPS => 1)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => complemented_expanded_man_result_s5,
Q => complemented_expanded_man_result_s6
);
bit_xor_0 : bit_xor
port map(
bit1_in => sign_1_s5,
bit2_in => sign_2_s5,
result => diff_signs
);
normalizer_0 : normalizer
generic map(TOTAL_BITS => TOTAL_BITS, EXP_BITS => EXP_BITS)
port map(
man_in => complemented_expanded_man_result_s5,
exp_in => exp_greater_s5,
cin => addition_cout_s5,
diff_signs => diff_signs,
rounding_bit => rounding_bit_s5,
man_out => man_result_s5,
exp_out => exp_result_s5
);
-- ########## STEP 6: COMPUTE SIGN #######################################################
step1_to_step6_sign1: shift_register
generic map(REGISTRY_BITS => 1, STEPS => 5)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D(0) => sign_1_s1,
Q(0) => sign_1_s6
);
step1_to_step6_sign2: shift_register
generic map(REGISTRY_BITS => 1, STEPS => 5)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D(0) => sign_2_s1,
Q(0) => sign_2_s6
);
step1_to_step6_man_1 : shift_register
generic map(REGISTRY_BITS => TOTAL_BITS - EXP_BITS - 1, STEPS => 5)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => man_1_s1,
Q => man_1_s6
);
step1_to_step6_man_2 : shift_register
generic map(REGISTRY_BITS => TOTAL_BITS - EXP_BITS - 1, STEPS => 5)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => man_2_s1,
Q => man_2_s6
);
step1_to_step6_man_greater : shift_register
generic map(REGISTRY_BITS => TOTAL_BITS - EXP_BITS - 1, STEPS => 5)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => man_greater_s1,
Q => man_greater_s6
);
sign_computer_0 : sign_computer
generic map(BITS => TOTAL_BITS - EXP_BITS - 1)
port map(
man_1_in => man_1_s6,
man_2_in => man_2_s6,
sign_1_in => sign_1_s6,
sign_2_in => sign_2_s6,
man_greater_in => man_greater_s6,
pre_complemented_result => expanded_man_result_s6,
complemented_result => complemented_expanded_man_result_s6,
sign_out => sign_result_s6
);
--#################### FINAL RESULT #################################
step5_to_result_man : shift_register
generic map(REGISTRY_BITS => TOTAL_BITS - EXP_BITS - 1, STEPS => 2)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => man_result_s5,
Q => man_result
);
step5_to_result_exp : shift_register
generic map(REGISTRY_BITS => EXP_BITS, STEPS => 2)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => exp_result_s5,
Q => exp_result
);
step6_to_result_sign: shift_register
generic map(REGISTRY_BITS => 1, STEPS => 1)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D(0) => sign_result_s6,
Q(0) => sign_result
);
process(clk,
reset,
enable_in,
reset_in,
clk_in,
number_1,
number_2,
man_1_s1,
man_2_s1,
exp_1,
exp_2,
sign_1_s1,
sign_2_s1,
man_greater_s1,
man_smaller_s1,
exp_greater_s1,
exp_smaller_s1,
man_smaller_s2,
man_greater_s2,
sign_1_s2,
sign_2_s2,
expanded_man_smaller,
expanded_man_greater_s2,
complemented_expanded_man_smaller_s2,
sign_1_s3,
sign_2_s3,
exp_greater_s3,
exp_smaller_s3,
complemented_expanded_man_smaller_s3,
shifted_complemented_expanded_man_smaller_s3,
rounding_bit_s3,
shifted_complemented_expanded_man_smaller_s4,
expanded_man_greater_s4,
expanded_man_result_s4,
addition_cout_s4,
sign_1_s5,
sign_2_s5,
diff_signs,
rounding_bit_s5,
exp_greater_s5,
expanded_man_result_s5,
addition_cout_s5,
complemented_expanded_man_result_s5,
man_result_s5,
exp_result_s5,
sign_1_s6,
sign_2_s6,
man_1_s6,
man_2_s6,
man_greater_s6,
expanded_man_result_s6,
complemented_expanded_man_result_s6,
sign_result_s6,
man_result,
exp_result,
sign_result) is
begin
enable_in <= enable;
reset_in <= reset;
clk_in <= clk;
number_1 <= number_1_in;
number_2 <= number_2_in;
result <= sign_result & exp_result & man_result;
end process;
end;
|
gpl-3.0
|
0f0d2cda6f1925a509f1ad5b97a5b61f
| 0.617686 | 2.76388 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/components/vga_controller.vhd
| 1 | 6,547 |
--------------------------------------------------------------------------
-- Modulo: Controlador VGA
-- Descripci?n:
-- Autor: Sistemas Digitales (66.17)
-- Universidad de Buenos Aires - Facultad de Ingenier?a
-- www.campus.fi.uba.ar
-- Fecha: 16/04/13
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity vga_ctrl is
port (
mclk: in std_logic;
red_i: in std_logic;
grn_i: in std_logic;
blu_i: in std_logic;
hs: out std_logic;
vs: out std_logic;
red_o: out std_logic_vector(2 downto 0);
grn_o: out std_logic_vector(2 downto 0);
blu_o: out std_logic_vector(1 downto 0);
pixel_row: out std_logic_vector(9 downto 0);
pixel_col: out std_logic_vector(9 downto 0)
);
attribute loc: string;
-- Mapeo de pines para el kit Nexys 2 (spartan 3E)
attribute loc of mclk: signal is "B8";
attribute loc of red_i: signal is "K18";
attribute loc of grn_i: signal is "H18";
attribute loc of blu_i: signal is "G18";
attribute loc of hs: signal is "T4";
attribute loc of vs: signal is "U3";
attribute loc of red_o: signal is "R8 T8 R9";
attribute loc of grn_o: signal is "P6 P8 N8";
attribute loc of blu_o: signal is "U4 U5";
-- Mapeo de pines para el kit spartan 3E
-- attribute loc of mclk: signal is "C9";
-- attribute loc of red_i: signal is "H18";
-- attribute loc of grn_i: signal is "L14";
-- attribute loc of blu_i: signal is "L13";
-- attribute loc of hs: signal is "F15";
-- attribute loc of vs: signal is "F14";
-- attribute loc of red_o: signal is "H14";
-- attribute loc of grn_o: signal is "H15";
-- attribute loc of blu_o: signal is "G15";
-- Mapeo de pines para el kit spartan 3
-- attribute loc of mclk: signal is "T9";
-- attribute loc of red_in: signal is "K13";
-- attribute loc of grn_in: signal is "K14";
-- attribute loc of blu_in: signal is "J13";
-- attribute loc of hs: signal is "R9";
-- attribute loc of vs: signal is "T10";
-- attribute loc of red_out: signal is "R12";
-- attribute loc of grn_out: signal is "T12";
-- attribute loc of blu_out: signal is "R11";
end vga_ctrl;
architecture vga_ctrl_arq of vga_ctrl is
-- Numero de pixeles en una linea horizontal (800)
constant hpixels: unsigned(9 downto 0) := "1100100000";
-- Numero de lineas horizontales en el display (521)
constant vlines: unsigned(9 downto 0) := "1000001001";
constant hbp: unsigned(9 downto 0) := "0010010000"; -- Back porch horizontal (144)
constant hfp: unsigned(9 downto 0) := "1100010000"; -- Front porch horizontal (784)
constant vbp: unsigned(9 downto 0) := "0000011111"; -- Back porch vertical (31)
constant vfp: unsigned(9 downto 0) := "0111111111"; -- Front porch vertical (511)
-- Contadores (horizontal y vertical)
signal hc, vc: unsigned(9 downto 0);
-- Flag para obtener una habilitaci?n cada dos ciclos de clock
signal clkdiv_flag: std_logic;
-- Senal para habilitar la visualizaci?n de datos
signal vidon: std_logic;
-- Senal para habilitar el contador vertical
signal vsenable: std_logic;
begin
-- Divisi?n de la frecuencia del reloj
process(mclk)
begin
if rising_edge(mclk) then
clkdiv_flag <= not clkdiv_flag;
end if;
end process;
-- Contador horizontal
process(mclk)
begin
if rising_edge(mclk) then
if clkdiv_flag = '1' then
if hc = hpixels then
hc <= (others => '0'); -- El cont horiz se resetea cuando alcanza la cuenta m?xima de pixeles
vsenable <= '1'; -- Habilitaci?n del cont vert
else
hc <= hc + 1; -- Incremento del cont horiz
vsenable <= '0'; -- El cont vert se mantiene deshabilitado
end if;
end if;
end if;
end process;
-- Contador vertical
process(mclk)
begin
if rising_edge(mclk) then
if clkdiv_flag = '1' then -- Flag que habilita la operaci?n una vez cada dos ciclos (25 MHz)
if vsenable = '1' then -- Cuando el cont horiz llega al m?ximo de su cuenta habilita al cont vert
if vc = vlines then
vc <= (others => '0'); -- El cont vert se resetea cuando alcanza la cantidad maxima de lineas
else
vc <= vc + 1; -- Incremento del cont vert
end if;
end if;
end if;
end if;
end process;
-- hs <= '1' when (hc(9 downto 7) = "000") else '0';
-- vs <= '1' when (vc(9 downto 1) = "000000000") else '0';
hs <= '1' when (hc < "0001100001") else '0'; -- Generaci?n de la se?al de sincronismo horizontal
vs <= '1' when (vc < "0000000011") else '0'; -- Generaci?n de la se?al de sincronismo vertical
pixel_col <= std_logic_vector(hc - 144) when (vidon = '1') else std_logic_vector(hc);
pixel_row <= std_logic_vector(vc - 31) when (vidon = '1') else std_logic_vector(vc);
-- Habilitaci?n de la salida de datos por el display cuando se encuentra entre los porches
vidon <= '1' when (((hc < hfp) and (hc > hbp)) and ((vc < vfp) and (vc > vbp))) else '0';
-- Ejemplos
-- Los colores est?n comandados por los switches de entrada del kit
-- Dibuja un cuadrado rojo
red_o <= (others => '1') when ((hc(9 downto 6) = "0111") and vc(9 downto 6) = "0100" and red_i = '1' and vidon ='1') else (others => '0');
-- Dibuja una linea roja (valor espec?fico del contador horizontal
-- red_o <= '1' when (hc = "1010101100" and red_i = '1' and vidon ='1') else '0';
-- Dibuja una linea verde (valor espec?fico del contador horizontal)
grn_o <= (others => '1') when (hc = "0100000100" and grn_i = '1' and vidon ='1') else (others => '0');
-- Dibuja una linea azul (valor espec?fico del contador vertical)
blu_o <= (others => '1') when (vc = "0100100001" and blu_i = '1' and vidon ='1') else (others => '0');
-- Pinta la pantalla del color formado por la combinaci?n de las entradas red_i, grn_i y blu_i (switches)
-- red_o <= '1' when (red_i = '1' and vidon = '1') else '0';
-- grn_o <= '1' when (grn_i = '1' and vidon = '1') else '0';
-- blu_o <= '1' when (blu_i = '1' and vidon = '1') else '0';
end vga_ctrl_arq;
|
gpl-3.0
|
13494095c4bac29d2daca3cf16a25ba2
| 0.5766 | 3.388716 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/multiplication/class_adder/class_adder.vhd
| 1 | 681 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity class_adder is
generic(N: integer:= 4);
port(
number1_in: in std_logic_vector(N-1 downto 0);
number2_in: in std_logic_vector(N-1 downto 0);
cin: in std_logic;
result: out std_logic_vector(N-1 downto 0);
cout: out std_logic
);
end;
architecture class_adder_arq of class_adder is
signal aux: signed (N+1 downto 0) := to_signed(0, N+2);
begin
aux <= ('0' & signed(number1_in) & cin) + ('0' & signed(number2_in) & '1');
result <= std_logic_vector( aux (N downto 1) );
cout <= aux (N+1);
end;
|
gpl-3.0
|
af209cc0521e7fefc155345de287851b
| 0.562408 | 3.053812 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/expanded_mantissa_adder/expanded_mantissa_adder.vhd
| 1 | 1,381 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--STEP 4
--This component takes 2 mantissas that were already equalized and adds them
entity expanded_mantissa_adder is
generic(
BITS : natural := 16
);
port(
man_1_in : in std_logic_vector(BITS - 1 downto 0);
man_2_in : in std_logic_vector(BITS - 1 downto 0);
result : out std_logic_vector(BITS - 1 downto 0);
cout : out std_logic
);
end expanded_mantissa_adder;
architecture expanded_mantissa_adder_arq of expanded_mantissa_adder is
signal sum_result : std_logic_vector(BITS - 1 downto 0) := (others => '0');
signal result_carry : std_logic := '0';
component class_adder is
generic(N: integer:= 4);
port(
number1_in: in std_logic_vector(N-1 downto 0);
number2_in: in std_logic_vector(N-1 downto 0);
cin: in std_logic;
result: out std_logic_vector(N-1 downto 0);
cout: out std_logic
);
end component;
for adder_0 : class_adder use entity work.class_adder;
begin
adder_0 : class_adder
generic map(N => BITS)
port map(
number1_in => man_1_in,
number2_in => man_2_in,
cin => '0',
result => sum_result,
cout => result_carry
);
process(man_1_in,man_2_in,sum_result,result_carry) is
begin
result <= sum_result;
cout <= result_carry;
end process;
end architecture;
|
gpl-3.0
|
7bbc1465076b476b5803b9096632b1e7
| 0.638668 | 3.008715 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/number_shifter/number_shifter.vhd
| 1 | 1,604 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--STEP 3
--This component shifts the number so that exponents match and completes the new bits with 1's or 0's according to signs
entity number_shifter is
generic(
BITS : natural := 32;
EXP_BITS : natural := 6
);
port(
sign_1_in : in std_logic;
sign_2_in : in std_logic;
greater_exp : in std_logic_vector(EXP_BITS - 1 downto 0);
smaller_exp : in std_logic_vector(EXP_BITS - 1 downto 0);
man_in : in std_logic_vector(BITS - 1 downto 0);
man_out : out std_logic_vector(BITS - 1 downto 0);
rounding_bit : out std_logic
);
end number_shifter;
architecture number_shifter_arq of number_shifter is
begin
process(sign_1_in, sign_2_in,greater_exp,smaller_exp, man_in) is
variable number_to_shift : std_logic_vector(BITS downto 0) := (others => '0'); --one more for the rounding bit
variable shifted_number : std_logic_vector(BITS downto 0) := (others => '0'); --one more for the rounding bit
variable shifting_difference : integer := 0;
begin
shifting_difference := to_integer(unsigned(greater_exp) - unsigned(smaller_exp));
number_to_shift := man_in & '0';
shifted_number := std_logic_vector(shift_right(unsigned(number_to_shift), shifting_difference));
if (sign_1_in /= sign_2_in) then
if(BITS + 1 >= shifting_difference) then
shifted_number(BITS downto BITS + 1 - shifting_difference) := (others => '1');
else
shifted_number := (others => '1');
end if;
end if;
man_out <= shifted_number(BITS downto 1);
rounding_bit <= shifted_number(0);
end process;
end;
|
gpl-3.0
|
4269f8a3c3551f7372ac9daf05ee044a
| 0.678928 | 3.084615 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/tb_find_correct_errors_n_v2.vhd
| 1 | 27,374 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Find_Correct_Errors_N_v2
-- Module Name: Tb_Find_Correct_Errors_N_v2
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Test bench for find_correct_errors_n and polynomial_evaluator_n_v2 circuits.
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- number_of_pipelines :
--
-- Number of pipelines used in the circuit to test the support elements and
-- correct the message. Each pipeline needs at least 2 memory ram to store
-- intermediate results.
--
-- pipeline_size :
--
-- The number of stages of the pipeline. More stages means more values of sigma
-- are tested at once.
--
-- size_pipeline_size :
--
-- The number of bits necessary to store the size of the pipeline.
-- This is ceil(log2(pipeline_size))
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- length_support_elements :
--
-- The number of support elements. This parameter depends of the Goppa code used.
--
-- size_support_elements :
--
-- The size of the memory that holds all support elements. This parameter
-- depends of the Goppa code used.
-- This is ceil(log2(length_support_elements))
--
-- x_memory_file :
--
-- File that holds the values to be evaluated on the polynomial. Support elements L.
--
-- sigma_memory_file :
--
-- File that holds polynomial sigma coefficients.
--
-- resp_memory_file :
--
-- File that holds all evaluations of support L on polynomial sigma.
-- This file holds the output of the circuit,
-- it is needed to detect if polynomial evaluator circuit worked properly.
--
-- dump_acc_memory_file :
--
-- File that will hold the output of all support L evaluations on polynomial sigma,
-- that were done by the circuit.
--
-- codeword_memory_file :
--
-- File that holds the ciphertext that will be corrected according to the polynomial
-- sigma roots that were found.
--
-- message_memory_file :
--
-- File that holds the ciphertext already corrected.
-- This file is necessary to detect
-- if the ciphertext correction was performed correctly by the circuit.
--
-- dump_codeword_memory_file :
--
-- File that will hold the ciphertext corrected by the circuit.
--
-- dump_error_memory_file :
--
-- File that will hold the errors found on the ciphertext by the circuit.
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- find_and_correct_errors_n Rev 1.0
-- polynomial_evaluator_n_v2 Rev 1.0
-- ram Rev 1.0
-- ram_bank Rev 1.0
-- ram_double_bank Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_find_correct_errors_n_v2 is
Generic(
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 6;
-- sigma_degree : integer := 4;
-- size_sigma_degree : integer := 2;
-- length_support_elements: integer := 52;
-- size_support_elements : integer := 6;
-- x_memory_file : string := "mceliece/data_tests/L_classic_qdgoppa_52_28_4_6.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_classic_qdgoppa_52_28_4_6.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_classic_qdgoppa_52_28_4_6.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_classic_qdgoppa_52_28_4_6.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_classic_qdgoppa_52_28_4_6.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_classic_qdgoppa_52_28_4_6.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_classic_qdgoppa_52_28_4_6.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_classic_qdgoppa_52_28_4_6.dat"
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 28;
-- size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 11;
-- sigma_degree : integer := 27;
-- size_sigma_degree : integer := 5;
-- length_support_elements: integer := 2048;
-- size_support_elements : integer := 11;
-- x_memory_file : string := "mceliece/data_tests/L_goppa_2048_1751_27_11.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_2048_1751_27_11.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_goppa_2048_1751_27_11.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_goppa_2048_1751_27_11.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_goppa_2048_1751_27_11.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_goppa_2048_1751_27_11.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_goppa_2048_1751_27_11.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_goppa_2048_1751_27_11.dat"
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 7;
-- size_pipeline_size : integer := 3;
-- gf_2_m : integer range 1 to 20 := 11;
-- sigma_degree : integer := 50;
-- size_sigma_degree : integer := 6;
-- length_support_elements: integer := 2048;
-- size_support_elements : integer := 11;
-- x_memory_file : string := "mceliece/data_tests/L_goppa_2048_1498_50_11.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_2048_1498_50_11.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_goppa_2048_1498_50_11.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_goppa_2048_1498_50_11.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_goppa_2048_1498_50_11.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_goppa_2048_1498_50_11.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_goppa_2048_1498_50_11.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_goppa_2048_1498_50_11.dat"
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 7;
-- size_pipeline_size : integer := 3;
-- gf_2_m : integer range 1 to 20 := 12;
-- sigma_degree : integer := 66;
-- size_sigma_degree : integer := 7;
-- length_support_elements: integer := 3307;
-- size_support_elements : integer := 12;
-- x_memory_file : string := "mceliece/data_tests/L_goppa_3307_2515_66_12.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_3307_2515_66_12.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_goppa_3307_2515_66_12.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_goppa_3307_2515_66_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_goppa_3307_2515_66_12.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_goppa_3307_2515_66_12.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_goppa_3307_2515_66_12.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_goppa_3307_2515_66_12.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 33;
-- size_pipeline_size : integer := 6;
-- gf_2_m : integer range 1 to 20 := 12;
-- sigma_degree : integer := 32;
-- size_sigma_degree : integer := 6;
-- length_support_elements: integer := 2528;
-- size_support_elements : integer := 12;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_2528_2144_32_12.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_2528_2144_32_12.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_2528_2144_32_12.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_2528_2144_32_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_2528_2144_32_12.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2528_2144_32_12.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_2528_2144_32_12.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_2528_2144_32_12.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- sigma_degree : integer := 64;
-- size_sigma_degree : integer := 7;
-- length_support_elements: integer := 2816;
-- size_support_elements : integer := 12;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_2816_2048_64_12.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_2816_2048_64_12.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_2816_2048_64_12.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_2816_2048_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_2816_2048_64_12.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2816_2048_64_12.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_2816_2048_64_12.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- sigma_degree : integer := 64;
-- size_sigma_degree : integer := 7;
-- length_support_elements: integer := 3328;
-- size_support_elements : integer := 12;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_3328_2560_64_12.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_3328_2560_64_12.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_3328_2560_64_12.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_3328_2560_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_3328_2560_64_12.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_3328_2560_64_12.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_3328_2560_64_12.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
number_of_pipelines : integer := 1;
pipeline_size : integer := 130;
size_pipeline_size : integer := 8;
gf_2_m : integer range 1 to 20 := 13;
sigma_degree : integer := 128;
size_sigma_degree : integer := 8;
length_support_elements: integer := 7296;
size_support_elements : integer := 13;
x_memory_file : string := "mceliece/data_tests/L_qdgoppa_7296_5632_128_13.dat";
sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_7296_5632_128_13.dat";
resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_7296_5632_128_13.dat";
dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_7296_5632_128_13.dat";
codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_7296_5632_128_13.dat";
message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_7296_5632_128_13.dat";
dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_7296_5632_128_13.dat";
dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_7296_5632_128_13.dat"
);
end tb_find_correct_errors_n_v2;
architecture Behavioral of tb_find_correct_errors_n_v2 is
component ram
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component ram_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component ram_double_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component find_correct_errors_n
Generic (
number_of_pipelines : integer := 1;
gf_2_m : integer range 1 to 20 := 11;
pipeline_size : integer := 28;
length_support_elements: integer := 2048;
size_support_elements : integer := 11
);
Port(
value_message : in STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_evaluated : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
address_value_evaluated : in STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
enable_correction : in STD_LOGIC;
evaluation_finalized : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
correction_finalized : out STD_LOGIC;
address_new_value_message : out STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
address_value_error : out STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
write_enable_new_value_message : out STD_LOGIC;
write_enable_value_error : out STD_LOGIC;
new_value_message : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_error : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0)
);
end component;
component polynomial_evaluator_n_v2
Generic (
number_of_values_x : integer := 2048;
size_number_of_values_x : integer := 11;
polynomial_degree : integer := 27;
number_of_pipelines : integer := 1;
gf_2_m : integer range 1 to 20 := 11;
pipeline_size : integer := 28;
size_polynomial_degree : integer := 5;
size_pipeline_size : integer := 5
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_evaluations : out STD_LOGIC;
evaluation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_polynomial_degree - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal value_message : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal value_evaluated : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal address_value_evaluated : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal enable_correction : STD_LOGIC;
signal correction_finalized : STD_LOGIC;
signal address_new_value_message : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_value_error : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal write_enable_new_value_message : STD_LOGIC;
signal write_enable_value_error : STD_LOGIC;
signal new_value_message : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal value_error : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal value_x : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal value_polynomial : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal last_evaluations : STD_LOGIC;
signal evaluation_finalized : STD_LOGIC;
signal address_value_polynomial : STD_LOGIC_VECTOR((size_sigma_degree - 1) downto 0);
signal address_value_x : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_value_acc : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_new_value_acc : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal write_enable_new_value_acc : STD_LOGIC;
signal new_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
constant test_codeword_rst_value : std_logic_vector(0 downto 0) := (others => '0');
constant true_codeword_rst_value : std_logic_vector(0 downto 0) := (others => '0');
constant error_rst_value : std_logic_vector(0 downto 0) := (others => '0');
constant x_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
constant sigma_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
constant true_acc_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
constant test_acc_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
signal test_codeword_dump : std_logic := '0';
signal true_codeword_dump : std_logic := '0';
signal x_dump : std_logic := '0';
signal sigma_dump : std_logic := '0';
signal true_acc_dump : std_logic := '0';
signal test_acc_dump : std_logic := '0';
signal error_dump : std_logic := '0';
signal test_acc_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal true_acc_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal true_codeword_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal test_codeword_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal true_acc_value : STD_LOGIC_VECTOR (((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal true_codeword_value : STD_LOGIC_VECTOR ((number_of_pipelines - 1) downto 0);
signal error_acc : STD_LOGIC;
signal error_message : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
for true_codeword : ram_bank use entity work.ram_bank(file_load);
for test_codeword : ram_double_bank use entity work.ram_double_bank(file_load);
for x : ram_bank use entity work.ram_bank(file_load);
for sigma : ram use entity work.ram(file_load);
for true_acc : ram_bank use entity work.ram_bank(file_load);
for test_acc : ram_double_bank use entity work.ram_double_bank(simple);
for error : ram_bank use entity work.ram_bank(simple);
begin
test_codeword : ram_double_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => codeword_memory_file,
dump_file_name => dump_codeword_memory_file
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_message,
rw_a => '0',
rw_b => write_enable_new_value_message,
clk => clk,
rst => rst,
dump => test_codeword_dump,
address_a => test_codeword_address,
address_b => address_new_value_message,
rst_value => test_codeword_rst_value,
data_out_a => value_message,
data_out_b => open
);
error : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => "",
dump_file_name => dump_error_memory_file
)
Port Map(
data_in => value_error,
rw => write_enable_value_error,
clk => clk,
rst => rst,
dump => error_dump,
address => address_value_error,
rst_value => error_rst_value,
data_out => open
);
true_codeword : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => message_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => true_codeword_dump,
address => true_codeword_address,
rst_value => true_codeword_rst_value,
data_out => true_codeword_value
);
x : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => x_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => x_dump,
address => address_value_x,
rst_value => x_rst_value,
data_out => value_x
);
true_acc : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => resp_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => true_acc_dump,
address => true_acc_address,
rst_value => true_acc_rst_value,
data_out => true_acc_value
);
test_acc : ram_double_bank
Generic Map(
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => dump_acc_memory_file
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_acc,
rw_a => '0',
rw_b => write_enable_new_value_acc,
clk => clk,
rst => rst,
dump => test_acc_dump,
address_a => test_acc_address,
address_b => address_new_value_acc,
rst_value => test_acc_rst_value,
data_out_a => value_acc,
data_out_b => open
);
sigma : ram
Generic Map (
ram_address_size => size_sigma_degree,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => sigma_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => sigma_dump,
address => address_value_polynomial,
rst_value => sigma_rst_value,
data_out => value_polynomial
);
test : find_correct_errors_n
Generic Map(
number_of_pipelines => number_of_pipelines,
gf_2_m => gf_2_m,
pipeline_size => pipeline_size,
length_support_elements => length_support_elements,
size_support_elements => size_support_elements
)
Port Map(
value_message => value_message,
value_evaluated => value_evaluated,
address_value_evaluated => address_value_evaluated,
enable_correction => enable_correction,
evaluation_finalized => evaluation_finalized,
clk => clk,
rst => rst,
correction_finalized => correction_finalized,
address_new_value_message => address_new_value_message,
address_value_error => address_value_error,
write_enable_new_value_message => write_enable_new_value_message,
write_enable_value_error => write_enable_value_error,
new_value_message => new_value_message,
value_error => value_error
);
poly : polynomial_evaluator_n_v2
Generic Map(
number_of_values_x => length_support_elements,
size_number_of_values_x => size_support_elements,
polynomial_degree => sigma_degree,
number_of_pipelines => number_of_pipelines,
gf_2_m => gf_2_m,
pipeline_size => pipeline_size,
size_polynomial_degree => size_sigma_degree,
size_pipeline_size => size_pipeline_size
)
Port Map(
value_x => value_x,
value_acc => value_acc,
value_polynomial => value_polynomial,
clk => clk,
rst => rst,
last_evaluations => last_evaluations,
evaluation_finalized => evaluation_finalized,
address_value_polynomial => address_value_polynomial,
address_value_x => address_value_x,
address_value_acc => address_value_acc,
address_new_value_acc => address_new_value_acc,
write_enable_new_value_acc => write_enable_new_value_acc,
new_value_acc => new_value_acc
);
value_evaluated <= new_value_acc;
address_value_evaluated <= address_new_value_acc;
enable_correction <= last_evaluations;
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
test_acc_address <= address_value_acc when correction_finalized = '0' else
true_acc_address;
test_codeword_address <= address_value_x when correction_finalized = '0' else
true_codeword_address;
process
variable i : integer;
begin
true_acc_address <= (others => '0');
true_codeword_address <= (others => '0');
rst <= '1';
error_acc <= '0';
error_message <= '0';
wait for PERIOD*2;
rst <= '0';
wait until correction_finalized = '1';
report "Circuit finish = " & integer'image((cycle_count - 2)/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (length_support_elements)) loop
error_message <= '0';
error_acc <= '0';
true_acc_address <= std_logic_vector(to_unsigned(i, true_acc_address'Length));
true_codeword_address <= std_logic_vector(to_unsigned(i, true_codeword_address'Length));
wait for PERIOD*2;
if (true_acc_value = value_acc) then
error_acc <= '0';
else
error_acc <= '1';
report "Computed values do not match expected ones";
end if;
if (true_codeword_value = value_message) then
error_message <= '0';
else
error_message <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
error_acc <= '0';
error_message <= '0';
wait for PERIOD;
i := i + number_of_pipelines;
end loop;
error_message <= '0';
error_acc <= '0';
test_acc_dump <= '1';
test_codeword_dump <= '1';
wait for PERIOD;
test_acc_dump <= '0';
test_codeword_dump <= '0';
test_bench_finish <= '1';
wait;
end process;
end Behavioral;
|
bsd-2-clause
|
d67b24d8a6908f6738bdad9bd28aa5fd
| 0.671586 | 2.899788 | false | true | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/multiplier/multiplier.vhd
| 1 | 2,200 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiplier is
port(
op_1_in: in std_logic_vector(31 downto 0) := (others => '0');
op_2_in: in std_logic_vector(31 downto 0) := (others => '0');
result_out: out std_logic_vector(63 downto 0) := (others => '0')
);
end multiplier;
architecture multiplier_arq of multiplier is
begin
process(op_1_in, op_2_in)
variable op_1_h : unsigned(15 downto 0) := (others => '0');
variable op_1_l : unsigned(15 downto 0) := (others => '0');
variable op_2_h : unsigned(15 downto 0) := (others => '0');
variable op_2_l : unsigned(15 downto 0) := (others => '0');
variable result_ll : unsigned(63 downto 0) := (others => '0');
variable result_lh : unsigned(63 downto 0) := (others => '0');
variable result_hl : unsigned(63 downto 0) := (others => '0');
variable result_hh : unsigned(63 downto 0) := (others => '0');
begin
op_1_l := unsigned(op_1_in(15 downto 0));
op_1_h := unsigned(op_1_in(31 downto 16));
op_2_l := unsigned(op_2_in(15 downto 0));
op_2_h := unsigned(op_2_in(31 downto 16));
--report "OP1L: " & integer'image(to_integer(op_1_l));
--report "OP1H: " & integer'image(to_integer(op_1_h));
--report "OP2L: " & integer'image(to_integer(op_2_l));
--report "OP2H: " & integer'image(to_integer(op_2_h));
result_ll := "00000000000000000000000000000000" & (op_1_l * op_2_l);
result_lh := shift_left("00000000000000000000000000000000" & (op_1_l * op_2_h), 16);
result_hl := shift_left("00000000000000000000000000000000" & (op_1_h * op_2_l), 16);
result_hh := shift_left("00000000000000000000000000000000" & (op_1_h * op_2_h), 32);
--report "LL: " & integer'image(to_integer(result_ll));
--report "LH: " & integer'image(to_integer(result_lh));
--report "HL: " & integer'image(to_integer(result_hl));
--report "HH: " & integer'image(to_integer(result_hh));
result_out <= std_logic_vector(result_ll + result_lh + result_hl + result_hh);
end process;
end architecture;
|
gpl-3.0
|
6f648bd6daca0628a383de1e9ceabdd8
| 0.578636 | 3.179191 | false | false | false | false |
laurivosandi/hdl
|
arithmetic/src/conditional_sum_adder.vhd
| 1 | 3,147 |
library ieee;
use ieee.std_logic_1164.all;
entity conditonal_sum_adder is
port (
a : in std_logic_vector (7 downto 0);
b : in std_logic_vector (7 downto 0);
s : out std_logic_vector (7 downto 0));
end conditonal_sum_adder;
architecture behavioral of conditonal_sum_adder is
-- Carries
signal c0 : std_logic_vector(7 downto 0);
signal c1 : std_logic_vector(7 downto 0);
signal d0 : std_logic_vector(3 downto 0);
signal d1 : std_logic_vector(3 downto 0);
signal e0 : std_logic_vector(1 downto 0);
signal e1 : std_logic_vector(1 downto 0);
-- Sums
signal s0 : std_logic_vector(7 downto 1);
signal s1 : std_logic_vector(7 downto 1);
signal t0 : std_logic_vector(7 downto 0);
signal t1 : std_logic_vector(7 downto 0);
signal u0 : std_logic_vector(4 downto 0);
signal u1 : std_logic_vector(4 downto 0);
signal v : std_logic_vector(4 downto 0);
begin
-- Result generators
s(0) <= a(0) xor b(0);
c0(0) <= a(0) and b(0);
c1(0) <= c0(0);
rg_loop: for i in 1 to 7 generate
s0(i) <= a(i) xor b(i);
s1(i) <= not s0(i);
c0(i) <= a(i) and b(i);
c1(i) <= a(i) or b(i);
end generate;
-- First stage carry selectors
d1(3) <= (c1(6) and c1(7)) or (not c1(6) and c0(7));
d0(3) <= (c0(6) and c1(7)) or (not c0(6) and c0(7));
d1(2) <= (c1(4) and c1(5)) or (not c1(4) and c0(5));
d0(2) <= (c0(4) and c1(5)) or (not c0(4) and c0(5));
d1(1) <= (c1(2) and c1(3)) or (not c1(2) and c0(3));
d0(1) <= (c0(2) and c1(3)) or (not c0(2) and c0(3));
d1(0) <= (c1(0) and c1(1)) or (not c1(0) and c0(1));
d0(0) <= (c0(0) and c1(1)) or (not c0(0) and c0(1));
-- Second stage carry selectors
e1(1) <= (d1(2) and d1(3)) or (not d1(2) and d0(3));
e0(1) <= (d0(2) and d1(3)) or (not d0(2) and d0(3));
e1(0) <= (d1(0) and d1(1)) or (not d1(0) and d0(1));
e0(0) <= (d0(0) and d1(1)) or (not d0(0) and d0(1));
-- First stage sum selectors
t1(3) <= (c1(6) and s1(7)) or (not c1(6) and s0(7));
t0(3) <= (c0(6) and s1(7)) or (not c0(6) and s0(7));
t1(2) <= (c1(4) and s1(5)) or (not c1(4) and s0(5));
t0(2) <= (c0(4) and s1(5)) or (not c0(4) and s0(5));
t1(1) <= (c1(2) and s1(3)) or (not c1(2) and s0(3));
t0(1) <= (c0(2) and s1(3)) or (not c0(2) and s0(3));
t1(0) <= (c1(0) and s1(1)) or (not c1(0) and s0(1));
s(1) <= (c0(0) and s1(1)) or (not c0(0) and s0(1));
-- Second stage sum selectors
u1(3) <= (d1(2) and t1(3)) or (not d1(2) and t0(3));
u0(3) <= (d0(2) and t1(3)) or (not d0(2) and t0(3));
u1(2) <= (d1(2) and s1(6)) or (not d1(2) and s0(6));
u0(2) <= (d0(2) and s1(6)) or (not d0(2) and s0(6));
s(3) <= (d0(0) and t1(1)) or (not d0(0) and t0(1));
s(2) <= (d0(0) and s1(2)) or (not d0(0) and s0(2));
-- Third stage sum selectors
s(7) <= (e0(0) and u1(3)) or (not e0(0) and u0(3));
s(6) <= (e0(0) and u1(2)) or (not e0(0) and u0(2));
s(5) <= (e0(0) and t1(2)) or (not e0(0) and t0(2));
s(4) <= (e0(0) and s1(4)) or (not e0(0) and s0(4));
end behavioral;
|
mit
|
54acc7efc0a7d8ed108f1d57bf6a270d
| 0.516365 | 2.171843 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
USB_TEST/USB_RAM_BUFFER.vhd
| 1 | 6,926 |
--FPGA application for this system.
--copyright(c) 2014 dtysky
--This program is free software; you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation; either version 2 of the License, or
--(at your option) any later version.
--This program is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License along
--with this program; if not, write to the Free Software Foundation, Inc.,
--51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
------------------------------------------------------------------------
--数据传输结束确定后进入LOCK状态，usb_end置1
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity USB_RAM_BUFFER is
port
(
inclk:in std_logic;
usb_clk:out std_logic;
usb_full,usb_empty:in std_logic;
sloe:out std_logic:='0';
slrd,pktend:out std_logic:='0';
slwr:out std_logic:='0';
fifoadr:out std_logic_vector(1 downto 0);
usb_data:inout std_logic_vector(15 downto 0);
pc_rqu:in std_logic;
usb_in:in std_logic
);
end entity;
architecture bufferx of usb_RAM_BUFFER is
component PLL is
port
(
inclk0:in std_logic;
c0,c1,c2,c3:out std_logic;
locked:out std_logic
);
end component;
component FIFO_TO_OTHER is
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end component;
component COUNTER_TIMEOUT IS
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
end component;
----------------Clock------------------
signal clk_usb_p,clk_usb_n,clk_usb_90,clk_usb_270,clk_usb_lock:std_logic;
----------------fifo例化----------------
signal data_to_ram:std_logic_vector(15 downto 0);
signal fifo_utr_write,fifo_utr_read:std_logic:='0';
signal fifo_utr_aclr:std_logic:='0';
signal data_from_usb:std_logic_vector(7 downto 0);
signal data_to_usb:std_logic_vector(15 downto 0);
--------------fifo已写/可读数据-----------
signal fifo_utr_num_w:std_logic_vector(9 downto 0);
signal fifo_utr_num_r:std_logic_vector(8 downto 0);
signal fifo_utr_num_w_buffer:std_logic_vector(9 downto 0);
signal fifo_utr_num_r_buffer:std_logic_vector(8 downto 0);
----------------pc cmd------------------
signal command:std_logic_vector(15 downto 0);
------------------usb-------------------
signal usb_in_rqu,usb_out_rqu:std_logic:='0';
signal usb_in_rqu_last:std_logic:='0';
signal usb_in_ready,usb_out_ready:std_logic:='0';
signal usb_in_ready_last,usb_out_ready_last:std_logic:='0';
signal usb_in_allow:std_logic:='0';
signal usb_out_allow:std_logic:='0';
signal usb_check:std_logic_vector(15 downto 0);
------------------timeout----------------
signal timeout_aclr:std_logic:='1';
signal timeout_clken:std_logic:='0';
signal timeout_q:std_logic_vector(11 downto 0);
signal timeout_buffer:std_logic_vector(11 downto 0);
-----------------flags-------------------
type ustates is (free,full,ack,rd,reset,lock);
signal usb_state,usb_state_buffer:ustates:=free;
begin
usb_clk<=clk_usb_270;
PLL_1:PLL
port map
(
inclk0=>inclk,
c0=>clk_usb_p,c1=>clk_usb_90,c2=>clk_usb_n,c3=>clk_usb_270,
locked=>clk_usb_lock
);
buffer_usb:FIFO_TO_OTHER
port map
(
aclr=>fifo_utr_aclr,
data=>data_from_usb,q(7 downto 0)=>data_to_ram(15 downto 8),q(15 downto 8)=>data_to_ram(7 downto 0),
wrclk=>clk_usb_270,rdclk=>clk_usb_270,
wrreq=>fifo_utr_write,rdreq=>fifo_utr_read,
wrusedw=>fifo_utr_num_w,rdusedw=>fifo_utr_num_r
);
timeout:COUNTER_TIMEOUT
port map
(
aclr=>timeout_aclr,
clk_en=>timeout_clken,
clock=>clk_usb_n,
q=>timeout_q
);
--------------USB------------
usb_control:process(clk_usb_p,clk_usb_lock)
variable con_full:integer range 0 to 7:=0;
variable con_ack:integer range 0 to 7:=0;
begin
if clk_usb_p'event and clk_usb_p='1' and clk_usb_lock='1' then
case usb_state is
-----------IDLE------------
when free =>
usb_data<="ZZZZZZZZZZZZZZZZ";
if usb_full='1' then
usb_state<=full;
else
usb_state<=free;
end if;
-----------FULL------------
when full =>
case con_full is
when 0 =>
fifo_utr_aclr<='0';
fifo_utr_write<='0';
sloe<='0';
slrd<='0';
fifoadr<="00";
con_full:=con_full+1;
when 1 =>
sloe<='1';
con_full:=con_full+1;
when 2 =>
con_full:=con_full+1;
when 3 =>
slrd<='1';
fifo_utr_write<='1';
con_full:=con_full+1;
when others =>
case fifo_utr_num_w_buffer is
when "0111111101" =>
usb_check(7 downto 0)<=usb_data(7 downto 0);
when "0111111110" =>
usb_check(15 downto 8)<=usb_data(7 downto 0);
sloe<='0';
slrd<='0';
fifo_utr_write<='0';
when "1000000000" =>
usb_state<=ack;
con_full:=0;
when others =>
fifo_utr_write<=fifo_utr_write;
end case;
end case;
-------------RD-------------
-- when rd =>
--
-- if fifo_utr_num_r="100000000" then
-- fifo_utr_read<='1';
-- elsif fifo_utr_num_r="000000000" then
-- fifo_utr_read<='0';
-- usb_state<=ack;
-- end if;
-------------ACK------------
when ack =>
case con_ack is
when 0 =>
fifoadr<="10";
slwr<='0';
pktend<='0';
con_ack:=con_ack+1;
when 2 =>
slwr<='1';
usb_data(7 downto 0)<=usb_check(7 downto 0);
con_ack:=con_ack+1;
when 3=>
usb_data(7 downto 0)<=usb_check(15 downto 8);
con_ack:=con_ack+1;
when 4 =>
slwr<='0';
pktend<='1';
con_ack:=con_ack+1;
when 5 =>
pktend<='0';
fifo_utr_aclr<='1';
usb_state<=free;
con_ack:=0;
when others =>
con_ack:=con_ack+1;
end case;
-----------RESET-----------
when reset =>
con_full:=0;
con_ack:=0;
slwr<='0';
fifo_utr_aclr<='1';
usb_state<=free;
-----------LOCK------------
when lock =>
fifo_utr_aclr<='1';
-----------ERROR-----------
when others =>
usb_state<=reset;
end case;
fifo_utr_num_w_buffer<=fifo_utr_num_w;
end if;
end process;
data_from_usb<=usb_data(7 downto 0);
--data_from_usb(15 downto 8)<=usb_data_in(7 downto 0);
end bufferx;
|
gpl-2.0
|
dd51c1f9323c76be79c473b8d1788b35
| 0.573983 | 2.93766 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/counter_load_rst_nbits.vhd
| 1 | 2,044 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_load_rst_n_bits
-- Module Name: Counter_load_rst_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Counter of size bits with reset signal, that only increments when ce equals to 1.
-- The reset is synchronous and the value loaded during reset is defined by reset_value.
-- The counter has a synchronous load signal, which will register the value on input d,
-- when load is 1 and reset is 0.
--
-- The circuits parameters
--
-- size :
--
-- The size of the counter in bits.
--
-- increment_value :
--
-- The amount will be incremented each cycle.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_load_rst_nbits is
Generic (
size : integer;
increment_value : integer
);
Port (
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
load : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end counter_load_rst_nbits;
architecture Behavioral of counter_load_rst_nbits is
signal internal_value : unsigned((size - 1) downto 0);
begin
process(clk, ce, load, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= unsigned(rst_value);
elsif(ce = '1') then
if(load = '1') then
internal_value <= unsigned(d);
else
internal_value <= internal_value + to_unsigned(increment_value, internal_value'Length);
end if;
else
null;
end if;
end if;
end process;
q <= std_logic_vector(internal_value);
end Behavioral;
|
bsd-2-clause
|
4d8b57b33d76366b518259c0fd933585
| 0.618885 | 3.384106 | false | false | false | false |
alainmarcel/Surelog
|
third_party/tests/ariane/fpga/src/apb_uart/src/slib_fifo.vhd
| 2 | 4,960 |
--
-- FIFO
--
-- Author: Sebastian Witt
-- Date: 29.01.2008
-- Version: 1.3
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_fifo is
generic (
WIDTH : integer := 8; -- FIFO width
SIZE_E : integer := 6 -- FIFO size (2^SIZE_E)
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear FIFO
WRITE : in std_logic; -- Write to FIFO
READ : in std_logic; -- Read from FIFO
D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input
Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output
EMPTY : out std_logic; -- FIFO is empty
FULL : out std_logic; -- FIFO is full
USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage
);
end slib_fifo;
architecture rtl of slib_fifo is
-- Signals
signal iEMPTY : std_logic; -- Internal EMPTY
signal iFULL : std_logic; -- Internal FULL
signal iWRAddr : unsigned(SIZE_E downto 0); -- FIFO write address
signal iRDAddr : unsigned(SIZE_E downto 0); -- FIFO read address
signal iUSAGE : unsigned(SIZE_E-1 downto 0); -- FIFO usage
-- FIFO memory
type FIFO_Mem_Type is array (2**SIZE_E-1 downto 0) of std_logic_vector(WIDTH-1 downto 0);
signal iFIFOMem : FIFO_Mem_Type := (others => (others => '0'));
begin
-- Full signal (biggest difference of read and write address)
iFULL <= '1' when (iRDAddr(SIZE_E-1 downto 0) = iWRAddr(SIZE_E-1 downto 0)) and
(iRDAddr(SIZE_E) /= iWRAddr(SIZE_E)) else '0';
-- Write/read address counter and empty signal
FF_ADDR: process (RST, CLK)
begin
if (RST = '1') then
iWRAddr <= (others => '0');
iRDAddr <= (others => '0');
iEMPTY <= '1';
elsif (CLK'event and CLK='1') then
if (WRITE = '1' and iFULL = '0') then -- Write to FIFO
iWRAddr <= iWRAddr + 1;
end if;
if (READ = '1' and iEMPTY = '0') then -- Read from FIFO
iRDAddr <= iRDAddr + 1;
end if;
if (CLEAR = '1') then -- Reset FIFO
iWRAddr <= (others => '0');
iRDAddr <= (others => '0');
end if;
if (iRDAddr = iWRAddr) then -- Empty signal (read address same as write address)
iEMPTY <= '1';
else
iEMPTY <= '0';
end if;
end if;
end process;
-- FIFO memory process
FF_MEM: process (RST, CLK)
begin
if (RST = '1') then
iFIFOMem(2**SIZE_E-1 downto 0) <= (others => (others => '0'));
Q <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (WRITE = '1' and iFULL = '0') then
iFIFOMem(to_integer(iWRAddr(SIZE_E-1 downto 0))) <= D;
end if;
Q <= iFIFOMem(to_integer(iRDAddr(SIZE_E-1 downto 0)));
end if;
end process;
-- Usage counter
FF_USAGE: process (RST, CLK)
begin
if (RST = '1') then
iUSAGE <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (CLEAR = '1') then
iUSAGE <= (others => '0');
else
if (READ = '0' and WRITE = '1' and iFULL = '0') then
iUSAGE <= iUSAGE + 1;
end if;
if (WRITE = '0' and READ = '1' and iEMPTY = '0') then
iUSAGE <= iUSAGE - 1;
end if;
end if;
end if;
end process;
-- Output signals
EMPTY <= iEMPTY;
FULL <= iFULL;
USAGE <= std_logic_vector(iUSAGE);
end rtl;
|
apache-2.0
|
858bf7e8a3a257082a7e2d9f444556b4
| 0.488105 | 4.171573 | false | false | false | false |
rajvinjamuri/ECE385_VHDL
|
edge_detector.vhd
| 1 | 1,816 |
---------------------------------------------------------------------------
-- edge-detector.vhd --
-- Raj Vinjamuri --
-- 3-13 --
-- --
-- Purpose/Description --
-- Takes FPGA clock and ps2Clk and outputs rising/falling/0/1 --
-- --
-- --
-- --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
-- --
-- --
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity edge_detector is
Port ( mod_Clk, ps2Clk : in std_logic;
status : out std_logic_vector(1 downto 0));
end edge_detector;
architecture Behavioral of edge_detector is
component Dreg is
port( D, clk, reset, ld: in std_logic;
Q : out std_logic);
end component Dreg;
signal chain : std_logic_vector(1 downto 0); --internal bus to hold outputs
begin
dff1: Dreg
port map( D => ps2Clk,
clk => mod_clk,
reset => '0',
ld => '1',
Q => chain(0)); --feeds into other d-ff
dff2: Dreg
port map( D => chain(0),
clk => mod_clk,
reset => '0',
ld => '1',
Q => chain(1));
status <= chain; --set output
end Behavioral;
|
mit
|
d208e771ec260d3186119554da90582e
| 0.345264 | 4.894879 | false | false | false | false |
andrecp/myhdl_simple_uart
|
generated_files/pck_myhdl_08.vhd
| 1 | 3,356 |
-- File: pck_myhdl_08.vhd
-- Generated by MyHDL 0.8
-- Date: Thu Aug 21 10:54:44 2014
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_08 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_logic;
function to_unsigned (arg: boolean; size: natural) return unsigned;
function to_signed (arg: boolean; size: natural) return signed;
function to_integer(arg: boolean) return integer;
function to_integer(arg: std_logic) return integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned;
function to_signed (arg: std_logic; size: natural) return signed;
function bool (arg: std_logic) return boolean;
function bool (arg: unsigned) return boolean;
function bool (arg: signed) return boolean;
function bool (arg: integer) return boolean;
function "-" (arg: unsigned) return signed;
end pck_myhdl_08;
package body pck_myhdl_08 is
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
end pck_myhdl_08;
|
mit
|
8d3595e843eb855eb407d41a8587fb0a
| 0.600715 | 4.023981 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/normalizer/normalizer_tb.vhd
| 1 | 2,461 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity normalizer_tb is
end entity;
architecture normalizer_tb_arq of normalizer_tb is
signal x_in : std_logic_vector(31 downto 0) := (others => '0');
signal y_in : std_logic_vector(31 downto 0) := (others => '0');
signal x_out : std_logic_vector(31 downto 0) := (others => '0');
signal y_out : std_logic_vector(31 downto 0) := (others => '0');
signal steps_applied : integer := 0;
component normalizer is
generic(TOTAL_BITS: integer := 32);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
steps_applied : in integer := 0;
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
begin
normalizer_0 : normalizer
generic map(TOTAL_BITS => 32)
port map(
x_in => x_in,
y_in => y_in,
steps_applied => steps_applied,
x_out => x_out,
y_out => y_out
);
process
type pattern_type is record
xi : std_logic_vector(31 downto 0);
yi : std_logic_vector(31 downto 0);
sa : integer;
xo : std_logic_vector(31 downto 0);
yo : std_logic_vector(31 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("00000000000000000000000000000000",
"00000000000000000000000000000000",
0,
"00000000000000000000000000000000",
"00000000000000000000000000000000"),
("00000000000000010000000000000000",
"00000000000000010000000000000000",
0,
"00000000000000000000000000000000",
"00000000000000000000000000000000"),
("00000000000000010000000000000000",
"00000000000000010000000000000000",
1,
"00000000000000001011010100000100",
"00000000000000001011010100000100")
);
begin
for i in patterns'range loop
-- Set the inputs.
x_in <= patterns(i).xi;
y_in <= patterns(i).yi;
steps_applied <= patterns(i).sa;
wait for 1 ns;
assert patterns(i).xo = x_out report "BAD X, GOT: " & integer'image(to_integer(signed(x_out)));
assert patterns(i).yo = y_out report "BAD Y, GOT: " & integer'image(to_integer(signed(y_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
7181b3467797115a20349d577d3944f4
| 0.655018 | 3.339213 | false | false | false | false |
rajvinjamuri/ECE385_VHDL
|
color_mapper.vhd
| 1 | 11,552 |
---------------------------------------------------------------------------
-- Color_Mapper.vhd --
-- Stephen Kempf, David Kesler, Raj Vinjamuri, Sai Koppula --
-- 4-13 --
-- --
-- For use with ECE 385 --
-- University of Illinois ECE Department --
-- --
-- --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Color_Mapper is
Port ( game_status : in std_logic_vector(3 downto 0);
BallX, BallY : in std_logic_vector(10 downto 0);
PaddleX, PaddleY : in std_logic_vector (10 downto 0);
BricksX, BricksY : in std_logic_vector(219 downto 0);
BricksOn : in std_logic_vector(19 downto 0);
DrawX, DrawY : in std_logic_vector(10 downto 0);
Ball_size : in std_logic_vector(10 downto 0);
Paddle_size : in std_logic_vector(10 downto 0);
-- Brick_size : in std_logic_vector(9 downto 0);
Red : out std_logic_vector(9 downto 0);
Green : out std_logic_vector(9 downto 0);
Blue : out std_logic_vector(9 downto 0));
end Color_Mapper;
architecture Behavioral of Color_Mapper is
signal Ball_on, Paddle_on, Brick_on : std_logic;
signal Brick_Width : std_logic_vector(10 downto 0);
signal Brick_Height : std_logic_vector(10 downto 0);
signal BrickX, BrickY : std_logic_vector(10 downto 0);
signal BrickOn : std_logic;
signal start , ender : natural;
--signal temp1, temp2 : std_logic_vector(9 downto 0) := CONV_STD_LOGIC_VECTOR(100, 10); --Step size on the Y axis (modified)
begin
Brick_Width <= CONV_STD_LOGIC_VECTOR(60, 11); -- assigns the value 4 as a 10-digit binary number, ie "0000000100"
Brick_Height <= CONV_STD_LOGIC_VECTOR(20, 11);
-----------------------------------------------------
Ball_on_proc : process (BallX, BallY, DrawX, DrawY, Ball_size)
begin
-- Old Ball: Generated square box by checking if the current pixel is within a square of length
-- 2*Ball_Size, centered at (BallX, BallY). Note that this requires unsigned comparisons, by using
-- IEEE.STD_LOGIC_UNSIGNED.ALL at the top.
-- if ((DrawX >= BallX - Ball_size) AND
-- (DrawX <= BallX + Ball_size) AND
-- (DrawY >= BallY - Ball_size) AND
-- (DrawY <= BallY + Ball_size)) then
-- New Ball: Generates (pixelated) circle by using the standard circle formula. Note that while
-- this single line is quite powerful descriptively, it causes the synthesis tool to use up three
-- of the 12 available multipliers on the chip! It also requires IEEE.STD_LOGIC_SIGNED.ALL for
-- the signed multiplication to operate correctly.
if ((((DrawX - BallX) * (DrawX - BallX)) + ((DrawY - BallY) * (DrawY - BallY))) <= (Ball_size*Ball_size)) then
Ball_on <= '1';
else
Ball_on <= '0';
end if;
end process Ball_on_proc;
-----------------------------------------------------
Paddle_on_proc : process (PaddleX, PaddleY, DrawX, DrawY, Paddle_size)
begin
if ((DrawX >= PaddleX - ("00000000110"*Paddle_size)) AND
(DrawX <= PaddleX + ("00000000110"*Paddle_size)) AND
(DrawY >= PaddleY - Paddle_size) AND
(DrawY <= PaddleY + Paddle_size)) then
Paddle_on <= '1';
else
Paddle_on <= '0';
end if;
end process Paddle_on_proc;
-----------------------------------------------------
-----------------------------------------------------
Brick_on_proc : process (BrickX, BrickY, DrawX, DrawY)
begin
Brick_On <= '0';
--for I in 0 to 19 loop
--start <= I*11+10;
--ender <= I*11;
--case I is
--when 0 =>
--BrickX <= BricksX(10 downto 0);
--BrickY <= BricksY(10 downto 0);
--BrickOn <= BricksOn(0);
--when others =>
--BrickX <= BricksX(219 downto 209);
--BrickY <= BricksY(219 downto 209);
--BrickOn <= BricksOn(19);
--end case;
--BrickX <= BricksX(10 downto 0);
--BrickY <= BricksY(10 downto 0);
--BrickOn <= BricksOn(0);
if (DrawX <= BricksX(10 downto 0) + Brick_Width) AND (DrawX >= BricksX(10 downto 0))
AND (DrawY>= BricksY(10 downto 0)) AND (DrawY<= BricksY(10 downto 0) + Brick_Height)
AND (BricksOn(0) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(21 downto 11) + Brick_Width) AND (DrawX >= BricksX(21 downto 11))
AND (DrawY>= BricksY(21 downto 11)) AND (DrawY<= BricksY(21 downto 11) + Brick_Height)
AND (BricksOn(1) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(32 downto 22) + Brick_Width) AND (DrawX >= BricksX(32 downto 22))
AND (DrawY>= BricksY(32 downto 22)) AND (DrawY<= BricksY(32 downto 22) + Brick_Height)
AND (BricksOn(2) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(43 downto 33) + Brick_Width) AND (DrawX >= BricksX(43 downto 33))
AND (DrawY>= BricksY(43 downto 33)) AND (DrawY<= BricksY(43 downto 33) + Brick_Height)
AND (BricksOn(3) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(54 downto 44) + Brick_Width) AND (DrawX >= BricksX(54 downto 44))
AND (DrawY>= BricksY(54 downto 44)) AND (DrawY<= BricksY(54 downto 44) + Brick_Height)
AND (BricksOn(4) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(65 downto 55) + Brick_Width) AND (DrawX >= BricksX(65 downto 55))
AND (DrawY>= BricksY(65 downto 55)) AND (DrawY<= BricksY(65 downto 55) + Brick_Height)
AND (BricksOn(5) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(76 downto 66) + Brick_Width) AND (DrawX >= BricksX(76 downto 66))
AND (DrawY>= BricksY(76 downto 66)) AND (DrawY<= BricksY(76 downto 66) + Brick_Height)
AND (BricksOn(6) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(87 downto 77) + Brick_Width) AND (DrawX >= BricksX(87 downto 77))
AND (DrawY>= BricksY(87 downto 77)) AND (DrawY<= BricksY(87 downto 77) + Brick_Height)
AND (BricksOn(7) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(98 downto 88) + Brick_Width) AND (DrawX >= BricksX(98 downto 88))
AND (DrawY>= BricksY(98 downto 88)) AND (DrawY<= BricksY(98 downto 88) + Brick_Height)
AND (BricksOn(8) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(109 downto 99) + Brick_Width) AND (DrawX >= BricksX(109 downto 99))
AND (DrawY>= BricksY(109 downto 99)) AND (DrawY<= BricksY(109 downto 99) + Brick_Height)
AND (BricksOn(9) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(120 downto 110) + Brick_Width) AND (DrawX >= BricksX(120 downto 110))
AND (DrawY>= BricksY(120 downto 110)) AND (DrawY<= BricksY(120 downto 110) + Brick_Height)
AND (BricksOn(10) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(131 downto 121) + Brick_Width) AND (DrawX >= BricksX(131 downto 121))
AND (DrawY>= BricksY(131 downto 121)) AND (DrawY<= BricksY(131 downto 121) + Brick_Height)
AND (BricksOn(11) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(142 downto 132) + Brick_Width) AND (DrawX >= BricksX(142 downto 132))
AND (DrawY>= BricksY(142 downto 132)) AND (DrawY<= BricksY(142 downto 132) + Brick_Height)
AND (BricksOn(12) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(153 downto 143) + Brick_Width) AND (DrawX >= BricksX(153 downto 143))
AND (DrawY>= BricksY(153 downto 143)) AND (DrawY<= BricksY(153 downto 143) + Brick_Height)
AND (BricksOn(13) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(164 downto 154) + Brick_Width) AND (DrawX >= BricksX(164 downto 154))
AND (DrawY>= BricksY(164 downto 154)) AND (DrawY<= BricksY(164 downto 154) + Brick_Height)
AND (BricksOn(14) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(175 downto 165) + Brick_Width) AND (DrawX >= BricksX(175 downto 165))
AND (DrawY>= BricksY(175 downto 165)) AND (DrawY<= BricksY(175 downto 165) + Brick_Height)
AND (BricksOn(15) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(186 downto 176) + Brick_Width) AND (DrawX >= BricksX(186 downto 176))
AND (DrawY>= BricksY(186 downto 176)) AND (DrawY<= BricksY(186 downto 176) + Brick_Height)
AND (BricksOn(16) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(197 downto 187) + Brick_Width) AND (DrawX >= BricksX(197 downto 187))
AND (DrawY>= BricksY(197 downto 187)) AND (DrawY<= BricksY(197 downto 187) + Brick_Height)
AND (BricksOn(17) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(208 downto 198) + Brick_Width) AND (DrawX >= BricksX(208 downto 198))
AND (DrawY>= BricksY(208 downto 198)) AND (DrawY<= BricksY(208 downto 198) + Brick_Height)
AND (BricksOn(18) = '1') then
Brick_On <= '1';
elsif (DrawX <= BricksX(219 downto 209) + Brick_Width) AND (DrawX >= BricksX(219 downto 209))
AND (DrawY>= BricksY(219 downto 209)) AND (DrawY<= BricksY(219 downto 209) + Brick_Height)
AND (BricksOn(19) = '1') then
Brick_On <= '1';
end if;
--end loop;
end process Brick_on_proc;
--
--
-----------------------------------------------------
RGB_Display : process (game_status, Ball_on, Paddle_on, Brick_on, DrawX, DrawY)
variable GreenVar, BlueVar : std_logic_vector(22 downto 0);
begin
if (Ball_on = '1') AND
(Paddle_on = '0') then -- turn ball on display --ball
if (game_status(0) = '0') then
Red <= "0101010101";
Green <= "1010101010";
Blue <= "1010101010";
else --change ball to black if lost
Red <= "0000000000";
Green <= "0000000000";
Blue <= "0000000000";
end if;
elsif (Paddle_on = '1') then -- turn paddle on display --paddle
if (game_status(0) = '0') then
Red <= "0000000000";
Green <= "1001100010";
Blue <= "0000000000";
else --change paddle to red if lost
Red <= "1001100010";
Green <= "0000000000";
Blue <= "0000000000";
end if;
elsif (Brick_On = '1') then --turn brick on display --bricks
if (game_status(0) = '0') then
Red <= "1010101010";
Green <= "0101010101";
Blue <= "0000000000";
else --change brick to White if lost
Red <= "1010101010";
Green <= "1010101010";
Blue <= "1010101010";
end if;
else -- turn on gradient background --BG
if (game_status(3) = '1') then
Red <= DrawY(9 downto 0);
Green <= "0111100010";
Blue <= DrawY(9 downto 0);
elsif (game_status(0) = '0') then
Red <= DrawY(9 downto 0);
Green <= DrawY(9 downto 0);
Blue <= DrawY(9 downto 0);
else --change background to if lost
Red <= "0111100010";
Green <= DrawY(9 downto 0);
Blue <= DrawY(9 downto 0);
end if;
end if;
end process RGB_Display;
-----------------------------------------------------
end Behavioral;
------------Previous Code, saved for possible reuse ------------------
-- BrickX <= temp1;
-- BrickY <= temp1;
-- Brick_size <= "0000000100"
--
-- --already lose? put all Bricks back
-- if (game_statusSig = '1') then Brick_statusSig <= '0';
-- end if;
--
-- if ((DrawX >= BrickX - ("0000000100"*Brick_size)) AND
-- (DrawX <= BrickX + ("0000000100"*Brick_size)) AND
-- (DrawY >= BrickY - Brick_size) AND
-- (DrawY <= BrickY + Brick_size)) then
-- Brick_on <= '1';
-- else
-- Brick_on <= '0';
-- end if;
---------------------------------------------------------------------
|
mit
|
ca212842ebdb9e2b8dcd36328cc5957f
| 0.57661 | 3.388677 | false | false | false | false |
achan1989/In64
|
FPGA/SD_card_test.srcs/sources_1/ip/mig_v3_92_0/ATLYS_DDR/example_design/rtl/memc3_wrapper.vhd
| 1 | 47,271 |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port0 Interface Signals
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0) ;
p0_cmd_bl : in std_logic_vector(5 downto 0) ;
p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
-- Data Wr Port signals
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0) ;
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
--Data Rd Port signals
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0) ;
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
--User Port2 Interface Signals
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0) ;
p2_cmd_bl : in std_logic_vector(5 downto 0) ;
p2_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
--Data Rd Port signals
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0) ;
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0) ;
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "000101";
constant C_PORT_CONFIG : string := "B32_B32_R32_R32_R32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_92_ddr2_s6, Coregen 14.2";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr2_s6,mig_v3_92,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR2_SDRAM, CLK_PERIOD=3000, MEMORY_PART=mt47h64m16xx-25e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=FULL, RTT_NOM=50OHMS, DQS#_ENABLE=YES, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0_Port2, CLASS_ADDR=II, CLASS_DATA=II, INPUT_PIN_TERMINATION=CALIB_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => mcb3_dram_odt,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => mcb3_dram_dqs_n,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => mcb3_dram_udqs_n,
mcbx_dram_ddr3_rst => open,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '1',
p0_cmd_clk => p0_cmd_clk,
p0_cmd_en => p0_cmd_en,
p0_cmd_instr => p0_cmd_instr,
p0_cmd_bl => p0_cmd_bl,
p0_cmd_byte_addr => p0_cmd_byte_addr,
p0_cmd_empty => p0_cmd_empty,
p0_cmd_full => p0_cmd_full,
p0_wr_clk => p0_wr_clk,
p0_wr_en => p0_wr_en,
p0_wr_mask => p0_wr_mask,
p0_wr_data => p0_wr_data,
p0_wr_full => p0_wr_full,
p0_wr_empty => p0_wr_empty,
p0_wr_count => p0_wr_count,
p0_wr_underrun => p0_wr_underrun,
p0_wr_error => p0_wr_error,
p0_rd_clk => p0_rd_clk,
p0_rd_en => p0_rd_en,
p0_rd_data => p0_rd_data,
p0_rd_full => p0_rd_full,
p0_rd_empty => p0_rd_empty,
p0_rd_count => p0_rd_count,
p0_rd_overflow => p0_rd_overflow,
p0_rd_error => p0_rd_error,
p1_arb_en => '0',
p1_cmd_clk => '0',
p1_cmd_en => '0',
p1_cmd_instr => (others => '0'),
p1_cmd_bl => (others => '0'),
p1_cmd_byte_addr => (others => '0'),
p1_cmd_empty => open,
p1_cmd_full => open,
p1_rd_clk => '0',
p1_rd_en => '0',
p1_rd_data => open,
p1_rd_full => open,
p1_rd_empty => open,
p1_rd_count => open,
p1_rd_overflow => open,
p1_rd_error => open,
p1_wr_clk => '0',
p1_wr_en => '0',
p1_wr_mask => (others => '0'),
p1_wr_data => (others => '0'),
p1_wr_full => open,
p1_wr_empty => open,
p1_wr_count => open,
p1_wr_underrun => open,
p1_wr_error => open,
p2_arb_en => '1',
p2_cmd_clk => p2_cmd_clk,
p2_cmd_en => p2_cmd_en,
p2_cmd_instr => p2_cmd_instr,
p2_cmd_bl => p2_cmd_bl,
p2_cmd_byte_addr => p2_cmd_byte_addr,
p2_cmd_empty => p2_cmd_empty,
p2_cmd_full => p2_cmd_full,
p2_rd_clk => p2_rd_clk,
p2_rd_en => p2_rd_en,
p2_rd_data => p2_rd_data,
p2_rd_full => p2_rd_full,
p2_rd_empty => p2_rd_empty,
p2_rd_count => p2_rd_count,
p2_rd_overflow => p2_rd_overflow,
p2_rd_error => p2_rd_error,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '0',
p3_cmd_clk => '0',
p3_cmd_en => '0',
p3_cmd_instr => (others => '0'),
p3_cmd_bl => (others => '0'),
p3_cmd_byte_addr => (others => '0'),
p3_cmd_empty => open,
p3_cmd_full => open,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => '0',
p3_wr_en => '0',
p3_wr_mask => (others => '0'),
p3_wr_data => (others => '0'),
p3_wr_full => open,
p3_wr_empty => open,
p3_wr_count => open,
p3_wr_underrun => open,
p3_wr_error => open,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
|
lgpl-3.0
|
5127f0a77c0d558ae53657e34c3db5c2
| 0.425652 | 3.501037 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/dual_port_ram/dual_port_ram.vhd
| 1 | 51,008 |
-- Module: XC3S_RAMB_1_PORT
-- Description: 18Kb Block SelectRAM example
-- Single Port 512 x 36 bits
-- Use template "SelectRAM_A36.vhd"
--
-- Device: Spartan-3 Family
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--
-- Syntax for Synopsys FPGA Express
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--
entity dual_port_ram is
port (
data_in : in std_logic_vector (0 downto 0) := (others => '0');
write_address : in std_logic_vector (13 downto 0) := (others => '0');
write_enable : in std_logic := '0';
ram_write_mask : in std_logic_vector(7 downto 0) := (others => '0');
enable : in std_logic := '0';
clk : in std_logic := '0';
reset : in std_logic := '0';
ram_read_mask : in std_logic_vector(7 downto 0) := (others => '0');
read_address : in std_logic_vector(13 downto 0) := (others => '0');
data_out : out std_logic_vector (0 downto 0) := (others => '0')
);
end dual_port_ram;
--
architecture dual_port_ram_arq of dual_port_ram is
signal clk_signal : std_logic := '0';
signal read_enable_0 : std_logic := '0';
signal write_enable_0 : std_logic := '0';
signal read_enable_1 : std_logic := '0';
signal write_enable_1 : std_logic := '0';
signal read_enable_2 : std_logic := '0';
signal write_enable_2 : std_logic := '0';
signal read_enable_3 : std_logic := '0';
signal write_enable_3 : std_logic := '0';
signal read_enable_4 : std_logic := '0';
signal write_enable_4 : std_logic := '0';
signal read_enable_5 : std_logic := '0';
signal write_enable_5 : std_logic := '0';
signal read_enable_6 : std_logic := '0';
signal write_enable_6 : std_logic := '0';
signal read_enable_7 : std_logic := '0';
signal write_enable_7 : std_logic := '0';
signal data_out_0 : std_logic_vector(0 downto 0) := (others => '0');
signal data_out_1 : std_logic_vector(0 downto 0) := (others => '0');
signal data_out_2 : std_logic_vector(0 downto 0) := (others => '0');
signal data_out_3 : std_logic_vector(0 downto 0) := (others => '0');
signal data_out_4 : std_logic_vector(0 downto 0) := (others => '0');
signal data_out_5 : std_logic_vector(0 downto 0) := (others => '0');
signal data_out_6 : std_logic_vector(0 downto 0) := (others => '0');
signal data_out_7 : std_logic_vector(0 downto 0) := (others => '0');
--
begin
--WRITE ON A READ ON B
--WRITE ON A READ ON B
--WRITE ON A READ ON B
--WRITE ON A READ ON B
-- Block SelectRAM Instantiation
ram_0: RAMB16_S1_S1
generic map(WRITE_MODE_B => "READ_FIRST")
-- INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF")
port map (
DOA => open,
DOB => data_out_0,
ADDRA => write_address,
ADDRB => read_address,
CLKA => clk_signal,
CLKB => clk_signal,
DIA => data_in,
DIB => "0",
ENA => write_enable_0,
ENB => read_enable_0,
SSRA => '0',
SSRB => '0',
WEA => write_enable,
WEB => '0' --will write 0 after read
);
ram_1: RAMB16_S1_S1
generic map(WRITE_MODE_B => "READ_FIRST")
-- INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF")
port map (
DOA => open,
DOB => data_out_1,
ADDRA => write_address,
ADDRB => read_address,
CLKA => clk_signal,
CLKB => clk_signal,
DIA => data_in,
DIB => "0",
ENA => write_enable_1,
ENB => read_enable_1,
SSRA => '0',
SSRB => '0',
WEA => write_enable,
WEB => '0' --will write 0 after read
);
ram_2: RAMB16_S1_S1
generic map(WRITE_MODE_B => "READ_FIRST")
-- INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF")
port map (
DOA => open,
DOB => data_out_2,
ADDRA => write_address,
ADDRB => read_address,
CLKA => clk_signal,
CLKB => clk_signal,
DIA => data_in,
DIB => "0",
ENA => write_enable_2,
ENB => read_enable_2,
SSRA => '0',
SSRB => '0',
WEA => write_enable,
WEB => '0' --will write 0 after read
);
ram_3: RAMB16_S1_S1
generic map(WRITE_MODE_B => "READ_FIRST")
-- INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF")
port map (
DOA => open,
DOB => data_out_3,
ADDRA => write_address,
ADDRB => read_address,
CLKA => clk_signal,
CLKB => clk_signal,
DIA => data_in,
DIB => "0",
ENA => write_enable_3,
ENB => read_enable_3,
SSRA => '0',
SSRB => '0',
WEA => write_enable,
WEB => '0' --will write 0 after read
);
ram_4: RAMB16_S1_S1
generic map(WRITE_MODE_B => "READ_FIRST")
-- INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF")
port map (
DOA => open,
DOB => data_out_4,
ADDRA => write_address,
ADDRB => read_address,
CLKA => clk_signal,
CLKB => clk_signal,
DIA => data_in,
DIB => "0",
ENA => write_enable_4,
ENB => read_enable_4,
SSRA => '0',
SSRB => '0',
WEA => write_enable,
WEB => '0' --will write 0 after read
);
ram_5: RAMB16_S1_S1
generic map(WRITE_MODE_B => "READ_FIRST")
-- INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF")
port map (
DOA => open,
DOB => data_out_5,
ADDRA => write_address,
ADDRB => read_address,
CLKA => clk_signal,
CLKB => clk_signal,
DIA => data_in,
DIB => "0",
ENA => write_enable_5,
ENB => read_enable_5,
SSRA => '0',
SSRB => '0',
WEA => write_enable,
WEB => '0' --will write 0 after read
);
ram_6: RAMB16_S1_S1
generic map(WRITE_MODE_B => "READ_FIRST")
-- INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF")
port map (
DOA => open,
DOB => data_out_6,
ADDRA => write_address,
ADDRB => read_address,
CLKA => clk_signal,
CLKB => clk_signal,
DIA => data_in,
DIB => "0",
ENA => write_enable_6,
ENB => read_enable_6,
SSRA => '0',
SSRB => '0',
WEA => write_enable,
WEB => '0' --will write 0 after read
);
ram_7: RAMB16_S1_S1
generic map(WRITE_MODE_B => "READ_FIRST")
-- INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_0f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_1f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_2f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3a => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3b => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3c => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3d => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3e => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
-- INIT_3f => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
port map (
DOA => open,
DOB => data_out_7,
ADDRA => write_address,
ADDRB => read_address,
CLKA => clk_signal,
CLKB => clk_signal,
DIA => data_in,
DIB => "0",
ENA => write_enable_7,
ENB => read_enable_7,
SSRA => '0',
SSRB => '0',
WEA => write_enable,
WEB => '0' --will write 0 after read
);
read_enable_0 <= enable and ram_read_mask(0);
write_enable_0 <= enable and ram_write_mask(0);
read_enable_1 <= enable and ram_read_mask(1);
write_enable_1 <= enable and ram_write_mask(1);
read_enable_2 <= enable and ram_read_mask(2);
write_enable_2 <= enable and ram_write_mask(2);
read_enable_3 <= enable and ram_read_mask(3);
write_enable_3 <= enable and ram_write_mask(3);
read_enable_4 <= enable and ram_read_mask(4);
write_enable_4 <= enable and ram_write_mask(4);
read_enable_5 <= enable and ram_read_mask(5);
write_enable_5 <= enable and ram_write_mask(5);
read_enable_6 <= enable and ram_read_mask(6);
write_enable_6 <= enable and ram_write_mask(6);
read_enable_7 <= enable and ram_read_mask(7);
write_enable_7 <= enable and ram_write_mask(7);
clk_signal <= clk;
data_out(0) <= (data_out_0(0) and ram_read_mask(0)) or (data_out_1(0) and ram_read_mask(1)) or (data_out_2(0) and ram_read_mask(2)) or (data_out_3(0) and ram_read_mask(3)) or (data_out_4(0) and ram_read_mask(4)) or (data_out_5(0) and ram_read_mask(5)) or (data_out_6(0) and ram_read_mask(6)) or (data_out_7(0) and ram_read_mask(7));
--end process;
--
end dual_port_ram_arq;
|
gpl-3.0
|
cdc8789af626dd1bbe1f4659a5f124ce
| 0.791601 | 5.796364 | false | false | false | false |
laurivosandi/hdl
|
arithmetic/src/carry_ripple_adder.vhd
| 1 | 768 |
library ieee;
use ieee.std_logic_1164.all;
entity carry_ripple_adder is
generic (
WIDTH : integer := 8
);
port (
a : in std_logic_vector (WIDTH-1 downto 0);
b : in std_logic_vector (WIDTH-1 downto 0);
ci : in std_logic;
s : out std_logic_vector (WIDTH-1 downto 0);
co : out std_logic
);
end;
architecture behavioral of carry_ripple_adder is
signal c: std_logic_vector (WIDTH downto 0);
begin
s(0) <= a(0) xor b(0) xor ci;
c(0) <= (a(0) and b(0)) or ((a(0) xor b(0)) and ci);
my_loop: for i in 1 to WIDTH-1 generate
s(i) <= a(i) xor b(i) xor c(i-1);
c(i) <= (a(i) and b(i)) or ((a(i) xor b(i)) and c(i-1));
end generate;
co <= c(WIDTH-1);
end Behavioral;
|
mit
|
e57f070ceeace4487b60d0d301e94f12
| 0.544271 | 2.782609 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/ram_double.vhd
| 1 | 3,816 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: RAM_Double
-- Module Name: RAM_Double
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavioral of a double memory RAM.
-- With this memory is possible to read and write at the same cycle.
-- Only used for tests.
--
-- The circuits parameters
--
-- ram_address_size :
--
-- Address size of the RAM used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word on the RAM.
--
-- file_ram_word_size :
--
-- The size of the word used in the file to be loaded on the RAM.(ARCH: FILE_LOAD)
--
-- load_file_name :
--
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
--
-- The name of the file to be used to dump the memory.(ARCH: FILE_LOAD)
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
entity ram_double is
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end ram_double;
architecture simple of ram_double is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
for I in 0 to (2**ram_address_size - 1) loop
memory_ram(I) <= rst_value;
end loop;
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw_a = '1' then
memory_ram(to_integer(unsigned(address_a))) <= data_in_a;
end if;
data_out_a <= memory_ram(to_integer(unsigned(address_a)));
if rw_b = '1' then
memory_ram(to_integer(unsigned(address_b))) <= data_in_b;
end if;
data_out_b <= memory_ram(to_integer(unsigned(address_b)));
end if;
end process;
end simple;
|
bsd-2-clause
|
dfad4b0af963cbff92759c59d13162be
| 0.533805 | 3.440938 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/multiplication/sign_computer/sign_computer_tb.vhd
| 1 | 1,367 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sign_computer_tb is
end entity;
architecture sign_computer_tb_arq of sign_computer_tb is
signal sign1_in : std_logic := '0';
signal sign2_in : std_logic := '0';
signal sign_out : std_logic := '0';
component sign_computer is
port(
sign1_in : in std_logic;
sign2_in : in std_logic;
sign_out : out std_logic
);
end component;
for sign_computer_0: sign_computer use entity work.sign_computer;
begin
sign_computer_0: sign_computer port map(
sign1_in => sign1_in,
sign2_in => sign2_in,
sign_out => sign_out
);
process
type pattern_type is record
s1i : std_logic;
s2i : std_logic;
so : std_logic;
end record;
-- The patterns to apply.
type pattern_array is array (natural range<>) of pattern_type;
constant patterns : pattern_array := (
('0','0','0'),
('0','1','1'),
('1','0','1'),
('1','1','0')
);
begin
for i in patterns'range loop
-- Set the inputs.
sign1_in <= patterns(i).s1i;
sign2_in <= patterns(i).s2i;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert sign_out = patterns(i).so report "BAD SIGN: " & std_logic'image(sign_out) severity error;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
7dcaf8d72e46d1ae51916d50414679c0
| 0.621068 | 2.946121 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/syndrome_calculator_n_pipe_v2.vhd
| 1 | 22,087 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Syndrome_Calculator_N_Pipe_v2
-- Module Name: Syndrome_Calculator_N_Pipe_v2
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st step in Goppa Code Decoding.
--
-- This circuit computes the syndrome from the ciphertext, support elements and
-- inverted evaluation of support elements into polynomial g, aka g(L)^(-1).
-- This circuit works by computing the syndrome of only the positions where the ciphertext
-- has value 1.
--
-- This is circuit version with a variable number of computation units and a pipeline for
-- both syndrome computation and ciphertext analyzes.
-- A optimized version that can have more than one pipeline computing the syndrome at the same time
-- was made named syndrome_calculator_n_pipe_v3.
--
-- The circuits parameters
--
-- number_of_units :
--
-- The number of units that compute each syndrome at the same time.
-- This number must be 1 or greater.
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword or in this case the ciphertext. Both the codeword
-- and ciphertext has the same size.
--
-- size_codeword :
--
-- The number of bits necessary to hold the ciphertext/codeword.
-- This is ceil(log2(length_codeword)).
--
-- length_syndrome :
--
-- The size of the syndrome array. This parameter depends of the
-- Goppa code used.
--
-- size_syndrome :
--
-- The number of bits necessary to hold the array syndrome.
-- This is ceil(log2(length_syndrome)).
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- controller_syndrome_calculator_2_pipe_v2 Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_decrement_rst_nbits Rev 1.0
-- shift_register_rst_nbits Rev 1.0
-- mult_gf_2_m Rev 1.0
-- adder_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity syndrome_calculator_n_pipe_v2 is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- length_syndrome : integer := 54;
-- size_syndrome : integer := 6
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- length_syndrome : integer := 100;
-- size_syndrome : integer := 7
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3307;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 132;
-- size_syndrome : integer := 8
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 64;
-- size_syndrome : integer := 6
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 128;
-- size_syndrome : integer := 7
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3200;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 256;
-- size_syndrome : integer := 8
-- QD-GOPPA [7296, 5632, 128, 13] --
number_of_units : integer := 32;
gf_2_m : integer range 1 to 20 := 15;
length_codeword : integer := 8320;
size_codeword : integer := 14;
length_syndrome : integer := 256;
size_syndrome : integer := 8
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_L : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR(0 downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_h : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_L : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
address_new_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0)
);
end syndrome_calculator_n_pipe_v2;
architecture Behavioral of syndrome_calculator_n_pipe_v2 is
component controller_syndrome_calculator_2_pipe_v2
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
almost_units_ready : in STD_LOGIC;
empty_units : in STD_LOGIC;
limit_ctr_codeword_q : in STD_LOGIC;
limit_ctr_syndrome_q : in STD_LOGIC;
reg_first_syndrome_q : in STD_LOGIC_VECTOR(0 downto 0);
reg_codeword_q : in STD_LOGIC_VECTOR(0 downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
control_units_ce : out STD_LOGIC;
control_units_rst : out STD_LOGIC;
int_reg_L_ce : out STD_LOGIC;
square_h : out STD_LOGIC;
int_reg_h_ce : out STD_LOGIC;
int_reg_h_rst : out STD_LOGIC;
int_sel_reg_h : out STD_LOGIC;
reg_load_L_ce : out STD_LOGIC;
reg_load_h_ce : out STD_LOGIC;
reg_load_h_rst : out STD_LOGIC;
reg_load_syndrome_ce : out STD_LOGIC;
reg_load_syndrome_rst : out STD_LOGIC;
reg_new_value_syndrome_ce : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_first_syndrome_ce : out STD_LOGIC;
reg_first_syndrome_rst : out STD_LOGIC;
ctr_load_address_syndrome_ce : out STD_LOGIC;
ctr_load_address_syndrome_rst : out STD_LOGIC;
reg_bus_address_syndrome_ce : out STD_LOGIC;
reg_calc_address_syndrome_ce : out STD_LOGIC;
reg_store_address_syndrome_ce : out STD_LOGIC;
ctr_load_address_codeword_ce : out STD_LOGIC;
ctr_load_address_codeword_rst : out STD_LOGIC;
reg_load_limit_codeword_rst : out STD_LOGIC;
reg_load_limit_codeword_ce : out STD_LOGIC;
reg_calc_limit_codeword_rst : out STD_LOGIC;
reg_calc_limit_codeword_ce : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_decrement_rst_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component shift_register_rst_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component mult_gf_2_m
Generic (gf_2_m : integer range 1 to 20 := 11);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component adder_gf_2_m
Generic(
gf_2_m : integer := 1;
number_of_elements : integer range 2 to integer'high := 2
);
Port(
a : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_elements) - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal reg_L_d : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal reg_L_ce : STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
signal reg_L_q : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal reg_h_d :STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal reg_h_ce : STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
signal reg_h_rst : STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
constant reg_h_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_h_q : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal sel_reg_h : STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
signal square_h : STD_LOGIC;
signal reg_load_L_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_load_L_ce : STD_LOGIC;
signal reg_load_L_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_load_h_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_load_h_ce : STD_LOGIC;
signal reg_load_h_rst : STD_LOGIC;
constant reg_load_h_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
signal reg_load_h_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_load_syndrome_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_load_syndrome_ce : STD_LOGIC;
signal reg_load_syndrome_rst : STD_LOGIC;
constant reg_load_syndrome_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
signal reg_load_syndrome_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_syndrome_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_syndrome_ce : STD_LOGIC;
signal reg_new_value_syndrome_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_codeword_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_codeword_ce : STD_LOGIC;
signal reg_codeword_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_first_syndrome_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_first_syndrome_ce : STD_LOGIC;
signal reg_first_syndrome_rst : STD_LOGIC;
constant reg_first_syndrome_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "1";
signal reg_first_syndrome_q : STD_LOGIC_VECTOR(0 downto 0);
signal mult_a : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal mult_b : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal mult_o : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal adder_a : STD_LOGIC_VECTOR(((number_of_units+1)*gf_2_m - 1) downto 0);
signal adder_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_load_address_syndrome_ce : STD_LOGIC;
signal ctr_load_address_syndrome_rst : STD_LOGIC;
constant ctr_load_address_syndrome_rst_value : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0) := std_logic_vector(to_unsigned(length_syndrome - 1, size_syndrome));
signal ctr_load_address_syndrome_q : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal reg_bus_address_syndrome_d : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal reg_bus_address_syndrome_ce : STD_LOGIC;
signal reg_bus_address_syndrome_q : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal reg_calc_address_syndrome_d : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal reg_calc_address_syndrome_ce : STD_LOGIC;
signal reg_calc_address_syndrome_q : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal reg_store_address_syndrome_d : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal reg_store_address_syndrome_ce : STD_LOGIC;
signal reg_store_address_syndrome_q : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal ctr_load_address_codeword_ce : STD_LOGIC;
signal ctr_load_address_codeword_rst : STD_LOGIC;
constant ctr_load_address_codeword_rst_value : STD_LOGIC_VECTOR((size_codeword - 1) downto 0) := std_logic_vector(to_unsigned(0, size_codeword));
signal ctr_load_address_codeword_q : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal reg_load_limit_codeword_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_load_limit_codeword_ce : STD_LOGIC;
signal reg_load_limit_codeword_rst : STD_LOGIC;
constant reg_load_limit_codeword_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_load_limit_codeword_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_calc_limit_codeword_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_calc_limit_codeword_ce : STD_LOGIC;
signal reg_calc_limit_codeword_rst : STD_LOGIC;
signal reg_calc_limit_codeword_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_calc_limit_codeword_q : STD_LOGIC_VECTOR(0 downto 0);
signal control_units_ce : STD_LOGIC;
signal control_units_rst : STD_LOGIC;
constant control_units_rst_value0 : STD_LOGIC_VECTOR((number_of_units - 1) downto 0) := (others => '0');
constant control_units_rst_value1 : STD_LOGIC_VECTOR((number_of_units) downto (number_of_units)) := "1";
constant control_units_rst_value : STD_LOGIC_VECTOR((number_of_units) downto 0) := control_units_rst_value1 & control_units_rst_value0;
signal control_units_q : STD_LOGIC_VECTOR((number_of_units) downto 0);
signal control_units_data_out : STD_LOGIC;
signal int_reg_L_ce : STD_LOGIC;
signal int_reg_h_ce : STD_LOGIC;
signal int_reg_h_rst: STD_LOGIC;
signal int_sel_reg_h : STD_LOGIC;
signal almost_units_ready : STD_LOGIC;
signal empty_units : STD_LOGIC;
signal limit_ctr_codeword_q : STD_LOGIC;
signal limit_ctr_syndrome_q : STD_LOGIC;
begin
controller : controller_syndrome_calculator_2_pipe_v2
Port Map(
clk => clk,
rst => rst,
almost_units_ready => almost_units_ready,
empty_units => empty_units,
limit_ctr_codeword_q => reg_calc_limit_codeword_q(0),
limit_ctr_syndrome_q => limit_ctr_syndrome_q,
reg_first_syndrome_q => reg_first_syndrome_q,
reg_codeword_q => reg_codeword_q,
syndrome_finalized => syndrome_finalized,
write_enable_new_syndrome => write_enable_new_syndrome,
control_units_ce => control_units_ce,
control_units_rst => control_units_rst,
int_reg_L_ce => int_reg_L_ce,
square_h => square_h,
int_reg_h_ce => int_reg_h_ce,
int_reg_h_rst => int_reg_h_rst,
int_sel_reg_h => int_sel_reg_h,
reg_load_L_ce => reg_load_L_ce,
reg_load_h_ce => reg_load_h_ce,
reg_load_h_rst => reg_load_h_rst,
reg_load_syndrome_ce => reg_load_syndrome_ce,
reg_load_syndrome_rst => reg_load_syndrome_rst,
reg_new_value_syndrome_ce => reg_new_value_syndrome_ce,
reg_codeword_ce => reg_codeword_ce,
reg_first_syndrome_ce => reg_first_syndrome_ce,
reg_first_syndrome_rst => reg_first_syndrome_rst,
ctr_load_address_syndrome_ce => ctr_load_address_syndrome_ce,
ctr_load_address_syndrome_rst => ctr_load_address_syndrome_rst,
reg_bus_address_syndrome_ce => reg_bus_address_syndrome_ce,
reg_calc_address_syndrome_ce => reg_calc_address_syndrome_ce,
reg_store_address_syndrome_ce => reg_store_address_syndrome_ce,
ctr_load_address_codeword_ce => ctr_load_address_codeword_ce,
ctr_load_address_codeword_rst => ctr_load_address_codeword_rst,
reg_load_limit_codeword_ce => reg_load_limit_codeword_ce,
reg_load_limit_codeword_rst => reg_load_limit_codeword_rst,
reg_calc_limit_codeword_ce => reg_calc_limit_codeword_ce,
reg_calc_limit_codeword_rst => reg_calc_limit_codeword_rst
);
calculator_units : for I in 0 to (number_of_units - 1) generate
reg_L_I : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_L_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
clk => clk,
ce => reg_L_ce(I),
q => reg_L_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
reg_h_I : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_h_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
clk => clk,
ce => reg_h_ce(I),
rst => reg_h_rst(I),
rst_value => reg_h_rst_value,
q => reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
mult_I : mult_gf_2_m
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => mult_a(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
b => mult_b(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
o => mult_o(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
reg_L_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_load_L_q;
reg_h_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= mult_o(((I + 1)*gf_2_m - 1) downto I*gf_2_m) when sel_reg_h(I) = '1' else
reg_load_h_q;
mult_a(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m) when square_h = '1' else
reg_L_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m);
mult_b(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m);
reg_L_ce(I) <= int_reg_L_ce and control_units_q(I);
reg_h_ce(I) <= int_reg_h_ce and (control_units_q(I) or int_sel_reg_h);
reg_h_rst(I) <= int_reg_h_rst and control_units_q(I);
sel_reg_h(I) <= int_sel_reg_h;
end generate;
control_units : shift_register_rst_nbits
Generic Map(
size => number_of_units+1
)
Port Map(
data_in => control_units_data_out,
clk => clk,
ce => control_units_ce,
rst => control_units_rst,
rst_value => control_units_rst_value,
q => control_units_q,
data_out => control_units_data_out
);
adder : adder_gf_2_m
Generic Map(
gf_2_m => gf_2_m,
number_of_elements => number_of_units+1
)
Port Map(
a => adder_a,
o => adder_o
);
reg_load_L : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_load_L_d,
clk => clk,
ce => reg_load_L_ce,
q => reg_load_L_q
);
reg_load_h : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_load_h_d,
clk => clk,
ce => reg_load_h_ce,
rst => reg_load_h_rst,
rst_value => reg_load_h_rst_value,
q => reg_load_h_q
);
reg_load_syndrome : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_load_syndrome_d,
clk => clk,
ce => reg_load_syndrome_ce,
rst => reg_load_syndrome_rst,
rst_value => reg_load_syndrome_rst_value,
q => reg_load_syndrome_q
);
reg_new_value_syndrome : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_syndrome_d,
clk => clk,
ce => reg_new_value_syndrome_ce,
q => reg_new_value_syndrome_q
);
reg_codeword : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_codeword_d,
clk => clk,
ce => reg_codeword_ce,
q => reg_codeword_q
);
reg_first_syndrome : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_first_syndrome_d,
clk => clk,
ce => reg_first_syndrome_ce,
rst => reg_first_syndrome_rst,
rst_value => reg_first_syndrome_rst_value,
q => reg_first_syndrome_q
);
ctr_load_address_syndrome : counter_decrement_rst_nbits
Generic Map(
size => size_syndrome,
decrement_value => 1
)
Port Map(
clk => clk,
ce => ctr_load_address_syndrome_ce,
rst => ctr_load_address_syndrome_rst,
rst_value => ctr_load_address_syndrome_rst_value,
q => ctr_load_address_syndrome_q
);
reg_bus_address_syndrome : register_nbits
Generic Map(
size => size_syndrome
)
Port Map(
d => reg_bus_address_syndrome_d,
clk => clk,
ce => reg_bus_address_syndrome_ce,
q => reg_bus_address_syndrome_q
);
reg_calc_address_syndrome : register_nbits
Generic Map(
size => size_syndrome
)
Port Map(
d => reg_calc_address_syndrome_d,
clk => clk,
ce => reg_calc_address_syndrome_ce,
q => reg_calc_address_syndrome_q
);
reg_store_address_syndrome : register_nbits
Generic Map(
size => size_syndrome
)
Port Map(
d => reg_store_address_syndrome_d,
clk => clk,
ce => reg_store_address_syndrome_ce,
q => reg_store_address_syndrome_q
);
ctr_load_address_codeword : counter_rst_nbits
Generic Map(
size => size_codeword,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_load_address_codeword_ce,
rst => ctr_load_address_codeword_rst,
rst_value => ctr_load_address_codeword_rst_value,
q => ctr_load_address_codeword_q
);
reg_load_limit_codeword : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_load_limit_codeword_d,
clk => clk,
ce => reg_load_limit_codeword_ce,
rst => reg_load_limit_codeword_rst,
rst_value => reg_load_limit_codeword_rst_value,
q => reg_load_limit_codeword_q
);
reg_calc_limit_codeword : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_calc_limit_codeword_d,
clk => clk,
ce => reg_calc_limit_codeword_ce,
rst => reg_calc_limit_codeword_rst,
rst_value => reg_calc_limit_codeword_rst_value,
q => reg_calc_limit_codeword_q
);
reg_load_limit_codeword_d(0) <= limit_ctr_codeword_q;
reg_calc_limit_codeword_d <= reg_load_limit_codeword_q;
adder_a <= reg_h_q & reg_load_syndrome_q;
reg_load_L_d <= value_L;
reg_load_h_d <= value_h;
reg_load_syndrome_d <= value_syndrome;
reg_codeword_d <= value_codeword;
reg_first_syndrome_d <= "0";
reg_new_value_syndrome_d <= adder_o;
new_value_syndrome <= reg_new_value_syndrome_q;
reg_bus_address_syndrome_d <= ctr_load_address_syndrome_q;
reg_calc_address_syndrome_d <= reg_bus_address_syndrome_q;
reg_store_address_syndrome_d <= reg_calc_address_syndrome_q;
address_h <= ctr_load_address_codeword_q;
address_L <= ctr_load_address_codeword_q;
address_codeword <= ctr_load_address_codeword_q;
address_syndrome <= ctr_load_address_syndrome_q;
address_new_syndrome <= reg_store_address_syndrome_q;
almost_units_ready <= control_units_q(number_of_units - 1);
empty_units <= control_units_q(0);
limit_ctr_codeword_q <= '1' when (ctr_load_address_codeword_q = std_logic_vector(to_unsigned(length_codeword - 1, ctr_load_address_codeword_q'length))) else '0';
limit_ctr_syndrome_q <= '1' when (reg_store_address_syndrome_q = std_logic_vector(to_unsigned(0, ctr_load_address_syndrome_q'length))) else '0';
end Behavioral;
|
bsd-2-clause
|
958bf4b6fb3062e8f0ac7ff3301cb5b0
| 0.663196 | 2.698143 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/bcd_controller/gen_ena.vhd
| 3 | 811 |
library ieee;
use ieee.std_logic_1164.all;
entity generic_enabler is
generic(PERIOD:natural := 1000000 ); --1MHz
port(
clk: in std_logic;
rst: in std_logic;
ena_out: out std_logic
);
end;
architecture generic_enabler_arq of generic_enabler is
component genericCounter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end component;
begin
genericCounterMap: genericCounter generic map (32,PERIOD) --32 bits son suficientes para hasta 4 GHz
port map(
clk => clk,
rst => rst,
ena => '1',
carry_o => ena_out); --El count_dummy esta conectado siempre a tierra.
end;
|
gpl-3.0
|
6ea40fdec737a8d2674293d13b2d4db2
| 0.633785 | 3.10728 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/scaling_values_lut/scaling_values_lut.vhd
| 1 | 1,710 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--Lookup table for scaling values to apply to the vector after rotating. It depends on the number of steps of the algorithm
entity scaling_values_lut is
generic(TOTAL_BITS: integer := 32);
port(
steps: in integer := 0;
scaling_value: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end scaling_values_lut;
architecture scaling_values_lut_arq of scaling_values_lut is
constant max_representable_value_index: integer := 9; --After this index, the fixed point representation can't show any difference
type scaling_values_table is array (natural range <>) of std_logic_vector(TOTAL_BITS - 1 downto 0);
constant scaling_values : scaling_values_table := (
"00000000000000001011010100000100", ---0.707092285156
"00000000000000001010000111101000", ---0.632446289062
"00000000000000001001110100010011", ---0.613571166992
"00000000000000001001101111011100", ---0.608825683594
"00000000000000001001101110001110", ---0.607635498047
"00000000000000001001101101111011", ---0.607345581055
"00000000000000001001101101110110", ---0.607269287109
"00000000000000001001101101110101", ---0.60725402832
"00000000000000001001101101110101", ---0.60725402832
"00000000000000001001101101110100" ---0.607238769531
);
begin
process (steps) is
begin
if(steps > max_representable_value_index) then
scaling_value <= scaling_values(max_representable_value_index);
elsif(steps = 0) then
scaling_value <= (others => '0');
else
scaling_value <= scaling_values(steps - 1);
end if;
end process;
end architecture;
|
gpl-3.0
|
b2a0c6f09a89c38a271224d2b3123432
| 0.712865 | 3.986014 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/codeword_generator_1.vhd
| 1 | 14,188 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Codeword Generator 1
-- Module Name: Codeword_Generator_1
-- Project Name: McEliece QD-Goppa Encoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The first and only step in QD-Goppa Code encoding.
-- This circuit transforms an k-bit message into a valid n-bit codeword.
-- The transformation is an multiplication of a message of k-bits by the
-- Generator matrix G. The Generator matrix is composed of Identity Matrix and
-- another matrix A. For this reason the first k bits of the codeword are equal
-- to the message, only the last n-k bits are computed. This circuit works only
-- only for QD-Goppa codes, where matrix A is composed of dyadic matrices and
-- can be stored only by the first row of each dyadic matrix.
-- Matrix A is supposed to be stored with a word of 1 bit and each dyadic matrix row
-- followed by each one, in a row-wise pattern.
--
-- This circuit process one bit at time, each is more than 1 cycle.
-- This circuit is inefficient and only a proof of concept for n_m version.
--
-- The circuits parameters
--
-- length_message :
--
-- Length in bits of message size and also part of matrix size.
--
-- size_message :
--
-- The number of bits necessary to store the message. The ceil(log2(lenght_message))
--
-- length_codeword :
--
-- Length in bits of codeword size and also part of matrix size.
--
-- size_codeword :
--
-- The number of bits necessary to store the codeword. The ceil(log2(length_codeword))
--
-- size_dyadic_matrix :
--
-- The number of bits necessary to store one row of the dyadic matrix.
-- It is also the ceil(log2(number of errors in the code))
--
-- number_dyadic_matrices :
--
-- The number of dyadic matrices present in matrix A.
--
-- size_number_dyadic_matrices :
--
-- The number of bits necessary to store the number of dyadic matrices.
-- The ceil(log2(number_dyadic_matrices))
--
-- Dependencies:
--
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- controller_codeword_generator_1 Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_rst_set_nbits Rev 1.0
--
-- Revision:
-- Revision 1.00 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity codeword_generator_1 is
Generic(
-- QD-GOPPA [2528, 2144, 32, 12] --
length_message : integer := 2144;
size_message : integer := 12;
length_codeword : integer := 2528;
size_codeword : integer := 12;
size_dyadic_matrix : integer := 5;
number_dyadic_matrices : integer := 804;
size_number_dyadic_matrices : integer := 10
-- QD-GOPPA [2816, 2048, 64, 12] --
-- length_message : integer := 2048;
-- size_message : integer := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 384;
-- size_number_dyadic_matrices : integer := 9
-- QD-GOPPA [3328, 2560, 64, 12] --
-- length_message : integer := 2560;
-- size_message : integer := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 480;
-- size_number_dyadic_matrices : integer := 9
-- QD-GOPPA [7296, 5632, 128, 13] --
-- length_message : integer := 5632;
-- size_message : integer := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- size_dyadic_matrix : integer := 7;
-- number_dyadic_matrices : integer := 572;
-- size_number_dyadic_matrices : integer := 10
);
Port(
codeword : in STD_LOGIC;
matrix : in STD_LOGIC;
message : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
new_codeword : out STD_LOGIC;
write_enable_new_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC;
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_message : out STD_LOGIC_VECTOR((size_message - 1) downto 0);
address_matrix : out STD_LOGIC_VECTOR((size_dyadic_matrix + size_number_dyadic_matrices - 1) downto 0)
);
end codeword_generator_1;
architecture Behavioral of codeword_generator_1 is
component controller_codeword_generator_1
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_ctr_dyadic_column_q : in STD_LOGIC;
limit_ctr_dyadic_row_q : in STD_LOGIC;
limit_ctr_address_message_q : in STD_LOGIC;
limit_ctr_address_codeword_q : in STD_LOGIC;
write_enable_new_codeword : out STD_LOGIC;
message_into_new_codeword : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_codeword_rst : out STD_LOGIC;
reg_message_ce : out STD_LOGIC;
reg_matrix_ce : out STD_LOGIC;
ctr_dyadic_column_ce : out STD_LOGIC;
ctr_dyadic_column_rst : out STD_LOGIC;
ctr_dyadic_row_ce : out STD_LOGIC;
ctr_dyadic_row_rst : out STD_LOGIC;
ctr_dyadic_matrices_ce : out STD_LOGIC;
ctr_dyadic_matrices_rst : out STD_LOGIC;
ctr_address_base_message_ce : out STD_LOGIC;
ctr_address_base_message_rst : out STD_LOGIC;
ctr_address_base_codeword_ce : out STD_LOGIC;
ctr_address_base_codeword_rst : out STD_LOGIC;
ctr_address_base_codeword_set : out STD_LOGIC;
internal_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_set_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
set : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
set_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
signal reg_codeword_d : STD_LOGIC;
signal reg_codeword_ce : STD_LOGIC;
signal reg_codeword_rst : STD_LOGIC;
constant reg_codeword_rst_value : STD_LOGIC := '0';
signal reg_codeword_q : STD_LOGIC;
signal reg_message_d : STD_LOGIC;
signal reg_message_ce : STD_LOGIC;
signal reg_message_q : STD_LOGIC;
signal reg_matrix_d : STD_LOGIC;
signal reg_matrix_ce : STD_LOGIC;
signal reg_matrix_q : STD_LOGIC;
signal ctr_dyadic_column_ce : STD_LOGIC;
signal ctr_dyadic_column_rst : STD_LOGIC;
constant ctr_dyadic_column_rst_value : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_dyadic_column_q : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0);
signal limit_ctr_dyadic_column_q : STD_LOGIC;
signal ctr_dyadic_row_ce : STD_LOGIC;
signal ctr_dyadic_row_rst : STD_LOGIC;
constant ctr_dyadic_row_rst_value : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_dyadic_row_q : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0);
signal limit_ctr_dyadic_row_q : STD_LOGIC;
signal ctr_dyadic_matrices_ce : STD_LOGIC;
signal ctr_dyadic_matrices_rst : STD_LOGIC;
constant ctr_dyadic_matrices_rst_value : STD_LOGIC_VECTOR((size_number_dyadic_matrices - 1) downto 0) := (others => '0');
signal ctr_dyadic_matrices_q : STD_LOGIC_VECTOR((size_number_dyadic_matrices - 1) downto 0);
signal limit_ctr_dyadic_matrices_q : STD_LOGIC;
signal ctr_address_base_message_ce : STD_LOGIC;
signal ctr_address_base_message_rst : STD_LOGIC;
constant ctr_address_base_message_rst_value : STD_LOGIC_VECTOR((size_message - size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_address_base_message_q : STD_LOGIC_VECTOR((size_message - size_dyadic_matrix - 1) downto 0);
signal limit_ctr_address_message_q : STD_LOGIC;
signal ctr_address_base_codeword_ce : STD_LOGIC;
signal ctr_address_base_codeword_rst : STD_LOGIC;
signal ctr_address_base_codeword_set : STD_LOGIC;
constant ctr_address_base_codeword_rst_value : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0) := (others => '0');
constant ctr_address_base_codeword_set_value : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0) := std_logic_vector(to_unsigned(length_message/2**size_dyadic_matrix, size_codeword - size_dyadic_matrix));
signal ctr_address_base_codeword_q : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0);
signal limit_ctr_address_codeword_q : STD_LOGIC;
signal internal_address_codeword : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal internal_address_message : STD_LOGIC_VECTOR((size_message - 1) downto 0);
signal internal_codeword : STD_LOGIC;
signal internal_new_codeword : STD_LOGIC;
signal message_into_new_codeword : STD_LOGIC;
begin
controller : controller_codeword_generator_1
Port Map(
clk => clk,
rst => rst,
limit_ctr_dyadic_column_q => limit_ctr_dyadic_column_q,
limit_ctr_dyadic_row_q => limit_ctr_dyadic_row_q,
limit_ctr_address_message_q => limit_ctr_address_message_q,
limit_ctr_address_codeword_q => limit_ctr_address_codeword_q,
write_enable_new_codeword => write_enable_new_codeword,
message_into_new_codeword => message_into_new_codeword,
reg_codeword_ce => reg_codeword_ce,
reg_codeword_rst => reg_codeword_rst,
reg_message_ce => reg_message_ce,
reg_matrix_ce => reg_matrix_ce,
ctr_dyadic_column_ce => ctr_dyadic_column_ce,
ctr_dyadic_column_rst => ctr_dyadic_column_rst,
ctr_dyadic_row_ce => ctr_dyadic_row_ce,
ctr_dyadic_row_rst => ctr_dyadic_row_rst,
ctr_dyadic_matrices_ce => ctr_dyadic_matrices_ce,
ctr_dyadic_matrices_rst => ctr_dyadic_matrices_rst,
ctr_address_base_message_ce => ctr_address_base_message_ce,
ctr_address_base_message_rst => ctr_address_base_message_rst,
ctr_address_base_codeword_ce => ctr_address_base_codeword_ce,
ctr_address_base_codeword_rst => ctr_address_base_codeword_rst,
ctr_address_base_codeword_set => ctr_address_base_codeword_set,
internal_codeword => internal_codeword,
codeword_finalized => codeword_finalized
);
reg_acc : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d(0) => reg_codeword_d,
clk => clk,
ce => reg_codeword_ce,
rst => reg_codeword_rst,
rst_value(0) => reg_codeword_rst_value,
q(0) => reg_codeword_q
);
reg_vector : register_nbits
Generic Map(
size => 1
)
Port Map(
d(0) => reg_message_d,
clk => clk,
ce => reg_message_ce,
q(0) => reg_message_q
);
reg_matrix : register_nbits
Generic Map(
size => 1
)
Port Map(
d(0) => reg_matrix_d,
clk => clk,
ce => reg_matrix_ce,
q(0) => reg_matrix_q
);
ctr_dyadic_column : counter_rst_nbits
Generic Map(
size => size_dyadic_matrix,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_dyadic_column_ce,
rst => ctr_dyadic_column_rst,
rst_value => ctr_dyadic_column_rst_value,
q => ctr_dyadic_column_q
);
ctr_dyadic_row : counter_rst_nbits
Generic Map(
size => size_dyadic_matrix,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_dyadic_row_ce,
rst => ctr_dyadic_row_rst,
rst_value => ctr_dyadic_row_rst_value,
q => ctr_dyadic_row_q
);
ctr_dyadic_matrices : counter_rst_nbits
Generic Map(
size => size_number_dyadic_matrices,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_dyadic_matrices_ce,
rst => ctr_dyadic_matrices_rst,
rst_value => ctr_dyadic_matrices_rst_value,
q => ctr_dyadic_matrices_q
);
ctr_address_base_vector : counter_rst_nbits
Generic Map(
size => size_message - size_dyadic_matrix,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_address_base_message_ce,
rst => ctr_address_base_message_rst,
rst_value => ctr_address_base_message_rst_value,
q => ctr_address_base_message_q
);
ctr_address_base_acc : counter_rst_set_nbits
Generic Map(
size => size_codeword - size_dyadic_matrix,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_address_base_codeword_ce,
set => ctr_address_base_codeword_set,
rst => ctr_address_base_codeword_rst,
set_value => ctr_address_base_codeword_set_value,
rst_value => ctr_address_base_codeword_rst_value,
q => ctr_address_base_codeword_q
);
internal_new_codeword <= (reg_message_q and reg_matrix_q) xor reg_codeword_q;
new_codeword <= reg_message_q when message_into_new_codeword = '1' else
internal_new_codeword;
reg_codeword_d <= internal_new_codeword when internal_codeword = '1' else
codeword;
reg_message_d <= message;
reg_matrix_d <= matrix;
internal_address_codeword <= ctr_address_base_codeword_q & ctr_dyadic_column_q;
internal_address_message <= ctr_address_base_message_q & ctr_dyadic_row_q;
address_codeword <= internal_address_codeword;
address_message <= internal_address_message;
address_matrix <= ctr_dyadic_matrices_q & (ctr_dyadic_column_q xor ctr_dyadic_row_q);
limit_ctr_dyadic_column_q <= '1' when ctr_dyadic_column_q = std_logic_vector(to_unsigned(2**size_dyadic_matrix - 1, ctr_dyadic_column_q'length)) else '0';
limit_ctr_dyadic_row_q <= '1' when ctr_dyadic_row_q = std_logic_vector(to_unsigned(2**size_dyadic_matrix - 1, ctr_dyadic_row_q'length)) else '0';
limit_ctr_address_message_q <= '1' when internal_address_message = std_logic_vector(to_unsigned(length_message - 1, internal_address_message'length)) else '0';
limit_ctr_address_codeword_q <= '1' when internal_address_codeword = std_logic_vector(to_unsigned(length_codeword - 1, internal_address_codeword'length)) else '0';
end Behavioral;
|
bsd-2-clause
|
a5d6f4dced4e9cefaa59ec08dd383851
| 0.684593 | 3.005295 | false | false | false | false |
hitomi2500/wasca
|
obsolete/fpga_firmware_V2/ip_repo/ABus2AXI4Lite/hdl/ABus2AXI4Lite_Slave_AXI.vhd
| 2 | 18,750 |
-- This one is a slave interface, it provides Zynq PS with access to system registers
-- and filesystem buffers. Since PS have its own memory interface, no need to provide
-- access for DDR here.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ABus2AXI4Lite_Slave_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_SLAVE_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_SLAVE_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
-- registers
PCNTR : out std_logic_vector(15 downto 0);
STATUS : out std_logic_vector(15 downto 0);
MODE : in std_logic_vector(15 downto 0);
HWVER : in std_logic_vector(15 downto 0);
SWVER : out std_logic_vector(15 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
SLAVE_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
SLAVE_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
SLAVE_AXI_AWADDR : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
SLAVE_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
SLAVE_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
SLAVE_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
SLAVE_AXI_WDATA : in std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
SLAVE_AXI_WSTRB : in std_logic_vector((C_SLAVE_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
SLAVE_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
SLAVE_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
SLAVE_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
SLAVE_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
SLAVE_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
SLAVE_AXI_ARADDR : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
SLAVE_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
SLAVE_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
SLAVE_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
SLAVE_AXI_RDATA : out std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
SLAVE_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
SLAVE_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
SLAVE_AXI_RREADY : in std_logic
);
end ABus2AXI4Lite_Slave_AXI;
architecture arch_imp of ABus2AXI4Lite_Slave_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_SLAVE_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_SLAVE_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 2;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 8
signal slv_reg0 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
SLAVE_AXI_AWREADY <= axi_awready;
SLAVE_AXI_WREADY <= axi_wready;
SLAVE_AXI_BRESP <= axi_bresp;
SLAVE_AXI_BVALID <= axi_bvalid;
SLAVE_AXI_ARREADY <= axi_arready;
SLAVE_AXI_RDATA <= axi_rdata;
SLAVE_AXI_RRESP <= axi_rresp;
SLAVE_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and SLAVE_AXI_AWVALID = '1' and SLAVE_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and SLAVE_AXI_AWVALID = '1' and SLAVE_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= SLAVE_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and SLAVE_AXI_WVALID = '1' and SLAVE_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and SLAVE_AXI_WVALID and axi_awready and SLAVE_AXI_AWVALID ;
process (SLAVE_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and SLAVE_AXI_AWVALID = '1' and axi_wready = '1' and SLAVE_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (SLAVE_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and SLAVE_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= SLAVE_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and SLAVE_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and SLAVE_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and SLAVE_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, axi_araddr, SLAVE_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000" =>
reg_data_out <= slv_reg0;
when b"001" =>
reg_data_out <= HWVER & MODE;--slv_reg1;
when b"010" =>
reg_data_out <= slv_reg2;
-- when b"011" =>
-- reg_data_out <= slv_reg3;
-- when b"100" =>
-- reg_data_out <= slv_reg4;
-- when b"101" =>
-- reg_data_out <= slv_reg5;
-- when b"110" =>
-- reg_data_out <= slv_reg6;
-- when b"111" =>
-- reg_data_out <= slv_reg7;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( SLAVE_AXI_ACLK ) is
begin
if (rising_edge (SLAVE_AXI_ACLK)) then
if ( SLAVE_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
PCNTR <= slv_reg0(15 downto 0);
STATUS <= slv_reg0(31 downto 16);
--MODE : in std_logic_vector(15 downto 0);
--HWVER : in std_logic_vector(15 downto 0);
SWVER <= slv_reg2(15 downto 0);
-- User logic ends
end arch_imp;
|
gpl-2.0
|
4c6db074e509701fd715d7d5c58de42f
| 0.612213 | 3.523112 | false | false | false | false |
pwuertz/digitizer2fw
|
sim/acquisition_tb.vhd
| 1 | 3,324 |
-------------------------------------------------------------------------------
-- Digitizer2 acquisition logic test bench
--
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
use work.sampling_pkg.all;
use work.tdc_sample_prep_pkg.all;
entity acquisition_tb is
end acquisition_tb;
architecture acquisition_tb_arch of acquisition_tb is
constant clk_samples_period : time := 4 ns;
signal clk_samples: std_logic := '0';
signal samples_d_in: din_samples_t( 0 to 3 ) := (others => (others => '0'));
signal samples_a_in: adc_samples_t( 0 to 1 ) := (others => (ovfl => '0', data => (others => '0')));
signal a_threshold: a_sample_t := (others => '0');
signal a_invert: std_logic := '0';
signal a_average: std_logic_vector( 1 downto 0 ) := (others => '0');
signal acq_mode: std_logic_vector( 1 downto 0 ) := (others => '0');
signal acq_start_src: std_logic_vector( 2 downto 0 ) := (others => '0');
signal acq_stop_src: std_logic_vector( 2 downto 0 ) := (others => '0');
signal acq_reset: std_logic := '0';
signal acq_stop: std_logic := '0';
signal acq_state: std_logic_vector( 2 downto 0 );
constant clk_rd_period : time := 10 ns;
signal clk_rd: std_logic := '0';
signal rd_en: std_logic := '0';
signal rd_empty: std_logic;
signal rd_data: std_logic_vector(15 downto 0);
signal rd_2xcnt: std_logic_vector(15 downto 0);
begin
process begin
clk_samples <= '0';
wait for clk_samples_period/2;
clk_samples <= '1';
wait for clk_samples_period/2;
end process;
process begin
clk_rd <= '0';
wait for clk_rd_period/2;
clk_rd <= '1';
wait for clk_rd_period/2;
end process;
acquisition_inst: entity work.acquisition
port map(
clk_samples => clk_samples,
samples_d_in => samples_d_in,
samples_a_in => samples_a_in,
a_threshold => a_threshold,
a_invert => a_invert,
a_average => a_average,
acq_mode => acq_mode,
acq_start_src => acq_start_src,
acq_stop_src => acq_stop_src,
acq_reset => acq_reset,
acq_stop => acq_stop,
acq_state => acq_state,
clk_rd => clk_rd,
rd_en => rd_en,
rd_empty => rd_empty,
rd_data => rd_data,
rd_2xcnt => rd_2xcnt
);
stimulus: process
begin
a_invert <= '1';
acq_mode <= "10";
acq_start_src <= std_logic_vector(to_unsigned(1, 3));
acq_stop_src <= std_logic_vector(to_unsigned(2, 3));
wait for 8*clk_samples_period;
acq_reset <= '1';
wait for 2*clk_samples_period;
acq_reset <= '0';
wait for 10*clk_samples_period;
samples_d_in <= ("00", "01", "01", "00");
wait for 8*clk_samples_period;
samples_d_in <= (others => (others => '0'));
wait for 10*clk_samples_period;
samples_a_in(0).data <= to_signed(-1000, ADC_SAMPLE_BITS);
samples_a_in(1).data <= to_signed(0, ADC_SAMPLE_BITS);
wait for clk_samples_period;
samples_a_in <= (others => (ovfl => '0', data => (others => '0')));
wait;
end process;
end acquisition_tb_arch;
|
gpl-3.0
|
37479587adef65bd56476203524f6b7f
| 0.592537 | 3.14678 | false | false | false | false |
laurivosandi/hdl
|
primitives/src/gray_testbench.vhd
| 1 | 1,410 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gray_testbench is end gray_testbench;
architecture behavioral of gray_testbench is
signal input : std_logic_vector(3 downto 0);
signal output : std_logic_vector(3 downto 0);
component mux
port (
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
s : in std_logic_vector(1 downto 0);
m : out std_logic
);
end component;
begin
process begin
for j in 0 to 15 loop
input <= std_logic_vector(to_unsigned(j,4));
wait for 10 ns;
end loop;
end process;
output(3) <= input(3);
uut1 : mux
port map (
a => '0',
b => '1',
c => '1',
d => '0',
s => input(3 downto 2),
m => output(2)
);
uut2 : mux
port map (
a => '0',
b => '1',
c => '1',
d => '0',
s => input(2 downto 1),
m => output(1)
);
uut3 : mux
port map (
a => '0',
b => '1',
c => '1',
d => '0',
s => input(1 downto 0),
m => output(0)
);
end;
|
mit
|
080dd101f580899b642cc4e7ce3e93ec
| 0.385816 | 3.927577 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/tp1/multiplex.vhd
| 1 | 889 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY bcd_mux IS
PORT(
bcd0_i : IN std_logic_vector(3 DOWNTO 0);
bcd1_i : IN std_logic_vector(3 DOWNTO 0);
bcd2_i : IN std_logic_vector(3 DOWNTO 0);
bcd3_i : IN std_logic_vector(3 DOWNTO 0);
m_sel : IN std_logic_vector(1 DOWNTO 0);
m_out : OUT std_logic_vector(3 DOWNTO 0));
END bcd_mux;
ARCHITECTURE bcd_mux_arq OF bcd_mux IS
BEGIN
PROCESS (bcd0_i,bcd1_i,bcd2_i,bcd3_i) IS
BEGIN
CASE m_sel IS
WHEN "00" => m_out <= bcd0_i;
WHEN "01" => m_out <= bcd1_i;
WHEN "10" => m_out <= bcd2_i;
WHEN "11" => m_out <= bcd3_i;
WHEN OTHERS => m_out <= (others => '0');
END CASE;
END PROCESS;
END bcd_mux_arq;
|
gpl-3.0
|
883adf610e4a0dd1126fd15f6b2086c1
| 0.498313 | 3.108392 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/codeword_generator_n_m_v3.vhd
| 1 | 20,141 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Codeword_Generator_n_m_v3
-- Module Name: Codeword_Generator_n_m_v3
-- Project Name: McEliece QD-Goppa Encoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The first and only step in QD-Goppa Code encoding.
-- This circuit transforms an k-bit message into a valid n-bit codeword.
-- The transformation is an multiplication of a message of k-bits by the
-- Generator matrix G. The Generator matrix is composed of Identity Matrix and
-- another matrix A. For this reason the first k bits of the codeword are equal
-- to the message, only the last n-k bits are computed. This circuit works only
-- only for QD-Goppa codes, where matrix A is composed of dyadic matrices and
-- can be stored only by the first row of each dyadic matrix.
-- Matrix A is supposed to be stored with a word with the same size as dyadic matrix rows.
-- Also, each dyadic matrix row followed by each one, in a row-wise pattern.
--
-- This circuit process n+m bits at time, each time is 1 cycle.
-- n and m are represented as number_of_multipliers_per_acc and number_of_accs parameters.
-- This circuit is efficient and does both steps at the same time:
-- Copies the first k bits.
-- Compute the last n-k bits.
--
-- The circuits parameters
--
-- The circuits parameters
--
-- number_of_multipliers_per_acc :
--
-- The number of matrix rows and message values calculate at once in one or more accumulators.
-- On this implementation this value, must be the same of number_of_accs,
-- because of copy message. When copying message message values loaded must be same stored in codeword.
--
-- number_of_accs :
--
-- The number of matrix columns and codeword values calculate at once.
-- On this implementation this value, must be the same of number_of_multipliers_per_acc,
-- because of copy message. When copying message message values loaded must be same stored in codeword.
--
-- length_message :
--
-- Length in bits of message size and also part of matrix size.
--
-- size_message :
--
-- The number of bits necessary to store the message. The ceil(log2(lenght_message))
--
-- length_codeword :
--
-- Length in bits of codeword size and also part of matrix size.
--
-- size_codeword :
--
-- The number of bits necessary to store the codeword. The ceil(log2(legth_codeword))
--
-- size_dyadic_matrix :
--
-- The number of bits necessary to store one row of the dyadic matrix.
-- It is also the ceil(log2(number of errors in the code))
--
-- number_dyadic_matrices :
--
-- The number of dyadic matrices present in matrix A.
--
-- size_number_dyadic_matrices :
--
-- The number of bits necessary to store the number of dyadic matrices.
-- The ceil(log2(number_dyadic_matrices))
--
-- Dependencies:
--
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- controller_codeword_generator_3 Rev 1.0
-- adder_gf_2_m Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_rst_set_nbits Rev 1.0
--
-- Revision:
-- Revision 1.00 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity codeword_generator_n_m_v3 is
Generic(
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_multipliers_per_acc : integer := 32;
-- number_of_accs : integer := 32;
-- length_message : integer := 2144;
-- size_message : integer := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 5;
-- number_dyadic_matrices : integer := 804;
-- size_number_dyadic_matrices : integer := 10
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_multipliers_per_acc : integer := 1;
-- number_of_accs : integer := 1;
-- length_message : integer := 2048;
-- size_message : integer := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 384;
-- size_number_dyadic_matrices : integer := 9
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_multipliers_per_acc : integer := 1;
-- number_of_accs : integer := 1;
-- length_message : integer := 2560;
-- size_message : integer := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 480;
-- size_number_dyadic_matrices : integer := 9
-- QD-GOPPA [7296, 5632, 128, 13] --
number_of_multipliers_per_acc : integer := 64;
number_of_accs : integer := 64;
length_message : integer := 5632;
size_message : integer := 13;
length_codeword : integer := 7296;
size_codeword : integer := 13;
size_dyadic_matrix : integer := 7;
number_dyadic_matrices : integer := 572;
size_number_dyadic_matrices : integer := 10
);
Port(
codeword : in STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
matrix : in STD_LOGIC_VECTOR((2**size_dyadic_matrix - 1) downto 0);
message : in STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
new_codeword : out STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
new_codeword_copy : out STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
write_enable_new_codeword : out STD_LOGIC;
write_enable_new_codeword_copy : out STD_LOGIC;
codeword_finalized : out STD_LOGIC;
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_new_codeword_copy : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_message : out STD_LOGIC_VECTOR((size_message - 1) downto 0);
address_matrix : out STD_LOGIC_VECTOR((size_dyadic_matrix + size_number_dyadic_matrices - 1) downto 0)
);
end codeword_generator_n_m_v3;
architecture RTL of codeword_generator_n_m_v3 is
component controller_codeword_generator_3
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_ctr_dyadic_column_q : in STD_LOGIC;
limit_ctr_dyadic_row_q : in STD_LOGIC;
limit_ctr_address_message_q : in STD_LOGIC;
limit_ctr_address_codeword_q : in STD_LOGIC;
zero_ctr_address_message_q : in STD_LOGIC;
write_enable_new_codeword : out STD_LOGIC;
write_enable_new_codeword_copy : out STD_LOGIC;
external_matrix_ce : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_codeword_rst : out STD_LOGIC;
reg_message_ce : out STD_LOGIC;
reg_matrix_ce : out STD_LOGIC;
ctr_dyadic_column_ce : out STD_LOGIC;
ctr_dyadic_column_rst : out STD_LOGIC;
ctr_dyadic_row_ce : out STD_LOGIC;
ctr_dyadic_row_rst : out STD_LOGIC;
ctr_dyadic_matrices_ce : out STD_LOGIC;
ctr_dyadic_matrices_rst : out STD_LOGIC;
ctr_address_base_message_ce : out STD_LOGIC;
ctr_address_base_message_rst : out STD_LOGIC;
ctr_address_base_codeword_ce : out STD_LOGIC;
ctr_address_base_codeword_rst : out STD_LOGIC;
reg_address_new_codeword_copy_ce : out STD_LOGIC;
internal_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_set_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
set : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
set_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component adder_gf_2_m
Generic(
gf_2_m : integer := 1;
number_of_elements : integer range 2 to integer'high := 2
);
Port(
a : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_elements) - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal reg_codeword_d : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal reg_codeword_ce : STD_LOGIC;
signal reg_codeword_rst : STD_LOGIC;
constant reg_codeword_rst_value : STD_LOGIC_VECTOR := "0";
signal reg_codeword_q : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal reg_message_d : STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
signal reg_message_ce : STD_LOGIC;
signal reg_message_q : STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
signal reg_matrix_d : STD_LOGIC_VECTOR((number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
signal reg_matrix_ce : STD_LOGIC;
signal reg_matrix_q : STD_LOGIC_VECTOR((number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
signal external_matrix_d : STD_LOGIC_VECTOR((2**size_dyadic_matrix - 1) downto 0);
signal external_matrix_ce : STD_LOGIC;
signal external_matrix_q : STD_LOGIC_VECTOR((2**size_dyadic_matrix - 1) downto 0);
signal ctr_dyadic_column_ce : STD_LOGIC;
signal ctr_dyadic_column_rst : STD_LOGIC;
constant ctr_dyadic_column_rst_value : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_dyadic_column_q : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0);
signal limit_ctr_dyadic_column_q : STD_LOGIC;
signal ctr_dyadic_row_ce : STD_LOGIC;
signal ctr_dyadic_row_rst : STD_LOGIC;
constant ctr_dyadic_row_rst_value : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_dyadic_row_q : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0);
signal limit_ctr_dyadic_row_q : STD_LOGIC;
signal ctr_dyadic_matrices_ce : STD_LOGIC;
signal ctr_dyadic_matrices_rst : STD_LOGIC;
constant ctr_dyadic_matrices_rst_value : STD_LOGIC_VECTOR((size_number_dyadic_matrices - 1) downto 0) := (others => '0');
signal ctr_dyadic_matrices_q : STD_LOGIC_VECTOR((size_number_dyadic_matrices - 1) downto 0);
signal ctr_address_base_message_ce : STD_LOGIC;
signal ctr_address_base_message_rst : STD_LOGIC;
constant ctr_address_base_message_rst_value : STD_LOGIC_VECTOR((size_message - size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_address_base_message_q : STD_LOGIC_VECTOR((size_message - size_dyadic_matrix - 1) downto 0);
signal limit_ctr_address_message_q : STD_LOGIC;
signal zero_ctr_address_message_q : STD_LOGIC;
signal ctr_address_base_codeword_ce : STD_LOGIC;
signal ctr_address_base_codeword_rst : STD_LOGIC;
constant ctr_address_base_codeword_rst_value : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0) := std_logic_vector(to_unsigned(length_message/2**size_dyadic_matrix, size_codeword - size_dyadic_matrix));
signal ctr_address_base_codeword_q : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0);
signal limit_ctr_address_codeword_q : STD_LOGIC;
signal reg_address_new_codeword_copy_d : STD_LOGIC_VECTOR((size_message - 1) downto 0);
signal reg_address_new_codeword_copy_ce : STD_LOGIC;
signal reg_address_new_codeword_copy_q : STD_LOGIC_VECTOR((size_message - 1) downto 0);
signal internal_address_codeword : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal internal_address_new_codeword_copy : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal internal_address_message : STD_LOGIC_VECTOR((size_message - 1) downto 0);
signal internal_address_matrix : STD_LOGIC_VECTOR(((size_dyadic_matrix + size_number_dyadic_matrices) - 1) downto 0);
signal internal_codeword : STD_LOGIC;
signal internal_new_codeword : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal partial_product : STD_LOGIC_VECTOR((number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
signal accumulated_values : STD_LOGIC_VECTOR((number_of_accs*(number_of_multipliers_per_acc+1) - 1) downto 0);
signal dyadic_matrix_address : STD_LOGIC_VECTOR(((size_dyadic_matrix)*number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
begin
controller : controller_codeword_generator_3
Port Map(
clk => clk,
rst => rst,
limit_ctr_dyadic_column_q => limit_ctr_dyadic_column_q,
limit_ctr_dyadic_row_q => limit_ctr_dyadic_row_q,
limit_ctr_address_message_q => limit_ctr_address_message_q,
limit_ctr_address_codeword_q => limit_ctr_address_codeword_q,
zero_ctr_address_message_q => zero_ctr_address_message_q,
write_enable_new_codeword => write_enable_new_codeword,
write_enable_new_codeword_copy => write_enable_new_codeword_copy,
external_matrix_ce => external_matrix_ce,
reg_codeword_ce => reg_codeword_ce,
reg_codeword_rst => reg_codeword_rst,
reg_message_ce => reg_message_ce,
reg_matrix_ce => reg_matrix_ce,
ctr_dyadic_column_ce => ctr_dyadic_column_ce,
ctr_dyadic_column_rst => ctr_dyadic_column_rst,
ctr_dyadic_row_ce => ctr_dyadic_row_ce,
ctr_dyadic_row_rst => ctr_dyadic_row_rst,
ctr_dyadic_matrices_ce => ctr_dyadic_matrices_ce,
ctr_dyadic_matrices_rst => ctr_dyadic_matrices_rst,
ctr_address_base_message_ce => ctr_address_base_message_ce,
ctr_address_base_message_rst => ctr_address_base_message_rst,
ctr_address_base_codeword_ce => ctr_address_base_codeword_ce,
ctr_address_base_codeword_rst => ctr_address_base_codeword_rst,
reg_address_new_codeword_copy_ce => reg_address_new_codeword_copy_ce,
internal_codeword => internal_codeword,
codeword_finalized => codeword_finalized
);
cod_accumulators : for I in 0 to (number_of_accs - 1) generate
cod_multipliers : for J in 0 to (number_of_multipliers_per_acc - 1) generate
reg_matrix_I_J : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_matrix_d((I*number_of_multipliers_per_acc + J) downto (I*number_of_multipliers_per_acc + J)),
clk => clk,
ce => reg_matrix_ce,
q => reg_matrix_q((I*number_of_multipliers_per_acc + J) downto (I*number_of_multipliers_per_acc + J))
);
dyadic_matrix_address(((I*number_of_multipliers_per_acc + J + 1)*(size_dyadic_matrix) - 1) downto ((I*number_of_multipliers_per_acc + J)*(size_dyadic_matrix))) <= ((std_logic_vector(unsigned(ctr_dyadic_column_q)+to_unsigned(I, ctr_dyadic_column_q'length))) xor (std_logic_vector(unsigned(ctr_dyadic_row_q)+to_unsigned(J, ctr_dyadic_row_q'length)-number_of_multipliers_per_acc)));
reg_matrix_d(I*number_of_multipliers_per_acc + J) <= external_matrix_q(to_integer(unsigned(dyadic_matrix_address(((I*number_of_multipliers_per_acc + J + 1)*(size_dyadic_matrix) - 1) downto ((I*number_of_multipliers_per_acc + J)*(size_dyadic_matrix))))));
partial_product((I*number_of_multipliers_per_acc + J)) <= reg_message_q(J) and reg_matrix_q((I*number_of_multipliers_per_acc + J));
end generate;
end generate;
accumulators : for I in 0 to (number_of_accs - 1) generate
adder_I : adder_gf_2_m
Generic Map(
gf_2_m => 1,
number_of_elements => number_of_multipliers_per_acc+1
)
Port Map(
a => accumulated_values(((I + 1)*(number_of_multipliers_per_acc+1) - 1) downto I*(number_of_multipliers_per_acc+1)),
o => internal_new_codeword(I downto I)
);
reg_acc_I : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_codeword_d(I downto I),
clk => clk,
ce => reg_codeword_ce,
rst => reg_codeword_rst,
rst_value => reg_codeword_rst_value,
q => reg_codeword_q(I downto I)
);
accumulated_values(((I + 1)*(number_of_multipliers_per_acc+1) - 1) downto I*(number_of_multipliers_per_acc+1)) <= partial_product(((I + 1)*number_of_multipliers_per_acc - 1) downto I*number_of_multipliers_per_acc) & reg_codeword_q(I downto I);
end generate;
multipliers : for I in 0 to (number_of_multipliers_per_acc - 1) generate
reg_vector_I : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_message_d(I downto I),
clk => clk,
ce => reg_message_ce,
q => reg_message_q(I downto I)
);
end generate;
external_matrix : register_nbits
Generic Map(
size => 2**size_dyadic_matrix
)
Port Map(
d => external_matrix_d,
clk => clk,
ce => external_matrix_ce,
q => external_matrix_q
);
ctr_dyadic_column : counter_rst_nbits
Generic Map(
size => size_dyadic_matrix,
increment_value => number_of_accs
)
Port Map(
clk => clk,
ce => ctr_dyadic_column_ce,
rst => ctr_dyadic_column_rst,
rst_value => ctr_dyadic_column_rst_value,
q => ctr_dyadic_column_q
);
ctr_dyadic_row : counter_rst_nbits
Generic Map(
size => size_dyadic_matrix,
increment_value => number_of_multipliers_per_acc
)
Port Map(
clk => clk,
ce => ctr_dyadic_row_ce,
rst => ctr_dyadic_row_rst,
rst_value => ctr_dyadic_row_rst_value,
q => ctr_dyadic_row_q
);
ctr_dyadic_matrices : counter_rst_nbits
Generic Map(
size => size_number_dyadic_matrices,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_dyadic_matrices_ce,
rst => ctr_dyadic_matrices_rst,
rst_value => ctr_dyadic_matrices_rst_value,
q => ctr_dyadic_matrices_q
);
ctr_address_base_vector : counter_rst_nbits
Generic Map(
size => size_message - size_dyadic_matrix,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_address_base_message_ce,
rst => ctr_address_base_message_rst,
rst_value => ctr_address_base_message_rst_value,
q => ctr_address_base_message_q
);
ctr_address_base_acc : counter_rst_nbits
Generic Map(
size => size_codeword - size_dyadic_matrix,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_address_base_codeword_ce,
rst => ctr_address_base_codeword_rst,
rst_value => ctr_address_base_codeword_rst_value,
q => ctr_address_base_codeword_q
);
reg_address_new_acc_copy : register_nbits
Generic Map(
size => size_message
)
Port Map(
d => reg_address_new_codeword_copy_d,
clk => clk,
ce => reg_address_new_codeword_copy_ce,
q => reg_address_new_codeword_copy_q
);
reg_address_new_codeword_copy_d <= ctr_address_base_message_q & ctr_dyadic_row_q;
external_matrix_d <= matrix;
new_codeword <= internal_new_codeword;
new_codeword_copy <= reg_message_q;
reg_codeword_d <= internal_new_codeword when internal_codeword = '1' else
codeword;
reg_message_d <= message;
internal_address_message <= ctr_address_base_message_q & ctr_dyadic_row_q;
internal_address_codeword <= ctr_address_base_codeword_q & ctr_dyadic_column_q;
internal_address_new_codeword_copy <= reg_address_new_codeword_copy_q;
internal_address_matrix((size_number_dyadic_matrices + size_dyadic_matrix - 1) downto size_dyadic_matrix) <= ctr_dyadic_matrices_q;
internal_address_matrix((size_dyadic_matrix - 1) downto 0) <= (others => '0');
address_codeword <= internal_address_codeword;
address_new_codeword_copy <= internal_address_new_codeword_copy;
address_message <= internal_address_message;
address_matrix <= internal_address_matrix;
limit_ctr_dyadic_column_q <= '1' when ctr_dyadic_column_q = std_logic_vector(to_unsigned(2**size_dyadic_matrix - number_of_accs, ctr_dyadic_column_q'length)) else '0';
limit_ctr_dyadic_row_q <= '1' when ctr_dyadic_row_q = std_logic_vector(to_unsigned(2**size_dyadic_matrix - number_of_multipliers_per_acc, ctr_dyadic_row_q'length)) else '0';
limit_ctr_address_message_q <= '1' when internal_address_message((size_message - 1) downto 0) = std_logic_vector(to_unsigned(length_message - number_of_multipliers_per_acc, size_message)) else '0';
limit_ctr_address_codeword_q <= '1' when internal_address_codeword((size_codeword - 1) downto 0) = std_logic_vector(to_unsigned(length_codeword - number_of_accs, size_codeword)) else '0';
zero_ctr_address_message_q <= '1' when internal_address_message((size_message - 1) downto 0) = std_logic_vector(to_unsigned(0, size_message)) else '0';
end RTL;
|
bsd-2-clause
|
4dd31435d8a5d372a78119802eacf860
| 0.691723 | 2.996281 | false | false | false | false |
rodrigoazs/-7-5-Reed-Solomon
|
code/reedsomolon_decoder.vhd
| 1 | 1,889 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity ReedSolomonDecoder is
Port ( Clock : in std_logic;
Count7 : in std_logic;
Qs0: in std_logic_vector(2 downto 0);
Dsyn1: out std_logic_vector(2 downto 0);
Dsyn2: out std_logic_vector(2 downto 0));
end ReedSolomonDecoder;
architecture Behavioral of ReedSolomonDecoder is
component flipflop is
Port ( D: in std_logic_vector(2 downto 0);
Clock : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector(2 downto 0));
end component;
component AdderXor is
Port ( a: in std_logic_vector(2 downto 0);
b: in std_logic_vector(2 downto 0);
c: out std_logic_vector(2 downto 0)) ;
end component;
component Mult is
port(uncoded_a, uncoded_b:
in std_logic_vector(2 downto 0);
uncoded_multab: out std_logic_vector(2 downto 0));
end component;
signal alpha3 : std_logic_vector(2 downto 0);
signal alpha4 : std_logic_vector(2 downto 0);
signal D1 : std_logic_vector(2 downto 0);
signal D2 : std_logic_vector(2 downto 0);
signal Q1 : std_logic_vector(2 downto 0);
signal Q2 : std_logic_vector(2 downto 0);
signal C0 : std_logic_vector(2 downto 0);
signal multa1 : std_logic_vector(2 downto 0);
signal multa2 : std_logic_vector(2 downto 0);
begin
alpha3(0) <= '0'; alpha3(1) <= '1'; alpha3(2) <= '1';
alpha4(0) <= '1'; alpha4(1) <= '1'; alpha4(2) <= '0';
add1 : AdderXor port map (multa1, Qs0, C0);
D1 <= C0;
ff1 : flipflop port map (D1,Clock,Count7,Q1);
add2 : AdderXor port map(Q1, multa2, D2);
ff2 : flipflop port map (D2,Clock,Count7,Q2);
mult1 : Mult port map (Q2, alpha3, multa1);
mult2 : Mult port map (Q2, alpha4, multa2);
Dsyn1 <= D1;
Dsyn2 <= D2;
end Behavioral;
|
mit
|
aa66c7601963a53a7ade1898ecca3193
| 0.696665 | 2.786136 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/controller_error_adder.vhd
| 1 | 4,690 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Error_Adder
-- Module Name: Controller_Error_Adder
-- Project Name: McEliece QD-Goppa Encryption
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This is the state machine controller for the error adder circuit.
-- The state machine only initializes the pipeline, starts adding all errors and
-- then computes the last values of the pipeline.
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.00
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_error_adder is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_ctr_address_codeword_q : in STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_error_ce : out STD_LOGIC;
ctr_address_codeword_ce : out STD_LOGIC;
ctr_address_codeword_rst : out STD_LOGIC;
ctr_address_ciphertext_ce : out STD_LOGIC;
ctr_address_ciphertext_rst : out STD_LOGIC;
write_enable_ciphertext : out STD_LOGIC;
error_added : out STD_LOGIC
);
end controller_error_adder;
architecture Behavioral of controller_error_adder is
type State is (reset, load_counter, load_codeword, add_error, last_error, write_last_error, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, limit_ctr_address_codeword_q)
begin
case (actual_state) is
when reset =>
write_enable_ciphertext <= '0';
reg_codeword_ce <= '0';
reg_error_ce <= '0';
ctr_address_codeword_ce <= '0';
ctr_address_codeword_rst <= '1';
ctr_address_ciphertext_ce <= '0';
ctr_address_ciphertext_rst <= '1';
error_added <= '0';
when load_counter =>
write_enable_ciphertext <= '0';
reg_codeword_ce <= '0';
reg_error_ce <= '0';
ctr_address_codeword_ce <= '1';
ctr_address_codeword_rst <= '0';
ctr_address_ciphertext_ce <= '0';
ctr_address_ciphertext_rst <= '0';
error_added <= '0';
when load_codeword =>
write_enable_ciphertext <= '0';
reg_codeword_ce <= '1';
reg_error_ce <= '1';
ctr_address_codeword_ce <= '1';
ctr_address_codeword_rst <= '0';
ctr_address_ciphertext_ce <= '0';
ctr_address_ciphertext_rst <= '0';
error_added <= '0';
when add_error =>
write_enable_ciphertext <= '1';
reg_codeword_ce <= '1';
reg_error_ce <= '1';
ctr_address_codeword_ce <= '1';
ctr_address_codeword_rst <= '0';
ctr_address_ciphertext_ce <= '1';
ctr_address_ciphertext_rst <= '0';
error_added <= '0';
when last_error =>
write_enable_ciphertext <= '1';
reg_codeword_ce <= '1';
reg_error_ce <= '1';
ctr_address_codeword_ce <= '0';
ctr_address_codeword_rst <= '0';
ctr_address_ciphertext_ce <= '1';
ctr_address_ciphertext_rst <= '0';
error_added <= '0';
when write_last_error =>
write_enable_ciphertext <= '1';
reg_codeword_ce <= '0';
reg_error_ce <= '0';
ctr_address_codeword_ce <= '0';
ctr_address_codeword_rst <= '0';
ctr_address_ciphertext_ce <= '0';
ctr_address_ciphertext_rst <= '0';
error_added <= '0';
when final =>
write_enable_ciphertext <= '0';
reg_codeword_ce <= '0';
reg_error_ce <= '0';
ctr_address_codeword_ce <= '0';
ctr_address_codeword_rst <= '0';
ctr_address_ciphertext_ce <= '0';
ctr_address_ciphertext_rst <= '0';
error_added <= '1';
when others =>
write_enable_ciphertext <= '0';
reg_codeword_ce <= '0';
reg_error_ce <= '0';
ctr_address_codeword_ce <= '0';
ctr_address_codeword_rst <= '0';
ctr_address_ciphertext_ce <= '0';
ctr_address_ciphertext_rst <= '0';
error_added <= '0';
end case;
end process;
NewState : process(actual_state, limit_ctr_address_codeword_q)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= load_codeword;
when load_codeword =>
next_state <= add_error;
when add_error =>
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_error;
else
next_state <= add_error;
end if;
when last_error =>
next_state <= write_last_error;
when write_last_error =>
next_state <= final;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
a226ba0e04247bbfbf4160c288ddc899
| 0.613646 | 3.045455 | false | false | false | false |
rajvinjamuri/ECE385_VHDL
|
block.vhd
| 1 | 3,904 |
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Brick.vhd (Ball.vhd) --
-- --
-- Modeled off ball.vhd version by Stephen Kempf and Viral Mehta --
-- --
-- by Raj Vinjamuri and Sai Koppula --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
---------------------------------------------------------------------------
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Brick is
Port ( clk, Reset, frame_clk : in std_logic;
BallX, BallY, BallS : in std_logic_vector(10 downto 0);
BrickXIn, BrickYIn : in std_logic_vector(10 downto 0);
--BrickX, BrickY: out std_logic_vector(10 downto 0);
brick_hit: out std_logic;
BrickOn: out std_logic);
end Brick;
architecture Behavioral of Brick is
signal Brick_statusSig : std_logic;
signal brick_hitSig : std_logic;
signal Brick_X_pos, Brick_Y_pos : std_logic_vector(10 downto 0);
signal Brick_Width : std_logic_vector(10 downto 0);
signal Brick_Height: std_logic_vector(10 downto 0);
signal Brick_X, Brick_Y : std_logic_vector (10 downto 0);
--constant Brick_X : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(0, 11); --Center position on the X axis
--constant Brick_Y : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(0, 11); --Center position on the Y axis
signal Brick_Y_Set : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(20, 11); --Center position on the Y axis
constant Brick_X_Min : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(0, 11); --Leftmost point on the X axis
constant Brick_X_Max : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(639, 11); --Rightmost point on the X axis
constant Brick_Y_Min : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(0, 11); --Topmost point on the Y axis
constant Brick_Y_Max : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(470, 11); --Bottommost point on the Y axis
begin
Brick_Width <= CONV_STD_LOGIC_VECTOR(60, 11);
Brick_Height <= CONV_STD_LOGIC_VECTOR(20, 11);
Brick_X <= BrickXIn;
Brick_Y <= BrickYIn;
Handle_Brick: process(Reset, frame_clk)
begin
if(Reset = '1') then --Asynchronous Reset
Brick_Y_pos <= Brick_Y;
Brick_X_pos <= Brick_X;
Brick_statusSig <= '1';
elsif(rising_edge(frame_clk)) then
brick_hitSig <= '0';
if (BallX-BallS <= Brick_X + Brick_Width) AND (BallX-BallS >= Brick_X)
AND (BallY+BallS>= Brick_Y) AND (BallY-BallS<= Brick_Y + Brick_Height) then
if (Brick_statusSig = '1') then brick_hitSig <= '1'; end if;
Brick_statusSig <= '0';
elsif (BallX+BallS <= Brick_X + Brick_Width) AND (BallX+BallS >= Brick_X)
AND (BallY+BallS>= Brick_Y) AND (BallY-BallS<= Brick_Y + Brick_Height) then
if (Brick_statusSig = '1') then brick_hitSig <= '1'; end if;
Brick_statusSig <= '0';
elsif (BallY-BallS <= Brick_Y + Brick_Height) AND (BallY-BallS >= Brick_Y)
AND (BallX+BallS>= Brick_X) AND (BallX-BallS<= Brick_X + Brick_Width) then
if (Brick_statusSig = '1') then brick_hitSig <= '1'; end if;
Brick_statusSig <= '0';
elsif (BallY+BallS <= Brick_Y + Brick_Height) AND (BallY+BallS >= Brick_Y)
AND (BallX+BallS>= Brick_X) AND (BallX-BallS<= Brick_X + Brick_Width) then
if (Brick_statusSig = '1') then brick_hitSig <= '1'; end if;
Brick_statusSig <= '0';
end if;
end if;
end process Handle_Brick;
--BrickX <= Brick_X_pos;
--BrickY <= Brick_Y_pos;
BrickOn <= Brick_statusSig;
brick_hit <= brick_hitSig;
end Behavioral;
|
mit
|
c9af48b5315d5db5d48af91acc11c7af
| 0.576332 | 3.439648 | false | false | false | false |
laurivosandi/hdl
|
primitives/src/sram.vhd
| 1 | 703 |
-- Single port 256-byte static RAM
entity sram is
port (
we : in std_logic := '1', -- Write enable
oe : in std_logic := '0', -- Output enable
a : in std_logic_vector(7 downto 0), -- Address
din : in std_logic_vector(7 downto 0), -- Data in
dout : out std_logic_vector(7 downto 0), -- Data out
signal address : integer range 0 to 255;
end sram;
architecture behavioral of sram is
begin
process(oe)
if (oe == '1') then
dout <= std_logic_vector(to_unsigned(mem(address),8));
end if
end process
address <= to_integer(unsigned(a));
end behavioral;
|
mit
|
5d19156d4f54084e3f4cd6ec60871bb7
| 0.533428 | 3.719577 | false | false | false | false |
sakolkar/4BitSorter
|
Synopsis/sorter.vhd
| 1 | 3,047 |
----------------------------------------------------------
-- EE453 Lab3 Tutorial - 4 Unsigned 4-Bit Inputs Bubble Sorter
-- Khaled Al-Amoodi
-- Top level: sorter
-- Sorts 4 unsigned 4-bit inputs (A-D) so that S1 is largest
-- and S4 is smallest.
----------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sorter IS
Port (
Clk : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(3 downto 0);
B : IN STD_LOGIC_VECTOR(3 downto 0);
C : IN STD_LOGIC_VECTOR(3 downto 0);
D : IN STD_LOGIC_VECTOR(3 downto 0);
S1reg : OUT STD_LOGIC_VECTOR(3 downto 0);
S2reg : OUT STD_LOGIC_VECTOR(3 downto 0);
S3reg : OUT STD_LOGIC_VECTOR(3 downto 0);
S4reg : OUT STD_LOGIC_VECTOR(3 downto 0)
);
END sorter;
architecture RTL of sorter is
-- Internal Signal Declaration
signal Areg : std_logic_vector(3 downto 0);
signal Breg : std_logic_vector(3 downto 0);
signal Creg : std_logic_vector(3 downto 0);
signal Dreg : std_logic_vector(3 downto 0);
signal S1 : std_logic_vector(3 downto 0);
signal S2 : std_logic_vector(3 downto 0);
signal S3 : std_logic_vector(3 downto 0);
signal S4 : std_logic_vector(3 downto 0);
-- Temporary signals within stages
signal T1_1, T1_2, T2_1, T2_2, T3_1, T3_2 : std_logic_vector(3 downto 0);
-- Signals between stages 1 and 2
signal O1_A, O1_B, O1_C, O1_D : std_logic_vector(3 downto 0);
-- Signals between stages 3 and 4
signal O2_A, O2_B, O2_C, O2_D : std_logic_vector(3 downto 0);
signal R1_A, R1_B, R1_C, R1_D : std_logic_vector(3 downto 0);
signal R2_A, R2_B, R2_C, R2_D : std_logic_vector(3 downto 0);
begin -- RTL
process (Clk)
begin -- process
if rising_edge(Clk) then
Areg <= A;
Breg <= B;
Creg <= C;
Dreg <= D;
R1_A <= O1_A;
R1_B <= O1_B;
R1_C <= O1_C;
R1_D <= O1_D;
R2_A <= O2_A;
R2_B <= O2_B;
R2_C <= O2_C;
R2_D <= O2_D;
S1reg <= S1;
S2reg <= S2;
S3reg <= S3;
S4reg <= S4;
end if;
end process;
-- Stage 1
O1_A <= Breg when (Areg < Breg) else Areg;
T1_1 <= Areg when (Areg < Breg) else Breg;
O1_B <= Creg when (T1_1 < Creg) else T1_1;
T1_2 <= T1_1 when (T1_1 < Creg) else Creg;
O1_C <= Dreg when (T1_2 < Dreg) else T1_2;
O1_D <= T1_2 when (T1_2 < Dreg) else Dreg;
-- Stage 2
O2_A <= R1_B when (R1_A < R1_B) else R1_A;
T2_1 <= R1_A when (R1_A < R1_B) else R1_B;
O2_B <= R1_C when (T2_1 < R1_C) else T2_1;
T2_2 <= T2_1 when (T2_1 < R1_C) else R1_C;
O2_C <= R1_D when (T2_2 < R1_D) else T2_2;
O2_D <= T2_2 when (T2_2 < R1_D) else R1_D;
-- Stage 3
S1 <= R2_B when (R2_A < R2_B) else R2_A;
T3_1 <= R2_A when (R2_A < R2_B) else R2_B;
S2 <= R2_C when (T3_1 < R2_C) else T3_1;
T3_2 <= T3_1 when (T3_1 < R2_C) else R2_C;
S3 <= R2_D when (T3_2 < R2_D) else T3_2;
S4 <= T3_2 when (T3_2 < R2_D) else R2_D;
END RTL;
|
apache-2.0
|
b76909763162bb590351e6dc0d616995
| 0.547424 | 2.362016 | false | false | false | false |
ruygargar/LCSE_lab
|
ram/tb_ram.vhd
| 1 | 3,338 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:21:46 01/03/2014
-- Design Name:
-- Module Name: C:/Users/Ruy/Desktop/LCSE_lab/ram/tb_ram.vhd
-- Project Name: ram
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ram
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
ENTITY tb_ram IS
END tb_ram;
ARCHITECTURE behavior OF tb_ram IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ram
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
WriteEnable : IN std_logic;
OutputEnable : IN std_logic;
ChipSelect : IN std_logic;
Address : IN std_logic_vector(7 downto 0);
Databus : INOUT std_logic_vector(7 downto 0) := (others => 'Z');
Switches : OUT std_logic_vector(7 downto 0);
Temp_L : OUT std_logic_vector(6 downto 0);
Temp_h : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal WriteEnable : std_logic := '0';
signal OutputEnable : std_logic := '0';
signal ChipSelect : std_logic := '0';
signal Address : std_logic_vector(7 downto 0) := (others => '0');
--BiDirs
signal Databus : std_logic_vector(7 downto 0) := (others => 'Z');
--Outputs
signal Switches : std_logic_vector(7 downto 0);
signal Temp_L : std_logic_vector(6 downto 0);
signal Temp_h : std_logic_vector(6 downto 0);
-- Clock period definitions
constant Clk_period : time := 25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ram PORT MAP (
Clk => Clk,
Reset => Reset,
WriteEnable => WriteEnable,
OutputEnable => OutputEnable,
ChipSelect => ChipSelect,
Address => Address,
Databus => Databus,
Switches => Switches,
Temp_L => Temp_L,
Temp_h => Temp_h
);
Clk <= not Clk after Clk_period;
-- Stimulus process
process
begin
wait for 100 ns;
Reset <= '1';
wait;
end process;
process
variable aux_address : integer range 0 to 255;
begin
wait for 150 ns;
ChipSelect <= '1';
WriteEnable <= '1';
OutputEnable <= '0';
Databus <= X"55";
for aux_address in 0 to 255 loop
Address <= conv_std_logic_vector(aux_address, 8);
wait for 50 ns;
end loop;
WriteEnable <= '0';
OutputEnable <= '1';
Databus <= (others => 'Z');
for aux_address in 0 to 255 loop
Address <= conv_std_logic_vector(aux_address, 8);
wait for 50 ns;
end loop;
wait;
end process;
END;
|
gpl-3.0
|
2c9f15899d05b5cececd31575ea21035
| 0.582385 | 3.708889 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/memory_read_proxy/memory_read_proxy_tb.vhd
| 1 | 2,642 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory_read_proxy_tb is
end entity;
architecture memory_read_proxy_tb_arq of memory_read_proxy_tb is
signal x_in : std_logic_vector(9 downto 0) := (others => '0');
signal y_in : std_logic_vector(9 downto 0) := (others => '0');
signal x_out : std_logic_vector(9 downto 0) := (others => '0');
signal y_out : std_logic_vector(9 downto 0) := (others => '0');
signal value_out : std_logic_vector(0 downto 0) := (others => '0');
component memory_read_proxy is
generic(STARTING_X: integer := 0; STARTING_Y: integer := 0);
port(
x_in: in std_logic_vector(9 downto 0) := (others => '0');
y_in: in std_logic_vector(9 downto 0) := (others => '0');
memory_value: in std_logic_vector(0 downto 0) := (others => '0');
x_out: out std_logic_vector(9 downto 0) := (others => '0');
y_out: out std_logic_vector(9 downto 0) := (others => '0');
proxy_value: out std_logic_vector(0 downto 0) := (others => '0')
);
end component;
begin
memory_read_proxy_0 : memory_read_proxy
generic map(STARTING_X => 4, STARTING_Y => 3)
port map(
x_in => x_in,
x_out => x_out,
y_in => y_in,
y_out => y_out,
memory_value => "1",
proxy_value => value_out
);
process
type pattern_type is record
xi : std_logic_vector(9 downto 0);
yi : std_logic_vector(9 downto 0);
xo : std_logic_vector(9 downto 0);
yo : std_logic_vector(9 downto 0);
vo : std_logic_vector(0 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("0000000000","0000000000","0000000000","0000000000","0"),
("0000000011","0000000010","0000000000","0000000000","0"),
("0000001110","0000000010","0000000000","0000000000","0"),
("0000000011","0000011111","0000000000","0000000000","0"),
("0000000111","0000000111","0000000011","0000000100","1")
);
begin
for i in patterns'range loop
-- Set the inputs.
x_in <= patterns(i).xi;
y_in <= patterns(i).yi;
wait for 1 ns;
assert patterns(i).vo = value_out report "BAD VALUE, EXPECTED: " & std_logic'image(patterns(i).vo(0)) & " GOT: " & std_logic'image(value_out(0));
assert patterns(i).xo = x_out report "BAD X, EXPECTED: " & integer'image(to_integer(signed(patterns(i).xo))) & " GOT: " & integer'image(to_integer(signed(x_out)));
assert patterns(i).yo = y_out report "BAD Y, GOT: " & integer'image(to_integer(signed(y_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
4121c390cf9c3353368becf812c028c2
| 0.62869 | 2.988688 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/codeword_generator_n_m.vhd
| 1 | 18,295 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Codeword_Generator_n_m
-- Module Name: Codeword_Generator_n_m
-- Project Name: McEliece QD-Goppa Encoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The first and only step in QD-Goppa Code encoding.
-- This circuit transforms an k-bit message into a valid n-bit codeword.
-- The transformation is an multiplication of a message of k-bits by the
-- Generator matrix G. The Generator matrix is composed of Identity Matrix and
-- another matrix A. For this reason the first k bits of the codeword are equal
-- to the message, only the last n-k bits are computed. This circuit works only
-- only for QD-Goppa codes, where matrix A is composed of dyadic matrices and
-- can be stored only by the first row of each dyadic matrix.
-- Matrix A is supposed to be stored with a word of 1 bit and each dyadic matrix row
-- followed by each one, in a row-wise pattern.
--
-- This circuit process n+m bits at time, each time is more than 1 cycle.
-- n and m are represented as number_of_multipliers_per_acc and number_of_accs parameters.
-- This circuit is efficient however is necessary to access n+m memories at the same time.
-- This problem is countered in version n_m_v2.
--
-- The circuits parameters
--
-- number_of_multipliers_per_acc :
--
-- The number of matrix rows and message values calculate at once in one or more accumulators.
-- On this implementation this value, must be the same of number_of_accs,
-- because of copy message. When copying message message values loaded must be same stored in codeword.
-- This value also must be power of 2.
--
-- number_of_accs :
--
-- The number of matrix columns and codeword values calculate at once.
-- On this implementation this value, must be the same of number_of_multipliers_per_acc,
-- because of copy message. When copying message message values loaded must be same stored in codeword.
-- This value also must be power of 2.
--
-- length_message :
--
-- Length in bits of message size and also part of matrix size.
--
-- size_message :
--
-- The number of bits necessary to store the message. The ceil(log2(lenght_message))
--
-- length_codeword :
--
-- Length in bits of codeword size and also part of matrix size.
--
-- size_codeword :
--
-- The number of bits necessary to store the codeword. The ceil(log2(legth_codeword))
--
-- size_dyadic_matrix :
--
-- The number of bits necessary to store one row of the dyadic matrix.
-- It is also the ceil(log2(number of errors in the code))
--
-- number_dyadic_matrices :
--
-- The number of dyadic matrices present in matrix A.
--
-- size_number_dyadic_matrices :
--
-- The number of bits necessary to store the number of dyadic matrices.
-- The ceil(log2(number_dyadic_matrices))
--
-- Dependencies:
--
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- controller_codeword_generator_1 Rev 1.0
-- adder_gf_2_m Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_rst_set_nbits Rev 1.0
--
-- Revision:
-- Revision 1.00 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity codeword_generator_n_m is
Generic(
-- QD-GOPPA [2528, 2144, 32, 12] --
number_of_multipliers_per_acc : integer := 4;
number_of_accs : integer := 4;
length_message : integer := 2144;
size_message : integer := 12;
length_codeword : integer := 2528;
size_codeword : integer := 12;
size_dyadic_matrix : integer := 5;
number_dyadic_matrices : integer := 804;
size_number_dyadic_matrices : integer := 10
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_multipliers_per_acc : integer := 1;
-- number_of_accs : integer := 1;
-- length_message : integer := 2048;
-- size_message : integer := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 384;
-- size_number_dyadic_matrices : integer := 9
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_multipliers_per_acc : integer := 1;
-- number_of_accs : integer := 1;
-- length_message : integer := 2560;
-- size_message : integer := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 480;
-- size_number_dyadic_matrices : integer := 9
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_multipliers_per_acc : integer := 128;
-- number_of_accs : integer := 128;
-- length_message : integer := 5632;
-- size_message : integer := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- size_dyadic_matrix : integer := 7;
-- number_dyadic_matrices : integer := 572;
-- size_number_dyadic_matrices : integer := 10
);
Port(
codeword : in STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
matrix : in STD_LOGIC_VECTOR((number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
message : in STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
new_codeword : out STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
write_enable_new_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC;
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_message : out STD_LOGIC_VECTOR((size_message - 1) downto 0);
address_matrix : out STD_LOGIC_VECTOR(((size_dyadic_matrix + size_number_dyadic_matrices)*number_of_accs*number_of_multipliers_per_acc - 1) downto 0)
);
end codeword_generator_n_m;
architecture RTL of codeword_generator_n_m is
component controller_codeword_generator_1
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_ctr_dyadic_column_q : in STD_LOGIC;
limit_ctr_dyadic_row_q : in STD_LOGIC;
limit_ctr_address_message_q : in STD_LOGIC;
limit_ctr_address_codeword_q : in STD_LOGIC;
write_enable_new_codeword : out STD_LOGIC;
message_into_new_codeword : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_codeword_rst : out STD_LOGIC;
reg_message_ce : out STD_LOGIC;
reg_matrix_ce : out STD_LOGIC;
ctr_dyadic_column_ce : out STD_LOGIC;
ctr_dyadic_column_rst : out STD_LOGIC;
ctr_dyadic_row_ce : out STD_LOGIC;
ctr_dyadic_row_rst : out STD_LOGIC;
ctr_dyadic_matrices_ce : out STD_LOGIC;
ctr_dyadic_matrices_rst : out STD_LOGIC;
ctr_address_base_message_ce : out STD_LOGIC;
ctr_address_base_message_rst : out STD_LOGIC;
ctr_address_base_codeword_ce : out STD_LOGIC;
ctr_address_base_codeword_rst : out STD_LOGIC;
ctr_address_base_codeword_set : out STD_LOGIC;
internal_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_set_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
set : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
set_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component adder_gf_2_m
Generic(
gf_2_m : integer := 1;
number_of_elements : integer range 2 to integer'high := 2
);
Port(
a : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_elements) - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal reg_codeword_d : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal reg_codeword_ce : STD_LOGIC;
signal reg_codeword_rst : STD_LOGIC;
constant reg_codeword_rst_value : STD_LOGIC_VECTOR := "0";
signal reg_codeword_q : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal reg_message_d : STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
signal reg_message_ce : STD_LOGIC;
signal reg_message_q : STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
signal reg_matrix_d : STD_LOGIC_VECTOR((number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
signal reg_matrix_ce : STD_LOGIC;
signal reg_matrix_q : STD_LOGIC_VECTOR((number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
signal ctr_dyadic_column_ce : STD_LOGIC;
signal ctr_dyadic_column_rst : STD_LOGIC;
constant ctr_dyadic_column_rst_value : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_dyadic_column_q : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0);
signal limit_ctr_dyadic_column_q : STD_LOGIC;
signal ctr_dyadic_row_ce : STD_LOGIC;
signal ctr_dyadic_row_rst : STD_LOGIC;
constant ctr_dyadic_row_rst_value : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_dyadic_row_q : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0);
signal limit_ctr_dyadic_row_q : STD_LOGIC;
signal ctr_dyadic_matrices_ce : STD_LOGIC;
signal ctr_dyadic_matrices_rst : STD_LOGIC;
constant ctr_dyadic_matrices_rst_value : STD_LOGIC_VECTOR((size_number_dyadic_matrices - 1) downto 0) := (others => '0');
signal ctr_dyadic_matrices_q : STD_LOGIC_VECTOR((size_number_dyadic_matrices - 1) downto 0);
signal ctr_address_base_message_ce : STD_LOGIC;
signal ctr_address_base_message_rst : STD_LOGIC;
constant ctr_address_base_message_rst_value : STD_LOGIC_VECTOR((size_message - size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_address_base_message_q : STD_LOGIC_VECTOR((size_message - size_dyadic_matrix - 1) downto 0);
signal limit_ctr_address_message_q : STD_LOGIC;
signal ctr_address_base_codeword_ce : STD_LOGIC;
signal ctr_address_base_codeword_rst : STD_LOGIC;
signal ctr_address_base_codeword_set : STD_LOGIC;
constant ctr_address_base_codeword_rst_value : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0) := (others => '0');
constant ctr_address_base_codeword_set_value : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0) := std_logic_vector(to_unsigned(length_message/2**size_dyadic_matrix, size_codeword - size_dyadic_matrix));
signal ctr_address_base_codeword_q : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0);
signal limit_ctr_address_codeword_q : STD_LOGIC;
signal internal_address_codeword : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal internal_address_message : STD_LOGIC_VECTOR((size_message - 1) downto 0);
signal internal_address_matrix : STD_LOGIC_VECTOR((number_of_accs*number_of_multipliers_per_acc*(size_dyadic_matrix + size_number_dyadic_matrices) - 1) downto 0);
signal internal_codeword : STD_LOGIC;
signal internal_new_codeword : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal message_into_new_codeword : STD_LOGIC;
signal partial_product : STD_LOGIC_VECTOR((number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
signal accumulated_values : STD_LOGIC_VECTOR((number_of_accs*(number_of_multipliers_per_acc+1) - 1) downto 0);
begin
controller : controller_codeword_generator_1
Port Map(
clk => clk,
rst => rst,
limit_ctr_dyadic_column_q => limit_ctr_dyadic_column_q,
limit_ctr_dyadic_row_q => limit_ctr_dyadic_row_q,
limit_ctr_address_message_q => limit_ctr_address_message_q,
limit_ctr_address_codeword_q => limit_ctr_address_codeword_q,
write_enable_new_codeword => write_enable_new_codeword,
message_into_new_codeword => message_into_new_codeword,
reg_codeword_ce => reg_codeword_ce,
reg_codeword_rst => reg_codeword_rst,
reg_message_ce => reg_message_ce,
reg_matrix_ce => reg_matrix_ce,
ctr_dyadic_column_ce => ctr_dyadic_column_ce,
ctr_dyadic_column_rst => ctr_dyadic_column_rst,
ctr_dyadic_row_ce => ctr_dyadic_row_ce,
ctr_dyadic_row_rst => ctr_dyadic_row_rst,
ctr_dyadic_matrices_ce => ctr_dyadic_matrices_ce,
ctr_dyadic_matrices_rst => ctr_dyadic_matrices_rst,
ctr_address_base_message_ce => ctr_address_base_message_ce,
ctr_address_base_message_rst => ctr_address_base_message_rst,
ctr_address_base_codeword_ce => ctr_address_base_codeword_ce,
ctr_address_base_codeword_rst => ctr_address_base_codeword_rst,
ctr_address_base_codeword_set => ctr_address_base_codeword_set,
internal_codeword => internal_codeword,
codeword_finalized => codeword_finalized
);
cod_accumulators : for I in 0 to (number_of_accs - 1) generate
cod_multipliers : for J in 0 to (number_of_multipliers_per_acc - 1) generate
reg_matrix_I_J : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_matrix_d((I*number_of_multipliers_per_acc + J) downto (I*number_of_multipliers_per_acc + J)),
clk => clk,
ce => reg_matrix_ce,
q => reg_matrix_q((I*number_of_multipliers_per_acc + J) downto (I*number_of_multipliers_per_acc + J))
);
partial_product((I*number_of_multipliers_per_acc + J)) <= reg_message_q(J) and reg_matrix_q((I*number_of_multipliers_per_acc + J));
internal_address_matrix(((I*number_of_multipliers_per_acc + J + 1)*(size_dyadic_matrix + size_number_dyadic_matrices) - 1) downto ((I*number_of_multipliers_per_acc + J)*(size_dyadic_matrix + size_number_dyadic_matrices))) <= ctr_dyadic_matrices_q & ((std_logic_vector(unsigned(ctr_dyadic_column_q)+to_unsigned(I, ctr_dyadic_column_q'length))) xor (std_logic_vector(unsigned(ctr_dyadic_row_q)+to_unsigned(J, ctr_dyadic_row_q'length))));
end generate;
end generate;
accumulators : for I in 0 to (number_of_accs - 1) generate
adder_I : adder_gf_2_m
Generic Map(
gf_2_m => 1,
number_of_elements => number_of_multipliers_per_acc+1
)
Port Map(
a => accumulated_values(((I + 1)*(number_of_multipliers_per_acc+1) - 1) downto I*(number_of_multipliers_per_acc+1)),
o => internal_new_codeword(I downto I)
);
reg_codeword_I : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_codeword_d(I downto I),
clk => clk,
ce => reg_codeword_ce,
rst => reg_codeword_rst,
rst_value => reg_codeword_rst_value,
q => reg_codeword_q(I downto I)
);
accumulated_values(((I + 1)*(number_of_multipliers_per_acc+1) - 1) downto I*(number_of_multipliers_per_acc+1)) <= partial_product(((I + 1)*number_of_multipliers_per_acc - 1) downto I*number_of_multipliers_per_acc) & reg_codeword_q(I downto I);
end generate;
multipliers : for I in 0 to (number_of_multipliers_per_acc - 1) generate
reg_message_I : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_message_d(I downto I),
clk => clk,
ce => reg_message_ce,
q => reg_message_q(I downto I)
);
end generate;
ctr_dyadic_column : counter_rst_nbits
Generic Map(
size => size_dyadic_matrix,
increment_value => number_of_accs
)
Port Map(
clk => clk,
ce => ctr_dyadic_column_ce,
rst => ctr_dyadic_column_rst,
rst_value => ctr_dyadic_column_rst_value,
q => ctr_dyadic_column_q
);
ctr_dyadic_row : counter_rst_nbits
Generic Map(
size => size_dyadic_matrix,
increment_value => number_of_multipliers_per_acc
)
Port Map(
clk => clk,
ce => ctr_dyadic_row_ce,
rst => ctr_dyadic_row_rst,
rst_value => ctr_dyadic_row_rst_value,
q => ctr_dyadic_row_q
);
ctr_dyadic_matrices : counter_rst_nbits
Generic Map(
size => size_number_dyadic_matrices,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_dyadic_matrices_ce,
rst => ctr_dyadic_matrices_rst,
rst_value => ctr_dyadic_matrices_rst_value,
q => ctr_dyadic_matrices_q
);
ctr_address_base_message : counter_rst_nbits
Generic Map(
size => size_message - size_dyadic_matrix,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_address_base_message_ce,
rst => ctr_address_base_message_rst,
rst_value => ctr_address_base_message_rst_value,
q => ctr_address_base_message_q
);
ctr_address_base_codeword : counter_rst_set_nbits
Generic Map(
size => size_codeword - size_dyadic_matrix,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_address_base_codeword_ce,
set => ctr_address_base_codeword_set,
rst => ctr_address_base_codeword_rst,
set_value => ctr_address_base_codeword_set_value,
rst_value => ctr_address_base_codeword_rst_value,
q => ctr_address_base_codeword_q
);
new_codeword <= reg_message_q when message_into_new_codeword = '1' else
internal_new_codeword;
reg_codeword_d <= internal_new_codeword when internal_codeword = '1' else
codeword;
reg_message_d <= message;
reg_matrix_d <= matrix;
internal_address_message <= ctr_address_base_message_q & ctr_dyadic_row_q;
internal_address_codeword <= ctr_address_base_codeword_q & ctr_dyadic_column_q;
address_codeword <= internal_address_codeword;
address_message <= internal_address_message;
address_matrix <= internal_address_matrix;
limit_ctr_dyadic_column_q <= '1' when ctr_dyadic_column_q = std_logic_vector(to_unsigned(2**size_dyadic_matrix - number_of_accs, ctr_dyadic_column_q'length)) else '0';
limit_ctr_dyadic_row_q <= '1' when ctr_dyadic_row_q = std_logic_vector(to_unsigned(2**size_dyadic_matrix - number_of_multipliers_per_acc, ctr_dyadic_row_q'length)) else '0';
limit_ctr_address_message_q <= '1' when internal_address_message((size_message - 1) downto 0) = std_logic_vector(to_unsigned(length_message - number_of_multipliers_per_acc, size_message)) else '0';
limit_ctr_address_codeword_q <= '1' when internal_address_codeword((size_codeword - 1) downto 0) = std_logic_vector(to_unsigned(length_codeword - number_of_accs, size_codeword)) else '0';
end RTL;
|
bsd-2-clause
|
222e1d3ed814b382fbf6e68d44e4202a
| 0.690517 | 3.012018 | false | false | false | false |
laurivosandi/hdl
|
zynq/src/bcd_counter.vhd
| 1 | 1,251 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd_counter is
port (
clk_in : in std_logic;
reset : in std_logic;
inc : in std_logic;
bcd : out std_logic_vector(3 downto 0);
clk_out : out std_logic);
end;
architecture behavioral of bcd_counter is
signal temporal: std_logic;
signal counter : integer range 0 to 10;
begin
counter_process: process (reset, clk_in) begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if inc = '1' then
if (counter = 9) then
temporal <= '1';
counter <= 0;
else
temporal <= '0';
counter <= counter + 1;
end if;
else
if (counter = 0) then
temporal <= '1';
counter <= 9;
else
temporal <= '0';
counter <= counter - 1;
end if;
end if;
end if;
end process;
clk_out <= temporal;
bcd <= std_logic_vector(to_unsigned(counter,4));
end;
|
mit
|
3547264de7240d58baaa515a650b80ac
| 0.449241 | 4.240678 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/memory_read_proxy/memory_read_proxy.vhd
| 1 | 1,547 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--This component will map an address sent to the memory so that
entity memory_read_proxy is
generic(STARTING_X: integer := 0; STARTING_Y: integer := 0; X_LENGTH: integer := 350; Y_LENGTH: integer := 350);
port(
x_in: in std_logic_vector(9 downto 0) := (others => '0');
y_in: in std_logic_vector(9 downto 0) := (others => '0');
memory_value: in std_logic_vector(0 downto 0) := (others => '0');
x_out: out std_logic_vector(9 downto 0) := (others => '0');
y_out: out std_logic_vector(9 downto 0) := (others => '0');
proxy_value: out std_logic_vector(0 downto 0) := (others => '0')
);
end memory_read_proxy;
architecture memory_read_proxy_arq of memory_read_proxy is
signal memory_data : std_logic_vector(0 downto 0) := (others => '0');
begin
process(x_in,y_in)
variable x_in_int : integer := 0;
variable y_in_int : integer := 0;
begin
x_in_int := to_integer(unsigned(x_in));
y_in_int := to_integer(unsigned(y_in));
memory_data <= memory_value;
if(x_in_int >= STARTING_X and
x_in_int <= (STARTING_X + X_LENGTH) and
y_in_int >= STARTING_Y and
y_in_int <= (STARTING_Y + Y_LENGTH)) then
x_out <= std_logic_vector(to_unsigned(x_in_int - STARTING_X,10));
y_out <= std_logic_vector(to_unsigned(y_in_int - STARTING_Y,10));
proxy_value <= memory_data;
else
x_out <= (others => '0');
y_out <= (others => '0');
proxy_value <= (others => '0');
end if;
end process;
end architecture;
|
gpl-3.0
|
835b7e82e9f4b12923e91b81e7973da5
| 0.616031 | 2.828154 | false | false | false | false |
KenKeeley/My68k-system
|
CircuitBoards/MainBoard/DRAMControllerCPLD/StateMachine.vhd
| 1 | 10,331 |
----------------------------------------------------------------------------------------------------
--
-- FileName: StateMachine.vhd
-- Description: MainBoard DRAM Controller CPLD State Machine.
--
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
LIBRARY work;
ENTITY StateMachine IS
PORT
(
Clk : IN STD_LOGIC; -- Clock
nReset : IN STD_LOGIC; -- Reset
nWR : IN STD_LOGIC; -- CPU Read/Write signal
nCS_DRAM : IN STD_LOGIC; -- DRAM Chip Select
nPage_Hit : IN STD_LOGIC; -- Request is in Same Page
nBank : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- DRAM Bank to Address
nByte : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- Byte/s Selected
nPreCharge : OUT STD_LOGIC; -- Flag to show when in PreCharge
nDSACK0 : OUT STD_LOGIC; -- Data size/ack signal 0 to CPU
nDSACK1 : OUT STD_LOGIC; -- Data size/ack signal 1 to CPU
nRAS : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- Row Address Select
nCAS : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- Column Address Select
nWE_DRAM : OUT STD_LOGIC -- DRAM Read/Write signal
);
END StateMachine;
ARCHITECTURE Behavioral OF StateMachine IS
-- Asynchronous Signals
SIGNAL nDSACK0_Async : STD_LOGIC;
SIGNAL nDSACK1_Async : STD_LOGIC;
SIGNAL nRAS_Async : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL nCAS_Async : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL nWR_Async : STD_LOGIC;
SIGNAL RefAck_Async : STD_LOGIC;
-- Internal Signals
SIGNAL CurrentState : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL NextState : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL RefReq : STD_LOGIC; -- Refresh Request
SIGNAL RefAck : STD_LOGIC; -- Refresh Async
SIGNAL tc : std_logic; -- Refresh counter terminal count signal
SIGNAL q : std_logic_vector(8 downto 0); -- The refresh counter
SIGNAL pRAS : STD_LOGIC_VECTOR (7 DOWNTO 0); -- Page mode RAS signals
-- State Declarations
CONSTANT idle : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
CONSTANT rw1 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
CONSTANT rw2 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
CONSTANT rw3 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT page1 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
CONSTANT page2 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
CONSTANT page3 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0110";
CONSTANT cbr1 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0111";
CONSTANT cbr2 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000";
CONSTANT cbr3 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1001";
CONSTANT cbr4 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1010";
CONSTANT dummy1 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1011";
CONSTANT dummy2 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1100";
CONSTANT dummy3 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1101";
CONSTANT dummy4 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1110";
CONSTANT prechg : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1111";
BEGIN
---------------------------------------
------ Asynchronous Process -----------
---------------------------------------
Async_Cont: PROCESS (nCS_DRAM, nPage_Hit, RefReq, CurrentState, nBank, nByte, nWR, pRAS)
BEGIN
CASE CurrentState IS
WHEN idle =>
nPreCharge <= '1';
nCAS_Async <= "1111";
nDSACK0_Async <= '1';
nDSACK1_Async <= '1';
RefAck_Async <= '0';
-- Do a refresh cycle
IF (RefReq = '1') THEN
NextState <= cbr1;
nWR_Async <= '1';
nRAS_Async <= "11111111";
-- Do a normal read/write cycle
ELSIF (nCS_DRAM = '0') THEN
NextState <= rw1;
nWR_Async <= nWR;
nRAS_Async <= nBank;
ELSE
NextState <= idle;
nWR_Async <= '1';
nRAS_Async <= nBank;
END IF;
-- DRAM Access Start
WHEN rw1 =>
NextState <= rw2;
nPreCharge <= '1';
nRAS_Async <= nBank;
nCAS_Async <= nByte;
nDSACK0_Async <= '0';
nDSACK1_Async <= '0';
RefAck_Async <= '0';
nWR_Async <= nWR;
WHEN rw2 =>
NextState <= rw3;
nPreCharge <= '1';
nRAS_Async <= nBank;
nCAS_Async <= "1111";
nDSACK0_Async <= '1';
nDSACK1_Async <= '1';
RefAck_Async <= '0';
nWR_Async <= nWR;
WHEN rw3 =>
nCAS_Async <= "1111";
nPreCharge <= '1';
nDSACK0_Async <= '1';
nDSACK1_Async <= '1';
RefAck_Async <= '0';
-- Goto Page Mode access
IF (nPage_Hit = '0') THEN
NextState <= page1;
nRAS_Async <= pRAS;
nWR_Async <= nWR;
ELSE
NextState <= prechg;
nRAS_Async <= "11111111";
nWR_Async <= '1';
END IF;
WHEN page1 =>
nPreCharge <= '1';
nRAS_Async <= pRAS;
nDSACK0_Async <= '1';
nDSACK1_Async <= '1';
RefAck_Async <= '0';
nWR_Async <= nWR;
IF (nCS_DRAM = '0' AND nPage_Hit = '0') THEN
NextState <= page2;
nCAS_Async <= nByte;
ELSIF (nPage_Hit = '1') THEN
NextState <= prechg;
nRAS_Async <= "11111111";
nCAS_Async <= "1111";
ELSE
NextState <= page1;
nCAS_Async <= nByte;
END IF;
WHEN page2 =>
nPreCharge <= '1';
nRAS_Async <= pRAS;
nCAS_Async <= "1111";
nDSACK0_Async <= '0';
nDSACK1_Async <= '0';
RefAck_Async <= '0';
nWR_Async <= nWR;
NextState <= page3;
WHEN page3 =>
nPreCharge <= '1';
nCAS_Async <= "1111";
nDSACK0_Async <= '1';
nDSACK1_Async <= '1';
RefAck_Async <= '0';
nWR_Async <= nWR;
IF (nPage_Hit = '0') THEN
NextState <= page1;
nRAS_Async <= pRAS;
ELSE
NextState <= prechg;
nRAS_Async <= "11111111";
END IF;
-- cbr(CAS Before RAS Refresh) mode start
WHEN cbr1 =>
NextState <= cbr2;
nPreCharge <= '1';
nRAS_Async <= "11111111";
nCAS_Async <= "0000";
nDSACK0_Async <= '1';
nDSACK1_Async <= '1';
RefAck_Async <= '1';
nWR_Async <= '1';
WHEN cbr2 =>
NextState <= cbr3;
nPreCharge <= '1';
nRAS_Async <= "00000000";
nCAS_Async <= "0000";
nDSACK0_Async <= '1';
nDSACK1_Async <= '1';
RefAck_Async <= '0';
nWR_Async <= '1';
WHEN cbr3 =>
NextState <= cbr4;
nPreCharge <= '1';
nRAS_Async <= "00000000";
nCAS_Async <= "1111";
nDSACK0_Async <= '1';
nDSACK1_Async <= '1';
RefAck_Async <= '0';
nWR_Async <= '1';
WHEN cbr4 =>
NextState <= prechg;
nPreCharge <= '1';
nRAS_Async <= "11111111";
nCAS_Async <= "1111";
nDSACK0_Async <= '1';
nDSACK1_Async <= '1';
RefAck_Async <= '0';
nWR_Async <= '1';
WHEN prechg =>
NextState <= idle;
nPreCharge <= '0';
nRAS_Async <= "11111111";
nCAS_Async <= "1111";
nDSACK0_Async <= '1';
nDSACK1_Async <= '1';
RefAck_Async <= '0';
nWR_Async <= '1';
WHEN OTHERS =>
NextState <= idle;
nPreCharge <= '1';
nRAS_Async <= "11111111";
nCAS_Async <= "1111";
nDSACK0_Async <= '1';
nDSACK1_Async <= '1';
RefAck_Async <= '0';
nWR_Async <= nWR;
END CASE;
END PROCESS;
---------------------------------------
------ Synchronous Process ------------
---------------------------------------
Sync_Cont: PROCESS (Clk, nReset)
BEGIN
IF (nReset = '0') THEN
CurrentState <= IDLE;
nRAS <= "11111111";
nCAS <= "1111";
nDSACK0 <= '1';
nDSACK1 <= '1';
nWE_DRAM <= '1';
RefAck <= '0';
ELSIF FALLING_EDGE(Clk) THEN
CurrentState <= NextState;
nRAS <= nRAS_Async;
nCAS <= nCAS_Async;
nDSACK0 <= nDSACK0_Async;
nDSACK1 <= nDSACK1_Async;
nWE_DRAM <= nWR_Async;
RefAck <= RefAck_Async;
END IF;
END PROCESS;
---------------------------------------
------ Refresh Counter Process --------
---------------------------------------
rfcnt: PROCESS (Clk, RefAck, nReset)
BEGIN
IF (nReset = '0') THEN
q <= "000000000";
ELSIF FALLING_EDGE(Clk) THEN
IF RefAck = '1' THEN
q <= "000000000";
ELSE
q <= q + 1;
END IF;
END IF;
END PROCESS;
-- 186hex = 110000110 binary = 390 decimal
-- assuming 25 MHz clock (40ns clock period)
-- 40ns (tCYC) x 390 = 15.6us is the refresh request rate.
tc <= '1' WHEN q = "110000110" ELSE '0';
---------------------------------------
------ Refresh Request Process --------
---------------------------------------
rreq: PROCESS (Clk, tc, RefAck, nReset)
BEGIN
IF (nReset = '0') THEN
RefReq <= '0';
ELSIF FALLING_EDGE(Clk) THEN
IF RefAck = '1' THEN
RefReq <= '0';
ELSIF tc = '1' THEN
RefReq <= '1';
END IF;
END IF;
END PROCESS;
-- The PRASx signals are used to maintain the RASOx outputs
-- between the actual CPU accesses of a page mode access.
pras_ctl: PROCESS (Clk, nReset)
BEGIN
IF (nReset = '0') THEN
pRAS <= "11111111";
ELSIF FALLING_EDGE(Clk) THEN
IF ((CurrentState = rw1) or (CurrentState = page2)) then
pRAS <= nBank;
END IF;
END IF;
END PROCESS;
END Behavioral;
|
gpl-3.0
|
f9c9980f4a74d340c6e0da0736d254d1
| 0.465202 | 4.203011 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/finite_field/product_generator_gf_2_m_Software.vhd
| 1 | 61,566 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Product_Generator_GF_2_M
-- Module Name: Product_Generator_GF_2_M
-- Project Name: GF_2_M Arithmetic
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit is part of the GF(2^m) multiplier.
-- This circuit generates the partial product to be latter used in the multiplier.
-- This version is for primitive polynomials present on the software implementation
-- of binary Goppa codes.
--
-- The circuits parameters
--
-- m :
--
-- The size of the field used in this circuit.
--
-- value :
--
-- Used to select the partial product generated by this circuit of
-- o = a * x^(value)
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
architecture Software_POLYNOMIAL of product_generator_gf_2_m is
constant final_value : integer := value mod m;
begin
GF_2_2 : if m = 2 generate -- x^2 + x^1 + 1
GF_2_2_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_2_P_1 : if final_value = 1 generate
o <= ( (a(0) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_3 : if m = 3 generate -- x^3 + x^1 + 1
GF_2_3_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_3_P_1 : if final_value = 1 generate
o <= ( a(1) & (a(0) xor a(2)) & a(2) );
end generate;
GF_2_3_P_2 : if final_value = 2 generate
o <= ( (a(0) xor a(2)) & (a(2) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_4 : if m = 4 generate -- x^4 + x^1 + 1
GF_2_4_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_4_P_1 : if final_value = 1 generate
o <= ( a(2 downto 1) & (a(0) xor a(3)) & a(3) );
end generate;
GF_2_4_P_2 : if final_value = 2 generate
o <= ( a(1) & (a(0) xor a(3)) & (a(3) xor a(2)) & a(2) );
end generate;
GF_2_4_P_3 : if final_value = 3 generate
o <= ( (a(0) xor a(3)) & (a(3) xor a(2)) & (a(2) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_5 : if m = 5 generate -- x^5 + x^2 + 1
GF_2_5_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_5_P_1 : if final_value = 1 generate
o <= ( a(3) & a(2) & (a(1) xor a(4)) & a(0) & a(4) );
end generate;
GF_2_5_P_2 : if final_value = 2 generate
o <= ( a(2) & (a(1) xor a(4)) & (a(0) xor a(3)) & a(4) & a(3) );
end generate;
GF_2_5_P_3 : if final_value = 3 generate
o <= ( (a(1) xor a(4)) & (a(0) xor a(3)) & (a(4) xor a(2)) & a(3) & a(2) );
end generate;
GF_2_5_P_4 : if final_value = 4 generate
o <= ( (a(0) xor a(3)) & (a(4) xor a(2)) & (a(3) xor a(1) xor a(4)) & a(2) & (a(1) xor a(4)) );
end generate;
end generate;
GF_2_6 : if m = 6 generate -- x^6 + x^1 + 1
GF_2_6_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_6_P_1 : if final_value = 1 generate
o <= ( a(4) & a(3) & a(2) & a(1) & (a(0) xor a(5)) & a(5) );
end generate;
GF_2_6_P_2 : if final_value = 2 generate
o <= ( a(3) & a(2) & a(1) & (a(0) xor a(5)) & (a(5) xor a(4)) & a(4) );
end generate;
GF_2_6_P_3 : if final_value = 3 generate
o <= ( a(2) & a(1) & (a(0) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & a(3) );
end generate;
GF_2_6_P_4 : if final_value = 4 generate
o <= ( a(1) & (a(0) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & a(2) );
end generate;
GF_2_6_P_5 : if final_value = 5 generate
o <= ( (a(0) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & (a(2) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_7 : if m = 7 generate -- x^7 + x^1 + 1
GF_2_7_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_7_P_1 : if final_value = 1 generate
o <= ( a(5) & a(4) & a(3) & a(2) & a(1) & (a(0) xor a(6)) & a(6) );
end generate;
GF_2_7_P_2 : if final_value = 2 generate
o <= ( a(4) & a(3) & a(2) & a(1) & (a(0) xor a(6)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_7_P_3 : if final_value = 3 generate
o <= ( a(3) & a(2) & a(1) & (a(0) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & a(4) );
end generate;
GF_2_7_P_4 : if final_value = 4 generate
o <= ( a(2) & a(1) & (a(0) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & a(3) );
end generate;
GF_2_7_P_5 : if final_value = 5 generate
o <= ( a(1) & (a(0) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & a(2) );
end generate;
GF_2_7_P_6 : if final_value = 6 generate
o <= ( (a(0) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & (a(2) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_8 : if m = 8 generate -- x^8 + x^4 + x^3 + x^2 + 1
GF_2_8_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_8_P_1 : if final_value = 1 generate
o <= ( a(6) & a(5) & a(4) & (a(3) xor a(7)) & (a(2) xor a(7)) & (a(1) xor a(7)) & a(0) & a(7) );
end generate;
GF_2_8_P_2 : if final_value = 2 generate
o <= ( a(5) & a(4) & (a(3) xor a(7)) & (a(2) xor a(7) xor a(6)) & (a(1) xor a(7) xor a(6)) & (a(0) xor a(6)) & a(7) & a(6) );
end generate;
GF_2_8_P_3 : if final_value = 3 generate
o <= ( a(4) & (a(3) xor a(7)) & (a(2) xor a(7) xor a(6)) & (a(1) xor a(7) xor a(6) xor a(5)) & (a(0) xor a(6) xor a(5)) & (a(7) xor a(5)) & a(6) & a(5) );
end generate;
GF_2_8_P_4 : if final_value = 4 generate
o <= ( (a(3) xor a(7)) & (a(2) xor a(7) xor a(6)) & (a(1) xor a(7) xor a(6) xor a(5)) & (a(0) xor a(6) xor a(5) xor a(4)) & (a(7) xor a(5) xor a(4)) & (a(6) xor a(4)) & a(5) & a(4) );
end generate;
GF_2_8_P_5 : if final_value = 5 generate
o <= ( (a(2) xor a(7) xor a(6)) & (a(1) xor a(7) xor a(6) xor a(5)) & (a(0) xor a(6) xor a(5) xor a(4)) & (a(5) xor a(4) xor a(3)) & (a(6) xor a(4) xor a(3) xor a(7)) & (a(5) xor a(3) xor a(7)) & a(4) & (a(3) xor a(7)) );
end generate;
GF_2_8_P_6 : if final_value = 6 generate
o <= ( (a(1) xor a(7) xor a(6) xor a(5)) & (a(0) xor a(6) xor a(5) xor a(4)) & (a(5) xor a(4) xor a(3)) & (a(4) xor a(3) xor a(2)) & (a(5) xor a(3) xor a(2) xor a(6)) & (a(4) xor a(2) xor a(7) xor a(6)) & (a(3) xor a(7)) & (a(2) xor a(7) xor a(6)) );
end generate;
GF_2_8_P_7 : if final_value = 7 generate
o <= ( (a(0) xor a(6) xor a(5) xor a(4)) & (a(5) xor a(4) xor a(3)) & (a(4) xor a(3) xor a(2)) & (a(3) xor a(2) xor a(1) xor a(7)) & (a(4) xor a(2) xor a(1) xor a(5)) & (a(3) xor a(1) xor a(6) xor a(5)) & (a(2) xor a(7) xor a(6)) & (a(1) xor a(7) xor a(6) xor a(5)) );
end generate;
end generate;
GF_2_9 : if m = 9 generate -- x^9 + x^4 + 1
GF_2_9_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_9_P_1 : if final_value = 1 generate
o <= ( a(7) & a(6) & a(5) & a(4) & (a(3) xor a(8)) & a(2) & a(1) & a(0) & a(8) );
end generate;
GF_2_9_P_2 : if final_value = 2 generate
o <= ( a(6) & a(5) & a(4) & (a(3) xor a(8)) & (a(2) xor a(7)) & a(1) & a(0) & a(8) & a(7) );
end generate;
GF_2_9_P_3 : if final_value = 3 generate
o <= ( a(5) & a(4) & (a(3) xor a(8)) & (a(2) xor a(7)) & (a(1) xor a(6)) & a(0) & a(8) & a(7) & a(6) );
end generate;
GF_2_9_P_4 : if final_value = 4 generate
o <= ( a(4) & (a(3) xor a(8)) & (a(2) xor a(7)) & (a(1) xor a(6)) & (a(0) xor a(5)) & a(8) & a(7) & a(6) & a(5) );
end generate;
GF_2_9_P_5 : if final_value = 5 generate
o <= ( (a(3) xor a(8)) & (a(2) xor a(7)) & (a(1) xor a(6)) & (a(0) xor a(5)) & (a(8) xor a(4)) & a(7) & a(6) & a(5) & a(4) );
end generate;
GF_2_9_P_6 : if final_value = 6 generate
o <= ( (a(2) xor a(7)) & (a(1) xor a(6)) & (a(0) xor a(5)) & (a(8) xor a(4)) & (a(7) xor a(3) xor a(8)) & a(6) & a(5) & a(4) & (a(3) xor a(8)) );
end generate;
GF_2_9_P_7 : if final_value = 7 generate
o <= ( (a(1) xor a(6)) & (a(0) xor a(5)) & (a(8) xor a(4)) & (a(7) xor a(3) xor a(8)) & (a(6) xor a(2) xor a(7)) & a(5) & a(4) & (a(3) xor a(8)) & (a(2) xor a(7)) );
end generate;
GF_2_9_P_8 : if final_value = 8 generate
o <= ( (a(0) xor a(5)) & (a(8) xor a(4)) & (a(7) xor a(3) xor a(8)) & (a(6) xor a(2) xor a(7)) & (a(5) xor a(1) xor a(6)) & a(4) & (a(3) xor a(8)) & (a(2) xor a(7)) & (a(1) xor a(6)) );
end generate;
end generate;
GF_2_10 : if m = 10 generate -- x^10 + x^3 + 1
GF_2_10_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_10_P_1 : if final_value = 1 generate
o <= ( a(8) & a(7) & a(6) & a(5) & a(4) & a(3) & (a(2) xor a(9)) & a(1) & a(0) & a(9) );
end generate;
GF_2_10_P_2 : if final_value = 2 generate
o <= ( a(7) & a(6) & a(5) & a(4) & a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) & a(0) & a(9) & a(8) );
end generate;
GF_2_10_P_3 : if final_value = 3 generate
o <= ( a(6) & a(5) & a(4) & a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) & (a(0) xor a(7)) & a(9) & a(8) & a(7) );
end generate;
GF_2_10_P_4 : if final_value = 4 generate
o <= ( a(5) & a(4) & a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) & (a(0) xor a(7)) & (a(9) xor a(6)) & a(8) & a(7) & a(6) );
end generate;
GF_2_10_P_5 : if final_value = 5 generate
o <= ( a(4) & a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) & (a(0) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & a(7) & a(6) & a(5) );
end generate;
GF_2_10_P_6 : if final_value = 6 generate
o <= ( a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) & (a(0) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & a(6) & a(5) & a(4) );
end generate;
GF_2_10_P_7 : if final_value = 7 generate
o <= ( (a(2) xor a(9)) & (a(1) xor a(8)) & (a(0) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & a(5) & a(4) & a(3) );
end generate;
GF_2_10_P_8 : if final_value = 8 generate
o <= ( (a(1) xor a(8)) & (a(0) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(9)) & a(4) & a(3) & (a(2) xor a(9)) );
end generate;
GF_2_10_P_9 : if final_value = 9 generate
o <= ( (a(0) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(9)) & (a(4) xor a(1) xor a(8)) & a(3) & (a(2) xor a(9)) & (a(1) xor a(8)) );
end generate;
end generate;
GF_2_11 : if m = 11 generate -- x^11 + x^2 + 1
GF_2_11_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_11_P_1 : if final_value = 1 generate
o <= ( a(9 downto 2) & (a(1) xor a(10)) & a(0) & a(10) );
end generate;
GF_2_11_P_2 : if final_value = 2 generate
o <= ( a(8 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & a(10) & a(9) );
end generate;
GF_2_11_P_3 : if final_value = 3 generate
o <= ( a(7 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & a(9) & a(8) );
end generate;
GF_2_11_P_4 : if final_value = 4 generate
o <= ( a(6 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & a(8) & a(7) );
end generate;
GF_2_11_P_5 : if final_value = 5 generate
o <= ( a(5 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & a(7) & a(6) );
end generate;
GF_2_11_P_6 : if final_value = 6 generate
o <= ( a(4 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & (a(7) xor a(5)) & a(6) & a(5) );
end generate;
GF_2_11_P_7 : if final_value = 7 generate
o <= ( a(3 downto 2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & (a(7) xor a(5)) & (a(6) xor a(4)) & a(5) & a(4) );
end generate;
GF_2_11_P_8 : if final_value = 8 generate
o <= ( a(2) & (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & (a(7) xor a(5)) & (a(6) xor a(4)) & (a(5) xor a(3)) & a(4) & a(3) );
end generate;
GF_2_11_P_9 : if final_value = 9 generate
o <= ( (a(1) xor a(10)) & (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & (a(7) xor a(5)) & (a(6) xor a(4)) & (a(5) xor a(3)) & (a(4) xor a(2)) & a(3) & a(2) );
end generate;
GF_2_11_P_10 : if final_value = 10 generate
o <= ( (a(0) xor a(9)) & (a(10) xor a(8)) & (a(9) xor a(7)) & (a(8) xor a(6)) & (a(7) xor a(5)) & (a(6) xor a(4)) & (a(5) xor a(3)) & (a(4) xor a(2)) & (a(3) xor a(1) xor a(10)) & a(2) & (a(1) xor a(10)) );
end generate;
end generate;
GF_2_12 : if m = 12 generate -- x^12 + x^6 + x^4 + x^1 + 1
GF_2_12_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_12_P_1 : if final_value = 1 generate
o <= ( a(10) & a(9) & a(8) & a(7) & a(6) & (a(5) xor a(11)) & a(4) & (a(3) xor a(11)) & a(2) & a(1) & (a(0) xor a(11)) & a(11) );
end generate;
GF_2_12_P_2 : if final_value = 2 generate
o <= ( a(9) & a(8) & a(7) & a(6) & (a(5) xor a(11)) & (a(4) xor a(10)) & (a(3) xor a(11)) & (a(2) xor a(10)) & a(1) & (a(0) xor a(11)) & (a(11) xor a(10)) & a(10) );
end generate;
GF_2_12_P_3 : if final_value = 3 generate
o <= ( a(8) & a(7) & a(6) & (a(5) xor a(11)) & (a(4) xor a(10)) & (a(3) xor a(11) xor a(9)) & (a(2) xor a(10)) & (a(1) xor a(9)) & (a(0) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & a(9) );
end generate;
GF_2_12_P_4 : if final_value = 4 generate
o <= ( a(7) & a(6) & (a(5) xor a(11)) & (a(4) xor a(10)) & (a(3) xor a(11) xor a(9)) & (a(2) xor a(10) xor a(8)) & (a(1) xor a(9)) & (a(0) xor a(11) xor a(8)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & a(8) );
end generate;
GF_2_12_P_5 : if final_value = 5 generate
o <= ( a(6) & (a(5) xor a(11)) & (a(4) xor a(10)) & (a(3) xor a(11) xor a(9)) & (a(2) xor a(10) xor a(8)) & (a(1) xor a(9) xor a(7)) & (a(0) xor a(11) xor a(8)) & (a(11) xor a(10) xor a(7)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & a(7) );
end generate;
GF_2_12_P_6 : if final_value = 6 generate
o <= ( (a(5) xor a(11)) & (a(4) xor a(10)) & (a(3) xor a(11) xor a(9)) & (a(2) xor a(10) xor a(8)) & (a(1) xor a(9) xor a(7)) & (a(0) xor a(11) xor a(8) xor a(6)) & (a(11) xor a(10) xor a(7)) & (a(10) xor a(9) xor a(6)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & a(6) );
end generate;
GF_2_12_P_7 : if final_value = 7 generate
o <= ( (a(4) xor a(10)) & (a(3) xor a(11) xor a(9)) & (a(2) xor a(10) xor a(8)) & (a(1) xor a(9) xor a(7)) & (a(0) xor a(11) xor a(8) xor a(6)) & (a(10) xor a(7) xor a(5)) & (a(10) xor a(9) xor a(6)) & (a(9) xor a(8) xor a(5) xor a(11)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5) xor a(11)) & (a(5) xor a(11)) );
end generate;
GF_2_12_P_8 : if final_value = 8 generate
o <= ( (a(3) xor a(11) xor a(9)) & (a(2) xor a(10) xor a(8)) & (a(1) xor a(9) xor a(7)) & (a(0) xor a(11) xor a(8) xor a(6)) & (a(10) xor a(7) xor a(5)) & (a(9) xor a(6) xor a(4)) & (a(9) xor a(8) xor a(5) xor a(11)) & (a(8) xor a(7) xor a(4) xor a(10)) & (a(7) xor a(6)) & (a(6) xor a(5) xor a(11)) & (a(5) xor a(11) xor a(4) xor a(10)) & (a(4) xor a(10)) );
end generate;
GF_2_12_P_9 : if final_value = 9 generate
o <= ( (a(2) xor a(10) xor a(8)) & (a(1) xor a(9) xor a(7)) & (a(0) xor a(11) xor a(8) xor a(6)) & (a(10) xor a(7) xor a(5)) & (a(9) xor a(6) xor a(4)) & (a(8) xor a(5) xor a(3)) & (a(8) xor a(7) xor a(4) xor a(10)) & (a(7) xor a(6) xor a(3) xor a(11) xor a(9)) & (a(6) xor a(5) xor a(11)) & (a(5) xor a(11) xor a(4) xor a(10)) & (a(4) xor a(10) xor a(3) xor a(11) xor a(9)) & (a(3) xor a(11) xor a(9)) );
end generate;
GF_2_12_P_10 : if final_value = 10 generate
o <= ( (a(1) xor a(9) xor a(7)) & (a(0) xor a(11) xor a(8) xor a(6)) & (a(10) xor a(7) xor a(5)) & (a(9) xor a(6) xor a(4)) & (a(8) xor a(5) xor a(3)) & (a(7) xor a(4) xor a(2)) & (a(7) xor a(6) xor a(3) xor a(11) xor a(9)) & (a(6) xor a(5) xor a(11) xor a(2) xor a(10) xor a(8)) & (a(5) xor a(11) xor a(4) xor a(10)) & (a(4) xor a(10) xor a(3) xor a(11) xor a(9)) & (a(3) xor a(11) xor a(9) xor a(2) xor a(10) xor a(8)) & (a(2) xor a(10) xor a(8)) );
end generate;
GF_2_12_P_11 : if final_value = 11 generate
o <= ( (a(0) xor a(11) xor a(8) xor a(6)) & (a(10) xor a(7) xor a(5)) & (a(9) xor a(6) xor a(4)) & (a(8) xor a(5) xor a(3)) & (a(7) xor a(4) xor a(2)) & (a(6) xor a(3) xor a(11) xor a(1)) & (a(6) xor a(5) xor a(11) xor a(2) xor a(10) xor a(8)) & (a(5) xor a(11) xor a(4) xor a(10) xor a(1) xor a(9) xor a(7)) & (a(4) xor a(10) xor a(3) xor a(11) xor a(9)) & (a(3) xor a(11) xor a(9) xor a(2) xor a(10) xor a(8)) & (a(2) xor a(10) xor a(8) xor a(1) xor a(9) xor a(7)) & (a(1) xor a(9) xor a(7)) );
end generate;
end generate;
GF_2_13 : if m = 13 generate -- x^13 + x^4 + x^3 + x^1 + 1
GF_2_13_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_13_P_1 : if final_value = 1 generate
o <= ( a(11 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12)) & a(1) & (a(0) xor a(12)) & a(12) );
end generate;
GF_2_13_P_2 : if final_value = 2 generate
o <= ( a(10 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11)) & (a(0) xor a(12)) & (a(12) xor a(11)) & a(11) );
end generate;
GF_2_13_P_3 : if final_value = 3 generate
o <= ( a(9 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10)) & (a(12) xor a(11)) & (a(11) xor a(10)) & a(10) );
end generate;
GF_2_13_P_4 : if final_value = 4 generate
o <= ( a(8 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9)) & (a(11) xor a(10)) & (a(10) xor a(9)) & a(9) );
end generate;
GF_2_13_P_5 : if final_value = 5 generate
o <= ( a(7 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8)) & (a(10) xor a(9)) & (a(9) xor a(8)) & a(8) );
end generate;
GF_2_13_P_6 : if final_value = 6 generate
o <= ( a(6 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7)) & (a(9) xor a(8)) & (a(8) xor a(7)) & a(7) );
end generate;
GF_2_13_P_7 : if final_value = 7 generate
o <= ( a(5 downto 4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6)) & (a(8) xor a(7)) & (a(7) xor a(6)) & a(6) );
end generate;
GF_2_13_P_8 : if final_value = 8 generate
o <= ( a(4) & (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6) xor a(5)) & (a(8) xor a(7) xor a(5)) & (a(7) xor a(6)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_13_P_9 : if final_value = 9 generate
o <= ( (a(3) xor a(12)) & (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6) xor a(5)) & (a(8) xor a(7) xor a(5) xor a(4)) & (a(7) xor a(6) xor a(4)) & (a(6) xor a(5)) & (a(5) xor a(4)) & a(4) );
end generate;
GF_2_13_P_10 : if final_value = 10 generate
o <= ( (a(2) xor a(12) xor a(11)) & (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6) xor a(5)) & (a(8) xor a(7) xor a(5) xor a(4)) & (a(7) xor a(6) xor a(4) xor a(3) xor a(12)) & (a(6) xor a(5) xor a(3) xor a(12)) & (a(5) xor a(4)) & (a(4) xor a(3) xor a(12)) & (a(3) xor a(12)) );
end generate;
GF_2_13_P_11 : if final_value = 11 generate
o <= ( (a(1) xor a(11) xor a(10)) & (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6) xor a(5)) & (a(8) xor a(7) xor a(5) xor a(4)) & (a(7) xor a(6) xor a(4) xor a(3) xor a(12)) & (a(6) xor a(5) xor a(3) xor a(2) xor a(11)) & (a(5) xor a(4) xor a(2) xor a(12) xor a(11)) & (a(4) xor a(3) xor a(12)) & (a(3) xor a(2) xor a(11)) & (a(2) xor a(12) xor a(11)) );
end generate;
GF_2_13_P_12 : if final_value = 12 generate
o <= ( (a(0) xor a(12) xor a(10) xor a(9)) & (a(12) xor a(11) xor a(9) xor a(8)) & (a(11) xor a(10) xor a(8) xor a(7)) & (a(10) xor a(9) xor a(7) xor a(6)) & (a(9) xor a(8) xor a(6) xor a(5)) & (a(8) xor a(7) xor a(5) xor a(4)) & (a(7) xor a(6) xor a(4) xor a(3) xor a(12)) & (a(6) xor a(5) xor a(3) xor a(2) xor a(11)) & (a(5) xor a(4) xor a(2) xor a(12) xor a(1) xor a(10)) & (a(4) xor a(3) xor a(12) xor a(1) xor a(11) xor a(10)) & (a(3) xor a(2) xor a(11)) & (a(2) xor a(12) xor a(1) xor a(10)) & (a(1) xor a(11) xor a(10)) );
end generate;
end generate;
GF_2_14 : if m = 14 generate -- x^14 + x^5 + x^3 + x^1 + 1
GF_2_14_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_14_P_1 : if final_value = 1 generate
o <= ( a(12) & a(11) & a(10) & a(9) & a(8) & a(7) & a(6) & a(5) & (a(4) xor a(13)) & a(3) & (a(2) xor a(13)) & a(1) & (a(0) xor a(13)) & a(13) );
end generate;
GF_2_14_P_2 : if final_value = 2 generate
o <= ( a(11) & a(10) & a(9) & a(8) & a(7) & a(6) & a(5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(13)) & (a(1) xor a(12)) & (a(0) xor a(13)) & (a(13) xor a(12)) & a(12) );
end generate;
GF_2_14_P_3 : if final_value = 3 generate
o <= ( a(10) & a(9) & a(8) & a(7) & a(6) & a(5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(13) xor a(11)) & (a(1) xor a(12)) & (a(0) xor a(13) xor a(11)) & (a(13) xor a(12)) & (a(12) xor a(11)) & a(11) );
end generate;
GF_2_14_P_4 : if final_value = 4 generate
o <= ( a(9) & a(8) & a(7) & a(6) & a(5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(13) xor a(11)) & (a(1) xor a(12) xor a(10)) & (a(0) xor a(13) xor a(11)) & (a(13) xor a(12) xor a(10)) & (a(12) xor a(11)) & (a(11) xor a(10)) & a(10) );
end generate;
GF_2_14_P_5 : if final_value = 5 generate
o <= ( a(8) & a(7) & a(6) & a(5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(13) xor a(11)) & (a(1) xor a(12) xor a(10)) & (a(0) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10)) & (a(12) xor a(11) xor a(9)) & (a(11) xor a(10)) & (a(10) xor a(9)) & a(9) );
end generate;
GF_2_14_P_6 : if final_value = 6 generate
o <= ( a(7) & a(6) & a(5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(13) xor a(11)) & (a(1) xor a(12) xor a(10)) & (a(0) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9)) & (a(11) xor a(10) xor a(8)) & (a(10) xor a(9)) & (a(9) xor a(8)) & a(8) );
end generate;
GF_2_14_P_7 : if final_value = 7 generate
o <= ( a(6) & a(5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(13) xor a(11)) & (a(1) xor a(12) xor a(10)) & (a(0) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8)) & (a(10) xor a(9) xor a(7)) & (a(9) xor a(8)) & (a(8) xor a(7)) & a(7) );
end generate;
GF_2_14_P_8 : if final_value = 8 generate
o <= ( a(5) & (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(13) xor a(11)) & (a(1) xor a(12) xor a(10)) & (a(0) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7)) & (a(9) xor a(8) xor a(6)) & (a(8) xor a(7)) & (a(7) xor a(6)) & a(6) );
end generate;
GF_2_14_P_9 : if final_value = 9 generate
o <= ( (a(4) xor a(13)) & (a(3) xor a(12)) & (a(2) xor a(13) xor a(11)) & (a(1) xor a(12) xor a(10)) & (a(0) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7) xor a(5)) & (a(9) xor a(8) xor a(6)) & (a(8) xor a(7) xor a(5)) & (a(7) xor a(6)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_14_P_10 : if final_value = 10 generate
o <= ( (a(3) xor a(12)) & (a(2) xor a(13) xor a(11)) & (a(1) xor a(12) xor a(10)) & (a(0) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7) xor a(5)) & (a(9) xor a(8) xor a(6) xor a(4) xor a(13)) & (a(8) xor a(7) xor a(5)) & (a(7) xor a(6) xor a(4) xor a(13)) & (a(6) xor a(5)) & (a(5) xor a(4) xor a(13)) & (a(4) xor a(13)) );
end generate;
GF_2_14_P_11 : if final_value = 11 generate
o <= ( (a(2) xor a(13) xor a(11)) & (a(1) xor a(12) xor a(10)) & (a(0) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7) xor a(5)) & (a(9) xor a(8) xor a(6) xor a(4) xor a(13)) & (a(8) xor a(7) xor a(5) xor a(3) xor a(12)) & (a(7) xor a(6) xor a(4) xor a(13)) & (a(6) xor a(5) xor a(3) xor a(12)) & (a(5) xor a(4) xor a(13)) & (a(4) xor a(13) xor a(3) xor a(12)) & (a(3) xor a(12)) );
end generate;
GF_2_14_P_12 : if final_value = 12 generate
o <= ( (a(1) xor a(12) xor a(10)) & (a(0) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7) xor a(5)) & (a(9) xor a(8) xor a(6) xor a(4) xor a(13)) & (a(8) xor a(7) xor a(5) xor a(3) xor a(12)) & (a(7) xor a(6) xor a(4) xor a(2) xor a(11)) & (a(6) xor a(5) xor a(3) xor a(12)) & (a(5) xor a(4) xor a(2) xor a(11)) & (a(4) xor a(13) xor a(3) xor a(12)) & (a(3) xor a(12) xor a(2) xor a(13) xor a(11)) & (a(2) xor a(13) xor a(11)) );
end generate;
GF_2_14_P_13 : if final_value = 13 generate
o <= ( (a(0) xor a(13) xor a(11) xor a(9)) & (a(13) xor a(12) xor a(10) xor a(8)) & (a(12) xor a(11) xor a(9) xor a(7)) & (a(11) xor a(10) xor a(8) xor a(6)) & (a(10) xor a(9) xor a(7) xor a(5)) & (a(9) xor a(8) xor a(6) xor a(4) xor a(13)) & (a(8) xor a(7) xor a(5) xor a(3) xor a(12)) & (a(7) xor a(6) xor a(4) xor a(2) xor a(11)) & (a(6) xor a(5) xor a(3) xor a(1) xor a(10)) & (a(5) xor a(4) xor a(2) xor a(11)) & (a(4) xor a(13) xor a(3) xor a(1) xor a(10)) & (a(3) xor a(12) xor a(2) xor a(13) xor a(11)) & (a(2) xor a(13) xor a(11) xor a(1) xor a(12) xor a(10)) & (a(1) xor a(12) xor a(10)) );
end generate;
end generate;
GF_2_15 : if m = 15 generate -- x^15 + x^1 + 1
GF_2_15_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_15_P_1 : if final_value = 1 generate
o <= ( a(13 downto 1) & (a(0) xor a(14)) & a(14) );
end generate;
GF_2_15_P_2 : if final_value = 2 generate
o <= ( a(12 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & a(13) );
end generate;
GF_2_15_P_3 : if final_value = 3 generate
o <= ( a(11 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & a(12) );
end generate;
GF_2_15_P_4 : if final_value = 4 generate
o <= ( a(10 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & a(11) );
end generate;
GF_2_15_P_5 : if final_value = 5 generate
o <= ( a(9 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & a(10) );
end generate;
GF_2_15_P_6 : if final_value = 6 generate
o <= ( a(8 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & a(9) );
end generate;
GF_2_15_P_7 : if final_value = 7 generate
o <= ( a(7 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & a(8) );
end generate;
GF_2_15_P_8 : if final_value = 8 generate
o <= ( a(6 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & a(7) );
end generate;
GF_2_15_P_9 : if final_value = 9 generate
o <= ( a(5 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & a(6) );
end generate;
GF_2_15_P_10 : if final_value = 10 generate
o <= ( a(4 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_15_P_11 : if final_value = 11 generate
o <= ( a(3 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & a(4) );
end generate;
GF_2_15_P_12 : if final_value = 12 generate
o <= ( a(2 downto 1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & a(3) );
end generate;
GF_2_15_P_13 : if final_value = 13 generate
o <= ( a(1) & (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & a(2) );
end generate;
GF_2_15_P_14 : if final_value = 14 generate
o <= ( (a(0) xor a(14)) & (a(14) xor a(13)) & (a(13) xor a(12)) & (a(12) xor a(11)) & (a(11) xor a(10)) & (a(10) xor a(9)) & (a(9) xor a(8)) & (a(8) xor a(7)) & (a(7) xor a(6)) & (a(6) xor a(5)) & (a(5) xor a(4)) & (a(4) xor a(3)) & (a(3) xor a(2)) & (a(2) xor a(1)) & a(1) );
end generate;
end generate;
GF_2_16 : if m = 16 generate -- x^16 + x^5 + x^3 + x^2 + 1
GF_2_16_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_16_P_1 : if final_value = 1 generate
o <= ( a(14) & a(13) & a(12) & a(11) & a(10) & a(9) & a(8) & a(7) & a(6) & a(5) & (a(4) xor a(15)) & a(3) & (a(2) xor a(15)) & (a(1) xor a(15)) & a(0) & a(15) );
end generate;
GF_2_16_P_2 : if final_value = 2 generate
o <= ( a(13) & a(12) & a(11) & a(10) & a(9) & a(8) & a(7) & a(6) & a(5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15)) & (a(1) xor a(15) xor a(14)) & (a(0) xor a(14)) & a(15) & a(14) );
end generate;
GF_2_16_P_3 : if final_value = 3 generate
o <= ( a(12) & a(11) & a(10) & a(9) & a(8) & a(7) & a(6) & a(5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(15) xor a(14)) & (a(0) xor a(14) xor a(13)) & (a(15) xor a(13)) & a(14) & a(13) );
end generate;
GF_2_16_P_4 : if final_value = 4 generate
o <= ( a(11) & a(10) & a(9) & a(8) & a(7) & a(6) & a(5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(15) xor a(14) xor a(12)) & (a(0) xor a(14) xor a(13)) & (a(15) xor a(13) xor a(12)) & (a(14) xor a(12)) & a(13) & a(12) );
end generate;
GF_2_16_P_5 : if final_value = 5 generate
o <= ( a(10) & a(9) & a(8) & a(7) & a(6) & a(5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(15) xor a(14) xor a(12)) & (a(0) xor a(14) xor a(13) xor a(11)) & (a(15) xor a(13) xor a(12)) & (a(14) xor a(12) xor a(11)) & (a(13) xor a(11)) & a(12) & a(11) );
end generate;
GF_2_16_P_6 : if final_value = 6 generate
o <= ( a(9) & a(8) & a(7) & a(6) & a(5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(15) xor a(14) xor a(12)) & (a(0) xor a(14) xor a(13) xor a(11)) & (a(15) xor a(13) xor a(12) xor a(10)) & (a(14) xor a(12) xor a(11)) & (a(13) xor a(11) xor a(10)) & (a(12) xor a(10)) & a(11) & a(10) );
end generate;
GF_2_16_P_7 : if final_value = 7 generate
o <= ( a(8) & a(7) & a(6) & a(5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(15) xor a(14) xor a(12)) & (a(0) xor a(14) xor a(13) xor a(11)) & (a(15) xor a(13) xor a(12) xor a(10)) & (a(14) xor a(12) xor a(11) xor a(9)) & (a(13) xor a(11) xor a(10)) & (a(12) xor a(10) xor a(9)) & (a(11) xor a(9)) & a(10) & a(9) );
end generate;
GF_2_16_P_8 : if final_value = 8 generate
o <= ( a(7) & a(6) & a(5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(15) xor a(14) xor a(12)) & (a(0) xor a(14) xor a(13) xor a(11)) & (a(15) xor a(13) xor a(12) xor a(10)) & (a(14) xor a(12) xor a(11) xor a(9)) & (a(13) xor a(11) xor a(10) xor a(8)) & (a(12) xor a(10) xor a(9)) & (a(11) xor a(9) xor a(8)) & (a(10) xor a(8)) & a(9) & a(8) );
end generate;
GF_2_16_P_9 : if final_value = 9 generate
o <= ( a(6) & a(5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(15) xor a(14) xor a(12)) & (a(0) xor a(14) xor a(13) xor a(11)) & (a(15) xor a(13) xor a(12) xor a(10)) & (a(14) xor a(12) xor a(11) xor a(9)) & (a(13) xor a(11) xor a(10) xor a(8)) & (a(12) xor a(10) xor a(9) xor a(7)) & (a(11) xor a(9) xor a(8)) & (a(10) xor a(8) xor a(7)) & (a(9) xor a(7)) & a(8) & a(7) );
end generate;
GF_2_16_P_10 : if final_value = 10 generate
o <= ( a(5) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(15) xor a(14) xor a(12)) & (a(0) xor a(14) xor a(13) xor a(11)) & (a(15) xor a(13) xor a(12) xor a(10)) & (a(14) xor a(12) xor a(11) xor a(9)) & (a(13) xor a(11) xor a(10) xor a(8)) & (a(12) xor a(10) xor a(9) xor a(7)) & (a(11) xor a(9) xor a(8) xor a(6)) & (a(10) xor a(8) xor a(7)) & (a(9) xor a(7) xor a(6)) & (a(8) xor a(6)) & a(7) & a(6) );
end generate;
GF_2_16_P_11 : if final_value = 11 generate
o <= ( (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(15) xor a(14) xor a(12)) & (a(0) xor a(14) xor a(13) xor a(11)) & (a(15) xor a(13) xor a(12) xor a(10)) & (a(14) xor a(12) xor a(11) xor a(9)) & (a(13) xor a(11) xor a(10) xor a(8)) & (a(12) xor a(10) xor a(9) xor a(7)) & (a(11) xor a(9) xor a(8) xor a(6)) & (a(10) xor a(8) xor a(7) xor a(5)) & (a(9) xor a(7) xor a(6)) & (a(8) xor a(6) xor a(5)) & (a(7) xor a(5)) & a(6) & a(5) );
end generate;
GF_2_16_P_12 : if final_value = 12 generate
o <= ( (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(15) xor a(14) xor a(12)) & (a(0) xor a(14) xor a(13) xor a(11)) & (a(15) xor a(13) xor a(12) xor a(10)) & (a(14) xor a(12) xor a(11) xor a(9)) & (a(13) xor a(11) xor a(10) xor a(8)) & (a(12) xor a(10) xor a(9) xor a(7)) & (a(11) xor a(9) xor a(8) xor a(6)) & (a(10) xor a(8) xor a(7) xor a(5)) & (a(9) xor a(7) xor a(6) xor a(4) xor a(15)) & (a(8) xor a(6) xor a(5)) & (a(7) xor a(5) xor a(4) xor a(15)) & (a(6) xor a(4) xor a(15)) & a(5) & (a(4) xor a(15)) );
end generate;
GF_2_16_P_13 : if final_value = 13 generate
o <= ( (a(2) xor a(15) xor a(13)) & (a(1) xor a(15) xor a(14) xor a(12)) & (a(0) xor a(14) xor a(13) xor a(11)) & (a(15) xor a(13) xor a(12) xor a(10)) & (a(14) xor a(12) xor a(11) xor a(9)) & (a(13) xor a(11) xor a(10) xor a(8)) & (a(12) xor a(10) xor a(9) xor a(7)) & (a(11) xor a(9) xor a(8) xor a(6)) & (a(10) xor a(8) xor a(7) xor a(5)) & (a(9) xor a(7) xor a(6) xor a(4) xor a(15)) & (a(8) xor a(6) xor a(5) xor a(3) xor a(14)) & (a(7) xor a(5) xor a(4) xor a(15)) & (a(6) xor a(4) xor a(15) xor a(3) xor a(14)) & (a(5) xor a(3) xor a(14)) & (a(4) xor a(15)) & (a(3) xor a(14)) );
end generate;
GF_2_16_P_14 : if final_value = 14 generate
o <= ( (a(1) xor a(15) xor a(14) xor a(12)) & (a(0) xor a(14) xor a(13) xor a(11)) & (a(15) xor a(13) xor a(12) xor a(10)) & (a(14) xor a(12) xor a(11) xor a(9)) & (a(13) xor a(11) xor a(10) xor a(8)) & (a(12) xor a(10) xor a(9) xor a(7)) & (a(11) xor a(9) xor a(8) xor a(6)) & (a(10) xor a(8) xor a(7) xor a(5)) & (a(9) xor a(7) xor a(6) xor a(4) xor a(15)) & (a(8) xor a(6) xor a(5) xor a(3) xor a(14)) & (a(7) xor a(5) xor a(4) xor a(2) xor a(13)) & (a(6) xor a(4) xor a(15) xor a(3) xor a(14)) & (a(5) xor a(3) xor a(14) xor a(2) xor a(15) xor a(13)) & (a(4) xor a(2) xor a(13)) & (a(3) xor a(14)) & (a(2) xor a(15) xor a(13)) );
end generate;
GF_2_16_P_15 : if final_value = 15 generate
o <= ( (a(0) xor a(14) xor a(13) xor a(11)) & (a(15) xor a(13) xor a(12) xor a(10)) & (a(14) xor a(12) xor a(11) xor a(9)) & (a(13) xor a(11) xor a(10) xor a(8)) & (a(12) xor a(10) xor a(9) xor a(7)) & (a(11) xor a(9) xor a(8) xor a(6)) & (a(10) xor a(8) xor a(7) xor a(5)) & (a(9) xor a(7) xor a(6) xor a(4) xor a(15)) & (a(8) xor a(6) xor a(5) xor a(3) xor a(14)) & (a(7) xor a(5) xor a(4) xor a(2) xor a(13)) & (a(6) xor a(4) xor a(3) xor a(1) xor a(12)) & (a(5) xor a(3) xor a(14) xor a(2) xor a(15) xor a(13)) & (a(4) xor a(2) xor a(13) xor a(1) xor a(15) xor a(14) xor a(12)) & (a(3) xor a(1) xor a(15) xor a(12)) & (a(2) xor a(15) xor a(13)) & (a(1) xor a(15) xor a(14) xor a(12)) );
end generate;
end generate;
GF_2_17 : if m = 17 generate -- x^17 + x^3 + 1
GF_2_17_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_17_P_1 : if final_value = 1 generate
o <= ( a(15 downto 3) & (a(2) xor a(16)) & a(1) & a(0) & a(16) );
end generate;
GF_2_17_P_2 : if final_value = 2 generate
o <= ( a(14 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & a(0) & a(16) & a(15) );
end generate;
GF_2_17_P_3 : if final_value = 3 generate
o <= ( a(13 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & a(16) & a(15) & a(14) );
end generate;
GF_2_17_P_4 : if final_value = 4 generate
o <= ( a(12 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & a(15) & a(14) & a(13) );
end generate;
GF_2_17_P_5 : if final_value = 5 generate
o <= ( a(11 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & a(14) & a(13) & a(12) );
end generate;
GF_2_17_P_6 : if final_value = 6 generate
o <= ( a(10 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & a(13) & a(12) & a(11) );
end generate;
GF_2_17_P_7 : if final_value = 7 generate
o <= ( a(9 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & a(12) & a(11) & a(10) );
end generate;
GF_2_17_P_8 : if final_value = 8 generate
o <= ( a(8 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & a(11) & a(10) & a(9) );
end generate;
GF_2_17_P_9 : if final_value = 9 generate
o <= ( a(7 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & a(10) & a(9) & a(8) );
end generate;
GF_2_17_P_10 : if final_value = 10 generate
o <= ( a(6 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & a(9) & a(8) & a(7) );
end generate;
GF_2_17_P_11 : if final_value = 11 generate
o <= ( a(5 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & a(8) & a(7) & a(6) );
end generate;
GF_2_17_P_12 : if final_value = 12 generate
o <= ( a(4 downto 3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & a(7) & a(6) & a(5) );
end generate;
GF_2_17_P_13 : if final_value = 13 generate
o <= ( a(3) & (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & a(6) & a(5) & a(4) );
end generate;
GF_2_17_P_14 : if final_value = 14 generate
o <= ( (a(2) xor a(16)) & (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & a(5) & a(4) & a(3) );
end generate;
GF_2_17_P_15 : if final_value = 15 generate
o <= ( (a(1) xor a(15)) & (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(16)) & a(4) & a(3) & (a(2) xor a(16)) );
end generate;
GF_2_17_P_16 : if final_value = 16 generate
o <= ( (a(0) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(16)) & (a(4) xor a(1) xor a(15)) & a(3) & (a(2) xor a(16)) & (a(1) xor a(15)) );
end generate;
end generate;
GF_2_18 : if m = 18 generate -- x^18 + x^7 + 1
GF_2_18_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_18_P_1 : if final_value = 1 generate
o <= ( a(16 downto 7) & (a(6) xor a(17)) & a(5) & a(4) & a(3) & a(2) & a(1) & a(0) & a(17) );
end generate;
GF_2_18_P_2 : if final_value = 2 generate
o <= ( a(15 downto 7) & (a(6) xor a(17)) & (a(5) xor a(16)) & a(4) & a(3) & a(2) & a(1) & a(0) & a(17) & a(16) );
end generate;
GF_2_18_P_3 : if final_value = 3 generate
o <= ( a(14 downto 7) & (a(6) xor a(17)) & (a(5) xor a(16)) & (a(4) xor a(15)) & a(3) & a(2) & a(1) & a(0) & a(17) & a(16) & a(15) );
end generate;
GF_2_18_P_4 : if final_value = 4 generate
o <= ( a(13 downto 7) & (a(6) xor a(17)) & (a(5) xor a(16)) & (a(4) xor a(15)) & (a(3) xor a(14)) & a(2) & a(1) & a(0) & a(17) & a(16) & a(15) & a(14) );
end generate;
GF_2_18_P_5 : if final_value = 5 generate
o <= ( a(12 downto 7) & (a(6) xor a(17)) & (a(5) xor a(16)) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(13)) & a(1) & a(0) & a(17) & a(16) & a(15) & a(14) & a(13) );
end generate;
GF_2_18_P_6 : if final_value = 6 generate
o <= ( a(11 downto 7) & (a(6) xor a(17)) & (a(5) xor a(16)) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(13)) & (a(1) xor a(12)) & a(0) & a(17) & a(16) & a(15) & a(14) & a(13) & a(12) );
end generate;
GF_2_18_P_7 : if final_value = 7 generate
o <= ( a(10 downto 7) & (a(6) xor a(17)) & (a(5) xor a(16)) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(13)) & (a(1) xor a(12)) & (a(0) xor a(11)) & a(17) & a(16) & a(15) & a(14) & a(13) & a(12) & a(11) );
end generate;
GF_2_18_P_8 : if final_value = 8 generate
o <= ( a(9 downto 7) & (a(6) xor a(17)) & (a(5) xor a(16)) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(13)) & (a(1) xor a(12)) & (a(0) xor a(11)) & (a(17) xor a(10)) & a(16) & a(15) & a(14) & a(13) & a(12) & a(11) & a(10) );
end generate;
GF_2_18_P_9 : if final_value = 9 generate
o <= ( a(8 downto 7) & (a(6) xor a(17)) & (a(5) xor a(16)) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(13)) & (a(1) xor a(12)) & (a(0) xor a(11)) & (a(17) xor a(10)) & (a(16) xor a(9)) & a(15) & a(14) & a(13) & a(12) & a(11) & a(10) & a(9) );
end generate;
GF_2_18_P_10 : if final_value = 10 generate
o <= ( a(7) & (a(6) xor a(17)) & (a(5) xor a(16)) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(13)) & (a(1) xor a(12)) & (a(0) xor a(11)) & (a(17) xor a(10)) & (a(16) xor a(9)) & (a(15) xor a(8)) & a(14) & a(13) & a(12) & a(11) & a(10) & a(9) & a(8) );
end generate;
GF_2_18_P_11 : if final_value = 11 generate
o <= ( (a(6) xor a(17)) & (a(5) xor a(16)) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(13)) & (a(1) xor a(12)) & (a(0) xor a(11)) & (a(17) xor a(10)) & (a(16) xor a(9)) & (a(15) xor a(8)) & (a(14) xor a(7)) & a(13) & a(12) & a(11) & a(10) & a(9) & a(8) & a(7) );
end generate;
GF_2_18_P_12 : if final_value = 12 generate
o <= ( (a(5) xor a(16)) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(13)) & (a(1) xor a(12)) & (a(0) xor a(11)) & (a(17) xor a(10)) & (a(16) xor a(9)) & (a(15) xor a(8)) & (a(14) xor a(7)) & (a(13) xor a(6) xor a(17)) & a(12) & a(11) & a(10) & a(9) & a(8) & a(7) & (a(6) xor a(17)) );
end generate;
GF_2_18_P_13 : if final_value = 13 generate
o <= ( (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(13)) & (a(1) xor a(12)) & (a(0) xor a(11)) & (a(17) xor a(10)) & (a(16) xor a(9)) & (a(15) xor a(8)) & (a(14) xor a(7)) & (a(13) xor a(6) xor a(17)) & (a(12) xor a(5) xor a(16)) & a(11) & a(10) & a(9) & a(8) & a(7) & (a(6) xor a(17)) & (a(5) xor a(16)) );
end generate;
GF_2_18_P_14 : if final_value = 14 generate
o <= ( (a(3) xor a(14)) & (a(2) xor a(13)) & (a(1) xor a(12)) & (a(0) xor a(11)) & (a(17) xor a(10)) & (a(16) xor a(9)) & (a(15) xor a(8)) & (a(14) xor a(7)) & (a(13) xor a(6) xor a(17)) & (a(12) xor a(5) xor a(16)) & (a(11) xor a(4) xor a(15)) & a(10) & a(9) & a(8) & a(7) & (a(6) xor a(17)) & (a(5) xor a(16)) & (a(4) xor a(15)) );
end generate;
GF_2_18_P_15 : if final_value = 15 generate
o <= ( (a(2) xor a(13)) & (a(1) xor a(12)) & (a(0) xor a(11)) & (a(17) xor a(10)) & (a(16) xor a(9)) & (a(15) xor a(8)) & (a(14) xor a(7)) & (a(13) xor a(6) xor a(17)) & (a(12) xor a(5) xor a(16)) & (a(11) xor a(4) xor a(15)) & (a(10) xor a(3) xor a(14)) & a(9) & a(8) & a(7) & (a(6) xor a(17)) & (a(5) xor a(16)) & (a(4) xor a(15)) & (a(3) xor a(14)) );
end generate;
GF_2_18_P_16 : if final_value = 16 generate
o <= ( (a(1) xor a(12)) & (a(0) xor a(11)) & (a(17) xor a(10)) & (a(16) xor a(9)) & (a(15) xor a(8)) & (a(14) xor a(7)) & (a(13) xor a(6) xor a(17)) & (a(12) xor a(5) xor a(16)) & (a(11) xor a(4) xor a(15)) & (a(10) xor a(3) xor a(14)) & (a(9) xor a(2) xor a(13)) & a(8) & a(7) & (a(6) xor a(17)) & (a(5) xor a(16)) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(13)) );
end generate;
GF_2_18_P_17 : if final_value = 17 generate
o <= ( (a(0) xor a(11)) & (a(17) xor a(10)) & (a(16) xor a(9)) & (a(15) xor a(8)) & (a(14) xor a(7)) & (a(13) xor a(6) xor a(17)) & (a(12) xor a(5) xor a(16)) & (a(11) xor a(4) xor a(15)) & (a(10) xor a(3) xor a(14)) & (a(9) xor a(2) xor a(13)) & (a(8) xor a(1) xor a(12)) & a(7) & (a(6) xor a(17)) & (a(5) xor a(16)) & (a(4) xor a(15)) & (a(3) xor a(14)) & (a(2) xor a(13)) & (a(1) xor a(12)) );
end generate;
end generate;
GF_2_19 : if m = 19 generate -- x^19 + x^5 + x^2 + x^1 + 1
GF_2_19_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_19_P_1 : if final_value = 1 generate
o <= ( a(17 downto 5) & (a(4) xor a(18)) & a(3) & a(2) & (a(1) xor a(18)) & (a(0) xor a(18)) & a(18) );
end generate;
GF_2_19_P_2 : if final_value = 2 generate
o <= ( a(16 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & a(2) & (a(1) xor a(18)) & (a(0) xor a(18) xor a(17)) & (a(18) xor a(17)) & a(17) );
end generate;
GF_2_19_P_3 : if final_value = 3 generate
o <= ( a(15 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18)) & (a(0) xor a(18) xor a(17)) & (a(18) xor a(17) xor a(16)) & (a(17) xor a(16)) & a(16) );
end generate;
GF_2_19_P_4 : if final_value = 4 generate
o <= ( a(14 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17)) & (a(18) xor a(17) xor a(16)) & (a(17) xor a(16) xor a(15)) & (a(16) xor a(15)) & a(15) );
end generate;
GF_2_19_P_5 : if final_value = 5 generate
o <= ( a(13 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16)) & (a(17) xor a(16) xor a(15)) & (a(16) xor a(15) xor a(14)) & (a(15) xor a(14)) & a(14) );
end generate;
GF_2_19_P_6 : if final_value = 6 generate
o <= ( a(12 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15)) & (a(16) xor a(15) xor a(14)) & (a(15) xor a(14) xor a(13)) & (a(14) xor a(13)) & a(13) );
end generate;
GF_2_19_P_7 : if final_value = 7 generate
o <= ( a(11 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14)) & (a(15) xor a(14) xor a(13)) & (a(14) xor a(13) xor a(12)) & (a(13) xor a(12)) & a(12) );
end generate;
GF_2_19_P_8 : if final_value = 8 generate
o <= ( a(10 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13)) & (a(14) xor a(13) xor a(12)) & (a(13) xor a(12) xor a(11)) & (a(12) xor a(11)) & a(11) );
end generate;
GF_2_19_P_9 : if final_value = 9 generate
o <= ( a(9 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12)) & (a(13) xor a(12) xor a(11)) & (a(12) xor a(11) xor a(10)) & (a(11) xor a(10)) & a(10) );
end generate;
GF_2_19_P_10 : if final_value = 10 generate
o <= ( a(8 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11)) & (a(12) xor a(11) xor a(10)) & (a(11) xor a(10) xor a(9)) & (a(10) xor a(9)) & a(9) );
end generate;
GF_2_19_P_11 : if final_value = 11 generate
o <= ( a(7 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10)) & (a(11) xor a(10) xor a(9)) & (a(10) xor a(9) xor a(8)) & (a(9) xor a(8)) & a(8) );
end generate;
GF_2_19_P_12 : if final_value = 12 generate
o <= ( a(6 downto 5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9)) & (a(10) xor a(9) xor a(8)) & (a(9) xor a(8) xor a(7)) & (a(8) xor a(7)) & a(7) );
end generate;
GF_2_19_P_13 : if final_value = 13 generate
o <= ( a(5) & (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8)) & (a(9) xor a(8) xor a(7)) & (a(8) xor a(7) xor a(6)) & (a(7) xor a(6)) & a(6) );
end generate;
GF_2_19_P_14 : if final_value = 14 generate
o <= ( (a(4) xor a(18)) & (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8) xor a(5)) & (a(9) xor a(8) xor a(7)) & (a(8) xor a(7) xor a(6)) & (a(7) xor a(6) xor a(5)) & (a(6) xor a(5)) & a(5) );
end generate;
GF_2_19_P_15 : if final_value = 15 generate
o <= ( (a(3) xor a(17)) & (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8) xor a(5)) & (a(9) xor a(8) xor a(7) xor a(4) xor a(18)) & (a(8) xor a(7) xor a(6)) & (a(7) xor a(6) xor a(5)) & (a(6) xor a(5) xor a(4) xor a(18)) & (a(5) xor a(4) xor a(18)) & (a(4) xor a(18)) );
end generate;
GF_2_19_P_16 : if final_value = 16 generate
o <= ( (a(2) xor a(16)) & (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8) xor a(5)) & (a(9) xor a(8) xor a(7) xor a(4) xor a(18)) & (a(8) xor a(7) xor a(6) xor a(3) xor a(17)) & (a(7) xor a(6) xor a(5)) & (a(6) xor a(5) xor a(4) xor a(18)) & (a(5) xor a(4) xor a(18) xor a(3) xor a(17)) & (a(4) xor a(18) xor a(3) xor a(17)) & (a(3) xor a(17)) );
end generate;
GF_2_19_P_17 : if final_value = 17 generate
o <= ( (a(1) xor a(18) xor a(15)) & (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8) xor a(5)) & (a(9) xor a(8) xor a(7) xor a(4) xor a(18)) & (a(8) xor a(7) xor a(6) xor a(3) xor a(17)) & (a(7) xor a(6) xor a(5) xor a(2) xor a(16)) & (a(6) xor a(5) xor a(4) xor a(18)) & (a(5) xor a(4) xor a(18) xor a(3) xor a(17)) & (a(4) xor a(18) xor a(3) xor a(17) xor a(2) xor a(16)) & (a(3) xor a(17) xor a(2) xor a(16)) & (a(2) xor a(16)) );
end generate;
GF_2_19_P_18 : if final_value = 18 generate
o <= ( (a(0) xor a(18) xor a(17) xor a(14)) & (a(18) xor a(17) xor a(16) xor a(13)) & (a(17) xor a(16) xor a(15) xor a(12)) & (a(16) xor a(15) xor a(14) xor a(11)) & (a(15) xor a(14) xor a(13) xor a(10)) & (a(14) xor a(13) xor a(12) xor a(9)) & (a(13) xor a(12) xor a(11) xor a(8)) & (a(12) xor a(11) xor a(10) xor a(7)) & (a(11) xor a(10) xor a(9) xor a(6)) & (a(10) xor a(9) xor a(8) xor a(5)) & (a(9) xor a(8) xor a(7) xor a(4) xor a(18)) & (a(8) xor a(7) xor a(6) xor a(3) xor a(17)) & (a(7) xor a(6) xor a(5) xor a(2) xor a(16)) & (a(6) xor a(5) xor a(4) xor a(1) xor a(15)) & (a(5) xor a(4) xor a(18) xor a(3) xor a(17)) & (a(4) xor a(18) xor a(3) xor a(17) xor a(2) xor a(16)) & (a(3) xor a(17) xor a(2) xor a(16) xor a(1) xor a(18) xor a(15)) & (a(2) xor a(16) xor a(1) xor a(18) xor a(15)) & (a(1) xor a(18) xor a(15)) );
end generate;
end generate;
GF_2_20 : if m = 20 generate -- x^20 + x^3 + 1
GF_2_20_P_0 : if final_value = 0 generate
o <= a;
end generate;
GF_2_20_P_1 : if final_value = 1 generate
o <= ( a(18 downto 3) & (a(2) xor a(19)) & a(1) & a(0) & a(19) );
end generate;
GF_2_20_P_2 : if final_value = 2 generate
o <= ( a(17 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & a(0) & a(19) & a(18) );
end generate;
GF_2_20_P_3 : if final_value = 3 generate
o <= ( a(16 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & a(19) & a(18) & a(17) );
end generate;
GF_2_20_P_4 : if final_value = 4 generate
o <= ( a(15 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & a(18) & a(17) & a(16) );
end generate;
GF_2_20_P_5 : if final_value = 5 generate
o <= ( a(14 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & a(17) & a(16) & a(15) );
end generate;
GF_2_20_P_6 : if final_value = 6 generate
o <= ( a(13 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & a(16) & a(15) & a(14) );
end generate;
GF_2_20_P_7 : if final_value = 7 generate
o <= ( a(12 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & a(15) & a(14) & a(13) );
end generate;
GF_2_20_P_8 : if final_value = 8 generate
o <= ( a(11 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & a(14) & a(13) & a(12) );
end generate;
GF_2_20_P_9 : if final_value = 9 generate
o <= ( a(10 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & a(13) & a(12) & a(11) );
end generate;
GF_2_20_P_10 : if final_value = 10 generate
o <= ( a(9 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & a(12) & a(11) & a(10) );
end generate;
GF_2_20_P_11 : if final_value = 11 generate
o <= ( a(8 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & a(11) & a(10) & a(9) );
end generate;
GF_2_20_P_12 : if final_value = 12 generate
o <= ( a(7 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & a(10) & a(9) & a(8) );
end generate;
GF_2_20_P_13 : if final_value = 13 generate
o <= ( a(6 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & a(9) & a(8) & a(7) );
end generate;
GF_2_20_P_14 : if final_value = 14 generate
o <= ( a(5 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & a(8) & a(7) & a(6) );
end generate;
GF_2_20_P_15 : if final_value = 15 generate
o <= ( a(4 downto 3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & a(7) & a(6) & a(5) );
end generate;
GF_2_20_P_16 : if final_value = 16 generate
o <= ( a(3) & (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & a(6) & a(5) & a(4) );
end generate;
GF_2_20_P_17 : if final_value = 17 generate
o <= ( (a(2) xor a(19)) & (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & a(5) & a(4) & a(3) );
end generate;
GF_2_20_P_18 : if final_value = 18 generate
o <= ( (a(1) xor a(18)) & (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(19)) & a(4) & a(3) & (a(2) xor a(19)) );
end generate;
GF_2_20_P_19 : if final_value = 19 generate
o <= ( (a(0) xor a(17)) & (a(19) xor a(16)) & (a(18) xor a(15)) & (a(17) xor a(14)) & (a(16) xor a(13)) & (a(15) xor a(12)) & (a(14) xor a(11)) & (a(13) xor a(10)) & (a(12) xor a(9)) & (a(11) xor a(8)) & (a(10) xor a(7)) & (a(9) xor a(6)) & (a(8) xor a(5)) & (a(7) xor a(4)) & (a(6) xor a(3)) & (a(5) xor a(2) xor a(19)) & (a(4) xor a(1) xor a(18)) & a(3) & (a(2) xor a(19)) & (a(1) xor a(18)) );
end generate;
end generate;
end Software_POLYNOMIAL;
|
bsd-2-clause
|
8795935617dd9090d6f286d7c5d3d2f7
| 0.487152 | 1.884597 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/shift_register/shift_register_tb.vhd
| 1 | 2,620 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity shift_register_tb is
end entity;
architecture shift_register_tb_arq of shift_register_tb is
signal d_in : std_logic_vector(31 downto 0) := (others => '0');
signal rst_in: std_logic:='0';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal q_out: std_logic_vector(31 downto 0) := (others => '0');
component shift_register is
generic(REGISTRY_BITS : integer := 32;
STEPS : integer := 4);
port(
enable: in std_logic;
reset: in std_logic;
clk: in std_logic;
D: in std_logic_vector(REGISTRY_BITS - 1 downto 0);
Q: out std_logic_vector(REGISTRY_BITS - 1 downto 0)
);
end component;
for shift_register_0: shift_register use entity work.shift_register;
begin
shift_register_0: shift_register
generic map(REGISTRY_BITS => 32, STEPS => 4)
port map(
enable => enable_in,
reset => rst_in,
clk => clk_in,
D => d_in,
Q => q_out
);
process
type pattern_type is record
en : std_logic;
r: std_logic;
clk: std_logic;
d: std_logic_vector(31 downto 0);
q: std_logic_vector(31 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range<>) of pattern_type;
constant patterns : pattern_array := (
('1', '0','1', "00000000000000000000000000000001", "00000000000000000000000000000000"),
('1', '0','1', "00000000000000000000000000000010", "00000000000000000000000000000000"),
('1', '0','1', "00000000000000000000000000000011", "00000000000000000000000000000000"),
('1', '0','1', "00000000000000000000000000000100", "00000000000000000000000000000001"),
('1', '0','1', "00000000000000000000000000000000", "00000000000000000000000000000010"),
('1', '0','1', "00000000000000000000000000000000", "00000000000000000000000000000011"),
('1', '0','1', "00000000000000000000000000000000", "00000000000000000000000000000100"),
('1', '0','1', "00000000000000000000000000000000", "00000000000000000000000000000000")
);
begin
for i in patterns'range loop
d_in <= patterns(i).d;
enable_in <= patterns(i).en;
rst_in <= patterns(i).r;
clk_in <= patterns(i).clk;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert q_out = patterns(i).q report "BAD Q, EXPECTED " & integer'image(to_integer(unsigned(patterns(i).q))) & " GOT: " & integer'image(to_integer(unsigned(q_out)));
clk_in <= '0'; --reset clock
wait for 1 ns;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
39772662bd4ba9ad43de2d1fb5e7efd7
| 0.658015 | 3.46103 | false | false | false | false |
alainmarcel/Surelog
|
third_party/tests/ariane/fpga/src/apb_uart/src/slib_edge_detect.vhd
| 5 | 1,699 |
--
-- Signal edge detect
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end slib_edge_detect;
architecture rtl of slib_edge_detect is
signal iDd : std_logic; -- D register
begin
-- Store D
ED_D: process (RST, CLK)
begin
if (RST = '1') then
iDd <= '0';
elsif (CLK'event and CLK='1') then
iDd <= D;
end if;
end process;
-- Output ports
RE <= '1' when iDd = '0' and D = '1' else '0';
FE <= '1' when iDd = '1' and D = '0' else '0';
end rtl;
|
apache-2.0
|
35af17661d3d436e1fa3bcdda39b3eda
| 0.606828 | 3.709607 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/stage_polynomial_calc_v4.vhd
| 1 | 2,815 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Stage_Polynomial_Calc_v4
-- Module Name: Stage_Polynomial_Calc_v4
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 3rd step in Goppa Code Decoding.
--
-- This circuit is the stage for pipeline_polynomial_calc_v4. The pipeline is composed of
-- an arbitrary number of this stages.
--
-- For the computation this circuit applies the Horner scheme, where at each stage
-- an accumulator is multiplied by respective x and then added accumulated with coefficient.
-- In Horner scheme algorithm, it begin from the most significative coefficient until reaches
-- lesser significative coefficient.
--
-- It can also change the inner working to compute syndrome at each stage.
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- Dependencies:
-- VHDL-93
--
-- mult_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity stage_polynomial_calc_v4 is
Generic(gf_2_m : integer range 1 to 20 := 11);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial_coefficient : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end stage_polynomial_calc_v4;
architecture Behavioral of stage_polynomial_calc_v4 is
component mult_gf_2_m
Generic(gf_2_m : integer range 1 to 20 := 11);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal mult_x_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_x_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_x_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_accumulated : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
begin
value_accumulated <= value_acc xor value_polynomial_coefficient;
mult_x : mult_gf_2_m
Generic Map (gf_2_m => gf_2_m)
Port Map (
a => mult_x_a,
b => mult_x_b,
o => mult_x_o
);
mult_x_a <= value_x;
mult_x_b <= value_acc when mode_polynomial_syndrome = '1' else
value_accumulated;
new_value_syndrome <= value_accumulated;
new_value_acc <= mult_x_o;
end Behavioral;
|
bsd-2-clause
|
aa7933e0c1e6b34016de40df7b4d8577
| 0.645471 | 3.159371 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/TP1-Contador/bcd_multiplexer_tb.vhd
| 1 | 1,455 |
library ieee;
use ieee.std_logic_1164.all;
entity bcd_multiplexer_tb is
end;
architecture bcd_multiplexer_tb_func of bcd_multiplexer_tb is
signal bcd0_in : std_logic_vector(3 downto 0);
signal bcd1_in : std_logic_vector(3 downto 0);
signal bcd2_in : std_logic_vector(3 downto 0);
signal bcd3_in : std_logic_vector(3 downto 0);
signal signal_in_a : std_logic:='0';
signal signal_in_b : std_logic:='0';
signal selector_in : std_logic_vector (1 downto 0);
signal mux_out: std_logic_vector(3 downto 0);
component bcd_multiplexer is
port(
bcd0_input : in std_logic_vector(3 downto 0);
bcd1_input : in std_logic_vector(3 downto 0);
bcd2_input : in std_logic_vector(3 downto 0);
bcd3_input : in std_logic_vector(3 downto 0);
mux_selector : in std_logic_vector (1 downto 0);
mux_output : out std_logic_vector (3 downto 0)
);
end component;
begin
bcd0_in <= b"0001";
bcd1_in <= b"0010";
bcd2_in <= b"0100";
bcd3_in <= b"1000";
signal_in_a <= not signal_in_a after 10 ns;
signal_in_b <= not signal_in_b after 20 ns;
selector_in(0) <= signal_in_a;
selector_in(1) <= signal_in_b;
bcd_multiplexerMap: bcd_multiplexer
port map(
bcd0_input => bcd0_in,
bcd1_input => bcd1_in,
bcd2_input => bcd2_in,
bcd3_input => bcd3_in,
mux_selector => selector_in,
mux_output => mux_out
);
end architecture;
|
gpl-3.0
|
84541155c78f1baa95d58f543bb372ba
| 0.624055 | 2.740113 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/tp1/bcd_counter/cont_bcd.vhd
| 1 | 812 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cont_bcd is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
s: out std_logic_vector(3 downto 0);
co: out std_logic
);
end;
architecture cont_bcd_arq of cont_bcd is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(clk,rst)
variable count: integer range 0 to 10;
begin
if rst = '1' then
s <= (others => '0');
co <= '0';
elsif rising_edge(clk) then
if ena = '1' then
count:=count + 1;
if count = 9 then
co <= '1';
elsif count = 10 then
count := 0;
co <= '0';
else
co <= '0';
end if;
end if;
end if;
s <= std_logic_vector(TO_UNSIGNED(count,4));
end process;
end;
|
gpl-3.0
|
860d65e7a7c3abb1d47ebad8d343bc03
| 0.578818 | 2.809689 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/tb_ram.vhd
| 1 | 2,761 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_RAM
-- Module Name: Tb_RAM
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Test bench to test memory RAM capacity to load from files.
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- ram Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_ram is
end tb_ram;
architecture Behavioral of tb_ram is
type vector is array(integer range <>) of std_logic_vector(10 downto 0);
constant ram_word : integer := 11;
constant ram_address : integer := 12;
constant PERIOD : time := 10 ns;
component ram
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "mceliece/util/ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
signal data_in : STD_LOGIC_VECTOR ((ram_word - 1) downto 0);
signal rw : STD_LOGIC;
signal clk : STD_LOGIC := '0';
signal address : STD_LOGIC_VECTOR ((ram_address - 1) downto 0);
signal data_out : STD_LOGIC_VECTOR ((ram_word - 1) downto 0);
for test : ram use entity work.ram(file_load);
begin
clk <= not clk after PERIOD;
test: ram
Generic Map(
ram_address_size => ram_address,
ram_word_size => ram_word,
file_ram_word_size => ram_word,
load_file_name => "mceliece/util/ram.dat",
dump_file_name => ""
)
Port Map(
data_in => data_in,
rw => rw,
clk => clk,
rst => '0',
dump => '0',
address => address,
rst_value => (others => '0'),
data_out => data_out
);
process
variable actual_address : unsigned((ram_address - 1) downto 0);
begin
actual_address := "000000000000";
data_in <= "00000000000";
rw <= '0';
wait for PERIOD;
while (actual_address < "111111111111") loop
address <= std_logic_vector(actual_address);
wait for PERIOD;
actual_address := actual_address + "1";
wait for PERIOD;
end loop;
wait;
end process;
end Behavioral;
|
bsd-2-clause
|
3d7cf932b63ce6ede924698071837772
| 0.61427 | 3.102247 | false | false | false | false |
pwuertz/digitizer2fw
|
src/rtl/ft2232_communication.vhd
| 1 | 5,720 |
-------------------------------------------------------------------------------
-- FT2232 Communication Interface
--
-- (De)serializes data to/from USB interface for writing/reading registers
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.communication_pkg.all;
entity ft2232_communication is
port (
clk: in std_logic;
rst: in std_logic;
error: out std_logic;
-- application bus interface
slave_addr: out unsigned(5 downto 0);
slave_port: out unsigned(5 downto 0);
comm_to_slave: out comm_to_slave_t;
comm_from_slave: in comm_from_slave_t;
-- ftdi interface
usb_clk: in std_logic;
usb_oe_n: out std_logic;
usb_rd_n: out std_logic;
usb_wr_n: out std_logic;
usb_rxf_n: in std_logic;
usb_txe_n: in std_logic;
usb_d: inout std_logic_vector(7 downto 0)
);
end ft2232_communication;
architecture ft2232_communication_arch of ft2232_communication is
component ft2232fifo
port (
-- ftdi interface
usb_clk: in std_logic;
usb_oe_n: out std_logic;
usb_rd_n: out std_logic;
usb_wr_n: out std_logic;
usb_rxf_n: in std_logic;
usb_txe_n: in std_logic;
usb_d: inout std_logic_vector(7 downto 0);
-- application/fifo interface
rst: in std_logic;
fifo_in_wr_en: out std_logic;
fifo_in_full: in std_logic;
fifo_in_data: out std_logic_vector(7 downto 0);
fifo_out_rd_en: out std_logic;
fifo_out_empty: in std_logic;
fifo_out_data: in std_logic_vector(7 downto 0)
);
end component;
component fifo_16_to_8
port (
rst: in std_logic;
wr_clk: in std_logic;
rd_clk: in std_logic;
din: in std_logic_vector(15 downto 0);
wr_en: in std_logic;
rd_en: in std_logic;
dout: out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end component;
component fifo_8_to_16
port (
rst: in std_logic;
wr_clk: in std_logic;
rd_clk: in std_logic;
din: in std_logic_vector(7 downto 0);
wr_en: in std_logic;
rd_en: in std_logic;
dout: out std_logic_vector(15 downto 0);
full: out std_logic;
empty: out std_logic
);
end component;
component communication
port (
clk: in std_logic;
rst: in std_logic;
error: out std_logic;
-- application bus interface
slave_addr: out unsigned(5 downto 0);
slave_port: out unsigned(5 downto 0);
comm_to_slave: out comm_to_slave_t;
comm_from_slave: in comm_from_slave_t;
-- fifo interface
fifo_out_wr_en: out std_logic;
fifo_out_full: in std_logic;
fifo_out_data: out std_logic_vector(COMM_BUS_WIDTH-1 downto 0);
fifo_in_rd_en: out std_logic;
fifo_in_empty: in std_logic;
fifo_in_data: in std_logic_vector(COMM_BUS_WIDTH-1 downto 0)
);
end component;
signal fifo_from_usb_rd, fifo_from_usb_empty: std_logic;
signal fifo_from_usb_wr, fifo_from_usb_full: std_logic;
signal fifo_to_usb_rd, fifo_to_usb_empty: std_logic;
signal fifo_to_usb_wr, fifo_to_usb_full: std_logic;
signal fifo_to_usb_dout, fifo_from_usb_din: std_logic_vector(7 downto 0);
signal fifo_to_usb_din, fifo_from_usb_dout: std_logic_vector(15 downto 0);
begin
communication_inst: communication
port map (
clk => clk,
rst => rst,
error => error,
-- application register interface
slave_addr => slave_addr,
slave_port => slave_port,
comm_to_slave => comm_to_slave,
comm_from_slave => comm_from_slave,
-- fifo interface
fifo_out_wr_en => fifo_to_usb_wr,
fifo_out_full => fifo_to_usb_full,
fifo_out_data => fifo_to_usb_din,
fifo_in_rd_en => fifo_from_usb_rd,
fifo_in_empty => fifo_from_usb_empty,
fifo_in_data => fifo_from_usb_dout
);
ft2232fifo_inst: ft2232fifo
port map (
-- ftdi interface
usb_clk => usb_clk,
usb_oe_n => usb_oe_n,
usb_rd_n => usb_rd_n,
usb_wr_n => usb_wr_n,
usb_rxf_n => usb_rxf_n,
usb_txe_n => usb_txe_n,
usb_d => usb_d,
-- application/fifo interface
rst => rst,
fifo_in_wr_en => fifo_from_usb_wr,
fifo_in_full => fifo_from_usb_full,
fifo_in_data => fifo_from_usb_din,
fifo_out_rd_en => fifo_to_usb_rd,
fifo_out_empty => fifo_to_usb_empty,
fifo_out_data => fifo_to_usb_dout
);
fifo_to_usb: fifo_16_to_8
port map (
rst => rst,
wr_clk => clk,
rd_clk => usb_clk,
din => fifo_to_usb_din,
wr_en => fifo_to_usb_wr,
rd_en => fifo_to_usb_rd,
dout => fifo_to_usb_dout,
full => fifo_to_usb_full,
empty => fifo_to_usb_empty
);
fifo_from_usb: fifo_8_to_16
port map (
rst => rst,
wr_clk => usb_clk,
rd_clk => clk,
din => fifo_from_usb_din,
wr_en => fifo_from_usb_wr,
rd_en => fifo_from_usb_rd,
dout => fifo_from_usb_dout,
full => fifo_from_usb_full,
empty => fifo_from_usb_empty
);
end ft2232_communication_arch;
|
gpl-3.0
|
3f107d4c0af11fa107e26d5eb88224c0
| 0.559713 | 3.317285 | false | false | false | false |
laurivosandi/hdl
|
zynq/src/ov7670_capture/debounce.vhd
| 1 | 1,020 |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Convert the push button to a 1PPS that can be used to restart
-- camera initialisation
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity debounce is
port (
clk : in std_logic;
i : in std_logic;
o : out std_logic
);
end debounce;
architecture behavioral of debounce is
signal c : unsigned(23 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if i = '1' then
if c = x"ffffff" then
o <= '1';
else
o <= '0';
end if;
c <= c+1;
else
c <= (others => '0');
o <= '0';
end if;
end if;
end process;
end behavioral;
|
mit
|
8101bb4e05a21cf66fb6fdf208d3071e
| 0.406863 | 4.513274 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/bcd_controller/4_port_multiplexer.vhd
| 2 | 969 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity four_port_multiplexer is
generic(
BITS:natural := 1);
port (
data_in_a: in std_logic_vector(BITS-1 downto 0);
data_in_b: in std_logic_vector(BITS-1 downto 0);
data_in_c: in std_logic_vector(BITS-1 downto 0);
data_in_d: in std_logic_vector(BITS-1 downto 0);
select_in: in std_logic_vector(1 downto 0); --2 bits, 4 opciones
data_out: out std_logic_vector(BITS-1 downto 0)
);
end;
architecture four_port_multiplexer_arq of four_port_multiplexer is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(select_in)
begin
SELECTED: case to_integer(unsigned(select_in)) is
when 0 =>
data_out <= data_in_a;
when 1 =>
data_out <= data_in_b;
when 2 =>
data_out <= data_in_c;
when 3 =>
data_out <= data_in_d;
when others => --Redundante
end case SELECTED;
end process;
end;
|
gpl-3.0
|
fefe40e50125e12f8664ddea4135ce50
| 0.654283 | 2.833333 | false | false | false | false |
ruygargar/LCSE_lab
|
dma/tb_dma_bus_controller.vhd
| 1 | 5,905 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:06:11 01/04/2014
-- Design Name:
-- Module Name: C:/Users/Ruy/Desktop/LCSE_lab/dma/tb_dma_bus_controller.vhd
-- Project Name: dma
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dma_bus_controller
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_dma_bus_controller IS
END tb_dma_bus_controller;
ARCHITECTURE behavior OF tb_dma_bus_controller IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dma_bus_controller
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
Databus : INOUT std_logic_vector(7 downto 0);
Address : OUT std_logic_vector(7 downto 0);
ChipSelect : OUT std_logic;
WriteEnable : OUT std_logic;
OutputEnable : OUT std_logic;
Send : IN std_logic;
Ready : OUT std_logic;
DMA_RQ : OUT std_logic;
DMA_ACK : IN std_logic;
RX_empty : IN std_logic;
-- pragma synthesis_off
BC_state_ns : out integer;
-- pragma synthesis_on
RX_Databus : IN std_logic_vector(7 downto 0);
RX_Address : IN std_logic_vector(7 downto 0);
RX_ChipSelect : IN std_logic;
RX_WriteEnable : IN std_logic;
RX_OutputEnable : IN std_logic;
RX_start : OUT std_logic;
RX_end : IN std_logic;
TX_Databus : OUT std_logic_vector(7 downto 0);
TX_Address : IN std_logic_vector(7 downto 0);
TX_ChipSelect : IN std_logic;
TX_WriteEnable : IN std_logic;
TX_OutputEnable : IN std_logic;
TX_start : OUT std_logic;
TX_ready : IN std_logic;
TX_end : IN std_logic
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal Send : std_logic := '0';
signal DMA_ACK : std_logic := '0';
signal RX_empty : std_logic := '1';
signal RX_Databus : std_logic_vector(7 downto 0) := X"AA";
signal RX_Address : std_logic_vector(7 downto 0) := X"AA";
signal RX_ChipSelect : std_logic := '1';
signal RX_WriteEnable : std_logic := '0';
signal RX_OutputEnable : std_logic := '1';
signal RX_end : std_logic := '0';
signal TX_Address : std_logic_vector(7 downto 0) := X"55";
signal TX_ChipSelect : std_logic := '1';
signal TX_WriteEnable : std_logic := '1';
signal TX_OutputEnable : std_logic := '0';
signal TX_ready : std_logic := '1';
signal TX_end : std_logic := '0';
--BiDirs
signal Databus : std_logic_vector(7 downto 0) := X"55";
--Outputs
signal Address : std_logic_vector(7 downto 0);
signal ChipSelect : std_logic;
signal WriteEnable : std_logic;
signal OutputEnable : std_logic;
signal Ready : std_logic;
signal DMA_RQ : std_logic;
signal RX_start : std_logic;
signal TX_Databus : std_logic_vector(7 downto 0);
signal TX_start : std_logic;
-- pragma synthesis_on
signal BC_state_ns : integer;
-- pragma synthesis_on
-- Clock period definitions
constant Clk_period : time := 25ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dma_bus_controller PORT MAP (
Clk => Clk,
Reset => Reset,
Databus => Databus,
Address => Address,
ChipSelect => ChipSelect,
WriteEnable => WriteEnable,
OutputEnable => OutputEnable,
Send => Send,
Ready => Ready,
DMA_RQ => DMA_RQ,
DMA_ACK => DMA_ACK,
RX_empty => RX_empty,
-- pragma synthesis_off
BC_state_ns => BC_state_ns,
-- pragma synthesis_on
RX_Databus => RX_Databus,
RX_Address => RX_Address,
RX_ChipSelect => RX_ChipSelect,
RX_WriteEnable => RX_WriteEnable,
RX_OutputEnable => RX_OutputEnable,
RX_start => RX_start,
RX_end => RX_end,
TX_Databus => TX_Databus,
TX_Address => TX_Address,
TX_ChipSelect => TX_ChipSelect,
TX_WriteEnable => TX_WriteEnable,
TX_OutputEnable => TX_OutputEnable,
TX_start => TX_start,
TX_ready => TX_ready,
TX_end => TX_end
);
Clk <= not Clk after Clk_period;
-- Stimulus process
process
begin
wait for 50 ns;
Reset <= '1';
wait for 100 ns;
RX_Empty <= '0';
wait until BC_state_ns = 2;
Databus <= (others => 'Z');
wait for 325 ns;
DMA_ACK <= '1';
wait for 175 ns;
RX_empty <= '1';
wait until DMA_RQ = '0';
DMA_ACK <= '0' after 2 ns;
wait until BC_state_ns = 0;
Databus <= X"22";
wait;
end process;
process
begin
wait until BC_state_ns = 1;
TX_ready <= '0';
wait for 325 ns;
TX_end <= '1';
wait for 50 ns;
TX_end <= '0';
wait for 500 ns;
TX_ready <= '1';
wait;
end process;
process
begin
wait until BC_state_ns = 4;
wait for 325 ns;
RX_end <= '1';
wait for 50 ns;
RX_end <= '0';
wait;
end process;
process
begin
wait for 300 ns;
Send <= '1';
wait until Ready = '1';
Send <= '0' after 10 ns;
wait;
end process;
END;
|
gpl-3.0
|
bf90ec8e34f2bb1d35d6ebc37ee42169
| 0.574936 | 3.527479 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/memory_matrix/memory_matrix.vhd
| 1 | 6,426 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory_matrix is
generic(ROWS: integer := 350; COLUMNS: integer := 350; CLK_DELAY_COUNT: integer := 9);
port(
x_write: in std_logic_vector(9 downto 0) := (others => '0');
y_write: in std_logic_vector(9 downto 0) := (others => '0');
write_data: in std_logic_vector(0 downto 0) := (others => '0');
write_enable: in std_logic := '0';
clk: in std_logic := '0';
enable: in std_logic := '0';
reset: in std_logic := '0';
x_read: in std_logic_vector(9 downto 0) := (others => '0');
y_read: in std_logic_vector(9 downto 0) := (others => '0');
read_data : out std_logic_vector(0 downto 0) := (others => '0')
);
end memory_matrix;
architecture memory_matrix_arq of memory_matrix is
constant MAX_ROWS : integer := 350;
constant MAX_COLUMNS : integer := 350;
constant RAM_SIZE : integer := 16384;
constant RAM_SIZE_1 : integer := 2 * RAM_SIZE;
constant RAM_SIZE_2 : integer := 3 * RAM_SIZE;
constant RAM_SIZE_3 : integer := 4 * RAM_SIZE;
constant RAM_SIZE_4 : integer := 5 * RAM_SIZE;
constant RAM_SIZE_5 : integer := 6 * RAM_SIZE;
constant RAM_SIZE_6 : integer := 7 * RAM_SIZE;
constant RAM_SIZE_7 : integer := 8 * RAM_SIZE;
constant default_ram_mask : unsigned(7 downto 0) := "00000001";
signal write_address : std_logic_vector(13 downto 0) := (others => '0');
signal read_address : std_logic_vector(13 downto 0) := (others => '0');
signal ram_write_mask : std_logic_vector(7 downto 0) := (others => '0');
signal ram_read_mask : std_logic_vector(7 downto 0) := (others => '0');
signal data : std_logic_vector(0 downto 0) := (others => '0');
signal rb : integer := 0;
component dual_port_ram is
port (
data_in : in std_logic_vector (0 downto 0) := (others => '0');
write_address : in std_logic_vector (13 downto 0) := (others => '0');
write_enable : in std_logic := '0';
ram_write_mask : in std_logic_vector(7 downto 0) := (others => '0');
enable : in std_logic := '0';
clk : in std_logic := '0';
reset : in std_logic := '0';
ram_read_mask : in std_logic_vector(7 downto 0) := (others => '0');
read_address : in std_logic_vector(13 downto 0) := (others => '0');
data_out : out std_logic_vector (0 downto 0) := (others => '0')
);
end component;
begin
dual_port_ram_0 : dual_port_ram
port map(
data_in => write_data,
write_address => write_address,
write_enable => write_enable,
ram_write_mask => ram_write_mask,
enable => enable,
reset => reset,
clk => clk,
ram_read_mask => ram_read_mask,
read_address => read_address,
data_out => data
);
write_process : process(enable, reset, write_enable, write_data, x_write, y_write)
variable x_write_int : integer := 0;
variable y_write_int : integer := 0;
variable tmp_write_ram : integer := 0;
variable write_bit_position : integer := 0;
variable write_pos_in_ram : integer := 0;
begin
x_write_int := to_integer(unsigned(x_write));
y_write_int := to_integer(unsigned(y_write));
--report "MATRIX-W " & integer'image(x_write_int) & " : " & integer'image(y_write_int) & "=>" & std_logic'image(write_data(0));
if(x_write_int <= COLUMNS and y_write_int <= ROWS) then
write_bit_position := x_write_int + y_write_int * ROWS;
case (write_bit_position) is
when 0 to RAM_SIZE-1 => tmp_write_ram := 0;
when RAM_SIZE to RAM_SIZE_1-1 => tmp_write_ram := 1;
when RAM_SIZE_1 to RAM_SIZE_2-1 => tmp_write_ram := 2;
when RAM_SIZE_2 to RAM_SIZE_3-1 => tmp_write_ram := 3;
when RAM_SIZE_3 to RAM_SIZE_4-1 => tmp_write_ram := 4;
when RAM_SIZE_4 to RAM_SIZE_5-1 => tmp_write_ram := 5;
when RAM_SIZE_5 to RAM_SIZE_6-1 => tmp_write_ram := 6;
when RAM_SIZE_6 to RAM_SIZE_7-1 => tmp_write_ram := 7;
when others => tmp_write_ram := 0;
end case;
write_pos_in_ram := write_bit_position - (tmp_write_ram * RAM_SIZE);
write_address <= std_logic_vector(to_unsigned(write_pos_in_ram, 14));
ram_write_mask <= std_logic_vector(shift_left(default_ram_mask, tmp_write_ram));
end if;
end process;
read_process : process(enable, reset, x_read, y_read, data)
variable x_read_int : integer := 0;
variable y_read_int : integer := 0;
variable tmp_read_ram : integer := 0;
variable read_bit_position : integer := 0;
variable read_pos_in_ram : integer := 0;
begin
x_read_int := to_integer(unsigned(x_read));
y_read_int := to_integer(unsigned(y_read));
--if(data(0) = '1') then
-- report "MATRIX-R " & integer'image(x_read_int) & " : " & integer'image(y_read_int) & "=>" & std_logic'image(data(0));
--end if;
if(ROWS > MAX_ROWS) then
report "MAX ROWS is: " & integer'image(MAX_ROWS) severity failure;
end if;
if(COLUMNS > MAX_COLUMNS) then
report "MAX COLUMNS is: " & integer'image(MAX_COLUMNS) severity failure;
end if;
if(x_read_int >= COLUMNS or y_read_int >= ROWS) then
read_data <= "0";
else
read_bit_position := x_read_int + y_read_int * COLUMNS;
rb <= read_bit_position;
case (read_bit_position) is
when 0 to RAM_SIZE-1 => tmp_read_ram := 0;
when RAM_SIZE to RAM_SIZE_1-1 => tmp_read_ram := 1;
when RAM_SIZE_1 to RAM_SIZE_2-1 => tmp_read_ram := 2;
when RAM_SIZE_2 to RAM_SIZE_3-1 => tmp_read_ram := 3;
when RAM_SIZE_3 to RAM_SIZE_4-1 => tmp_read_ram := 4;
when RAM_SIZE_4 to RAM_SIZE_5-1 => tmp_read_ram := 5;
when RAM_SIZE_5 to RAM_SIZE_6-1 => tmp_read_ram := 6;
when RAM_SIZE_6 to RAM_SIZE_7-1 => tmp_read_ram := 7;
when others => tmp_read_ram := 0;
end case;
read_pos_in_ram := read_bit_position - (tmp_read_ram * RAM_SIZE);
read_address <= std_logic_vector(to_unsigned(read_pos_in_ram, 14));
ram_read_mask <= std_logic_vector(shift_left(default_ram_mask, tmp_read_ram));
read_data <= data;
end if;
end process;
end architecture;
|
gpl-3.0
|
731c98d10e86bc34f9db5b649336ee31
| 0.56676 | 3.211394 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
VHDL_PLANB/PLL.vhd
| 1 | 18,049 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: PLL.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY PLL IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END PLL;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 5,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 5,
clk1_duty_cycle => 50,
clk1_multiply_by => 16,
clk1_phase_shift => "0",
clk2_divide_by => 5,
clk2_duty_cycle => 50,
clk2_multiply_by => 16,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=PLL",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "5"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "160.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "160.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "160.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "160.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
gpl-2.0
|
a20868ff8274d34fb5f2001080b9f95f
| 0.699485 | 3.290011 | false | false | false | false |
laurivosandi/hdl
|
zynq/src/bcd_segment_driver.vhd
| 1 | 754 |
library ieee;
use ieee.std_logic_1164.all;
entity bcd_segment_driver is
port (
bcd : in std_logic_vector(3 downto 0);
segments : out std_logic_vector(6 downto 0));
end;
architecture behavioral of bcd_segment_driver is
begin
segments <=
"1111110" when bcd = "0000" else -- 0
"0110000" when bcd = "0001" else -- 1
"1101101" when bcd = "0010" else -- 2
"1111001" when bcd = "0011" else -- 3
"0110011" when bcd = "0100" else -- 4
"1011011" when bcd = "0101" else -- 5
"1011111" when bcd = "0110" else -- 6
"1110000" when bcd = "0111" else -- 7
"1111111" when bcd = "1000" else -- 8
"1111011" when bcd = "1001" else -- 9
"0000000";
end;
|
mit
|
3a809592edce968baed1fa4006d23d7a
| 0.555703 | 3.523364 | false | false | false | false |
alainmarcel/Surelog
|
third_party/tests/YosysTests/verific/chparam/top.vhd
| 2 | 397 |
entity top_vhdl is
generic (WIDTH : integer := 1; INIT : bit := '1'; greeting : string(1 to 9) := "hello ");
port (clk : in bit; i : in bit_vector(WIDTH-1 downto 0); o : out bit := INIT);
end entity;
architecture rtl of top_vhdl is
begin
process
begin
report greeting;
--wait;
end process;
process (clk)
begin
if rising_edge(clk) then
o <= xor i;
end if;
end process;
end rtl;
|
apache-2.0
|
314902f0c1e9d2dc3f522fafcd810069
| 0.639798 | 2.835714 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-LuGus/TP2-Voltimetro/vga_controller.vhd
| 1 | 6,861 |
--------------------------------------------------------------------------
-- Modulo: Controlador VGA
-- Descripci?n:
-- Autor: Sistemas Digitales (66.17)
-- Universidad de Buenos Aires - Facultad de Ingenier?a
-- www.campus.fi.uba.ar
-- Fecha: 16/04/13
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity vga_ctrl is
port (
mclk: in std_logic;
red_i: in std_logic;
grn_i: in std_logic;
blu_i: in std_logic;
hs: out std_logic;
vs: out std_logic;
red_o: out std_logic_vector(2 downto 0);
grn_o: out std_logic_vector(2 downto 0);
blu_o: out std_logic_vector(1 downto 0);
--red_o: out std_logic;
--grn_o: out std_logic;
--blu_o: out std_logic;
pixel_row: out std_logic_vector(9 downto 0);
pixel_col: out std_logic_vector(9 downto 0)
);
attribute loc: string;
-- Mapeo de pines para el kit Nexys 2 (spartan 3E)
-- attribute loc of mclk: signal is "B8";
-- attribute loc of red_i: signal is "K18";
-- attribute loc of grn_i: signal is "H18";
-- attribute loc of blu_i: signal is "G18";
-- attribute loc of hs: signal is "T4";
-- attribute loc of vs: signal is "U3";
-- attribute loc of red_o: signal is "R8 T8 R9";
-- attribute loc of grn_o: signal is "P6 P8 N8";
-- attribute loc of blu_o: signal is "U4 U5";
-- Mapeo de pines para el kit spartan 3E
-- attribute loc of mclk: signal is "C9";
-- attribute loc of red_i: signal is "H18";
-- attribute loc of grn_i: signal is "L14";
-- attribute loc of blu_i: signal is "L13";
-- attribute loc of hs: signal is "F15";
-- attribute loc of vs: signal is "F14";
-- attribute loc of red_o: signal is "H14";
-- attribute loc of grn_o: signal is "H15";
-- attribute loc of blu_o: signal is "G15";
-- Mapeo de pines para el kit spartan 3
-- attribute loc of mclk: signal is "T9";
-- attribute loc of red_in: signal is "K13";
-- attribute loc of grn_in: signal is "K14";
-- attribute loc of blu_in: signal is "J13";
-- attribute loc of hs: signal is "R9";
-- attribute loc of vs: signal is "T10";
-- attribute loc of red_out: signal is "R12";
-- attribute loc of grn_out: signal is "T12";
-- attribute loc of blu_out: signal is "R11";
end vga_ctrl;
architecture vga_ctrl_arq of vga_ctrl is
-- Numero de pixeles en una linea horizontal (800)
constant hpixels: unsigned(9 downto 0) := "1100100000";
-- Numero de lineas horizontales en el display (521)
constant vlines: unsigned(9 downto 0) := "1000001001";
constant hbp: unsigned(9 downto 0) := "0010010000"; -- Back porch horizontal (144)
constant hfp: unsigned(9 downto 0) := "1100010000"; -- Front porch horizontal (784)
constant vbp: unsigned(9 downto 0) := "0000011111"; -- Back porch vertical (31)
constant vfp: unsigned(9 downto 0) := "0111111111"; -- Front porch vertical (511)
-- Contadores (horizontal y vertical)
signal hc, vc: unsigned(9 downto 0);
-- Flag para obtener una habilitaci?n cada dos ciclos de clock
signal clkdiv_flag: std_logic;
-- Senal para habilitar la visualizaci?n de datos
signal vidon: std_logic;
-- Senal para habilitar el contador vertical
signal vsenable: std_logic;
begin
-- Divisi?n de la frecuencia del reloj
process(mclk)
begin
if rising_edge(mclk) then
clkdiv_flag <= not clkdiv_flag;
end if;
end process;
-- Contador horizontal
process(mclk)
begin
if rising_edge(mclk) then
if clkdiv_flag = '1' then
if hc = hpixels then
hc <= (others => '0'); -- El cont horiz se resetea cuando alcanza la cuenta m?xima de pixeles
vsenable <= '1'; -- Habilitaci?n del cont vert
else
hc <= hc + 1; -- Incremento del cont horiz
vsenable <= '0'; -- El cont vert se mantiene deshabilitado
end if;
end if;
end if;
end process;
-- Contador vertical
process(mclk)
begin
if rising_edge(mclk) then
if clkdiv_flag = '1' then -- Flag que habilita la operaci?n una vez cada dos ciclos (25 MHz)
if vsenable = '1' then -- Cuando el cont horiz llega al m?ximo de su cuenta habilita al cont vert
if vc = vlines then
vc <= (others => '0'); -- El cont vert se resetea cuando alcanza la cantidad maxima de lineas
else
vc <= vc + 1; -- Incremento del cont vert
end if;
end if;
end if;
end if;
end process;
-- hs <= '1' when (hc(9 downto 7) = "000") else '0';
-- vs <= '1' when (vc(9 downto 1) = "000000000") else '0';
hs <= '1' when (hc < "0001100001") else '0'; -- Generaci?n de la se?al de sincronismo horizontal
vs <= '1' when (vc < "0000000011") else '0'; -- Generaci?n de la se?al de sincronismo vertical
pixel_col <= std_logic_vector(hc - 144) when (vidon = '1') else std_logic_vector(hc);
pixel_row <= std_logic_vector(vc - 31) when (vidon = '1') else std_logic_vector(vc);
-- Habilitaci?n de la salida de datos por el display cuando se encuentra entre los porches
vidon <= '1' when (((hc < hfp) and (hc > hbp)) and ((vc < vfp) and (vc > vbp))) else '0';
-- Ejemplos
-- Los colores est?n comandados por los switches de entrada del kit
-- Dibuja un cuadrado rojo
-- red_o <= (others => '1') when ((hc(9 downto 6) = "0111") and vc(9 downto 6) = "0100" and red_i = '1' and vidon ='1') else (others => '0');
-- Dibuja una linea roja (valor espec?fico del contador horizontal
-- red_o <= '1' when (hc = "1010101100" and red_i = '1' and vidon ='1') else '0';
-- Dibuja una linea verde (valor espec?fico del contador horizontal)
-- grn_o <= (others => '1') when (hc = "0100000100" and grn_i = '1' and vidon ='1') else (others => '0');
-- Dibuja una linea azul (valor espec?fico del contador vertical)
-- blu_o <= (others => '1') when (vc = "0100100001" and blu_i = '1' and vidon ='1') else (others => '0');
-- Pinta la pantalla del color formado por la combinaci?n de las entradas red_i, grn_i y blu_i (switches)
-- red_o <= "111" when (red_i = '1' and vidon = '1') else "000";
-- grn_o <= "111" when (grn_i = '1' and vidon = '1') else "000";
-- blu_o <= "11" when (blu_i = '1' and vidon = '1') else "00";
red_o <= "111" when (red_i = '1' and vidon = '1') else "000";
grn_o <= "111" when (grn_i = '1' and vidon = '1') else "000";
blu_o <= "11" when (blu_i = '1' and vidon = '1') else "00";
end vga_ctrl_arq;
|
gpl-3.0
|
0d84ee211f9eb60f62abbab71484db56
| 0.571928 | 3.319303 | false | false | false | false |
ruygargar/LCSE_lab
|
doc/PIC/PIC_pkg.vhd
| 1 | 5,060 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
PACKAGE PIC_pkg IS
-------------------------------------------------------------------------------
-- Types for the RAM memory
-------------------------------------------------------------------------------
SUBTYPE item_array8_ram IS std_logic_vector (7 downto 0);
TYPE array8_ram IS array (integer range <>) of item_array8_ram;
-------------------------------------------------------------------------------
-- Useful constants for addressing purposes
-------------------------------------------------------------------------------
constant DMA_RX_BUFFER_MSB : std_logic_vector(7 downto 0) := X"00";
constant DMA_RX_BUFFER_MID : std_logic_vector(7 downto 0) := X"01";
constant DMA_RX_BUFFER_LSB : std_logic_vector(7 downto 0) := X"02";
constant NEW_INST : std_logic_vector(7 downto 0) := X"03";
constant DMA_TX_BUFFER_MSB : std_logic_vector(7 downto 0) := X"04";
constant DMA_TX_BUFFER_LSB : std_logic_vector(7 downto 0) := X"05";
constant SWITCH_BASE : std_logic_vector(7 downto 0) := X"10";
constant LEVER_BASE : std_logic_vector(7 downto 0) := X"20";
constant CAL_OP : std_logic_vector(7 downto 0) := X"30";
constant T_STAT : std_logic_vector(7 downto 0) := X"31";
constant GP_RAM_BASE : std_logic_vector(7 downto 0) := X"40";
-------------------------------------------------------------------------------
-- Constants to define Type 1 instructions (ALU)
-------------------------------------------------------------------------------
constant TYPE_1 : std_logic_vector(1 downto 0) := "00";
constant ALU_ADD : std_logic_vector(5 downto 0) := "000000";
constant ALU_SUB : std_logic_vector(5 downto 0) := "000001";
constant ALU_SHIFTL : std_logic_vector(5 downto 0) := "000010";
constant ALU_SHIFTR : std_logic_vector(5 downto 0) := "000011";
constant ALU_AND : std_logic_vector(5 downto 0) := "000100";
constant ALU_OR : std_logic_vector(5 downto 0) := "000101";
constant ALU_XOR : std_logic_vector(5 downto 0) := "000110";
constant ALU_CMPE : std_logic_vector(5 downto 0) := "000111";
constant ALU_CMPG : std_logic_vector(5 downto 0) := "001000";
constant ALU_CMPL : std_logic_vector(5 downto 0) := "001001";
constant ALU_ASCII2BIN : std_logic_vector(5 downto 0) := "001010";
constant ALU_BIN2ASCII : std_logic_vector(5 downto 0) := "001011";
-------------------------------------------------------------------------------
-- Constants to define Type 2 instructions (JUMP)
-------------------------------------------------------------------------------
constant TYPE_2 : std_logic_vector(1 downto 0) := "01";
constant JMP_UNCOND : std_logic_vector(5 downto 0) := "00" & X"0";
constant JMP_COND : std_logic_vector(5 downto 0) := "00" & X"1";
-------------------------------------------------------------------------------
-- Constants to define Type 3 instructions (LOAD & STORE)
-------------------------------------------------------------------------------
constant TYPE_3 : std_logic_vector(1 downto 0) := "10";
-- instruction
constant LD : std_logic := '0';
constant WR : std_logic := '1';
-- source
constant SRC_ACC : std_logic_vector(1 downto 0) := "00";
constant SRC_CONSTANT : std_logic_vector(1 downto 0) := "01";
constant SRC_MEM : std_logic_vector(1 downto 0) := "10";
constant SRC_INDXD_MEM : std_logic_vector(1 downto 0) := "11";
-- destination
constant DST_ACC : std_logic_vector(2 downto 0) := "000";
constant DST_A : std_logic_vector(2 downto 0) := "001";
constant DST_B : std_logic_vector(2 downto 0) := "010";
constant DST_INDX : std_logic_vector(2 downto 0) := "011";
constant DST_MEM : std_logic_vector(2 downto 0) := "100";
constant DST_INDXD_MEM : std_logic_vector(2 downto 0) := "101";
-------------------------------------------------------------------------------
-- Constants to define Type 4 instructions (SEND)
-------------------------------------------------------------------------------
constant TYPE_4 : std_logic_vector(1 downto 0) := "11";
-------------------------------------------------------------------------------
-- Type containing the ALU instruction set
-------------------------------------------------------------------------------
TYPE alu_op IS (
nop, -- no operation
op_lda, op_ldb, op_ldacc, op_ldid, -- external value load
op_mvacc2id, op_mvacc2a, op_mvacc2b, -- internal load
op_add, op_sub, op_shiftl, op_shiftr, -- arithmetic operations
op_and, op_or, op_xor, -- logic operations
op_cmpe, op_cmpl, op_cmpg, -- compare operations
op_ascii2bin, op_bin2ascii, -- conversion operations
op_oeacc); -- output enable
END PIC_pkg;
PACKAGE BODY PIC_pkg IS
END PIC_pkg;
|
gpl-3.0
|
4c430a670d0e5bfa0844b6709fea215b
| 0.473518 | 4.150943 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/ram_double_multiple_access.vhd
| 1 | 5,296 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: RAM_double_multiple_access
-- Module Name: RAM_double_multiple_access
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavioral of multiple memory RAM that shares the same content.
-- It is useful when you want to access more than one location at the same time, and
-- the locations for each access can be anywhere in the memory, where in banks in most
-- time is one address after another.
-- It can be seen as one single with multiple I/O operating at the same time.
-- In this double version it is possible to read and write at same cycle.
--
-- The circuits parameters
--
-- number_of_memories :
--
-- The total number of memories or the total number of I/O's applied.
--
-- ram_address_size :
--
-- Address size of the RAM used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word of the RAM.
--
-- file_ram_word_size :
--
-- The size of the word used in the file to be loaded on the RAM.(ARCH: FILE_LOAD)
--
-- load_file_name :
--
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
--
-- The name of the file to be used to dump the memory.(ARCH: FILE_LOAD)
--
-- Dependencies:
-- VHDL-93
--
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
entity ram_double_multiple_access is
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR (((ram_address_size)*(number_of_memories) - 1) downto 0);
address_b : in STD_LOGIC_VECTOR (((ram_address_size)*(number_of_memories) - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end ram_double_multiple_access;
architecture simple of ram_double_multiple_access is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
for I in ramtype'range loop
memory_ram(I) <= rst_value;
end loop;
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw_a = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address_a(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))) <= data_in_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
if rw_b = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address_b(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))) <= data_in_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
for index in 0 to (number_of_memories - 1) loop
data_out_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_a(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index)))));
data_out_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_b(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index)))));
end loop;
end if;
end process;
end simple;
|
bsd-2-clause
|
8ba8b4b689043401dce205bbed39197e
| 0.563444 | 3.488801 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/controller_solving_key_equation_1.vhd
| 1 | 43,311 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Solving_Key_Equation_1
-- Module Name: Controller_Solving_Key_Equation_1
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 2nd step in Goppa Code Decoding.
--
-- This is a state machine circuit that controls solving_key_equation_1.
-- This state machine have 3 phases: first phase variable initialization,
-- second computation of polynomial sigma, third step writing the polynomial sigma
-- on a specific memory position.
--
-- This is the first circuit version. It is a non pipeline version of the algorithm,
-- each coefficient takes more than 1 cycle to be computed.
-- A more optimized version, still non pipeline was made called solving_key_equation_1_v2
-- This improved version, has new address resolution logic and internal degree counters.
--
-- Dependencies:
--
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_solving_key_equation_1 is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
FB_equal_zero : in STD_LOGIC;
i_equal_zero : in STD_LOGIC;
i_minus_j_less_than_zero : in STD_LOGIC;
degree_G_less_equal_final_degree : in STD_LOGIC;
degree_F_less_than_degree_G : in STD_LOGIC;
degree_B_equal_degree_C_plus_j : in STD_LOGIC;
degree_B_less_than_degree_C_plus_j : in STD_LOGIC;
reg_looking_degree_q : in STD_LOGIC_VECTOR(0 downto 0);
key_equation_found : out STD_LOGIC;
signal_inv : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
sel_base_mul : out STD_LOGIC;
reg_h_ce : out STD_LOGIC;
ctr_i_ce : out STD_LOGIC;
ctr_i_rst : out STD_LOGIC;
sel_ctr_i_rst_value : out STD_LOGIC_VECTOR(1 downto 0);
reg_j_ce : out STD_LOGIC;
reg_FB_ce : out STD_LOGIC;
reg_FB_rst : out STD_LOGIC;
sel_reg_FB : out STD_LOGIC;
reg_GC_ce : out STD_LOGIC;
reg_GC_rst : out STD_LOGIC;
sel_reg_GC : out STD_LOGIC;
reg_degree_F_ce : out STD_LOGIC;
reg_degree_F_rst : out STD_LOGIC;
sel_reg_degree_F : out STD_LOGIC;
reg_degree_G_ce : out STD_LOGIC;
reg_degree_G_rst : out STD_LOGIC;
reg_degree_B_ce : out STD_LOGIC;
reg_degree_B_rst : out STD_LOGIC;
sel_reg_degree_B : out STD_LOGIC_VECTOR(1 downto 0);
reg_degree_C_ce : out STD_LOGIC;
reg_degree_C_rst : out STD_LOGIC;
reg_looking_degree_d : out STD_LOGIC_VECTOR(0 downto 0);
reg_looking_degree_ce : out STD_LOGIC;
reg_swap_ce : out STD_LOGIC;
reg_swap_rst : out STD_LOGIC;
sel_int_new_value_FB : out STD_LOGIC;
sel_address_FB : out STD_LOGIC;
sel_address_GC : out STD_LOGIC_VECTOR(1 downto 0);
BC_calculation : out STD_LOGIC;
enable_external_swap : out STD_LOGIC
);
end controller_solving_key_equation_1;
architecture Behavioral of controller_solving_key_equation_1 is
type State is (reset, load_counter, store_G2t, prepare_load_F_store_G, load_F_store_G, wait_F, last_load_F_store_G, last_wait_F, store_B_C, last_store_B_C, swap_F_G_B_C, load_j, load_first_G_first_F, send_inv, wait_inv, load_h, prepare_load_F_G, load_F_G, store_F, last_load_F_G, last_store_F, prepare_i, prepare_load_B_C, load_B_C, store_B, last_load_B_C, last_store_B, prepare_final_swap, prepare_load_sigma, load_sigma, last_load_sigma, store_sigma, last_store_sigma, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process(actual_state, ready_inv, FB_equal_zero, i_equal_zero, i_minus_j_less_than_zero, degree_G_less_equal_final_degree, degree_F_less_than_degree_G, degree_B_equal_degree_C_plus_j, degree_B_less_than_degree_C_plus_j, reg_looking_degree_q)
begin
case (actual_state) is
when reset =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '1';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '1';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '0';
enable_external_swap <= '1';
when load_counter =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= "01";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
sel_reg_GC <= '1';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '1';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '1';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "01";
BC_calculation <= '0';
enable_external_swap <= '1';
when store_G2t =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= "01";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '1';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '1';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "1";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "01";
BC_calculation <= '0';
enable_external_swap <= '1';
when prepare_load_F_store_G =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '0';
enable_external_swap <= '1';
when load_F_store_G | last_load_F_store_G =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '0';
enable_external_swap <= '1';
when wait_F =>
if(reg_looking_degree_q(0) = '1' and FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '1';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '0';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '0';
enable_external_swap <= '1';
end if;
when last_wait_F =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '0';
enable_external_swap <= '1';
when store_B_C =>
if(i_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '1';
enable_external_swap <= '1';
end if;
when last_store_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '1';
enable_external_swap <= '1';
when swap_F_G_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '1';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '1';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '1';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '1';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '1';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '0';
enable_external_swap <= '1';
when load_j =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= "11";
reg_j_ce <= '1';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '1';
sel_address_GC <= "01";
BC_calculation <= '0';
enable_external_swap <= '1';
when load_first_G_first_F =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "01";
BC_calculation <= '0';
enable_external_swap <= '1';
when send_inv =>
key_equation_found <= '0';
signal_inv <= '1';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '0';
enable_external_swap <= '1';
when wait_inv =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '1';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '0';
enable_external_swap <= '1';
when load_h =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '1';
reg_h_ce <= '1';
ctr_i_ce <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "1";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "10";
BC_calculation <= '0';
enable_external_swap <= '1';
when prepare_load_F_G =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '1';
sel_address_FB <= '0';
sel_address_GC <= "10";
BC_calculation <= '0';
enable_external_swap <= '1';
when load_F_G | last_load_F_G =>
if(i_minus_j_less_than_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '1';
sel_address_FB <= '0';
sel_address_GC <= "10";
BC_calculation <= '0';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '1';
sel_address_FB <= '0';
sel_address_GC <= "10";
BC_calculation <= '0';
enable_external_swap <= '1';
end if;
when store_F =>
if(reg_looking_degree_q(0) = '1' and FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '1';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '1';
sel_address_FB <= '0';
sel_address_GC <= "10";
BC_calculation <= '0';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '1';
sel_address_FB <= '0';
sel_address_GC <= "10";
BC_calculation <= '0';
enable_external_swap <= '1';
end if;
when last_store_F =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '1';
sel_address_FB <= '0';
sel_address_GC <= "10";
BC_calculation <= '0';
enable_external_swap <= '1';
when prepare_i =>
if(degree_B_equal_degree_C_plus_j = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= "10";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "1";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '1';
sel_address_FB <= '0';
sel_address_GC <= "10";
BC_calculation <= '1';
enable_external_swap <= '1';
elsif(degree_B_less_than_degree_C_plus_j = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= "10";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '1';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "10";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '1';
sel_address_FB <= '0';
sel_address_GC <= "10";
BC_calculation <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= "10";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '1';
sel_address_FB <= '0';
sel_address_GC <= "10";
BC_calculation <= '1';
enable_external_swap <= '1';
end if;
when prepare_load_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '1';
sel_address_FB <= '0';
sel_address_GC <= "10";
BC_calculation <= '1';
enable_external_swap <= '1';
when load_B_C | last_load_B_C =>
if(i_minus_j_less_than_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '1';
sel_address_FB <= '0';
sel_address_GC <= "10";
BC_calculation <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '1';
sel_address_FB <= '0';
sel_address_GC <= "10";
BC_calculation <= '1';
enable_external_swap <= '1';
end if;
when store_B =>
if(reg_looking_degree_q(0) = '1' and FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '1';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "01";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '1';
sel_address_FB <= '0';
sel_address_GC <= "10";
BC_calculation <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '1';
sel_address_FB <= '0';
sel_address_GC <= "10";
BC_calculation <= '1';
enable_external_swap <= '1';
end if;
when last_store_B =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '1';
sel_address_FB <= '0';
sel_address_GC <= "10";
BC_calculation <= '1';
enable_external_swap <= '1';
when prepare_final_swap =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '0';
enable_external_swap <= '1';
when prepare_load_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '1';
enable_external_swap <= '1';
when load_sigma | last_load_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '1';
enable_external_swap <= '1';
when store_sigma | last_store_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '0';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '0';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '0';
enable_external_swap <= '0';
when final =>
key_equation_found <= '1';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '1';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '1';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '0';
enable_external_swap <= '0';
when others =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= "00";
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
sel_reg_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
sel_reg_GC <= '0';
reg_degree_F_ce <= '0';
reg_degree_F_rst <= '1';
sel_reg_degree_F <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
reg_degree_B_ce <= '0';
reg_degree_B_rst <= '1';
sel_reg_degree_B <= "00";
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_int_new_value_FB <= '0';
sel_address_FB <= '0';
sel_address_GC <= "00";
BC_calculation <= '0';
enable_external_swap <= '0';
end case;
end process;
New_State : process(actual_state, ready_inv, FB_equal_zero, i_equal_zero, i_minus_j_less_than_zero, degree_G_less_equal_final_degree, degree_F_less_than_degree_G, degree_B_equal_degree_C_plus_j, degree_B_less_than_degree_C_plus_j, reg_looking_degree_q)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= store_G2t;
when store_G2t =>
next_state <= prepare_load_F_store_G;
when prepare_load_F_store_G =>
if(i_equal_zero = '1') then
next_state <= last_load_F_store_G;
else
next_state <= load_F_store_G;
end if;
when load_F_store_G =>
next_state <= wait_F;
when wait_F =>
next_state <= prepare_load_F_store_G;
when last_load_F_store_G =>
next_state <= last_wait_F;
when last_wait_F =>
next_state <= store_B_C;
when store_B_C =>
if(i_equal_zero = '1') then
next_state <= last_store_B_C;
else
next_state <= store_B_C;
end if;
when last_store_B_C =>
next_state <= swap_F_G_B_C;
when swap_F_G_B_C =>
next_state <= load_j;
when load_j =>
next_state <= load_first_G_first_F;
when load_first_G_first_F =>
next_state <= send_inv;
when send_inv =>
next_state <= wait_inv;
when wait_inv =>
if(ready_inv = '1') then
next_state <= load_h;
else
next_state <= wait_inv;
end if;
when load_h =>
next_state <= prepare_load_F_G;
when prepare_load_F_G =>
if(i_equal_zero = '1') then
next_state <= last_load_F_G;
else
next_state <= load_F_G;
end if;
when load_F_G =>
next_state <= store_F;
when store_F =>
next_state <= prepare_load_F_G;
when last_load_F_G =>
next_state <= last_store_F;
when last_store_F =>
next_state <= prepare_i;
when prepare_i =>
next_state <= prepare_load_B_C;
when prepare_load_B_C =>
if(i_equal_zero = '1') then
next_state <= last_load_B_C;
else
next_state <= load_B_C;
end if;
when load_B_C =>
next_state <= store_B;
when store_B =>
next_state <= prepare_load_B_C;
when last_load_B_C =>
next_state <= last_store_B;
when last_store_B =>
if(degree_G_less_equal_final_degree = '1') then
next_state <= prepare_final_swap;
elsif(degree_F_less_than_degree_G = '1') then
next_state <= swap_F_G_B_C;
else
next_state <= load_j;
end if;
when prepare_final_swap =>
next_state <= prepare_load_sigma;
when prepare_load_sigma =>
if(i_equal_zero = '1') then
next_state <= last_load_sigma;
else
next_state <= load_sigma;
end if;
when load_sigma =>
next_state <= store_sigma;
when last_load_sigma =>
next_state <= last_store_sigma;
when store_sigma =>
next_state <= prepare_load_sigma;
when last_store_sigma =>
next_state <= final;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
6697ac7006b5263b3e0b5323fbf4f907
| 0.506015 | 2.302552 | false | false | false | false |
andrecp/myhdl_simple_uart
|
generated_files/serial_tx.vhd
| 1 | 3,557 |
-- File: serial_tx.vhd
-- Generated by MyHDL 0.8
-- Date: Thu Aug 21 10:54:44 2014
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity serial_tx is
port (
sysclk: in std_logic;
reset_n: in std_logic;
start_i: in std_logic;
data_i: in unsigned(7 downto 0);
baud_rate_tick_i: in std_logic;
transmit_o: out std_logic
);
end entity serial_tx;
-- Serial
-- This module implements a transmitter serial interface
--
-- Ports:
-- -----
-- sysclk: sysclk input
-- reset_n: reset input
-- baud_rate_tick_i: the baud rate
-- start_i: start sending data
-- data_i: the data to send
-- n_stop_bits_i: number of stop bits
-- transmit_o: data output
-- -----
architecture MyHDL of serial_tx is
constant n_stop_bits_i: integer := 2;
constant END_OF_BYTE: integer := 7;
type t_enum_t_State_1 is (
ST_WAIT_START,
ST_SEND_START_BIT,
ST_SEND_DATA,
ST_SEND_STOP_BIT
);
signal transmit_reg: std_logic;
signal count_8_bits: unsigned(2 downto 0);
signal count_8_bits_reg: unsigned(2 downto 0);
signal state: t_enum_t_State_1;
signal transmit: std_logic;
signal count_stop_bits_reg: unsigned(2 downto 0);
signal count_stop_bits: unsigned(2 downto 0);
signal state_reg: t_enum_t_State_1;
begin
transmit_o <= transmit_reg;
SERIAL_TX_SEQUENTIAL_PROCESS: process (sysclk, reset_n) is
begin
if (reset_n = '0') then
count_8_bits_reg <= to_unsigned(0, 3);
count_stop_bits_reg <= to_unsigned(0, 3);
transmit_reg <= '0';
state_reg <= ST_WAIT_START;
elsif rising_edge(sysclk) then
state_reg <= state;
transmit_reg <= transmit;
count_8_bits_reg <= count_8_bits;
count_stop_bits_reg <= count_stop_bits;
end if;
end process SERIAL_TX_SEQUENTIAL_PROCESS;
SERIAL_TX_COMBINATIONAL_PROCESS: process (transmit_reg, start_i, count_8_bits_reg, data_i, baud_rate_tick_i, count_stop_bits_reg, state_reg) is
begin
state <= state_reg;
transmit <= transmit_reg;
count_8_bits <= count_8_bits_reg;
count_stop_bits <= count_stop_bits_reg;
case state_reg is
when ST_WAIT_START =>
transmit <= '1';
if (start_i = '1') then
state <= ST_SEND_START_BIT;
end if;
when ST_SEND_START_BIT =>
transmit <= '0';
if (baud_rate_tick_i = '1') then
state <= ST_SEND_DATA;
end if;
when ST_SEND_DATA =>
transmit <= data_i(to_integer(count_8_bits_reg));
if (baud_rate_tick_i = '1') then
if (count_8_bits_reg = END_OF_BYTE) then
count_8_bits <= to_unsigned(0, 3);
state <= ST_SEND_STOP_BIT;
else
count_8_bits <= (count_8_bits_reg + 1);
state <= ST_SEND_DATA;
end if;
end if;
when ST_SEND_STOP_BIT =>
transmit <= '1';
if (baud_rate_tick_i = '1') then
if (signed(resize(count_stop_bits_reg, 4)) = (n_stop_bits_i - 1)) then
count_stop_bits <= to_unsigned(0, 3);
state <= ST_WAIT_START;
else
count_stop_bits <= (count_stop_bits_reg + 1);
end if;
end if;
when others =>
assert False report "End of Simulation" severity Failure;
end case;
end process SERIAL_TX_COMBINATIONAL_PROCESS;
end architecture MyHDL;
|
mit
|
09d6a1c6e7fda3dd49ff9c7f04f02980
| 0.569862 | 3.315005 | false | false | false | false |
hitomi2500/wasca
|
obsolete/fpga_firmware_V2/ip_repo/ABus2AXI4Lite/hdl/ABus2AXI4Lite_Filesys_regs_AXI.vhd
| 2 | 17,439 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ABus2AXI4Lite_Filesys_regs_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_FILESYS_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_FILESYS_AXI_ADDR_WIDTH : integer := 12
);
port (
-- Users to add ports here
abus_we : in std_logic_vector(1 downto 0);
abus_we_cmd : in std_logic_vector(1 downto 0);
abus_we_data : in std_logic_vector(1 downto 0);
abus_we_regs : in std_logic_vector(1 downto 0);
abus_addr : in std_logic_vector(12 downto 0);
abus_data_in : in std_logic_vector(15 downto 0);
abus_data_out : out std_logic_vector(15 downto 0);
abus_data_out_data : out std_logic_vector(15 downto 0);
abus_data_out_cmd : out std_logic_vector(15 downto 0);
abus_data_out_regs : out std_logic_vector(15 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
FILESYS_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
FILESYS_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
FILESYS_AXI_AWADDR : in std_logic_vector(C_FILESYS_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
FILESYS_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
FILESYS_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
FILESYS_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
FILESYS_AXI_WDATA : in std_logic_vector(C_FILESYS_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
FILESYS_AXI_WSTRB : in std_logic_vector((C_FILESYS_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
FILESYS_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
FILESYS_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
FILESYS_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
FILESYS_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
FILESYS_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
FILESYS_AXI_ARADDR : in std_logic_vector(C_FILESYS_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
FILESYS_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
FILESYS_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
FILESYS_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
FILESYS_AXI_RDATA : out std_logic_vector(C_FILESYS_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
FILESYS_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
FILESYS_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
FILESYS_AXI_RREADY : in std_logic
);
end ABus2AXI4Lite_Filesys_regs_AXI;
architecture arch_imp of ABus2AXI4Lite_Filesys_regs_AXI is
component buffer_mem IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END component;
-- AXI4LITE signals
signal axi_addr : std_logic_vector(C_FILESYS_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_FILESYS_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_FILESYS_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_FILESYS_AXI_DATA_WIDTH/32)+ 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 8
signal slv_reg0 :std_logic_vector(C_FILESYS_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_FILESYS_AXI_DATA_WIDTH-1 downto 0);
signal slv_rden : std_logic;
signal slv_wren : std_logic;
signal reg_data_out :std_logic_vector(C_FILESYS_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
signal axi_data_out_data :std_logic_vector(C_FILESYS_AXI_DATA_WIDTH-1 downto 0);
signal axi_data_out_cmd :std_logic_vector(C_FILESYS_AXI_DATA_WIDTH-1 downto 0);
-- signal command_buffer_in :std_logic_vector(C_FILESYS_AXI_DATA_WIDTH-1 downto 0);
--signal command_buffer_addr :std_logic_vector(9 downto 0);
--signal data_buffer_addr :std_logic_vector(9 downto 0);
signal axi_we_data :std_logic_vector((C_FILESYS_AXI_DATA_WIDTH/8)-1 downto 0);
signal axi_we_cmd :std_logic_vector((C_FILESYS_AXI_DATA_WIDTH/8)-1 downto 0);
begin
-- I/O Connections assignments
FILESYS_AXI_AWREADY <= axi_awready;
FILESYS_AXI_WREADY <= axi_wready;
FILESYS_AXI_BRESP <= axi_bresp;
FILESYS_AXI_BVALID <= axi_bvalid;
FILESYS_AXI_ARREADY <= axi_arready;
FILESYS_AXI_RDATA <= axi_rdata;
FILESYS_AXI_RRESP <= axi_rresp;
FILESYS_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (FILESYS_AXI_ACLK)
begin
if rising_edge(FILESYS_AXI_ACLK) then
if FILESYS_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and FILESYS_AXI_AWVALID = '1' and FILESYS_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (FILESYS_AXI_ACLK)
begin
if rising_edge(FILESYS_AXI_ACLK) then
if FILESYS_AXI_ARESETN = '0' then
axi_addr <= (others => '0');
else
if (axi_awready = '0' and FILESYS_AXI_AWVALID = '1' and FILESYS_AXI_WVALID = '1') then
-- Write Address latching
axi_addr <= FILESYS_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (FILESYS_AXI_ACLK)
begin
if rising_edge(FILESYS_AXI_ACLK) then
if FILESYS_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and FILESYS_AXI_WVALID = '1' and FILESYS_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_wren <= axi_wready and FILESYS_AXI_WVALID and axi_awready and FILESYS_AXI_AWVALID ;
process (FILESYS_AXI_ACLK)
variable reg_addr :std_logic_vector(2 downto 0);
begin
if rising_edge(FILESYS_AXI_ACLK) then
if FILESYS_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
else
reg_addr := axi_addr(ADDR_LSB + 2 downto ADDR_LSB);
axi_we_data <= (others=>'0');
axi_we_cmd <= (others=>'0');
if (slv_wren = '1') then
if axi_addr(C_FILESYS_AXI_ADDR_WIDTH-1) = '0' then --data buffer
axi_we_data <= FILESYS_AXI_WSTRB;
elsif axi_addr(C_FILESYS_AXI_ADDR_WIDTH-1 downto C_FILESYS_AXI_ADDR_WIDTH-9) = X"FF" then --registers
case reg_addr is
--only reg0 is writable
when b"000" =>
for byte_index in 0 to (C_FILESYS_AXI_DATA_WIDTH/8-1) loop
if ( FILESYS_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= FILESYS_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
else
axi_we_cmd <= FILESYS_AXI_WSTRB;
end if;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (FILESYS_AXI_ACLK)
begin
if rising_edge(FILESYS_AXI_ACLK) then
if FILESYS_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and FILESYS_AXI_AWVALID = '1' and axi_wready = '1' and FILESYS_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (FILESYS_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (FILESYS_AXI_ACLK)
begin
if rising_edge(FILESYS_AXI_ACLK) then
if FILESYS_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_addr <= (others => '1');
else
if (axi_arready = '0' and FILESYS_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_addr <= FILESYS_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (FILESYS_AXI_ACLK)
begin
if rising_edge(FILESYS_AXI_ACLK) then
if FILESYS_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and FILESYS_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and FILESYS_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_rden <= axi_arready and FILESYS_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, axi_addr, FILESYS_AXI_ARESETN, slv_rden)
variable reg_addr :std_logic_vector(2 downto 0);
begin
-- Address decoding for reading registers
reg_addr := axi_addr(ADDR_LSB + 2 downto ADDR_LSB);
if axi_addr(C_FILESYS_AXI_ADDR_WIDTH-1) = '0' then--data buffer
reg_data_out <= axi_data_out_data;
elsif axi_addr(C_FILESYS_AXI_ADDR_WIDTH-1 downto C_FILESYS_AXI_ADDR_WIDTH-9) = X"FF" then--registers
case reg_addr is
when b"000" =>
reg_data_out <= slv_reg0;
when b"001" =>
reg_data_out <= slv_reg1;
when others =>
reg_data_out <= (others => '0');
end case;
else --command buffer
reg_data_out <= axi_data_out_cmd;
end if;
end process;
axi_we_cmd <= FILESYS_AXI_WSTRB when slv_wren = '1' and axi_addr(C_FILESYS_AXI_ADDR_WIDTH-1) = '1'
and axi_addr(C_FILESYS_AXI_ADDR_WIDTH-1 downto C_FILESYS_AXI_ADDR_WIDTH-9) /= X"FF"
else (others => '0');
-- Output register or memory read data
process( FILESYS_AXI_ACLK ) is
begin
if (rising_edge (FILESYS_AXI_ACLK)) then
if ( FILESYS_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
--command_buffer_addr <= axi_addr(ADDR_LSB+9 downto ADDR_LSB);
command_buffer: buffer_mem
PORT map(
--ABus port
clka => FILESYS_AXI_ACLK,
ena => '1',
wea => abus_we_cmd,
addra => abus_addr(10 downto 1),
dina => abus_data_in,
douta => abus_data_out_cmd,
--axi port
clkb => FILESYS_AXI_ACLK,
enb => '1',
web => axi_we_cmd,
addrb => axi_addr(ADDR_LSB+9 downto ADDR_LSB),
dinb => FILESYS_AXI_WDATA,
doutb => axi_data_out_cmd
);
--data_buffer_addr <= axi_addr(ADDR_LSB+9 downto ADDR_LSB);
data_buffer: buffer_mem
PORT map(
--ABus port
clka => FILESYS_AXI_ACLK,
ena => '1',
wea => abus_we_data,
addra => abus_addr(10 downto 1),
dina => abus_data_in,
douta => abus_data_out_data,
--axi port
clkb => FILESYS_AXI_ACLK,
enb => '1',
web => axi_we_data,
addrb => axi_addr(ADDR_LSB+9 downto ADDR_LSB),
dinb => FILESYS_AXI_WDATA,
doutb => axi_data_out_data
);
end arch_imp;
|
gpl-2.0
|
55ae60660d62dc9f3cef2f91a20ff167
| 0.626068 | 3.556802 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/UART/mode_decoder.vhd
| 1 | 4,470 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mode_decoder is
generic(
N: integer:= 6;
M: integer:= 3;
W: integer:= 8
);
port(
clk: in std_logic := '0';
char_in: in std_logic_vector(7 downto 0) := (others => '0');
RxRdy: in std_logic := '0';
mode: out std_logic_vector(1 downto 0) := (others => '0');
angle: out std_logic_vector(31 downto 0) := (others => '0')
);
end mode_decoder;
architecture mode_decoder_arq of mode_decoder is
constant LETTER_R : std_logic_vector(7 downto 0) := "01010010";
constant LETTER_O : std_logic_vector(7 downto 0) := "01001111";
constant LETTER_T : std_logic_vector(7 downto 0) := "01010100";
constant LETTER_SPACE : std_logic_vector(7 downto 0) := "00100000";
constant LETTER_C : std_logic_vector(7 downto 0) := "01000011";
constant LETTER_A : std_logic_vector(7 downto 0) := "01000001";
constant LETTER_H : std_logic_vector(7 downto 0) := "01001000";
constant LETTER_0 : std_logic_vector(7 downto 0) := "00110000";
constant LETTER_1 : std_logic_vector(7 downto 0) := "00110001";
constant LETTER_2 : std_logic_vector(7 downto 0) := "00110010";
constant LETTER_3 : std_logic_vector(7 downto 0) := "00110011";
constant LETTER_4 : std_logic_vector(7 downto 0) := "00110100";
constant LETTER_5 : std_logic_vector(7 downto 0) := "00110101";
constant LETTER_6 : std_logic_vector(7 downto 0) := "00110110";
constant LETTER_7 : std_logic_vector(7 downto 0) := "00110111";
constant LETTER_8 : std_logic_vector(7 downto 0) := "00111000";
constant LETTER_9 : std_logic_vector(7 downto 0) := "00111001";
constant LETTER_ENTER : std_logic_vector(7 downto 0) := "00001010";
constant SINGLE_ROTATION : std_logic_vector(1 downto 0) := "00";
constant CONSTANT_ROTATION_RIGHT : std_logic_vector(1 downto 0) := "11";
constant CONSTANT_ROTATION_LEFT : std_logic_vector(1 downto 0) := "01";
signal rom_out, enable: std_logic;
signal address: std_logic_vector(5 downto 0);
signal font_row, font_col: std_logic_vector(M-1 downto 0);
signal red_in, grn_in, blu_in: std_logic;
signal pixel_row, pixel_col, pixel_col_aux, pixel_row_aux: std_logic_vector(9 downto 0);
signal sig_startTX: std_logic;
function CHAR_TO_NUMBER(INPUT_CHARACTER : std_logic_vector(7 downto 0) := "00000000") return integer is
begin
case( INPUT_CHARACTER ) is
when LETTER_O => return 0;
when LETTER_1 => return 1;
when LETTER_2 => return 2;
when LETTER_3 => return 3;
when LETTER_4 => return 4;
when LETTER_5 => return 5;
when LETTER_6 => return 6;
when LETTER_7 => return 7;
when LETTER_8 => return 8;
when LETTER_9 => return 9;
when others => return 0;
end case ;
end CHAR_TO_NUMBER;
begin
process(RxRdy)
variable step_to_check : integer := 0;
variable valid : boolean := false;
variable tmp_angle : integer := 0;
variable angle_integer_part : std_logic_vector(15 downto 0) := (others => '0');
variable position : integer := 0;
type string_array is array (8 downto 0) of std_logic_vector(7 downto 0);
variable accumm_chars : string_array := (LETTER_R,LETTER_O,LETTER_C,LETTER_SPACE,LETTER_A,LETTER_SPACE,LETTER_0,LETTER_0,LETTER_0);
begin
if(char_in = LETTER_ENTER) then
if(accumm_chars(0) = LETTER_R and
accumm_chars(1) = LETTER_O and
accumm_chars(2) = LETTER_C and
accumm_chars(3) = LETTER_SPACE) then
if(accumm_chars(4) = LETTER_C) then
if(accumm_chars(5) = LETTER_SPACE) then
if(accumm_chars(6) = LETTER_A) then
mode <= CONSTANT_ROTATION_LEFT;
elsif (accumm_chars(6) = LETTER_H) then
mode <= CONSTANT_ROTATION_RIGHT;
end if;
end if;
elsif(accumm_chars(4) = LETTER_A) then
if(accumm_chars(5) = LETTER_SPACE) then
if(position = 8) then --Means that the angle is a 3 digit one
tmp_angle := CHAR_TO_NUMBER(accumm_chars(6)) * 100 + CHAR_TO_NUMBER(accumm_chars(7)) * 10 + CHAR_TO_NUMBER(accumm_chars(8));
else --2 digit angle
tmp_angle := CHAR_TO_NUMBER(accumm_chars(6)) * 10 + CHAR_TO_NUMBER(accumm_chars(7));
end if;
angle_integer_part := std_logic_vector(to_signed(tmp_angle,16));
angle <= angle_integer_part & "0000000000000000";
mode <= SINGLE_ROTATION;
end if;
end if;
end if;
elsif(position > 8) then
valid := false;
else
accumm_chars(position) := char_in;
position := position + 1;
end if;
end process;
end mode_decoder_arq;
|
gpl-3.0
|
1892d746beea963b5ac614b286f03e2a
| 0.654139 | 3.02027 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/solving_key_equation_1.vhd
| 1 | 21,073 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Solving_Key_Equation_1
-- Module Name: Solving_Key_Equation_1
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 2nd step in Goppa Code Decoding.
--
-- This circuit solves the polynomial key equation sigma with the polynomial syndrome.
-- To solve the key equation, this circuit employs a modified extended euclidean algorithm
-- The modification is made to stop the algorithm when polynomial, represented here as G, has
-- degree less or equal than the polynomial key equation sigma desired degree.
-- The syndrome is the input and expected to be of degree 2*final_degree, and after computations
-- polynomial C, will hold sigma with degree less or equal to final_degree.
--
-- This is the first circuit version. It is a non pipeline version of the algorithm,
-- each coefficient takes more than 1 cycle to be computed.
-- A more optimized version, still non pipeline was made called solving_key_equation_1_v2
-- This improved version, has new address resolution logic and internal degree counters.
--
-- Parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- final_degree :
--
-- The final degree size expected for polynomial sigma to have. This parameter depends
-- of the Goppa code used.
--
-- size_final_degree :
--
-- The number of bits necessary to hold the polynomial with degree of final_degree, which
-- has final_degree + 1 coefficients. This is ceil(log2(final_degree+1)).
--
-- Dependencies:
--
-- VHDL-93
--
-- controller_solving_key_equation_1 Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_decrement_rst_nbits Rev 1.0
-- mult_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity solving_key_equation_1 is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
gf_2_m : integer range 1 to 20 := 11;
final_degree : integer := 27;
size_final_degree : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6
-- QD-GOPPA [2528, 2144, 32, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 32;
-- size_final_degree : integer := 5
-- QD-GOPPA [2816, 2048, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [3328, 2560, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [7296, 5632, 128, 13] --
-- gf_2_m : integer range 1 to 20 := 13;
-- final_degree : integer := 128;
-- size_final_degree : integer := 7
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_FB : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_GC : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_FB : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_GC : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_FB : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_GC : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end solving_key_equation_1;
architecture Behavioral of solving_key_equation_1 is
component controller_solving_key_equation_1
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
FB_equal_zero : in STD_LOGIC;
i_equal_zero : in STD_LOGIC;
i_minus_j_less_than_zero : in STD_LOGIC;
degree_G_less_equal_final_degree : in STD_LOGIC;
degree_F_less_than_degree_G : in STD_LOGIC;
degree_B_equal_degree_C_plus_j : in STD_LOGIC;
degree_B_less_than_degree_C_plus_j : in STD_LOGIC;
reg_looking_degree_q : in STD_LOGIC_VECTOR(0 downto 0);
key_equation_found : out STD_LOGIC;
signal_inv : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
sel_base_mul : out STD_LOGIC;
reg_h_ce : out STD_LOGIC;
ctr_i_ce : out STD_LOGIC;
ctr_i_rst : out STD_LOGIC;
sel_ctr_i_rst_value : out STD_LOGIC_VECTOR(1 downto 0);
reg_j_ce : out STD_LOGIC;
reg_FB_ce : out STD_LOGIC;
reg_FB_rst : out STD_LOGIC;
sel_reg_FB : out STD_LOGIC;
reg_GC_ce : out STD_LOGIC;
reg_GC_rst : out STD_LOGIC;
sel_reg_GC : out STD_LOGIC;
reg_degree_F_ce : out STD_LOGIC;
reg_degree_F_rst : out STD_LOGIC;
sel_reg_degree_F : out STD_LOGIC;
reg_degree_G_ce : out STD_LOGIC;
reg_degree_G_rst : out STD_LOGIC;
reg_degree_B_ce : out STD_LOGIC;
reg_degree_B_rst : out STD_LOGIC;
sel_reg_degree_B : out STD_LOGIC_VECTOR(1 downto 0);
reg_degree_C_ce : out STD_LOGIC;
reg_degree_C_rst : out STD_LOGIC;
reg_looking_degree_d : out STD_LOGIC_VECTOR(0 downto 0);
reg_looking_degree_ce : out STD_LOGIC;
reg_swap_ce : out STD_LOGIC;
reg_swap_rst : out STD_LOGIC;
sel_int_new_value_FB : out STD_LOGIC;
sel_address_FB : out STD_LOGIC;
sel_address_GC : out STD_LOGIC_VECTOR(1 downto 0);
BC_calculation : out STD_LOGIC;
enable_external_swap : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_decrement_rst_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component mult_gf_2_m
Generic (gf_2_m : integer range 1 to 20 := 11);
Port (
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal base_mult_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal base_mult_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal base_mult_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_base_mul : STD_LOGIC;
signal reg_h_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_h_ce : STD_LOGIC;
signal reg_h_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_ce : STD_LOGIC;
signal reg_inv_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_i_ce : STD_LOGIC;
signal ctr_i_rst : STD_LOGIC;
signal ctr_i_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_i_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_ctr_i_rst_value : STD_LOGIC_VECTOR(1 downto 0);
constant ctr_i_rst_value_F : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree - 1,size_final_degree + 2));
constant ctr_i_rst_value_B : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(final_degree,size_final_degree + 2));
signal reg_j_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_j_ce : STD_LOGIC;
signal reg_j_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_FB_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_FB_ce : STD_LOGIC;
signal reg_FB_rst : STD_LOGIC;
constant reg_FB_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_FB_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_reg_FB : STD_LOGIC;
signal reg_GC_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_GC_ce : STD_LOGIC;
signal reg_GC_rst : STD_LOGIC;
constant reg_GC_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_GC_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_reg_GC : STD_LOGIC;
signal reg_degree_F_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_F_ce : STD_LOGIC;
signal reg_degree_F_rst : STD_LOGIC;
constant reg_degree_F_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree - 1,size_final_degree + 2));
signal reg_degree_F_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_reg_degree_F : STD_LOGIC;
signal reg_degree_G_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_G_ce : STD_LOGIC;
signal reg_degree_G_rst : STD_LOGIC;
constant reg_degree_G_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree,size_final_degree + 2));
signal reg_degree_G_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_B_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_B_ce : STD_LOGIC;
signal reg_degree_B_rst : STD_LOGIC;
constant reg_degree_B_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal reg_degree_B_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_reg_degree_B : STD_LOGIC_VECTOR(1 downto 0);
signal reg_degree_C_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_C_ce : STD_LOGIC;
signal reg_degree_C_rst : STD_LOGIC;
constant reg_degree_C_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal reg_degree_C_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_looking_degree_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_looking_degree_ce : STD_LOGIC;
signal reg_looking_degree_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_swap_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_swap_ce : STD_LOGIC;
signal reg_swap_rst : STD_LOGIC;
constant reg_swap_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_swap_q : STD_LOGIC_VECTOR(0 downto 0);
signal i_minus_j : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal degree_C_plus_j : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal int_value_FB : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_int_new_value_FB : STD_LOGIC;
signal int_new_value_FB : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_new_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_write_enable_FB : STD_LOGIC;
signal int_write_enable_GC : STD_LOGIC;
signal int_address_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal int_address_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_i_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_degree_FB_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_i_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_degree_GC_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_i_minus_j_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_address_FB : STD_LOGIC;
signal sel_address_GC : STD_LOGIC_VECTOR(1 downto 0);
signal BC_calculation : STD_LOGIC;
signal enable_external_swap : STD_LOGIC;
signal FB_equal_zero : STD_LOGIC;
signal i_equal_zero : STD_LOGIC;
signal i_minus_j_less_than_zero : STD_LOGIC;
signal degree_G_less_equal_final_degree : STD_LOGIC;
signal degree_F_less_than_degree_G : STD_LOGIC;
signal degree_B_equal_degree_C_plus_j : STD_LOGIC;
signal degree_B_less_than_degree_C_plus_j : STD_LOGIC;
begin
controller : controller_solving_key_equation_1
Port Map(
clk => clk,
rst => rst,
ready_inv => ready_inv,
FB_equal_zero => FB_equal_zero,
i_equal_zero => i_equal_zero,
i_minus_j_less_than_zero => i_minus_j_less_than_zero,
degree_G_less_equal_final_degree => degree_G_less_equal_final_degree,
degree_F_less_than_degree_G => degree_F_less_than_degree_G,
degree_B_equal_degree_C_plus_j => degree_B_equal_degree_C_plus_j,
degree_B_less_than_degree_C_plus_j => degree_B_less_than_degree_C_plus_j,
reg_looking_degree_q => reg_looking_degree_q,
key_equation_found => key_equation_found,
signal_inv => signal_inv,
write_enable_FB => int_write_enable_FB,
write_enable_GC => int_write_enable_GC,
sel_base_mul => sel_base_mul,
reg_h_ce => reg_h_ce,
ctr_i_ce => ctr_i_ce,
ctr_i_rst => ctr_i_rst,
sel_ctr_i_rst_value => sel_ctr_i_rst_value,
reg_j_ce => reg_j_ce,
reg_FB_ce => reg_FB_ce,
reg_FB_rst => reg_FB_rst,
sel_reg_FB => sel_reg_FB,
reg_GC_ce => reg_GC_ce,
reg_GC_rst => reg_GC_rst,
sel_reg_GC => sel_reg_GC,
reg_degree_F_ce => reg_degree_F_ce,
reg_degree_F_rst => reg_degree_F_rst,
sel_reg_degree_F => sel_reg_degree_F,
reg_degree_G_ce => reg_degree_G_ce,
reg_degree_G_rst => reg_degree_G_rst,
reg_degree_B_ce => reg_degree_B_ce,
reg_degree_B_rst => reg_degree_B_rst,
sel_reg_degree_B => sel_reg_degree_B,
reg_degree_C_ce => reg_degree_C_ce,
reg_degree_C_rst => reg_degree_C_rst,
reg_looking_degree_d => reg_looking_degree_d,
reg_looking_degree_ce => reg_looking_degree_ce,
reg_swap_ce => reg_swap_ce,
reg_swap_rst => reg_swap_rst,
sel_int_new_value_FB => sel_int_new_value_FB,
sel_address_FB => sel_address_FB,
sel_address_GC => sel_address_GC,
BC_calculation => BC_calculation,
enable_external_swap => enable_external_swap
);
base_mult : mult_gf_2_m
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => base_mult_a,
b => base_mult_b,
o => base_mult_o
);
reg_h : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_h_d,
clk => clk,
ce => reg_h_ce,
q => reg_h_q
);
reg_inv : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_inv_d,
clk => clk,
ce => reg_inv_ce,
q => reg_inv_q
);
ctr_i : counter_decrement_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
clk => clk,
ce => ctr_i_ce,
rst => ctr_i_rst,
rst_value => ctr_i_rst_value,
q => ctr_i_q
);
reg_j : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_j_d,
clk => clk,
ce => reg_j_ce,
q => reg_j_q
);
reg_FB : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_FB_d,
clk => clk,
rst => reg_FB_rst,
rst_value => reg_FB_rst_value,
ce => reg_FB_ce,
q => reg_FB_q
);
reg_GC : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_GC_d,
clk => clk,
rst => reg_GC_rst,
rst_value => reg_GC_rst_value,
ce => reg_GC_ce,
q => reg_GC_q
);
reg_degree_F : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_F_d,
clk => clk,
rst => reg_degree_F_rst,
rst_value => reg_degree_F_rst_value,
ce => reg_degree_F_ce,
q => reg_degree_F_q
);
reg_degree_G : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_G_d,
clk => clk,
rst => reg_degree_G_rst,
rst_value => reg_degree_G_rst_value,
ce => reg_degree_G_ce,
q => reg_degree_G_q
);
reg_degree_B : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_B_d,
clk => clk,
rst => reg_degree_B_rst,
rst_value => reg_degree_B_rst_value,
ce => reg_degree_B_ce,
q => reg_degree_B_q
);
reg_degree_C : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_C_d,
clk => clk,
rst => reg_degree_C_rst,
rst_value => reg_degree_C_rst_value,
ce => reg_degree_C_ce,
q => reg_degree_C_q
);
reg_looking_degree : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_looking_degree_d,
clk => clk,
ce => reg_looking_degree_ce,
q => reg_looking_degree_q
);
reg_swap : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_swap_d,
clk => clk,
ce => reg_swap_ce,
rst => reg_swap_rst,
rst_value => reg_swap_rst_value,
q => reg_swap_q
);
base_mult_a <= reg_inv_q when sel_base_mul = '1' else
reg_h_q;
base_mult_b <= reg_FB_q when sel_base_mul = '1' else
reg_GC_q;
reg_h_d <= base_mult_o;
reg_inv_d <= value_inv;
reg_inv_ce <= ready_inv;
ctr_i_rst_value <= reg_degree_F_q when sel_ctr_i_rst_value = "11" else
degree_C_plus_j when sel_ctr_i_rst_value = "10" else
ctr_i_rst_value_F when sel_ctr_i_rst_value = "01" else
ctr_i_rst_value_B;
reg_j_d <= std_logic_vector(unsigned(reg_degree_F_q) - unsigned(reg_degree_G_q));
reg_FB_d <= std_logic_vector(to_unsigned(1, reg_FB_d'length)) when sel_reg_FB = '1' else
int_value_FB;
reg_GC_d <= std_logic_vector(to_unsigned(1, reg_GC_d'length)) when sel_reg_GC = '1' else
int_value_GC;
reg_degree_F_d <= std_logic_vector((unsigned(reg_degree_F_q) - to_unsigned(1, reg_degree_F_q'length))) when sel_reg_degree_F = '1' else
reg_degree_G_q;
reg_degree_G_d <= reg_degree_F_q;
reg_degree_B_d <= degree_C_plus_j when sel_reg_degree_B = "10" else
std_logic_vector(unsigned(reg_degree_B_q) - to_unsigned(1, reg_degree_B_q'length)) when sel_reg_degree_B = "01" else
reg_degree_C_q when sel_reg_degree_B = "00" else
(others => '-');
degree_C_plus_j <= std_logic_vector(unsigned(reg_degree_C_q) + unsigned(reg_j_q));
i_minus_j <= std_logic_vector(unsigned(ctr_i_q) - unsigned(reg_j_q));
reg_degree_C_d <= reg_degree_B_q;
reg_swap_d <= not reg_swap_q;
int_new_value_FB <= (base_mult_o xor reg_FB_q) when sel_int_new_value_FB = '1' else
reg_FB_q;
int_new_value_GC <= reg_GC_q;
int_value_FB <= value_GC when reg_swap_q = "1" else value_FB;
int_value_GC <= value_FB when reg_swap_q = "1" else value_GC;
new_value_inv <= int_new_value_GC;
new_value_FB <= int_new_value_GC when (reg_swap_q(0) and enable_external_swap) = '1' else int_new_value_FB;
new_value_GC <= int_new_value_FB when (reg_swap_q(0) and enable_external_swap) = '1' else int_new_value_GC;
write_enable_FB <= int_write_enable_GC when (reg_swap_q(0) and enable_external_swap) = '1' else int_write_enable_FB;
write_enable_GC <= int_write_enable_FB when (reg_swap_q(0) and enable_external_swap) = '1' else int_write_enable_GC;
address_i_FB <= std_logic_vector(to_unsigned(2*final_degree + 1, address_i_FB'length) + unsigned(ctr_i_q)) when BC_calculation = '1' else
ctr_i_q;
address_degree_FB_FB <= std_logic_vector(to_unsigned(2*final_degree + 1, address_degree_FB_FB'length) + unsigned(reg_degree_B_q)) when BC_calculation = '1' else
reg_degree_F_q;
address_i_GC <= std_logic_vector(to_unsigned(2*final_degree + 1, address_i_GC'length) + unsigned(ctr_i_q)) when BC_calculation = '1' else
ctr_i_q;
address_degree_GC_GC <= std_logic_vector(to_unsigned(2*final_degree + 1, address_degree_GC_GC'length) + unsigned(reg_degree_C_q)) when BC_calculation = '1' else
reg_degree_G_q;
address_i_minus_j_GC <= std_logic_vector(to_unsigned(2*final_degree + 1, address_i_minus_j_GC'length) + unsigned(i_minus_j)) when BC_calculation = '1' else
i_minus_j;
int_address_FB <= address_degree_FB_FB when sel_address_FB = '1' else
address_i_FB;
int_address_GC <= address_i_minus_j_GC when sel_address_GC = "10" else
address_degree_GC_GC when sel_address_GC = "01" else
address_i_GC when sel_address_GC = "00" else
(others => '-');
address_FB <= int_address_GC when (reg_swap_q(0) and enable_external_swap) = '1' else int_address_FB;
address_GC <= int_address_FB when (reg_swap_q(0) and enable_external_swap) = '1' else int_address_GC;
FB_equal_zero <= '1' when (int_new_value_FB = std_logic_vector(to_unsigned(0,reg_FB_q'length))) else '0';
i_equal_zero <= '1' when (ctr_i_q = std_logic_vector(to_unsigned(0,ctr_i_q'length))) else '0';
i_minus_j_less_than_zero <= '1' when (signed(i_minus_j) < to_signed(0,i_minus_j'length)) else '0';
degree_G_less_equal_final_degree <= '1' when (unsigned(reg_degree_G_q) <= to_unsigned(final_degree-1,reg_degree_G_q'length)) else '0';
degree_F_less_than_degree_G <= '1' when (unsigned(reg_degree_F_q) < unsigned(reg_degree_G_q)) else '0';
degree_B_equal_degree_C_plus_j <= '1' when (reg_degree_B_q = degree_C_plus_j) else '0';
degree_B_less_than_degree_C_plus_j <= '1' when (unsigned(reg_degree_B_q) < unsigned(degree_C_plus_j)) else '0';
end Behavioral;
|
bsd-2-clause
|
42154cc1fd4647395b05f5745daff7e0
| 0.655436 | 2.597116 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/multiplication/mantissa_multiplier/mantissa_multiplier_tb.vhd
| 1 | 1,676 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mantissa_multiplier_tb is
end entity;
architecture mantissa_multiplier_tb_arq of mantissa_multiplier_tb is
signal man1_in: std_logic_vector(5 downto 0);
signal man2_in: std_logic_vector(5 downto 0);
signal result: std_logic_vector(7 downto 0);
component mantissa_multiplier is
generic(
BITS:natural := 16
);
port (
man1_in: in std_logic_vector(BITS - 1 downto 0);
man2_in: in std_logic_vector(BITS - 1 downto 0);
result: out std_logic_vector(BITS + 1 downto 0) --Add one to shift if necessary
);
end component;
for mantissa_multiplier_0: mantissa_multiplier use entity work.mantissa_multiplier;
begin
mantissa_multiplier_0: mantissa_multiplier
generic map(BITS => 6)
port map(
man1_in => man1_in,
man2_in => man2_in,
result => result
);
process
type pattern_type is record
m1 : std_logic_vector(5 downto 0);
m2 : std_logic_vector(5 downto 0);
r : std_logic_vector(7 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range<>) of pattern_type;
constant patterns : pattern_array := (
("000000","000000","01000000"),
("111111","111111","11111100")
);
begin
for i in patterns'range loop
-- Set the inputs.
man1_in <= patterns(i).m1;
man2_in <= patterns(i).m2;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert result = patterns(i).r report "BAD RESULT: " & integer'image(to_integer(unsigned(result))) severity error;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
0a4b6d9d58449a07753855f8db9823ae
| 0.668854 | 3.204589 | false | false | false | false |
pwuertz/digitizer2fw
|
src/rtl/tdc_sample_prep_pkg.vhd
| 1 | 2,499 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sampling_pkg.all;
package tdc_sample_prep_pkg is
constant TDC_EVENT_POS_BITS: natural := 2;
type tdc_event_t is
record
valid: std_logic;
pos: unsigned(1 downto 0);
end record;
function to_std_logic_vector(x: tdc_event_t) return std_logic_vector;
function to_tdc_event_t(x: std_logic_vector) return tdc_event_t;
-- convert vector to a single event encoded as valid flag + position. extract first event only.
function flat_events_to_event_t(flat: std_logic_vector(3 downto 0)) return tdc_event_t;
type tdc_events_t is
record
d1_rising: tdc_event_t;
d1_falling: tdc_event_t;
d2_rising: tdc_event_t;
d2_falling: tdc_event_t;
a_maxfound: tdc_event_t;
a_maxvalue: a_sample_t;
end record;
component tdc_sample_prep is
generic (
CNT_BITS: natural := 16
);
port (
clk: in std_logic;
samples_d_in: in din_samples_t(0 to 3);
samples_a_in: in adc_samples_t(0 to 1);
a_threshold: in a_sample_t;
a_invert: in std_logic;
a_average: in std_logic_vector(1 downto 0);
--
samples_d_out: out din_samples_t(0 to 3);
samples_a_out: out a_samples_t(0 to 1);
cnt: out unsigned(CNT_BITS-1 downto 0);
tdc_events: out tdc_events_t
);
end component;
end tdc_sample_prep_pkg;
package body tdc_sample_prep_pkg is
function to_std_logic_vector(x: tdc_event_t) return std_logic_vector is
variable result: std_logic_vector(1+TDC_EVENT_POS_BITS-1 downto 0);
begin
result(TDC_EVENT_POS_BITS) := x.valid;
result(TDC_EVENT_POS_BITS-1 downto 0) := std_logic_vector(x.pos);
return result;
end to_std_logic_vector;
function to_tdc_event_t(x: std_logic_vector) return tdc_event_t is
variable result: tdc_event_t;
begin
result.valid := x(x'low + TDC_EVENT_POS_BITS);
result.pos := unsigned(x(x'low + TDC_EVENT_POS_BITS-1 downto x'low));
return result;
end to_tdc_event_t;
function flat_events_to_event_t(flat: std_logic_vector(3 downto 0)) return tdc_event_t is
variable result: tdc_event_t := (valid => '0', pos => (others => '-'));
begin
for I in 0 to 3 loop
if flat(I) = '1' then
result.valid := '1';
result.pos := to_unsigned(3-I, 2);
end if;
end loop;
return result;
end flat_events_to_event_t;
end tdc_sample_prep_pkg;
|
gpl-3.0
|
5c0c635692bc23eca70ef5ed7f7121aa
| 0.62585 | 3.058752 | false | false | false | false |
achan1989/In64
|
FPGA/SD_card_test.srcs/sources_1/ip/mig_v3_92_0/ATLYS_DDR/example_design/sim/functional/sim_tb_top.vhd
| 1 | 16,489 |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C3_HW_TESTING : string := "FALSE";
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_MEMCLK_PERIOD : integer := 3000;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CLK_PERIOD_NS : real := 3000.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 13;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_SIMULATION : string := "TRUE";
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component example_top is
generic
(
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_HW_TESTING : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end component;
component ddr2_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_rdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
rdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal rzq3 : std_logic;
signal zio3 : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
-- The PULLDOWN component is connected to the ZIO signal primarily to avoid the
-- unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
zio_pulldown3 : PULLDOWN port map(O => zio3);
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : example_top generic map
(
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_HW_TESTING => C3_HW_TESTING,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
calib_done => calib_done,
error => error,
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => rzq3,
mcb3_zio => zio3,
mcb3_dram_dqs => mcb3_dram_dqs
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr2_model_c3 port map(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_rdqs => mcb3_dram_dm_vector ,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
rdqs_n => open,
odt => mcb3_dram_odt
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
|
lgpl-3.0
|
b4407a3acaa667d86159dc2808539e25
| 0.476014 | 3.707059 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/counter_decrement_load_rst_nbits.vhd
| 1 | 2,088 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_decrement_load_rst_n_bits
-- Module Name: Counter_decrement_load_rst_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Counter of size bits with reset signal, that only decrements when ce equals to 1.
-- The reset is synchronous and the value loaded during reset is defined by reset_value.
-- The counter has a synchronous load signal, which will register the value on input d,
-- when load is 1 and reset is 0.
--
-- The circuits parameters
--
-- size :
--
-- The size of the counter in bits.
--
-- decrement_value :
--
-- The amount will be decremented each cycle.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_decrement_load_rst_nbits is
Generic (
size : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
load : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end counter_decrement_load_rst_nbits;
architecture Behavioral of counter_decrement_load_rst_nbits is
signal internal_value : UNSIGNED((size - 1) downto 0);
begin
process(clk, ce, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= unsigned(rst_value);
elsif(ce = '1') then
if(load = '1') then
internal_value <= unsigned(d);
else
internal_value <= internal_value - to_unsigned(decrement_value, internal_value'Length);
end if;
else
null;
end if;
end if;
end process;
q <= std_logic_vector(internal_value);
end Behavioral;
|
bsd-2-clause
|
f21204c98455ef24aed77528c5e0cbf0
| 0.625479 | 3.411765 | false | false | false | false |
ruygargar/LCSE_lab
|
rs232/rs232_top.vhd
| 1 | 4,558 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RS232top is
port (
Reset : in std_logic; -- Low_level-active asynchronous reset
Clk : in std_logic; -- System clock (20MHz), rising edge used
Data_in : in std_logic_vector(7 downto 0); -- Data to be sent
Valid_D : in std_logic; -- Handshake signal
-- from guest system, low when data is valid
Ack_in : out std_logic; -- ACK for data received, low once data
-- has been stored
TX_RDY : out std_logic; -- System ready to transmit
TD : out std_logic; -- RS232 Transmission line
RD : in std_logic; -- RS232 Reception line
Data_out : out std_logic_vector(7 downto 0); -- Received data
Data_read : in std_logic; -- Data read for guest system
Full : out std_logic; -- Full internal memory
Empty : out std_logic); -- Empty internal memory
end RS232top;
architecture RTL of RS232top is
------------------------------------------------------------------------
-- Components for Transmitter Block
------------------------------------------------------------------------
component RS232_TX
port (
Clk : in std_logic;
Reset : in std_logic;
Start : in std_logic;
Data : in std_logic_vector(7 downto 0);
EOT : out std_logic;
TX : out std_logic);
end component;
------------------------------------------------------------------------
-- Components for Receiver Block
------------------------------------------------------------------------
component ShiftRegister
port (
Reset : in std_logic;
Clk : in std_logic;
Enable : in std_logic;
D : in std_logic;
Q : out std_logic_vector(7 downto 0));
end component;
component RS232_RX
port (
Clk : in std_logic;
Reset : in std_logic;
LineRD_in : in std_logic;
Valid_out : out std_logic;
Code_out : out std_logic;
Store_out : out std_logic);
end component;
component fifo
port (
clk : IN std_logic;
rst : IN std_logic;
din : IN std_logic_VECTOR(7 downto 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(7 downto 0);
full : OUT std_logic;
empty : OUT std_logic);
end component;
------------------------------------------------------------------------
-- Internal Signals
------------------------------------------------------------------------
signal Data_FF : std_logic_vector(7 downto 0);
signal StartTX : std_logic; -- start signal for transmitter
signal LineRD_in : std_logic; -- internal RX line
signal Valid_out : std_logic; -- valid bit @ receiver
signal Code_out : std_logic; -- bit @ receiver output
signal sinit : std_logic; -- fifo reset
signal Fifo_in : std_logic_vector(7 downto 0);
signal Fifo_write : std_logic;
signal TX_RDY_i : std_logic;
begin -- RTL
Transmitter: RS232_TX
port map (
Clk => Clk,
Reset => Reset,
Start => StartTX,
Data => Data_FF,
EOT => TX_RDY_i,
TX => TD);
Receiver: RS232_RX
port map (
Clk => Clk,
Reset => Reset,
LineRD_in => LineRD_in,
Valid_out => Valid_out,
Code_out => Code_out,
Store_out => Fifo_write);
Shift: ShiftRegister
port map (
Reset => Reset,
Clk => Clk,
Enable => Valid_Out,
D => Code_Out,
Q => Fifo_in);
sinit <= not reset;
Internal_memory: fifo
port map (
clk => clk,
rst => sinit,
din => Fifo_in,
wr_en => Fifo_write,
rd_en => Data_read,
dout => Data_out,
full => Full,
empty => Empty);
-- purpose: Clocking process for input protocol
Clocking : process (Clk, Reset)
begin
if Reset = '0' then -- asynchronous reset (active low)
Data_FF <= (others => '0');
LineRD_in <= '1';
Ack_in <= '1';
elsif Clk'event and Clk = '1' then -- rising edge clock
LineRD_in <= RD;
if Valid_D = '0' and TX_RDY_i = '1' then
Data_FF <= Data_in;
Ack_in <= '0';
StartTX <= '1';
else
Ack_in <= '1';
StartTX <= '0';
end if;
end if;
end process Clocking;
TX_RDY <= TX_RDY_i;
end RTL;
|
gpl-3.0
|
472bf556c016ea6b624d178dad1c7d02
| 0.493418 | 3.807853 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/number_expander/number_expander_tb.vhd
| 1 | 1,508 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity number_expander_tb is
end entity;
architecture number_expander_tb_arq of number_expander_tb is
signal number_in : std_logic_vector(15 downto 0) := (others => '0');
signal number_out : std_logic_vector(16 downto 0) := (others => '0');
component number_expander is
generic(
BITS : natural := 16
);
port(
number_in : in std_logic_vector(BITS - 1 downto 0);
number_out : out std_logic_vector(BITS downto 0)
);
end component;
for number_expander_0 : number_expander use entity work.number_expander;
begin
number_expander_0 : number_expander
generic map(BITS => 16)
port map(
number_in => number_in,
number_out => number_out
);
process
type pattern_type is record
ni : std_logic_vector(15 downto 0);
no : std_logic_vector(16 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("0000000000000000","10000000000000000"),
("1111111111111111","11111111111111111"),
("1010101010101010","11010101010101010")
);
begin
for i in patterns'range loop
-- Set the inputs.
number_in <= patterns(i).ni;
wait for 1 ns;
assert patterns(i).no = number_out report "BAD NUMBER, GOT: " & integer'image(to_integer(unsigned(number_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
7c34c42cfb1a1a86d9b1dc539c1cd999
| 0.676393 | 3.201699 | false | false | false | false |
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