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pmassolino/hw-goppa-mceliece
|
mceliece/backup/controller_polynomial_evaluator.vhd
| 1 | 15,145 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Polynomial_Evaluator
-- Module Name: Controller_Polynomial_Evaluator
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 3rd step in Goppa Code Decoding.
--
-- This circuit is the state machine to control both polynomial_evaluator_n and
-- polynomial_evaluator_n_v2. Because both circuits have similar behavioral on
-- how the registers are loaded, they can share the same state machine.
-- The difference is how each pipeline computes inside each, which does not matter
-- for state machine inner workings.
--
-- This state machine works by preparing the pipeline by loading the polynomial
-- coefficients and respective first values to be evaluated. Then it loads the
-- remaining evaluated values. When there are no more values to be evaluated,
-- it restarts loading the values to be evaluated and the remaining polynomial
-- coefficients.
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_polynomial_evaluator is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_load_x_values : in STD_LOGIC;
last_store_x_values : in STD_LOGIC;
limit_polynomial_degree : in STD_LOGIC;
pipeline_ready : in STD_LOGIC;
evaluation_data_in : out STD_LOGIC;
reg_write_enable_rst : out STD_LOGIC;
ctr_load_x_address_ce : out STD_LOGIC;
ctr_load_x_address_rst : out STD_LOGIC;
ctr_store_x_address_ce : out STD_LOGIC;
ctr_store_x_address_rst : out STD_LOGIC;
reg_first_values_ce : out STD_LOGIC;
reg_first_values_rst : out STD_LOGIC;
ctr_address_polynomial_ce : out STD_LOGIC;
ctr_address_polynomial_rst : out STD_LOGIC;
reg_x_rst_rst : out STD_LOGIC;
shift_polynomial_ce_ce : out STD_LOGIC;
shift_polynomial_ce_rst : out STD_LOGIC;
last_coefficients : out STD_LOGIC;
evaluation_finalized : out STD_LOGIC
);
end controller_polynomial_evaluator;
architecture Behavioral of controller_polynomial_evaluator is
type State is (reset, load_counter, load_first_polynomial_coefficient, reset_first_polynomial_coefficient, prepare_load_polynomial_coefficient, load_polynomial_coefficient, reset_polynomial_coefficient, load_x_write_x, last_load_x_write_x, write_x, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, last_load_x_values, last_store_x_values, limit_polynomial_degree, pipeline_ready)
begin
case (actual_state) is
when reset =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '1';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '1';
reg_x_rst_rst <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '1';
last_coefficients <= '0';
evaluation_finalized <= '0';
when load_counter =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '1';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
when load_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
elsif(limit_polynomial_degree = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '1';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
end if;
when reset_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '1';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '1';
evaluation_finalized <= '0';
end if;
when prepare_load_polynomial_coefficient =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '1';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '1';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
when load_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
elsif(limit_polynomial_degree = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '1';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
end if;
when reset_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '1';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '1';
evaluation_finalized <= '0';
end if;
when load_x_write_x =>
if(last_load_x_values = '1' and limit_polynomial_degree = '0') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
end if;
when last_load_x_write_x =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
when write_x =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
when final =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '1';
when others =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
end case;
end process;
NewState: process (actual_state, last_load_x_values, last_store_x_values, limit_polynomial_degree, pipeline_ready)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= load_first_polynomial_coefficient;
when load_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= load_x_write_x;
elsif(limit_polynomial_degree = '1') then
next_state <= reset_first_polynomial_coefficient;
else
next_state <= load_first_polynomial_coefficient;
end if;
when reset_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= load_x_write_x;
else
next_state <= reset_first_polynomial_coefficient;
end if;
when prepare_load_polynomial_coefficient =>
next_state <= load_polynomial_coefficient;
when load_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= load_x_write_x;
elsif(limit_polynomial_degree = '1') then
next_state <= reset_polynomial_coefficient;
else
next_state <= load_polynomial_coefficient;
end if;
when reset_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= load_x_write_x;
else
next_state <= reset_polynomial_coefficient;
end if;
when load_x_write_x =>
if(last_load_x_values = '1') then
if(limit_polynomial_degree = '1') then
next_state <= last_load_x_write_x;
else
next_state <= prepare_load_polynomial_coefficient;
end if;
else
next_state <= load_x_write_x;
end if;
when last_load_x_write_x =>
next_state <= write_x;
when write_x =>
if(last_store_x_values = '1') then
next_state <= final;
else
next_state <= write_x;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
44b01e6af15fb178ab69c77d44c92e14
| 0.60482 | 2.8224 | false | false | false | false |
ruygargar/LCSE_lab
|
rs232/tb_ShiftRegister.vhd
| 1 | 2,384 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:02:57 11/15/2013
-- Design Name:
-- Module Name: C:/Users/Silvia/Desktop/RS232 project/RS232/tb_ShiftRegister.vhd
-- Project Name: RS232
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ShiftRegister
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_ShiftRegister IS
END tb_ShiftRegister;
ARCHITECTURE behavior OF tb_ShiftRegister IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ShiftRegister
PORT(
Reset : IN std_logic;
Clk : IN std_logic;
Enable : IN std_logic;
D : IN std_logic;
Q : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal Reset : std_logic := '0';
signal Clk : std_logic := '0';
signal Enable : std_logic := '0';
signal D : std_logic := '0';
--Outputs
signal Q : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 50 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ShiftRegister PORT MAP (
Reset => Reset,
Clk => Clk,
Enable => Enable,
D => D,
Q => Q
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
D <= NOT D after 51 ns;
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
Reset <= '1';
wait for 300 ns;
Enable <= '1';
wait for 300 ns;
Enable <= '0';
wait;
end process;
END;
|
gpl-3.0
|
8fbf6934b301cf6b16b6980bd4c8de1d
| 0.58557 | 3.9018 | false | true | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/and_reduce.vhd
| 1 | 1,855 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 07/01/2013
-- Design Name: AND_Reduce
-- Module Name: AND_Reduce
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- AND reduction for any std_logic_vector
--
-- The circuits parameters
--
-- size_vector :
--
-- The size of the std_logic_vector to be reduced.
--
-- number_of_vectors :
--
-- The number of vector to be reduced in one vector of size size_vector.
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_reduce is
Generic(
vector_size : integer := 1;
number_of_vectors : integer range 2 to integer'high := 2
);
Port(
a : in STD_LOGIC_VECTOR(((vector_size)*(number_of_vectors) - 1) downto 0);
o : out STD_LOGIC_VECTOR((vector_size - 1) downto 0)
);
end and_reduce;
architecture RTL of and_reduce is
signal b : STD_LOGIC_VECTOR(((vector_size)*(number_of_vectors - 1) - 1) downto 0);
begin
b((vector_size - 1) downto 0) <= a((vector_size - 1) downto 0) and a((2*vector_size - 1) downto (vector_size));
more_than_two : if number_of_vectors > 2 generate
reduction : for Index in 0 to (number_of_vectors - 3) generate
b(((vector_size)*(Index + 2) - 1) downto ((vector_size)*(Index + 1))) <= a(((vector_size)*(Index + 3) - 1) downto ((vector_size)*(Index + 2))) and b(((vector_size)*(Index + 1) - 1) downto ((vector_size)*(Index)));
end generate;
end generate;
o <= b(((vector_size)*(number_of_vectors - 1) - 1) downto ((vector_size)*(number_of_vectors - 2)));
end RTL;
|
bsd-2-clause
|
9060c35c6517b138e525dd4f4c437a8c
| 0.595687 | 3.360507 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/finite_field/inv_gf_2_m_pipeline.vhd
| 1 | 114,500 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Inv_GF_2_M
-- Module Name: Inv_GF_2_M
-- Project Name: GF_2_M Arithmetic
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit computes the inversion of a element in GF(2^m)
-- This circuit has a pipeline strategy.
-- Register were added on the pure combinatorial to increase circuit frequency operation.
--
-- The register were added with the following rules:
-- At most 3 pow2 units.
-- One pow2 followed by one multiplier.
--
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit.
--
-- Dependencies:
-- VHDL-93
--
-- mult_gf_2_m Rev 1.0
-- pow2_gf_2_m Rev 1.0
-- register_nbits Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity inv_gf_2_m_pipeline is
Generic(gf_2_m : integer range 1 to 20 := 13);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
flag : in STD_LOGIC;
clk : in STD_LOGIC;
oflag : out STD_LOGIC;
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end inv_gf_2_m_pipeline;
architecture Behavioral of inv_gf_2_m_pipeline is
component pow2_gf_2_m
Generic(gf_2_m : integer range 1 to 20 := 11);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component mult_gf_2_m
Generic(gf_2_m : integer range 1 to 20 := 11);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
type vector is array(integer range <>) of STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal intermediate_values : vector(0 to 40);
signal previous_values_1 : vector(0 to 10);
signal previous_values_3 : vector(0 to 10);
signal previous_values_7 : vector(0 to 10);
signal previous_values_15 : vector(0 to 10);
signal previous_values_63 : vector(0 to 10);
signal previous_values_255 : vector(0 to 10);
signal intermediate_flags : STD_LOGIC_VECTOR(0 to 10);
--for all : pow2_gf_2_m use entity work.pow2_gf_2_m(Software_POLYNOMIAL);
begin
GF_2_1 : if gf_2_m = 1 generate
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
o <= intermediate_values(0);
oflag <= intermediate_flags(0);
end generate;
GF_2_2 : if gf_2_m = 2 generate -- x^2 + x^1 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_2_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
o <= intermediate_values(1);
oflag <= intermediate_flags(0);
end generate;
GF_2_3 : if gf_2_m = 3 generate -- x^3 + x^1 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_3_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_3_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_3_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
o <= intermediate_values(4);
oflag <= intermediate_flags(1);
end generate;
GF_2_4 : if gf_2_m = 4 generate -- x^4 + x^1 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_4_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_4_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_previous1_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(0),
clk => clk,
ce => '1',
q => previous_values_1(0)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_4_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_4_op_3 : mult_gf_2_m -- a^7
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_1(0),
b => intermediate_values(4),
o => intermediate_values(5)
);
reg_value2 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(5),
clk => clk,
ce => '1',
q => intermediate_values(6)
);
reg_flag2 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(1),
clk => clk,
ce => '1',
q(0) => intermediate_flags(2)
);
GF_2_4_op_4 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^14
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(6),
o => intermediate_values(7)
);
o <= intermediate_values(7);
oflag <= intermediate_flags(2);
end generate;
GF_2_5 : if gf_2_m = 5 generate -- x^5 + x^2 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_5_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_5_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_5_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_5_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
reg_value2 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(5),
clk => clk,
ce => '1',
q => intermediate_values(6)
);
reg_previous2_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(3),
clk => clk,
ce => '1',
q => previous_values_3(0)
);
reg_flag2 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(1),
clk => clk,
ce => '1',
q(0) => intermediate_flags(2)
);
GF_2_5_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(0),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_5_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
o <= intermediate_values(8);
oflag <= intermediate_flags(2);
end generate;
GF_2_6 : if gf_2_m = 6 generate -- x^6 + x^1 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_6_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_6_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_previous1_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(0),
clk => clk,
ce => '1',
q => previous_values_1(0)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_6_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_6_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
reg_value2 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(5),
clk => clk,
ce => '1',
q => intermediate_values(6)
);
reg_previous2_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(0),
clk => clk,
ce => '1',
q => previous_values_1(1)
);
reg_previous2_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(3),
clk => clk,
ce => '1',
q => previous_values_3(0)
);
reg_flag2 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(1),
clk => clk,
ce => '1',
q(0) => intermediate_flags(2)
);
GF_2_6_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(0),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_6_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
reg_value3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(8),
clk => clk,
ce => '1',
q => intermediate_values(9)
);
reg_previous3_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(1),
clk => clk,
ce => '1',
q => previous_values_1(2)
);
reg_flag3 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(2),
clk => clk,
ce => '1',
q(0) => intermediate_flags(3)
);
GF_2_6_op_6 : mult_gf_2_m -- a^31
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_1(2),
b => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_6_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^62
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
o <= intermediate_values(11);
oflag <= intermediate_flags(3);
end generate;
GF_2_7 : if gf_2_m = 7 generate -- x^7 + x^1 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_7_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_7_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_7_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_7_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
reg_value2 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(5),
clk => clk,
ce => '1',
q => intermediate_values(6)
);
reg_previous2_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(3),
clk => clk,
ce => '1',
q => previous_values_3(0)
);
reg_flag2 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(1),
clk => clk,
ce => '1',
q(0) => intermediate_flags(2)
);
GF_2_7_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(0),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_7_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
reg_value3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(8),
clk => clk,
ce => '1',
q => intermediate_values(9)
);
reg_previous3_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(0),
clk => clk,
ce => '1',
q => previous_values_3(1)
);
reg_flag3 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(2),
clk => clk,
ce => '1',
q(0) => intermediate_flags(3)
);
GF_2_7_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_7_op_7 : mult_gf_2_m -- a^63
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(1),
b => intermediate_values(10),
o => intermediate_values(11)
);
reg_value4 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(11),
clk => clk,
ce => '1',
q => intermediate_values(12)
);
reg_flag4 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(3),
clk => clk,
ce => '1',
q(0) => intermediate_flags(4)
);
GF_2_7_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^126
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(12),
o => intermediate_values(13)
);
o <= intermediate_values(13);
oflag <= intermediate_flags(4);
end generate;
GF_2_8 : if gf_2_m = 8 generate -- x^8 + x^4 + x^3 + x^1 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_8_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_8_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_previous1_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(0),
clk => clk,
ce => '1',
q => previous_values_1(0)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_8_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_8_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
reg_value2 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(5),
clk => clk,
ce => '1',
q => intermediate_values(6)
);
reg_previous2_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(0),
clk => clk,
ce => '1',
q => previous_values_1(1)
);
reg_previous2_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(3),
clk => clk,
ce => '1',
q => previous_values_3(0)
);
reg_flag2 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(1),
clk => clk,
ce => '1',
q(0) => intermediate_flags(2)
);
GF_2_8_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(0),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_8_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
reg_value3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(8),
clk => clk,
ce => '1',
q => intermediate_values(9)
);
reg_previous3_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(1),
clk => clk,
ce => '1',
q => previous_values_1(2)
);
reg_previous3_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(0),
clk => clk,
ce => '1',
q => previous_values_3(1)
);
reg_flag3 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(2),
clk => clk,
ce => '1',
q(0) => intermediate_flags(3)
);
GF_2_8_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_8_op_7 : mult_gf_2_m -- a^63
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(1),
b => intermediate_values(10),
o => intermediate_values(11)
);
reg_value4 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(11),
clk => clk,
ce => '1',
q => intermediate_values(12)
);
reg_previous4_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(2),
clk => clk,
ce => '1',
q => previous_values_1(3)
);
reg_flag4 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(3),
clk => clk,
ce => '1',
q(0) => intermediate_flags(4)
);
GF_2_8_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^126
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(12),
o => intermediate_values(13)
);
GF_2_8_op_9 : mult_gf_2_m -- a^127
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_1(3),
b => intermediate_values(13),
o => intermediate_values(14)
);
reg_value5 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(14),
clk => clk,
ce => '1',
q => intermediate_values(15)
);
reg_flag5 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(4),
clk => clk,
ce => '1',
q(0) => intermediate_flags(5)
);
GF_2_8_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^254
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(15),
o => intermediate_values(16)
);
o <= intermediate_values(16);
oflag <= intermediate_flags(5);
end generate;
GF_2_9 : if gf_2_m = 9 generate -- x^9 + x^1 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_9_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_9_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_9_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_9_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
reg_value2 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(5),
clk => clk,
ce => '1',
q => intermediate_values(6)
);
reg_previous2_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(3),
clk => clk,
ce => '1',
q => previous_values_3(0)
);
reg_flag2 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(1),
clk => clk,
ce => '1',
q(0) => intermediate_flags(2)
);
GF_2_9_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(0),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_9_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
reg_value3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(8),
clk => clk,
ce => '1',
q => intermediate_values(9)
);
reg_previous3_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(7),
clk => clk,
ce => '1',
q => previous_values_15(0)
);
reg_flag3 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(2),
clk => clk,
ce => '1',
q(0) => intermediate_flags(3)
);
GF_2_9_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_9_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_9_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
reg_value4 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(12),
clk => clk,
ce => '1',
q => intermediate_values(13)
);
reg_previous4_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_15(0),
clk => clk,
ce => '1',
q => previous_values_15(1)
);
reg_flag4 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(3),
clk => clk,
ce => '1',
q(0) => intermediate_flags(4)
);
GF_2_9_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_15(1),
b => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_9_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
o <= intermediate_values(15);
oflag <= intermediate_flags(4);
end generate;
GF_2_10 : if gf_2_m = 10 generate -- x^10 + x^3 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_10_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_10_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_previous1_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(0),
clk => clk,
ce => '1',
q => previous_values_1(0)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_10_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_10_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
reg_value2 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(5),
clk => clk,
ce => '1',
q => intermediate_values(6)
);
reg_previous2_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(0),
clk => clk,
ce => '1',
q => previous_values_1(1)
);
reg_previous2_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(3),
clk => clk,
ce => '1',
q => previous_values_3(0)
);
reg_flag2 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(1),
clk => clk,
ce => '1',
q(0) => intermediate_flags(2)
);
GF_2_10_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(0),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_10_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
reg_value3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(8),
clk => clk,
ce => '1',
q => intermediate_values(9)
);
reg_previous3_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(1),
clk => clk,
ce => '1',
q => previous_values_1(2)
);
reg_previous3_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(7),
clk => clk,
ce => '1',
q => previous_values_15(0)
);
reg_flag3 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(2),
clk => clk,
ce => '1',
q(0) => intermediate_flags(3)
);
GF_2_10_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_10_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_10_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
reg_value4 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(12),
clk => clk,
ce => '1',
q => intermediate_values(13)
);
reg_previous4_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(2),
clk => clk,
ce => '1',
q => previous_values_1(3)
);
reg_previous4_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_15(0),
clk => clk,
ce => '1',
q => previous_values_15(1)
);
reg_flag4 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(3),
clk => clk,
ce => '1',
q(0) => intermediate_flags(4)
);
GF_2_10_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_15(1),
b => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_10_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
reg_value5 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(15),
clk => clk,
ce => '1',
q => intermediate_values(16)
);
reg_previous5_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(3),
clk => clk,
ce => '1',
q => previous_values_1(4)
);
reg_flag5 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(4),
clk => clk,
ce => '1',
q(0) => intermediate_flags(5)
);
GF_2_10_op_11 : mult_gf_2_m -- a^511
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_1(4),
b => intermediate_values(16),
o => intermediate_values(17)
);
GF_2_10_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1022
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(17),
o => intermediate_values(18)
);
o <= intermediate_values(18);
oflag <= intermediate_flags(5);
end generate;
GF_2_11 : if gf_2_m = 11 generate -- x^11 + x^2 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_11_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_11_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_11_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_11_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
reg_value2 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(5),
clk => clk,
ce => '1',
q => intermediate_values(6)
);
reg_previous2_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(3),
clk => clk,
ce => '1',
q => previous_values_3(0)
);
reg_flag2 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(1),
clk => clk,
ce => '1',
q(0) => intermediate_flags(2)
);
GF_2_11_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(0),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_11_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
reg_value3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(8),
clk => clk,
ce => '1',
q => intermediate_values(9)
);
reg_previous3_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(0),
clk => clk,
ce => '1',
q => previous_values_3(1)
);
reg_previous3_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(7),
clk => clk,
ce => '1',
q => previous_values_15(0)
);
reg_flag3 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(2),
clk => clk,
ce => '1',
q(0) => intermediate_flags(3)
);
GF_2_11_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_11_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_11_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
reg_value4 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(12),
clk => clk,
ce => '1',
q => intermediate_values(13)
);
reg_previous4_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(1),
clk => clk,
ce => '1',
q => previous_values_3(2)
);
reg_previous4_7 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_15(0),
clk => clk,
ce => '1',
q => previous_values_15(1)
);
reg_flag4 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(3),
clk => clk,
ce => '1',
q(0) => intermediate_flags(4)
);
GF_2_11_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_15(1),
b => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_11_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
reg_value5 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(15),
clk => clk,
ce => '1',
q => intermediate_values(16)
);
reg_previous5_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(2),
clk => clk,
ce => '1',
q => previous_values_3(3)
);
reg_flag5 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(4),
clk => clk,
ce => '1',
q(0) => intermediate_flags(5)
);
GF_2_11_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(16),
o => intermediate_values(17)
);
GF_2_11_op_12 : mult_gf_2_m -- a^1023
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(3),
b => intermediate_values(17),
o => intermediate_values(18)
);
reg_value6 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(18),
clk => clk,
ce => '1',
q => intermediate_values(19)
);
reg_flag6 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(5),
clk => clk,
ce => '1',
q(0) => intermediate_flags(6)
);
GF_2_11_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2046
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(19),
o => intermediate_values(20)
);
o <= intermediate_values(20);
oflag <= intermediate_flags(6);
end generate;
GF_2_12 : if gf_2_m = 12 generate -- x^12 + x^3 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_12_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_12_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_previous1_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(0),
clk => clk,
ce => '1',
q => previous_values_1(0)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_12_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_12_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
reg_value2 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(5),
clk => clk,
ce => '1',
q => intermediate_values(6)
);
reg_previous2_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(0),
clk => clk,
ce => '1',
q => previous_values_1(1)
);
reg_previous2_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(3),
clk => clk,
ce => '1',
q => previous_values_3(0)
);
reg_flag2 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(1),
clk => clk,
ce => '1',
q(0) => intermediate_flags(2)
);
GF_2_12_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(0),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_12_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
reg_value3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(8),
clk => clk,
ce => '1',
q => intermediate_values(9)
);
reg_previous3_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(1),
clk => clk,
ce => '1',
q => previous_values_1(2)
);
reg_previous3_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(0),
clk => clk,
ce => '1',
q => previous_values_3(1)
);
reg_previous3_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(7),
clk => clk,
ce => '1',
q => previous_values_15(0)
);
reg_flag3 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(2),
clk => clk,
ce => '1',
q(0) => intermediate_flags(3)
);
GF_2_12_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_12_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_12_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
reg_value4 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(12),
clk => clk,
ce => '1',
q => intermediate_values(13)
);
reg_previous4_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(2),
clk => clk,
ce => '1',
q => previous_values_1(3)
);
reg_previous4_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(1),
clk => clk,
ce => '1',
q => previous_values_3(2)
);
reg_previous4_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_15(0),
clk => clk,
ce => '1',
q => previous_values_15(1)
);
reg_flag4 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(3),
clk => clk,
ce => '1',
q(0) => intermediate_flags(4)
);
GF_2_12_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_15(1),
b => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_12_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
reg_value5 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(15),
clk => clk,
ce => '1',
q => intermediate_values(16)
);
reg_previous5_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(3),
clk => clk,
ce => '1',
q => previous_values_1(4)
);
reg_previous5_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(2),
clk => clk,
ce => '1',
q => previous_values_3(3)
);
reg_flag5 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(4),
clk => clk,
ce => '1',
q(0) => intermediate_flags(5)
);
GF_2_12_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(16),
o => intermediate_values(17)
);
GF_2_12_op_12 : mult_gf_2_m -- a^1023
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(3),
b => intermediate_values(17),
o => intermediate_values(18)
);
reg_value6 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(18),
clk => clk,
ce => '1',
q => intermediate_values(19)
);
reg_previous6_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(4),
clk => clk,
ce => '1',
q => previous_values_1(5)
);
reg_flag6 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(5),
clk => clk,
ce => '1',
q(0) => intermediate_flags(6)
);
GF_2_12_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2046
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(19),
o => intermediate_values(20)
);
GF_2_12_op_14 : mult_gf_2_m -- a^2047
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_1(5),
b => intermediate_values(20),
o => intermediate_values(21)
);
reg_value7 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(21),
clk => clk,
ce => '1',
q => intermediate_values(22)
);
reg_flag7 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(6),
clk => clk,
ce => '1',
q(0) => intermediate_flags(7)
);
GF_2_12_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4094
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(22),
o => intermediate_values(23)
);
o <= intermediate_values(23);
oflag <= intermediate_flags(7);
end generate;
GF_2_13 : if gf_2_m = 13 generate -- x^13 + x^4 + x^3 + x^1 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_13_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_13_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_13_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_13_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
reg_value2 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(5),
clk => clk,
ce => '1',
q => intermediate_values(6)
);
reg_previous2_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(3),
clk => clk,
ce => '1',
q => previous_values_3(0)
);
reg_flag2 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(1),
clk => clk,
ce => '1',
q(0) => intermediate_flags(2)
);
GF_2_13_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(0),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_13_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
reg_value3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(8),
clk => clk,
ce => '1',
q => intermediate_values(9)
);
reg_previous3_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(7),
clk => clk,
ce => '1',
q => previous_values_15(0)
);
reg_flag3 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(2),
clk => clk,
ce => '1',
q(0) => intermediate_flags(3)
);
GF_2_13_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_13_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_13_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
reg_value4 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(12),
clk => clk,
ce => '1',
q => intermediate_values(13)
);
reg_previous4_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_15(0),
clk => clk,
ce => '1',
q => previous_values_15(1)
);
reg_flag4 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(3),
clk => clk,
ce => '1',
q(0) => intermediate_flags(4)
);
GF_2_13_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_15(1),
b => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_13_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
reg_value5 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(15),
clk => clk,
ce => '1',
q => intermediate_values(16)
);
reg_previous5_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_15(1),
clk => clk,
ce => '1',
q => previous_values_15(2)
);
reg_flag5 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(4),
clk => clk,
ce => '1',
q(0) => intermediate_flags(5)
);
GF_2_13_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(16),
o => intermediate_values(17)
);
GF_2_13_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2040
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(17),
o => intermediate_values(18)
);
GF_2_13_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4080
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(18),
o => intermediate_values(19)
);
reg_value6 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(19),
clk => clk,
ce => '1',
q => intermediate_values(20)
);
reg_previous6_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_15(2),
clk => clk,
ce => '1',
q => previous_values_15(3)
);
reg_flag6 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(5),
clk => clk,
ce => '1',
q(0) => intermediate_flags(6)
);
GF_2_13_op_14 : mult_gf_2_m -- a^4095
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_15(3),
b => intermediate_values(20),
o => intermediate_values(21)
);
GF_2_13_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^8190
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(21),
o => intermediate_values(22)
);
o <= intermediate_values(22);
oflag <= intermediate_flags(6);
end generate;
GF_2_14 : if gf_2_m = 14 generate -- x^14 + x^5 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_14_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_14_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_previous1_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(0),
clk => clk,
ce => '1',
q => previous_values_1(0)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_14_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_14_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
reg_value2 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(5),
clk => clk,
ce => '1',
q => intermediate_values(6)
);
reg_previous2_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(0),
clk => clk,
ce => '1',
q => previous_values_1(1)
);
reg_previous2_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(3),
clk => clk,
ce => '1',
q => previous_values_3(0)
);
reg_flag2 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(1),
clk => clk,
ce => '1',
q(0) => intermediate_flags(2)
);
GF_2_14_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(0),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_14_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
reg_value3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(8),
clk => clk,
ce => '1',
q => intermediate_values(9)
);
reg_previous3_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(1),
clk => clk,
ce => '1',
q => previous_values_1(2)
);
reg_previous3_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(7),
clk => clk,
ce => '1',
q => previous_values_15(0)
);
reg_flag3 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(2),
clk => clk,
ce => '1',
q(0) => intermediate_flags(3)
);
GF_2_14_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_14_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_14_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
reg_value4 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(12),
clk => clk,
ce => '1',
q => intermediate_values(13)
);
reg_previous4_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(2),
clk => clk,
ce => '1',
q => previous_values_1(3)
);
reg_previous4_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_15(0),
clk => clk,
ce => '1',
q => previous_values_15(1)
);
reg_flag4 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(3),
clk => clk,
ce => '1',
q(0) => intermediate_flags(4)
);
GF_2_14_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_15(1),
b => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_14_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
reg_value5 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(15),
clk => clk,
ce => '1',
q => intermediate_values(16)
);
reg_previous5_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(3),
clk => clk,
ce => '1',
q => previous_values_1(4)
);
reg_previous5_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_15(1),
clk => clk,
ce => '1',
q => previous_values_15(2)
);
reg_flag5 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(4),
clk => clk,
ce => '1',
q(0) => intermediate_flags(5)
);
GF_2_14_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(16),
o => intermediate_values(17)
);
GF_2_14_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2040
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(17),
o => intermediate_values(18)
);
GF_2_14_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4080
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(18),
o => intermediate_values(19)
);
reg_value6 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(19),
clk => clk,
ce => '1',
q => intermediate_values(20)
);
reg_previous6_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(4),
clk => clk,
ce => '1',
q => previous_values_1(5)
);
reg_previous6_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_15(2),
clk => clk,
ce => '1',
q => previous_values_15(3)
);
reg_flag6 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(5),
clk => clk,
ce => '1',
q(0) => intermediate_flags(6)
);
GF_2_14_op_14 : mult_gf_2_m -- a^4095
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_15(3),
b => intermediate_values(20),
o => intermediate_values(21)
);
GF_2_14_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^8190
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(21),
o => intermediate_values(22)
);
reg_value7 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(22),
clk => clk,
ce => '1',
q => intermediate_values(23)
);
reg_previous7_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(5),
clk => clk,
ce => '1',
q => previous_values_1(6)
);
reg_flag7 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(6),
clk => clk,
ce => '1',
q(0) => intermediate_flags(7)
);
GF_2_14_op_16 : mult_gf_2_m -- a^8191
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_1(6),
b => intermediate_values(23),
o => intermediate_values(24)
);
GF_2_14_op_17 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^16382
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(24),
o => intermediate_values(25)
);
o <= intermediate_values(25);
oflag <= intermediate_flags(7);
end generate;
GF_2_15 : if gf_2_m = 15 generate -- x^15 + x^1 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_15_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_15_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_15_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_15_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
reg_value2 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(5),
clk => clk,
ce => '1',
q => intermediate_values(6)
);
reg_previous2_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(3),
clk => clk,
ce => '1',
q => previous_values_3(0)
);
reg_flag2 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(1),
clk => clk,
ce => '1',
q(0) => intermediate_flags(2)
);
GF_2_15_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(0),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_15_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
reg_value3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(8),
clk => clk,
ce => '1',
q => intermediate_values(9)
);
reg_previous3_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(0),
clk => clk,
ce => '1',
q => previous_values_3(1)
);
reg_previous3_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(7),
clk => clk,
ce => '1',
q => previous_values_15(0)
);
reg_flag3 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(2),
clk => clk,
ce => '1',
q(0) => intermediate_flags(3)
);
GF_2_15_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_15_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_15_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
reg_value4 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(12),
clk => clk,
ce => '1',
q => intermediate_values(13)
);
reg_previous4_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(1),
clk => clk,
ce => '1',
q => previous_values_3(2)
);
reg_previous4_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_15(0),
clk => clk,
ce => '1',
q => previous_values_15(1)
);
reg_flag4 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(3),
clk => clk,
ce => '1',
q(0) => intermediate_flags(4)
);
GF_2_15_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_15(1),
b => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_15_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
reg_value5 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(15),
clk => clk,
ce => '1',
q => intermediate_values(16)
);
reg_previous5_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(2),
clk => clk,
ce => '1',
q => previous_values_3(3)
);
reg_previous5_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_15(1),
clk => clk,
ce => '1',
q => previous_values_15(2)
);
reg_flag5 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(4),
clk => clk,
ce => '1',
q(0) => intermediate_flags(5)
);
GF_2_15_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(16),
o => intermediate_values(17)
);
GF_2_15_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2040
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(17),
o => intermediate_values(18)
);
GF_2_15_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4080
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(18),
o => intermediate_values(19)
);
reg_value6 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(19),
clk => clk,
ce => '1',
q => intermediate_values(20)
);
reg_previous6_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(3),
clk => clk,
ce => '1',
q => previous_values_3(4)
);
reg_previous6_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_15(2),
clk => clk,
ce => '1',
q => previous_values_15(3)
);
reg_flag6 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(5),
clk => clk,
ce => '1',
q(0) => intermediate_flags(6)
);
GF_2_15_op_14 : mult_gf_2_m -- a^4095
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_15(3),
b => intermediate_values(20),
o => intermediate_values(21)
);
GF_2_15_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^8190
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(21),
o => intermediate_values(22)
);
reg_value7 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(22),
clk => clk,
ce => '1',
q => intermediate_values(23)
);
reg_previous7_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(4),
clk => clk,
ce => '1',
q => previous_values_3(5)
);
reg_flag7 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(6),
clk => clk,
ce => '1',
q(0) => intermediate_flags(7)
);
GF_2_15_op_16 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^16380
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(23),
o => intermediate_values(24)
);
GF_2_15_op_17 : mult_gf_2_m -- a^16383
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(5),
b => intermediate_values(24),
o => intermediate_values(25)
);
reg_value8 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(25),
clk => clk,
ce => '1',
q => intermediate_values(26)
);
reg_flag8 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(7),
clk => clk,
ce => '1',
q(0) => intermediate_flags(8)
);
GF_2_15_op_18 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^32766
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(26),
o => intermediate_values(27)
);
o <= intermediate_values(27);
oflag <= intermediate_flags(8);
end generate;
GF_2_16 : if gf_2_m = 16 generate -- x^16 + x^5 + x^3 + x^1 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_16_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_16_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_previous1_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(0),
clk => clk,
ce => '1',
q => previous_values_1(0)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_16_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_16_op_3 : mult_gf_2_m -- a^7
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_1(0),
b => intermediate_values(4),
o => intermediate_values(5)
);
reg_value2 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(5),
clk => clk,
ce => '1',
q => intermediate_values(6)
);
reg_flag2 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(1),
clk => clk,
ce => '1',
q(0) => intermediate_flags(2)
);
GF_2_16_op_4 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^14
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_16_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^28
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
GF_2_16_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^56
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(8),
o => intermediate_values(9)
);
reg_value3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(9),
clk => clk,
ce => '1',
q => intermediate_values(10)
);
reg_previous3_7 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(6),
clk => clk,
ce => '1',
q => previous_values_7(0)
);
reg_flag3 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(2),
clk => clk,
ce => '1',
q(0) => intermediate_flags(3)
);
GF_2_16_op_7 : mult_gf_2_m -- a^63
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_7(0),
b => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_16_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^126
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
reg_value4 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(12),
clk => clk,
ce => '1',
q => intermediate_values(13)
);
reg_previous4_7 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_7(0),
clk => clk,
ce => '1',
q => previous_values_7(1)
);
reg_previous4_63 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(11),
clk => clk,
ce => '1',
q => previous_values_63(0)
);
reg_flag4 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(3),
clk => clk,
ce => '1',
q(0) => intermediate_flags(4)
);
GF_2_16_op_9 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^252
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_16_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^504
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
GF_2_16_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1008
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(15),
o => intermediate_values(16)
);
reg_value5 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(16),
clk => clk,
ce => '1',
q => intermediate_values(17)
);
reg_previous5_7 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_7(1),
clk => clk,
ce => '1',
q => previous_values_7(2)
);
reg_previous5_63 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_63(0),
clk => clk,
ce => '1',
q => previous_values_63(1)
);
reg_flag5 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(4),
clk => clk,
ce => '1',
q(0) => intermediate_flags(5)
);
GF_2_16_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2016
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(17),
o => intermediate_values(18)
);
GF_2_16_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4032
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(18),
o => intermediate_values(19)
);
reg_value6 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(19),
clk => clk,
ce => '1',
q => intermediate_values(20)
);
reg_previous6_7 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_7(2),
clk => clk,
ce => '1',
q => previous_values_7(3)
);
reg_previous6_63 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_63(1),
clk => clk,
ce => '1',
q => previous_values_63(2)
);
reg_flag6 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(5),
clk => clk,
ce => '1',
q(0) => intermediate_flags(6)
);
GF_2_16_op_14 : mult_gf_2_m -- a^4095
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_63(2),
b => intermediate_values(20),
o => intermediate_values(21)
);
GF_2_16_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^8190
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(21),
o => intermediate_values(22)
);
reg_value7 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(22),
clk => clk,
ce => '1',
q => intermediate_values(23)
);
reg_previous7_7 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_7(3),
clk => clk,
ce => '1',
q => previous_values_7(4)
);
reg_flag7 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(6),
clk => clk,
ce => '1',
q(0) => intermediate_flags(7)
);
GF_2_16_op_16 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^16380
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(23),
o => intermediate_values(24)
);
GF_2_16_op_17 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^32760
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(24),
o => intermediate_values(25)
);
reg_value8 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(25),
clk => clk,
ce => '1',
q => intermediate_values(26)
);
reg_previous8_7 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_7(4),
clk => clk,
ce => '1',
q => previous_values_7(5)
);
reg_flag8 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(7),
clk => clk,
ce => '1',
q(0) => intermediate_flags(8)
);
GF_2_16_op_18 : mult_gf_2_m -- a^32767
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_7(5),
b => intermediate_values(26),
o => intermediate_values(27)
);
GF_2_16_op_19 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^65534
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(27),
o => intermediate_values(28)
);
o <= intermediate_values(28);
oflag <= intermediate_flags(8);
end generate;
GF_2_17 : if gf_2_m = 17 generate -- x^17 + x^3 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_17_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_17_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_17_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_17_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
reg_value2 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(5),
clk => clk,
ce => '1',
q => intermediate_values(6)
);
reg_previous2_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(3),
clk => clk,
ce => '1',
q => previous_values_3(0)
);
reg_flag2 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(1),
clk => clk,
ce => '1',
q(0) => intermediate_flags(2)
);
GF_2_17_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(0),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_17_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
reg_value3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(8),
clk => clk,
ce => '1',
q => intermediate_values(9)
);
reg_previous3_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(7),
clk => clk,
ce => '1',
q => previous_values_15(0)
);
reg_flag3 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(2),
clk => clk,
ce => '1',
q(0) => intermediate_flags(3)
);
GF_2_17_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_17_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_17_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
reg_value4 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(12),
clk => clk,
ce => '1',
q => intermediate_values(13)
);
reg_previous4_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_15(0),
clk => clk,
ce => '1',
q => previous_values_15(1)
);
reg_flag4 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(3),
clk => clk,
ce => '1',
q(0) => intermediate_flags(4)
);
GF_2_17_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_15(1),
b => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_17_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
reg_value5 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(15),
clk => clk,
ce => '1',
q => intermediate_values(16)
);
reg_previous5_255 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(14),
clk => clk,
ce => '1',
q => previous_values_255(0)
);
reg_flag5 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(4),
clk => clk,
ce => '1',
q(0) => intermediate_flags(5)
);
GF_2_17_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(16),
o => intermediate_values(17)
);
GF_2_17_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2040
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(17),
o => intermediate_values(18)
);
GF_2_17_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4080
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(18),
o => intermediate_values(19)
);
reg_value6 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(19),
clk => clk,
ce => '1',
q => intermediate_values(20)
);
reg_previous6_255 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_255(0),
clk => clk,
ce => '1',
q => previous_values_255(1)
);
reg_flag6 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(5),
clk => clk,
ce => '1',
q(0) => intermediate_flags(6)
);
GF_2_17_op_14 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^8160
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(20),
o => intermediate_values(21)
);
GF_2_17_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^16320
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(21),
o => intermediate_values(22)
);
GF_2_17_op_16 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^32640
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(22),
o => intermediate_values(23)
);
reg_value7 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(23),
clk => clk,
ce => '1',
q => intermediate_values(24)
);
reg_previous7_255 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_255(1),
clk => clk,
ce => '1',
q => previous_values_255(2)
);
reg_flag7 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(6),
clk => clk,
ce => '1',
q(0) => intermediate_flags(7)
);
GF_2_17_op_17 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^65280
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(24),
o => intermediate_values(25)
);
GF_2_17_op_18 : mult_gf_2_m -- a^65535
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_255(2),
b => intermediate_values(25),
o => intermediate_values(26)
);
reg_value8 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(26),
clk => clk,
ce => '1',
q => intermediate_values(27)
);
reg_flag8 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(7),
clk => clk,
ce => '1',
q(0) => intermediate_flags(8)
);
GF_2_17_op_19 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^131070
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(27),
o => intermediate_values(28)
);
o <= intermediate_values(28);
oflag <= intermediate_flags(8);
end generate;
GF_2_18 : if gf_2_m = 18 generate -- x^18 + x^3 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_18_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_18_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_previous1_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(0),
clk => clk,
ce => '1',
q => previous_values_1(0)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_18_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_18_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
reg_value2 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(5),
clk => clk,
ce => '1',
q => intermediate_values(6)
);
reg_previous2_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(0),
clk => clk,
ce => '1',
q => previous_values_1(1)
);
reg_previous2_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(3),
clk => clk,
ce => '1',
q => previous_values_3(0)
);
reg_flag2 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(1),
clk => clk,
ce => '1',
q(0) => intermediate_flags(2)
);
GF_2_18_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(0),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_18_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
reg_value3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(8),
clk => clk,
ce => '1',
q => intermediate_values(9)
);
reg_previous3_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(1),
clk => clk,
ce => '1',
q => previous_values_1(2)
);
reg_previous3_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(7),
clk => clk,
ce => '1',
q => previous_values_15(0)
);
reg_flag3 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(2),
clk => clk,
ce => '1',
q(0) => intermediate_flags(3)
);
GF_2_18_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_18_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_18_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
reg_value4 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(12),
clk => clk,
ce => '1',
q => intermediate_values(13)
);
reg_previous4_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(2),
clk => clk,
ce => '1',
q => previous_values_1(3)
);
reg_previous4_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_15(0),
clk => clk,
ce => '1',
q => previous_values_15(1)
);
reg_flag4 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(3),
clk => clk,
ce => '1',
q(0) => intermediate_flags(4)
);
GF_2_18_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_15(1),
b => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_18_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
reg_value5 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(15),
clk => clk,
ce => '1',
q => intermediate_values(16)
);
reg_previous5_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(3),
clk => clk,
ce => '1',
q => previous_values_1(4)
);
reg_previous5_255 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(14),
clk => clk,
ce => '1',
q => previous_values_255(0)
);
reg_flag5 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(4),
clk => clk,
ce => '1',
q(0) => intermediate_flags(5)
);
GF_2_18_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(16),
o => intermediate_values(17)
);
GF_2_18_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2040
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(17),
o => intermediate_values(18)
);
GF_2_18_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4080
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(18),
o => intermediate_values(19)
);
reg_value6 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(19),
clk => clk,
ce => '1',
q => intermediate_values(20)
);
reg_previous6_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(4),
clk => clk,
ce => '1',
q => previous_values_1(5)
);
reg_previous6_255 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_255(0),
clk => clk,
ce => '1',
q => previous_values_255(1)
);
reg_flag6 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(5),
clk => clk,
ce => '1',
q(0) => intermediate_flags(6)
);
GF_2_18_op_14 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^8160
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(20),
o => intermediate_values(21)
);
GF_2_18_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^16320
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(21),
o => intermediate_values(22)
);
GF_2_18_op_16 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^32640
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(22),
o => intermediate_values(23)
);
reg_value7 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(23),
clk => clk,
ce => '1',
q => intermediate_values(24)
);
reg_previous7_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(5),
clk => clk,
ce => '1',
q => previous_values_1(6)
);
reg_previous7_255 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_255(1),
clk => clk,
ce => '1',
q => previous_values_255(2)
);
reg_flag7 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(6),
clk => clk,
ce => '1',
q(0) => intermediate_flags(7)
);
GF_2_18_op_17 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^65280
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(24),
o => intermediate_values(25)
);
GF_2_18_op_18 : mult_gf_2_m -- a^65535
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_255(2),
b => intermediate_values(25),
o => intermediate_values(26)
);
reg_value8 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(26),
clk => clk,
ce => '1',
q => intermediate_values(27)
);
reg_previous8_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(6),
clk => clk,
ce => '1',
q => previous_values_1(7)
);
reg_flag8 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(7),
clk => clk,
ce => '1',
q(0) => intermediate_flags(8)
);
GF_2_18_op_19 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^131070
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(27),
o => intermediate_values(28)
);
GF_2_18_op_20 : mult_gf_2_m -- a^131071
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_1(7),
b => intermediate_values(28),
o => intermediate_values(29)
);
reg_value9 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(29),
clk => clk,
ce => '1',
q => intermediate_values(30)
);
reg_flag9 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(8),
clk => clk,
ce => '1',
q(0) => intermediate_flags(9)
);
GF_2_18_op_21 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^262142
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(30),
o => intermediate_values(31)
);
o <= intermediate_values(31);
oflag <= intermediate_flags(9);
end generate;
GF_2_19 : if gf_2_m = 19 generate -- x^19 + x^5 + x^2 + x^1 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_19_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_19_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_19_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_19_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
reg_value2 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(5),
clk => clk,
ce => '1',
q => intermediate_values(6)
);
reg_previous2_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(3),
clk => clk,
ce => '1',
q => previous_values_3(0)
);
reg_flag2 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(1),
clk => clk,
ce => '1',
q(0) => intermediate_flags(2)
);
GF_2_19_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(0),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_19_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
reg_value3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(8),
clk => clk,
ce => '1',
q => intermediate_values(9)
);
reg_previous3_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(0),
clk => clk,
ce => '1',
q => previous_values_3(1)
);
reg_previous3_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(7),
clk => clk,
ce => '1',
q => previous_values_15(0)
);
reg_flag3 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(2),
clk => clk,
ce => '1',
q(0) => intermediate_flags(3)
);
GF_2_19_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_19_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_19_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
reg_value4 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(12),
clk => clk,
ce => '1',
q => intermediate_values(13)
);
reg_previous4_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(1),
clk => clk,
ce => '1',
q => previous_values_3(2)
);
reg_previous4_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_15(0),
clk => clk,
ce => '1',
q => previous_values_15(1)
);
reg_flag4 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(3),
clk => clk,
ce => '1',
q(0) => intermediate_flags(4)
);
GF_2_19_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_15(1),
b => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_19_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
reg_value5 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(15),
clk => clk,
ce => '1',
q => intermediate_values(16)
);
reg_previous5_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(2),
clk => clk,
ce => '1',
q => previous_values_3(3)
);
reg_previous5_255 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(14),
clk => clk,
ce => '1',
q => previous_values_255(0)
);
reg_flag5 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(4),
clk => clk,
ce => '1',
q(0) => intermediate_flags(5)
);
GF_2_19_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(16),
o => intermediate_values(17)
);
GF_2_19_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2040
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(17),
o => intermediate_values(18)
);
GF_2_19_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4080
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(18),
o => intermediate_values(19)
);
reg_value6 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(19),
clk => clk,
ce => '1',
q => intermediate_values(20)
);
reg_previous6_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(3),
clk => clk,
ce => '1',
q => previous_values_3(4)
);
reg_previous6_255 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_255(0),
clk => clk,
ce => '1',
q => previous_values_255(1)
);
reg_flag6 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(5),
clk => clk,
ce => '1',
q(0) => intermediate_flags(6)
);
GF_2_19_op_14 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^8160
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(20),
o => intermediate_values(21)
);
GF_2_19_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^16320
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(21),
o => intermediate_values(22)
);
GF_2_19_op_16 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^32640
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(22),
o => intermediate_values(23)
);
reg_value7 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(23),
clk => clk,
ce => '1',
q => intermediate_values(24)
);
reg_previous7_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(4),
clk => clk,
ce => '1',
q => previous_values_3(5)
);
reg_previous7_255 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_255(1),
clk => clk,
ce => '1',
q => previous_values_255(2)
);
reg_flag7 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(6),
clk => clk,
ce => '1',
q(0) => intermediate_flags(7)
);
GF_2_19_op_17 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^65280
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(24),
o => intermediate_values(25)
);
GF_2_19_op_18 : mult_gf_2_m -- a^65535
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_255(2),
b => intermediate_values(25),
o => intermediate_values(26)
);
reg_value8 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(26),
clk => clk,
ce => '1',
q => intermediate_values(27)
);
reg_previous8_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(5),
clk => clk,
ce => '1',
q => previous_values_3(6)
);
reg_flag8 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(7),
clk => clk,
ce => '1',
q(0) => intermediate_flags(8)
);
GF_2_19_op_19 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^131070
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(27),
o => intermediate_values(28)
);
GF_2_19_op_20 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^262140
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(28),
o => intermediate_values(29)
);
reg_value9 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(29),
clk => clk,
ce => '1',
q => intermediate_values(30)
);
reg_previous9_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(6),
clk => clk,
ce => '1',
q => previous_values_3(7)
);
reg_flag9 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(8),
clk => clk,
ce => '1',
q(0) => intermediate_flags(9)
);
GF_2_19_op_21 : mult_gf_2_m -- a^262143
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(7),
b => intermediate_values(30),
o => intermediate_values(31)
);
GF_2_19_op_22 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^524286
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(31),
o => intermediate_values(32)
);
o <= intermediate_values(32);
oflag <= intermediate_flags(9);
end generate;
GF_2_20 : if gf_2_m = 20 generate -- x^20 + x^3 + 1
reg_value0 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => a,
clk => clk,
ce => '1',
q => intermediate_values(0)
);
reg_flag0 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => flag,
clk => clk,
ce => '1',
q(0) => intermediate_flags(0)
);
GF_2_20_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_20_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(0),
b => intermediate_values(1),
o => intermediate_values(2)
);
reg_value1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(2),
clk => clk,
ce => '1',
q => intermediate_values(3)
);
reg_previous1_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(0),
clk => clk,
ce => '1',
q => previous_values_1(0)
);
reg_flag1 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(0),
clk => clk,
ce => '1',
q(0) => intermediate_flags(1)
);
GF_2_20_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_20_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
reg_value2 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(5),
clk => clk,
ce => '1',
q => intermediate_values(6)
);
reg_previous2_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(0),
clk => clk,
ce => '1',
q => previous_values_1(1)
);
reg_previous2_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(3),
clk => clk,
ce => '1',
q => previous_values_3(0)
);
reg_flag2 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(1),
clk => clk,
ce => '1',
q(0) => intermediate_flags(2)
);
GF_2_20_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(0),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_20_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
reg_value3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(8),
clk => clk,
ce => '1',
q => intermediate_values(9)
);
reg_previous3_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(1),
clk => clk,
ce => '1',
q => previous_values_1(2)
);
reg_previous3_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(0),
clk => clk,
ce => '1',
q => previous_values_3(1)
);
reg_previous3_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(7),
clk => clk,
ce => '1',
q => previous_values_15(0)
);
reg_flag3 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(2),
clk => clk,
ce => '1',
q(0) => intermediate_flags(3)
);
GF_2_20_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_20_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_20_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
reg_value4 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(12),
clk => clk,
ce => '1',
q => intermediate_values(13)
);
reg_previous4_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(2),
clk => clk,
ce => '1',
q => previous_values_1(3)
);
reg_previous4_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(1),
clk => clk,
ce => '1',
q => previous_values_3(2)
);
reg_previous4_15 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_15(0),
clk => clk,
ce => '1',
q => previous_values_15(1)
);
reg_flag4 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(3),
clk => clk,
ce => '1',
q(0) => intermediate_flags(4)
);
GF_2_20_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_15(1),
b => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_20_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
reg_value5 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(15),
clk => clk,
ce => '1',
q => intermediate_values(16)
);
reg_previous5_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(3),
clk => clk,
ce => '1',
q => previous_values_1(4)
);
reg_previous5_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(2),
clk => clk,
ce => '1',
q => previous_values_3(3)
);
reg_previous5_255 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(14),
clk => clk,
ce => '1',
q => previous_values_255(0)
);
reg_flag5 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(4),
clk => clk,
ce => '1',
q(0) => intermediate_flags(5)
);
GF_2_20_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(16),
o => intermediate_values(17)
);
GF_2_20_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2040
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(17),
o => intermediate_values(18)
);
GF_2_20_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4080
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(18),
o => intermediate_values(19)
);
reg_value6 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(19),
clk => clk,
ce => '1',
q => intermediate_values(20)
);
reg_previous6_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(4),
clk => clk,
ce => '1',
q => previous_values_1(5)
);
reg_previous6_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(3),
clk => clk,
ce => '1',
q => previous_values_3(4)
);
reg_previous6_255 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_255(0),
clk => clk,
ce => '1',
q => previous_values_255(1)
);
reg_flag6 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(5),
clk => clk,
ce => '1',
q(0) => intermediate_flags(6)
);
GF_2_20_op_14 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^8160
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(20),
o => intermediate_values(21)
);
GF_2_20_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^16320
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(21),
o => intermediate_values(22)
);
GF_2_20_op_16 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^32640
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(22),
o => intermediate_values(23)
);
reg_value7 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(23),
clk => clk,
ce => '1',
q => intermediate_values(24)
);
reg_previous7_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(5),
clk => clk,
ce => '1',
q => previous_values_1(6)
);
reg_previous7_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(4),
clk => clk,
ce => '1',
q => previous_values_3(5)
);
reg_previous7_255 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_255(1),
clk => clk,
ce => '1',
q => previous_values_255(2)
);
reg_flag7 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(6),
clk => clk,
ce => '1',
q(0) => intermediate_flags(7)
);
GF_2_20_op_17 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^65280
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(24),
o => intermediate_values(25)
);
GF_2_20_op_18 : mult_gf_2_m -- a^65535
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_255(2),
b => intermediate_values(25),
o => intermediate_values(26)
);
reg_value8 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(26),
clk => clk,
ce => '1',
q => intermediate_values(27)
);
reg_previous8_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(6),
clk => clk,
ce => '1',
q => previous_values_1(7)
);
reg_previous8_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(5),
clk => clk,
ce => '1',
q => previous_values_3(6)
);
reg_flag8 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(7),
clk => clk,
ce => '1',
q(0) => intermediate_flags(8)
);
GF_2_20_op_19 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^131070
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(27),
o => intermediate_values(28)
);
GF_2_20_op_20 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^262140
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(28),
o => intermediate_values(29)
);
reg_value9 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(29),
clk => clk,
ce => '1',
q => intermediate_values(30)
);
reg_previous9_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(7),
clk => clk,
ce => '1',
q => previous_values_1(8)
);
reg_previous9_3 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_3(6),
clk => clk,
ce => '1',
q => previous_values_3(7)
);
reg_flag9 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(8),
clk => clk,
ce => '1',
q(0) => intermediate_flags(9)
);
GF_2_20_op_21 : mult_gf_2_m -- a^262143
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_3(7),
b => intermediate_values(30),
o => intermediate_values(31)
);
GF_2_20_op_22 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^524286
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(31),
o => intermediate_values(32)
);
reg_value10 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => intermediate_values(32),
clk => clk,
ce => '1',
q => intermediate_values(33)
);
reg_previous10_1 : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => previous_values_1(8),
clk => clk,
ce => '1',
q => previous_values_1(9)
);
reg_flag10 : register_nbits
Generic Map(size => 1)
Port Map(
d(0) => intermediate_flags(9),
clk => clk,
ce => '1',
q(0) => intermediate_flags(10)
);
GF_2_20_op_23 : mult_gf_2_m -- a^524287
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => previous_values_1(9),
b => intermediate_values(33),
o => intermediate_values(34)
);
GF_2_20_op_24 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1048574
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(34),
o => intermediate_values(35)
);
o <= intermediate_values(35);
oflag <= intermediate_flags(10);
end generate;
end Behavioral;
|
bsd-2-clause
|
df6d0f1841b8a4aa593bc894d0f8cf5f
| 0.594873 | 2.357228 | false | false | false | false |
ruygargar/LCSE_lab
|
rs232/tb_RS232top.vhd
| 1 | 2,052 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RS232top_TB is
end RS232top_TB;
architecture Testbench of RS232top_TB is
component RS232top
port (
Reset : in std_logic;
Clk : in std_logic;
Data_in : in std_logic_vector(7 downto 0);
Valid_D : in std_logic;
Ack_in : out std_logic;
TX_RDY : out std_logic;
TD : out std_logic;
RD : in std_logic;
Data_out : out std_logic_vector(7 downto 0);
Data_read : in std_logic;
Full : out std_logic;
Empty : out std_logic);
end component;
signal Reset, Clk, Valid_D, Ack_in, TX_RDY : std_logic;
signal TD, RD, Data_read, Full, Empty : std_logic;
signal Data_out, Data_in : std_logic_vector(7 downto 0);
begin
UUT: RS232top
port map (
Reset => Reset,
Clk => Clk,
Data_in => Data_in,
Valid_D => Valid_D,
Ack_in => Ack_in,
TX_RDY => TX_RDY,
TD => TD,
RD => RD,
Data_out => Data_out,
Data_read => Data_read,
Full => Full,
Empty => Empty);
Data_in <= "10101010";
-- Clock generator
p_clk : PROCESS
BEGIN
clk <= '1', '0' after 25 ns;
wait for 50 ns;
END PROCESS;
-- Reset & Start generator
p_reset : PROCESS
BEGIN
reset <= '0', '1' after 10 ns;
Valid_D <= '1', '0' after 110 ns,
'1' after 400 ns;
RD <= '1',
'0' after 500 ns, -- StartBit
'1' after 9150 ns, -- LSb
'0' after 17800 ns,
'1' after 26450 ns,
'0' after 35100 ns,
'1' after 43750 ns,
'0' after 52400 ns,
'1' after 61050 ns,
'1' after 69700 ns, -- MSb
'1' after 78350 ns, -- Stopbit
'1' after 87000 ns;
Data_read <= '0','1'after 88000 ns;
wait for 100000 ns;
END PROCESS;
end Testbench;
|
gpl-3.0
|
af1957c0a5dc1260e7ec360b6af45a80
| 0.511696 | 3.226415 | false | false | false | false |
pwuertz/digitizer2fw
|
src/rtl/maxfinder_simple.vhd
| 1 | 5,119 |
-------------------------------------------------------------------------------
-- Simple interface to the maxfinder module
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.maxfinder_pkg.all;
use work.sampling_pkg.all;
entity maxfinder_simple is
generic (
N_FRAC_BITS: natural := 8;
N_ADIFF_CLIP: natural := 0
);
port (
clk: in std_logic;
samples_in: in a_samples_t(0 to 1);
threshold: in a_sample_t;
max_found: out std_logic;
max_pos: out unsigned(1+N_FRAC_BITS-1 downto 0);
max_height: out a_sample_t
);
end maxfinder_simple;
architecture maxfinder_simple_arch of maxfinder_simple is
component division_lut
generic (ROUND_FLOAT: boolean);
port (
clk: in std_logic;
clk_en: in std_logic;
divisor: in unsigned;
result: out unsigned
);
end component;
signal smax_samples_in: std_logic_vector(2*ADC_SAMPLE_BITS-1 downto 0);
signal smax_found: std_logic_vector(0 downto 0);
signal smax_pos: std_logic_vector(0 downto 0);
signal smax_adiff0: std_logic_vector(ADC_SAMPLE_BITS-1 downto 0);
signal smax_adiff1: std_logic_vector(ADC_SAMPLE_BITS-1 downto 0);
signal smax_sample0: std_logic_vector(ADC_SAMPLE_BITS-1 downto 0);
signal smax_sample1: std_logic_vector(ADC_SAMPLE_BITS-1 downto 0);
-- stage 0, prepare nominator and denominator for interpolation, average max samples
signal s0_nominator: unsigned(ADC_SAMPLE_BITS-N_ADIFF_CLIP-1 downto 0);
signal s0_denominator: unsigned(ADC_SAMPLE_BITS-N_ADIFF_CLIP downto 0);
signal s0_sample_avg: signed(ADC_SAMPLE_BITS-1 downto 0);
signal s0_valid: std_logic := '0';
signal s0_pos: unsigned(0 downto 0);
-- stage 1, calculate division and queue signals required at output
signal s1_nominator: unsigned(s0_nominator'range);
signal s1_division_result: unsigned(s0_denominator'high+1 downto 0);
signal s1_valid: std_logic;
signal s1_pos: unsigned(0 downto 0);
signal s1_sample_avg: signed(s0_sample_avg'range);
-- stage 2, multiply with d0 and register result
begin
stage0: process(clk)
variable denom: unsigned(s0_denominator'range);
variable sample0, sample1: signed(s0_sample_avg'high+1 downto 0);
begin
if rising_edge(clk) then
s0_nominator <= unsigned(smax_adiff0(s0_nominator'range));
denom := resize(unsigned(smax_adiff0(s0_nominator'range)), denom'length) + resize(unsigned(smax_adiff1(s0_nominator'range)), denom'length);
s0_denominator <= denom;
--
sample0 := resize(signed(smax_sample0), sample0'length);
sample1 := resize(signed(smax_sample1), sample0'length);
s0_sample_avg <= resize(shift_right(sample0 + sample1, 1), s0_sample_avg'length);
--
s0_valid <= smax_found(0);
s0_pos <= unsigned(smax_pos);
end if;
end process;
stage1_lut: division_lut
generic map (ROUND_FLOAT => FALSE) -- always convert to smaller result so the interpolation never exceeds 1.0 later
port map (
clk => clk,
clk_en => s0_valid,
divisor => s0_denominator,
result => s1_division_result
);
stage1: process(clk)
begin
if rising_edge(clk) then
s1_nominator <= s0_nominator;
s1_valid <= s0_valid;
s1_pos <= s0_pos;
s1_sample_avg <= s0_sample_avg;
end if;
end process;
stage2: process(clk)
variable x: unsigned(s1_nominator'length+s1_division_result'length-1 downto 0);
variable fraction: unsigned(N_FRAC_BITS-1 downto 0);
begin
if rising_edge(clk) then
x := s1_nominator * s1_division_result;
-- TODO: assert x(high downto s1_division_result'high) is zero
fraction := x(s1_division_result'high-1 downto s1_division_result'high-1 - (fraction'length-1));
max_found <= s1_valid;
if s1_valid = '1' then
max_pos <= s1_pos & fraction;
max_height <= s1_sample_avg;
else
max_pos <= (others => '-');
max_height <= (others => '0');
end if;
end if;
end process;
-------------------------------------------------------------------------------
smax_samples_in <= std_logic_vector(samples_in(1)) & std_logic_vector(samples_in(0));
maxfinder_inst: maxfinder_base
generic map (
N_WINDOW_LENGTH => 2,
N_OUTPUTS => 1,
N_SAMPLE_BITS => ADC_SAMPLE_BITS,
SYNC_STAGE1 => TRUE,
SYNC_STAGE2 => TRUE,
SYNC_STAGE3 => TRUE
)
port map (
clk => clk,
samples => smax_samples_in,
threshold => std_logic_vector(threshold),
max_found => smax_found,
max_pos => smax_pos,
max_adiff0 => smax_adiff0,
max_adiff1 => smax_adiff1,
max_sample0 => smax_sample0,
max_sample1 => smax_sample1
);
end maxfinder_simple_arch;
|
gpl-3.0
|
c95dc709e137b2fd55b32a546dd482d2
| 0.616843 | 3.50308 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/angle_step_applier/angle_step_applier.vhd
| 1 | 3,408 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--This component applies a step of the CORDIC algorithm acording to the accumulated angle.
entity angle_step_applier is
generic(TOTAL_BITS: integer := 32);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
z_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
step_index : in integer := 0;
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
z_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end angle_step_applier;
architecture angle_step_applier_arq of angle_step_applier is
signal lut_index : integer := 0;
signal arctg_lut_angle : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
component arctg_lut is
generic(TOTAL_BITS: integer := 32);
port(
step_index: in integer := 0;
angle: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
for arctg_lut_0 : arctg_lut use entity work.arctg_lut;
begin
arctg_lut_0 : arctg_lut
generic map(TOTAL_BITS => 32)
port map(
step_index => lut_index,
angle => arctg_lut_angle
);
process (x_in, y_in, z_in, step_index, lut_index, arctg_lut_angle) is
variable angle_offset : integer := 0;
variable d : integer := 0;
variable x_integer : integer := 0;
variable y_integer : integer := 0;
variable z_integer : integer := 0;
variable x_offset : integer := 0;
variable y_offset : integer := 0;
variable x_offset_vector : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
variable y_offset_vector : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
begin
--report integer'image(step_index);
--report integer'image(to_integer(unsigned(x_in)));
--report integer'image(to_integer(unsigned(y_in)));
lut_index <= step_index;
x_integer := to_integer(signed(x_in));
y_integer := to_integer(signed(y_in));
z_integer := to_integer(signed(z_in));
if(z_integer > 0) then
d := 1;
else
d := -1;
--else
-- d := 0; --No longer not applying step if the angle is exactly as expected. In every step the vercor will move a little bit
end if;
x_offset_vector := std_logic_vector(shift_right(signed(y_in),step_index));
y_offset_vector := std_logic_vector(shift_right(signed(x_in),step_index));
angle_offset := to_integer(signed(arctg_lut_angle)) * d;
x_offset := to_integer(signed(x_offset_vector)) * d;
y_offset := to_integer(signed(y_offset_vector)) * d;
x_out <= std_logic_vector(to_signed(x_integer - x_offset, TOTAL_BITS));
y_out <= std_logic_vector(to_signed(y_integer + y_offset, TOTAL_BITS));
z_out <= std_logic_vector(to_signed(z_integer - angle_offset, TOTAL_BITS));
end process;
end architecture;
|
gpl-3.0
|
b15bc2d22c40563c66e026f81a35a9d6
| 0.563087 | 3.546306 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/xor_reduce.vhd
| 1 | 1,881 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 07/01/2013
-- Design Name: XOR_Reduce
-- Module Name: XOR_Reduce
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- XOR reduction for any std_logic_vector
--
-- The circuits parameters
--
-- size_vector :
--
-- The size of the std_logic_vector to be reduced.
--
-- number_of_vectors :
--
-- The number of vector to be reduced in one vector of size size_vector.
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor_reduce is
Generic(
size_vector : integer := 1;
number_of_vectors : integer range 2 to integer'high := 2
);
Port(
a : in STD_LOGIC_VECTOR(((size_vector)*(number_of_vectors) - 1) downto 0);
o : out STD_LOGIC_VECTOR((size_vector - 1) downto 0)
);
end xor_reduce;
architecture Behavioral of xor_reduce is
signal b : STD_LOGIC_VECTOR(((size_vector)*(number_of_vectors - 1) - 1) downto 0);
begin
b((size_vector - 1) downto 0) <= a((size_vector - 1) downto 0) xor a((2*size_vector - 1) downto (size_vector));
more_than_two : if number_of_vectors = 2 generate
reduction : for Index in 0 to number_of_vectors generate
b(((size_vector)*(Index + 2) - 1) downto ((size_vector)*(Index + 1) - 1)) <= a(((size_vector)*(Index + 3) - 1) downto ((size_vector)*(Index + 2) - 1)) xor b(((size_vector)*(Index + 1) - 1) downto ((size_vector)*(Index) - 1));
end generate;
end generate;
o <= b(((size_vector)*(number_of_vectors - 1) - 1) downto ((size_vector)*(number_of_vectors - 2) - 1));
end Behavioral;
|
bsd-2-clause
|
5d2c8f39d43eadfdd08252efdfa59307
| 0.596491 | 3.352941 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/tb_codeword_generator_1.vhd
| 1 | 11,723 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Codeword Generator 1
-- Module Name: Tb_Codeword_Generator_1
-- Project Name: McEliece QD-Goppa Encoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Test bench for codeword_generator_1 circuit.
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- length_message :
--
-- Length in bits of message size and also part of matrix size.
--
-- size_message :
--
-- The number of bits necessary to store the message. The ceil(log2(lenght_message))
--
-- length_codeword :
--
-- Length in bits of codeword size and also part of matrix size.
--
-- size_codeword :
--
-- The number of bits necessary to store the codeword. The ceil(log2(length_codeword))
--
-- size_dyadic_matrix :
--
-- The number of bits necessary to store one row of the dyadic matrix.
-- It is also the ceil(log2(number of errors in the code))
--
-- number_dyadic_matrices :
--
-- The number of dyadic matrices present in matrix A.
--
-- size_number_dyadic_matrices :
--
-- The number of bits necessary to store the number of dyadic matrices.
-- The ceil(log2(number_dyadic_matrices))
--
-- message_memory_file :
--
-- File that holds the message to be encoded.
--
-- codeword_memory_file :
--
-- File that holds the encoded message.
-- This will be used to verify if the circuit worked correctly.
--
-- generator_matrix_memory_file :
--
-- File that holds the public key, matrix A, in a reduced form.
--
-- dump_test_codeword_file :
--
-- File that will hold the encoded message computed by the circuit.
--
--
-- Dependencies:
--
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- codeword_generator_1 Rev 1.0
-- ram Rev 1.0
--
-- Revision:
-- Revision 1.00 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_codeword_generator_1 is
Generic (
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
-- length_message : integer := 28;
-- size_message : integer := 5;
-- length_codeword : integer := 52;
-- size_codeword : integer := 6;
-- size_dyadic_matrix : integer := 2;
-- number_dyadic_matrices : integer := 42;
-- size_number_dyadic_matrices : integer := 6;
-- message_memory_file : string := "mceliece/data_tests/message_qdgoppa_52_28_4_6.dat";
-- codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_52_28_4_6.dat";
-- generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_52_28_4_6.dat";
-- dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_52_28_4_6.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
length_message : integer := 2144;
size_message : integer := 12;
length_codeword : integer := 2528;
size_codeword : integer := 12;
size_dyadic_matrix : integer := 5;
number_dyadic_matrices : integer := 804;
size_number_dyadic_matrices : integer := 10;
message_memory_file : string := "mceliece/data_tests/message_qdgoppa_2528_2144_32_12.dat";
codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2528_2144_32_12.dat";
generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_2528_2144_32_12.dat";
dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_2528_2144_32_12.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- length_message : integer := 2048;
-- size_message : integer := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 384;
-- size_number_dyadic_matrices : integer := 9;
-- message_memory_file : string := "mceliece/data_tests/message_qdgoppa_2816_2048_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2816_2048_64_12.dat";
-- generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_2816_2048_64_12.dat";
-- dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- length_message : integer := 2560;
-- size_message : integer := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 480;
-- size_number_dyadic_matrices : integer := 9;
-- message_memory_file : string := "mceliece/data_tests/message_qdgoppa_3328_2560_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_3328_2560_64_12.dat";
-- generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_3328_2560_64_12.dat";
-- dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- length_message : integer := 5632;
-- size_message : integer := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- size_dyadic_matrix : integer := 7;
-- number_dyadic_matrices : integer := 572;
-- size_number_dyadic_matrices : integer := 10;
-- message_memory_file : string := "mceliece/data_tests/message_qdgoppa_7296_5632_128_13.dat";
-- codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_7296_5632_128_13.dat";
-- generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_7296_5632_128_13.dat";
-- dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_7296_5632_128_13.dat"
);
end tb_codeword_generator_1;
architecture Behavioral of tb_codeword_generator_1 is
component codeword_generator_1
Generic(
length_message : integer;
size_message : integer;
length_codeword : integer;
size_codeword : integer;
size_dyadic_matrix : integer;
number_dyadic_matrices : integer;
size_number_dyadic_matrices : integer
);
Port(
codeword : in STD_LOGIC;
matrix : in STD_LOGIC;
message : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
new_codeword : out STD_LOGIC;
write_enable_new_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC;
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_message : out STD_LOGIC_VECTOR((size_message - 1) downto 0);
address_matrix : out STD_LOGIC_VECTOR((size_dyadic_matrix + size_number_dyadic_matrices - 1) downto 0)
);
end component;
component ram
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal codeword : STD_LOGIC;
signal matrix : STD_LOGIC;
signal message : STD_LOGIC;
signal new_codeword : STD_LOGIC;
signal write_enable_new_codeword : STD_LOGIC;
signal codeword_finalized : STD_LOGIC;
signal address_codeword : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal address_message : STD_LOGIC_VECTOR((size_message - 1) downto 0);
signal address_matrix : STD_LOGIC_VECTOR((size_dyadic_matrix + size_number_dyadic_matrices - 1) downto 0);
signal test_address_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal final_address_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal true_acc : STD_LOGIC;
signal error : STD_LOGIC;
signal dump_test_codeword : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
for message_memory : ram use entity work.ram(file_load);
for generator_matrix_memory : ram use entity work.ram(file_load);
for test_codeword_memory : ram use entity work.ram(simple);
for true_codeword_memory : ram use entity work.ram(file_load);
begin
test : codeword_generator_1
Generic Map(
length_message => length_message,
size_message => size_message,
length_codeword => length_codeword,
size_codeword => size_codeword,
size_dyadic_matrix => size_dyadic_matrix,
number_dyadic_matrices => number_dyadic_matrices,
size_number_dyadic_matrices => size_number_dyadic_matrices
)
Port Map(
codeword => codeword,
matrix => matrix,
message => message,
clk => clk,
rst => rst,
new_codeword => new_codeword,
write_enable_new_codeword => write_enable_new_codeword,
codeword_finalized => codeword_finalized,
address_codeword => address_codeword,
address_message => address_message,
address_matrix => address_matrix
);
message_memory : ram
Generic Map(
ram_address_size => size_message,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => message_memory_file,
dump_file_name => ""
)
Port Map(
data_in => "0",
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_message,
rst_value => "0",
data_out(0) => message
);
generator_matrix_memory : ram
Generic Map(
ram_address_size => size_dyadic_matrix + size_number_dyadic_matrices,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => generator_matrix_memory_file,
dump_file_name => ""
)
Port Map(
data_in => "0",
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_matrix,
rst_value => "0",
data_out(0) => matrix
);
test_codeword_memory : ram
Generic Map(
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => "",
dump_file_name => dump_test_codeword_file
)
Port Map(
data_in(0) => new_codeword,
rw => write_enable_new_codeword,
clk => clk,
rst => rst,
dump => dump_test_codeword,
address => final_address_acc,
rst_value => "0",
data_out(0) => codeword
);
true_codeword_memory : ram
Generic Map(
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => codeword_memory_file,
dump_file_name => ""
)
Port Map(
data_in => "0",
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => final_address_acc,
rst_value => "0",
data_out(0) => true_acc
);
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
final_address_acc <= address_codeword when codeword_finalized = '0' else test_address_acc;
process
variable i : integer;
begin
test_address_acc <= (others => '0');
rst <= '1';
error <= '0';
dump_test_codeword <= '0';
wait for PERIOD*2;
rst <= '0';
wait until codeword_finalized = '1';
report "Circuit finish = " & integer'image((cycle_count - 2)/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (length_codeword)) loop
test_address_acc <= std_logic_vector(to_unsigned(i, test_address_acc'Length));
wait for PERIOD*2;
if (true_acc = codeword) then
error <= '0';
else
error <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
error <= '0';
wait for PERIOD;
i := i + 1;
end loop;
dump_test_codeword <= '1';
wait for PERIOD;
dump_test_codeword <= '0';
test_bench_finish <= '1';
wait;
end process;
end Behavioral;
|
bsd-2-clause
|
b027dab3892f9cb6a2fc9f08a0335770
| 0.662458 | 3.033903 | false | true | false | false |
KenKeeley/My68k-system
|
CircuitBoards/MainBoard/SupportCPLD/Address_Decoder.vhd
| 1 | 5,441 |
----------------------------------------------------------------------------------------------------
--
-- FileName: Address_Decoder.vhd
-- Description: Address Decoder Logic.
--
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY work;
ENTITY Address_Decoder IS
PORT
(
nReset : IN STD_LOGIC; -- Reset
nAS : IN STD_LOGIC; -- Address Strobe
nHigh_Address : IN STD_LOGIC; -- Upper Address Range
Function_In : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- System Function
Address_In : IN STD_LOGIC_VECTOR (23 DOWNTO 0); -- Address Bus
nCS_FPU : OUT STD_LOGIC; -- FPU Chip Select
nCS_ATA : OUT STD_LOGIC; -- ATA Buffer Chip Select
nCS_ATA0 : OUT STD_LOGIC; -- ATA Chip Select 0
nCS_ATA1 : OUT STD_LOGIC; -- ATA Chip Select 1
nCS_RTC : OUT STD_LOGIC; -- RTC Chip Select
AS_RTC : OUT STD_LOGIC; -- RTC AS Select
DS_RTC : OUT STD_LOGIC; -- RTC DS Select
nCS_PS2 : OUT STD_LOGIC; -- PS2 Chip Select
nCS_ID1 : OUT STD_LOGIC; -- Hardware ID 1
nCS_ID2 : OUT STD_LOGIC; -- Hardware ID 2
nPS_OFF : OUT STD_LOGIC; -- Power Off
nCS_DUART : OUT STD_LOGIC; -- DUART Chip Select
nCS_NET : OUT STD_LOGIC; -- Network Chip Select
nCS_SRAM : OUT STD_LOGIC; -- SRAM Chip Select
nCS_ROM : OUT STD_LOGIC -- ROM Chip Select
);
END Address_Decoder;
ARCHITECTURE Behavioral OF Address_Decoder IS
SIGNAL nPhantom : STD_LOGIC;
SIGNAL Counter : UNSIGNED(2 DOWNTO 0);
BEGIN
PROCESS(nReset, nAS)
BEGIN
IF (nReset = '0') THEN
nPhantom <= '0';
Counter <= "000";
ELSIF RISING_EDGE(nAS) THEN
IF Counter < 7 THEN
nPhantom <= '0';
Counter <= Counter + 1;
ELSE
nPhantom <= '1';
END IF;
END IF;
END PROCESS;
PROCESS(nReset, nAS, nPhantom)
BEGIN
IF (nReset = '0' OR nAS = '1') THEN
nCS_FPU <= '1';
nCS_ATA <= '1';
nCS_ATA0 <= '1';
nCS_ATA1 <= '1';
nCS_RTC <= '1';
AS_RTC <= '0';
DS_RTC <= '0';
nCS_PS2 <= '1';
nCS_ID1<= '1';
nCS_ID2 <= '1';
nPS_OFF <= '1';
nCS_DUART <= '1';
nCS_NET <= '1';
nCS_SRAM <= '1';
nCS_ROM <= '1';
ELSIF FALLING_EDGE(nAS) THEN
IF (Function_In = "111" AND Address_In = X"022000") THEN
nCS_FPU <= '0';
ELSIF ( (Function_In(1 DOWNTO 0) = "01" OR Function_In(1 DOWNTO 0) = "10" ) AND nHigh_Address = '1' AND nPhantom = '0' AND Address_In < X"000008") THEN
nCS_ROM <= '0';
ELSIF ( (Function_In(1 DOWNTO 0) = "01" OR Function_In(1 DOWNTO 0) = "10" ) AND nHigh_Address = '0') THEN
IF Address_In >= X"FC0000" AND Address_In <= X"FC001F" AND Address_In(0) = '0' THEN
nCS_ATA <= '0';
nCS_ATA1 <= '0';
IF Address_In(4) = '0' THEN
nCS_ATA0 <= '0';
END IF;
ELSIF Address_In >= X"FC0020" AND Address_In <= X"FC002F" AND Address_In(0) = '0' THEN
nCS_ATA <= '0';
IF Address_In(4) = '0' THEN
nCS_ATA0 <= '0';
END IF;
ELSIF Address_In = X"FC0030" THEN
nCS_RTC <= '0';
AS_RTC <= '1';
ELSIF Address_In = X"FC0031" THEN
nCS_RTC <= '0';
DS_RTC <= '1';
ELSIF Address_In = X"FC0032" THEN
nCS_PS2 <= '0';
ELSIF Address_In = X"FC0033" THEN
nCS_PS2 <= '0';
ELSIF Address_In = X"FC0034" THEN
nCS_ID1 <= '0';
ELSIF Address_In = X"FC0035" THEN
nCS_ID2 <= '0';
ELSIF Address_In = X"FC0038" THEN
nPS_OFF <= '0';
ELSIF Address_In >= X"FC0040" AND Address_In <= X"FC004F" THEN
nCS_DUART <= '0';
ELSIF Address_In >= X"FC0060" AND Address_In <= X"FC007F" THEN
nCS_NET <= '0';
ELSIF Address_In >= X"FD0000" AND Address_In <= X"FD7FFF" THEN
nCS_SRAM <= '0';
ELSIF Address_In >= X"FE0000" THEN
nCS_ROM <= '0';
END IF;
ELSE
nCS_FPU <= '1';
nCS_ATA <= '1';
nCS_ATA0 <= '1';
nCS_ATA1 <= '1';
nCS_RTC <= '1';
AS_RTC <= '0';
DS_RTC <= '0';
nCS_PS2 <= '1';
nCS_ID1<= '1';
nCS_ID2 <= '1';
nPS_OFF <= '1';
nCS_DUART <= '1';
nCS_NET <= '1';
nCS_SRAM <= '1';
nCS_ROM <= '1';
END IF;
END IF;
END PROCESS;
END Behavioral;
|
gpl-3.0
|
1438366e730c9a9a89d7883c72f4cfac
| 0.404705 | 3.957091 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/multiplication/number_splitter/number_splitter.vhd
| 1 | 673 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity number_splitter is
generic(
TOTAL_BITS:natural := 23;
EXP_BITS:natural := 6
);
port (
number_in: in std_logic_vector(TOTAL_BITS-1 downto 0);
sign_out: out std_logic;
exp_out: out std_logic_vector(EXP_BITS-1 downto 0);
mant_out: out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0)
);
end;
architecture number_splitter_arq of number_splitter is
begin
process(number_in)
begin
sign_out <= number_in(TOTAL_BITS-1);
exp_out <= number_in(TOTAL_BITS-2 downto TOTAL_BITS-1-EXP_BITS);
mant_out <= number_in(TOTAL_BITS-EXP_BITS-2 downto 0);
end process;
end architecture;
|
gpl-3.0
|
0eb5ae27176e6c7327910bbe4c355776
| 0.705795 | 2.735772 | false | false | false | false |
rodrigoazs/-7-5-Reed-Solomon
|
code/symbol_power_encoder.vhd
| 1 | 819 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity SymbolPowerEncoder is
Port ( n1 : in std_logic_vector(2 downto 0);
n1c : out std_logic_vector(2 downto 0));
end SymbolPowerEncoder;
architecture Behavioral of SymbolPowerEncoder is
begin
process ( n1 )
begin
case n1 is
when "100"=> n1c <="000" ;
when "010"=> n1c <="001" ;
when "001"=> n1c <="010" ;
when "110"=> n1c <="011" ;
when "011"=> n1c <="100" ;
when "111"=> n1c <="101" ;
when "101"=> n1c <="110" ;
when others=> n1c <="---" ;
end case ;
end process ;
end Behavioral;
|
mit
|
899640db4727e95bf36d379f0a977030
| 0.637363 | 3.011029 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/tp1.vhd
| 1 | 2,352 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tp1 is
port (
clk_in: in std_logic;
rst_in: in std_logic;
clk_anode_ouput: out std_logic_vector(3 downto 0);
clk_led_output: out std_logic_vector(7 downto 0)
);
end;
architecture tp1_arq of tp1 is
signal enabler_output : std_logic := '0';
signal bcd0_out : std_logic_vector(3 downto 0) := (others => '0');
signal bcd1_out : std_logic_vector(3 downto 0) := (others => '0');
signal bcd2_out : std_logic_vector(3 downto 0) := (others => '0');
signal bcd3_out : std_logic_vector(3 downto 0) := (others => '0');
signal co_bcd0 : std_logic := '0';
signal co_bcd1 : std_logic := '0';
signal co_bcd2 : std_logic := '0';
signal co_bcd3 : std_logic := '0';
component led_display_controller is
port (
clk_in: in std_logic;
bcd0: in std_logic_vector(3 downto 0);
bcd1: in std_logic_vector(3 downto 0);
bcd2: in std_logic_vector(3 downto 0);
bcd3: in std_logic_vector(3 downto 0);
anode_output: out std_logic_vector(3 downto 0);
led_output: out std_logic_vector(7 downto 0)
);
end component;
component cont_bcd is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
s: out std_logic_vector(3 downto 0);
co: out std_logic
);
end component;
component generic_enabler is
generic(PERIOD:natural := 1000000 ); --1MHz
port(
clk: in std_logic;
rst: in std_logic;
ena_out: out std_logic
);
end component;
begin
generic_enablerMap: generic_enabler generic map(10000)
port map (
clk => clk_in,
rst => rst_in,
ena_out => enabler_output
);
cont_bcd0Map: cont_bcd port map(
clk => clk_in,
rst => rst_in,
ena => enabler_output,
s => bcd0_out,
co => co_bcd0
);
cont_bcd1Map: cont_bcd port map(
clk => clk_in,
rst => rst_in,
ena => co_bcd0,
s => bcd1_out,
co => co_bcd1
);
cont_bcd2Map: cont_bcd port map(
clk => clk_in,
rst => rst_in,
ena => co_bcd1,
s => bcd2_out,
co => co_bcd2
);
cont_bcd3Map: cont_bcd port map(
clk => clk_in,
rst => rst_in,
ena => co_bcd2,
s => bcd3_out,
co => co_bcd3
);
led_display_controllerMap: led_display_controller port map (
clk_in => clk_in,
bcd0 => bcd0_out,
bcd1 => bcd1_out,
bcd2 => bcd2_out,
bcd3 => bcd3_out,
anode_output => clk_anode_ouput,
led_output => clk_led_output
);
end;
|
gpl-3.0
|
45d0e0643b7fa6f3c5045166e83019bc
| 0.62415 | 2.581778 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/codic_commander/cordic_commander_tb.vhd
| 1 | 1,691 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cordic_commander_tb is
end entity;
architecture cordic_commander_tb_arq of cordic_commander_tb is
signal clk : std_logic := '0';
signal mode: std_logic_vector(1 downto 0) := (others => '0');
signal angle : std_logic_vector(31 downto 0) := (others => '0');
component cordic_commander is
generic(TOTAL_BITS : integer := 32);
port(
clk : in std_logic := '0';
enable : in std_logic := '0';
mode : in std_logic_vector(1 downto 0) := (others => '0');
angle : out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
begin
cordic_commander_0 : cordic_commander
port map(
clk => clk,
enable => '1',
mode => mode,
angle => angle
);
process
type pattern_type is record
m : std_logic_vector(1 downto 0);
a : std_logic_vector(31 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("00","00000000000000000000000000000000"),
("00","00000000000000000000000000000000"),
("01","00000000000000001011010000000000"),
("11","11111111111111110100110000000000")
);
begin
for i in patterns'range loop
-- Set the inputs.
mode <= patterns(i).m;
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
assert patterns(i).a = angle report "BAD ANGLE, EXPECTED: " & integer'image(to_integer(signed(patterns(i).a))) & " GOT: " & integer'image(to_integer(signed(angle)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
80f92b0cf774585e35679ff7b02b3414
| 0.639267 | 3.245681 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/TP1-Contador/anode_selector.vhd
| 1 | 791 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity anode_selector is
port(
selector_in : in std_logic_vector (1 downto 0);
selector_out : out std_logic_vector (3 downto 0)
);
end anode_selector;
architecture anode_selector_arq of anode_selector is
begin
process (selector_in) is
begin
case selector_in is
when "00" => selector_out <= not b"0001";
when "01" => selector_out <= not b"0010";
when "10" => selector_out <= not b"0100";
when "11" => selector_out <= not b"1000";
when others => selector_out <= (others => '0');
end case;
end process;
end anode_selector_arq;
|
gpl-3.0
|
3f20ab8702831caf845de6aed9080a33
| 0.528445 | 3.696262 | false | false | false | false |
laurivosandi/hdl
|
arithmetic/src/counter42.vhd
| 1 | 933 |
library ieee;
use ieee.std_logic_1164.all;
-- 15-bit 4:2 counter
entity counter42 is
port ( a : in STD_LOGIC_VECTOR (14 downto 0);
b : in STD_LOGIC_VECTOR (14 downto 0);
c : in STD_LOGIC_VECTOR (14 downto 0);
d : in STD_LOGIC_VECTOR (14 downto 0);
s : out STD_LOGIC_VECTOR (14 downto 0);
co : out STD_LOGIC_VECTOR (14 downto 0));
end counter42;
architecture behavioral of counter42 is
signal si : STD_LOGIC_VECTOR (14 downto 0);
signal ti : STD_LOGIC_VECTOR (15 downto 0);
begin
ti(0) <= '0';
counter_loop: for j in 0 to 14 generate
-- First 3:2 counter
si(j) <= c(j) xor b(j) xor a(j);
ti(j+1) <= (c(j) and b(j)) or ((b(j) xor c(j)) and a(j));
-- Second 3:2 counter
s(j) <= si(j) xor d(j) xor ti(j);
co(j) <= (si(j) and d(j)) or ((si(j) xor d(j)) and ti(j));
end generate;
end behavioral;
|
mit
|
7be5027dc6ac013465c9e9460d482e7f
| 0.547696 | 2.915625 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
VHDL_PLANB/DECODER/DECODER.vhd
| 1 | 4,676 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity DECODER is
generic
(
constant fpr:integer:=360;
constant cmd_end:std_logic_vector(1 downto 0):="11"
);
port
(
inclk,rst:in std_logic;
control_begin:out std_logic:='0';
load_next:in std_logic;
fifo_en_w_1:out std_logic:='0';
fifo_en_w_2:out std_logic:='0';
fifo_en_w_3:out std_logic:='0';
fifo_aclr:out std_logic:='0';
fifo_data_1:out std_logic_vector(127 downto 0);
fifo_data_2:out std_logic_vector(127 downto 0);
fifo_data_3:out std_logic_vector(127 downto 0)
);
end entity;
architecture RTL of DECODER is
component ROM is
port
(
clock:in std_logic;
address:in std_logic_vector(12 downto 0);
q:out std_logic_vector(15 downto 0)
);
end component;
type state is (init,idle,load);
signal st:state:=init;
type load_state is (read_next,judge,set,clear,do_write);
signal load_st:load_state:=judge;
signal data_cmd:std_logic_vector(1 downto 0):="00";
signal data_x,data_y:std_logic_vector(6 downto 0):="0000000";
signal x_now,y_now,y_last,y_sub:integer range 0 to 127:=0;
signal fifo_tmp:std_logic_vector(127 downto 0);
signal row_tmp:std_logic_vector(119 downto 0);
signal rom_addr:std_logic_vector(12 downto 0):="0000000000000";
signal rom_data:std_logic_vector(15 downto 0):=x"0000";
signal write_fin:std_logic:='0';
procedure row_clear(
signal row:inout std_logic_vector(119 downto 0)
) is
begin
row<=x"000000000000000000000000000000";
end row_clear;
procedure fifo_write(
signal row_num:in integer range 0 to 127;
signal write_fin:inout std_logic;
signal fifo_en_w_1:out std_logic;
signal fifo_en_w_2:out std_logic;
signal fifo_en_w_3:out std_logic;
variable con_wr:inout integer
) is
begin
if con_wr=1 then
fifo_en_w_1<='0';
fifo_en_w_2<='0';
fifo_en_w_3<='0';
write_fin<='1';
else
if row_num<40 then
fifo_en_w_1<='1';
elsif row_num<80 then
fifo_en_w_2<='1';
else
fifo_en_w_3<='1';
end if;
write_fin<='0';
con_wr:=con_wr+1;
end if;
end fifo_write;
begin
fifo_tmp(127 downto 120)<=x"00";
fifo_tmp(119 downto 0)<=row_tmp;
data_cmd<=rom_data(15 downto 14);
data_x<=rom_data(13 downto 7);
data_y<=rom_data(6 downto 0);
x_now<=conv_integer(data_x);
y_now<=conv_integer(data_y);
fifo_data_1<=fifo_tmp;
fifo_data_2<=fifo_tmp;
fifo_data_3<=fifo_tmp;
ROM1:ROM
port map
(
clock=>inclk,
address=>rom_addr,
q=>rom_data
);
MAIN:process(inclk,rst)
variable con_frame:integer range 0 to fpr:=0;
variable con_wr:integer range 0 to 3:=0;
variable con_init:integer range 0 to 15:=0;
variable con_read_rom:integer range 0 to 3:=0;
begin
if rst='1' then
con_init:=0;
st<=init;
elsif rising_edge(inclk) then
case st is
when init =>
if con_init=15 then
rom_addr<="0000000000000";
control_begin<='0';
row_clear(row_tmp);
fifo_aclr<='1';
y_last<=0;
con_read_rom:=1;
load_st<=read_next;
st<=load;
else
con_init:=con_init+1;
end if;
when idle =>
if load_next='1' then
if con_frame=fpr-1 then
rom_addr<="0000000000000";
con_frame:=0;
else
con_frame:=con_frame+1;
rom_addr<=rom_addr+1;
end if;
row_clear(row_tmp);
fifo_aclr<='1';
y_last<=0;
con_read_rom:=1;
load_st<=read_next;
st<=load;
else
st<=st;
end if;
when load =>
fifo_aclr<='0';
case load_st is
when read_next =>
if con_read_rom=3 then
load_st<=judge;
con_read_rom:=0;
elsif con_read_rom=0 then
rom_addr<=rom_addr+1;
con_read_rom:=con_read_rom+1;
else
con_read_rom:=con_read_rom+1;
end if;
when judge =>
if data_cmd=cmd_end then
con_wr:=0;
load_st<=do_write;
elsif y_now=y_last then
load_st<=set;
else
con_wr:=0;
load_st<=do_write;
end if;
when set =>
row_tmp(x_now)<='1';
load_st<=read_next;
when clear =>
row_clear(row_tmp);
if y_sub=0 then
if data_cmd=cmd_end then
control_begin<='1';
st<=idle;
else
y_last<=y_now;
load_st<=set;
end if;
else
y_last<=y_last+1;
con_wr:=0;
load_st<=do_write;
end if;
when do_write =>
fifo_write(y_last,write_fin,fifo_en_w_1,fifo_en_w_2,fifo_en_w_3,con_wr);
if write_fin='1' then
if data_cmd=cmd_end then
y_sub<=113-y_last-1;
else
y_sub<=y_now-y_last-1;
end if;
write_fin<='0';
load_st<=clear;
else
load_st<=load_st;
end if;
end case;
end case;
end if;
end process;
end RTL;
|
gpl-2.0
|
22cc8cf6e223221ee8cbb62e642bf6d0
| 0.609923 | 2.559387 | false | false | false | false |
alainmarcel/Surelog
|
third_party/tests/YosysTestSuite/sva/basic04.vhd
| 11 | 471 |
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
clock : in std_logic;
ctrl : in std_logic;
x : out std_logic
);
end entity;
architecture rtl of top is
signal read : std_logic := '0';
signal write : std_logic := '0';
signal ready : std_logic := '0';
begin
process (clock) begin
if (rising_edge(clock)) then
read <= not ctrl;
write <= ctrl;
ready <= write;
end if;
end process;
x <= read xor write xor ready;
end architecture;
|
apache-2.0
|
a9706a94b055258cd8e854852c4dc022
| 0.643312 | 2.871951 | false | false | false | false |
OpticalMeasurementsSystems/2DImageProcessing
|
2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ip/image_processing_2d_design_proc_sys_reset_0_1/synth/image_processing_2d_design_proc_sys_reset_0_1.vhd
| 1 | 6,819 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY image_processing_2d_design_proc_sys_reset_0_1 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END image_processing_2d_design_proc_sys_reset_0_1;
ARCHITECTURE image_processing_2d_design_proc_sys_reset_0_1_arch OF image_processing_2d_design_proc_sys_reset_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF image_processing_2d_design_proc_sys_reset_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF image_processing_2d_design_proc_sys_reset_0_1_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF image_processing_2d_design_proc_sys_reset_0_1_arch : ARCHITECTURE IS "image_processing_2d_design_proc_sys_reset_0_1,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF image_processing_2d_design_proc_sys_reset_0_1_arch: ARCHITECTURE IS "image_processing_2d_design_proc_sys_reset_0_1,proc_sys_reset,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=16,C_AUX_RST_WIDTH=16,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 16,
C_AUX_RST_WIDTH => 16,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END image_processing_2d_design_proc_sys_reset_0_1_arch;
|
gpl-2.0
|
a810a1e253caad9ebc28e23fe7847e03
| 0.71814 | 3.470229 | false | false | false | false |
laurivosandi/hdl
|
zynq/src/ov7670_axi_stream_capture/ov7670_axi_stream_capture_tb.vhd
| 1 | 2,665 |
library ieee;
use ieee.std_logic_1164.all;
entity ov7670_axi_stream_capture_tb is
end ov7670_axi_stream_capture_tb;
architecture behavior of ov7670_axi_stream_capture_tb is
constant t_byte : time := 20 ns;
constant t_pixel : time := 2 * t_byte;
constant t_line : time := 784 * t_pixel;
component ov7670_axi_stream_capture is
port (
pclk : in std_logic;
vsync : in std_logic;
href : in std_logic;
d : in std_logic_vector (7 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tlast : out std_logic;
m_axis_tdata : out std_logic_vector ( 31 downto 0 );
m_axis_tuser : out std_logic;
aclk : out std_logic
);
end component;
signal in_pclk : std_logic := '0';
signal in_vsync : std_logic := '0';
signal in_href : std_logic := '0';
signal in_d : std_logic_vector (7 downto 0) := "11111111";
signal out_m_axis_tvalid : std_logic;
signal out_m_axis_tready : std_logic;
signal out_m_axis_tlast : std_logic;
signal out_m_axis_tdata : std_logic_vector ( 31 downto 0 );
signal out_m_axis_tuser : std_logic;
signal out_aclk : std_logic;
begin
uut: ov7670_axi_stream_capture port map (
pclk => in_pclk,
vsync => in_vsync,
href => in_href,
d => in_d,
m_axis_tvalid => out_m_axis_tvalid,
m_axis_tready => out_m_axis_tready,
m_axis_tlast => out_m_axis_tlast,
m_axis_tdata => out_m_axis_tdata,
m_axis_tuser => out_m_axis_tuser,
aclk => out_aclk
);
clk_process :process
begin
in_pclk <= '0';
wait for 10 ns;
in_pclk <= '1';
wait for 10 ns;
end process;
vsync_process: process
begin
in_vsync <= '0';
wait for 5 * t_line;
in_vsync <= '1';
wait for 3 * t_line;
in_vsync <= '0';
wait for (510-3-5)*t_line;
end process;
href_process: process
begin
in_href <= '0';
wait until falling_edge(in_vsync);
wait for 17 * t_line;
for i in 0 to 480 loop -- Count over lines
in_href <= '1';
wait for 640 * t_pixel; -- Pixels are actually transmitted here, rest is garbage
in_href <= '0';
wait for 144 * t_pixel;
end loop;
end process;
stim_proc: process
begin
wait until rising_edge(in_pclk);
in_d <= "10101010";
end process;
end;
|
mit
|
c3ce7312012559086a527a56913a5401
| 0.521576 | 3.48366 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/vga_controller/vga_controller.vhd
| 1 | 3,861 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity vga_ctrl is
port( mclk : in std_logic; -- 25.175 Mhz mclk
red_i, grn_i, blu_i : in std_logic; -- input values for RGB signals
pixel_row, pixel_col : out std_logic_vector(9 downto 0); -- for current pixel
red_o, grn_o, blu_o, hs, vs : out std_logic); -- VGA drive signals
-- The signals red_o, grn_o, blu_o, hs and vs are output to the monitor.
-- The pixel_row and pixel_col outputs are used to know when to assert red_i,
-- grn_i and blu_i to color the current pixel. For VGA, the pixel_col
-- values that are valid are from 0 to 639, all other values should
-- be ignored. The pixel_row values that are valid are from 0 to 479 and
-- again, all other values are ignored. To turn on a pixel on the
-- VGA monitor, some combination of red_i, grn_i and blu_i should be
-- asserted before the rising edge of the mclk. Objects which are
-- displayed on the monitor, assert their combination of red_i, grn_i and
-- blu_i when they detect the pixel_row and pixel_col values are within their
-- range. For multiple objects sharing a screen, they must be combined
-- using logic to create single red_i, grn_i, and blu_i signals.
end;
architecture behaviour1 of vga_ctrl is
-- names are referenced from Altera University Program Design
-- Laboratory Package November 1997, ver. 1.1 User Guide Supplement
-- mclk period = 39.72 ns; the constants are integer multiples of the
-- mclk frequency and are close but not exact
-- pixel_row counter will go from 0 to 524; pixel_col counter from 0 to 799
subtype counter is std_logic_vector(9 downto 0);
constant B : natural := 93; -- horizontal blank: 3.77 us
constant C : natural := 45; -- front guard: 1.89 us
constant D : natural := 640; -- horizontal columns: 25.17 us
constant E : natural := 22; -- rear guard: 0.94 us
constant A : natural := B + C + D + E; -- one horizontal sync cycle: 31.77 us
constant P : natural := 2; -- vertical blank: 64 us
constant Q : natural := 32; -- front guard: 1.02 ms
constant R : natural := 480; -- vertical rows: 15.25 ms
constant S : natural := 11; -- rear guard: 0.35 ms
constant O : natural := P + Q + R + S; -- one vertical sync cycle: 16.6 ms
signal vidon, hor, ver : std_logic := '0';
signal vertical, horizontal : unsigned(9 downto 0) := (others => '0'); -- define counters
begin
process
variable clk_div : std_logic := '0';
begin
--report integer'image(to_integer(horizontal)) & " : " & integer'image(to_integer(vertical));
--report std_logic'image(hs) & " : " & std_logic'image(vs);
wait until mclk = '1';
if(clk_div = '1') then
clk_div := '0';
-- increment counters
if horizontal < A - 1 then
horizontal <= horizontal + 1;
else
horizontal <= (others => '0');
if vertical < O - 1 then -- less than oh
vertical <= vertical + 1;
else
vertical <= (others => '0'); -- is set to zero
end if;
end if;
-- define hs pulse
if horizontal >= (D + E) and horizontal < (D + E + B) then
hor <= '1';
else
hor <= '0';
end if;
-- define vs pulse
if vertical >= (R + S) and vertical < (R + S + P) then
ver <= '1';
else
ver <= '0';
end if;
if(ver = '0' and hor = '0') then
vidon <= '1';
else
vidon <= '0';
end if;
else
clk_div := '1';
end if;
end process;
vs <= ver;
hs <= hor;
pixel_row <= std_logic_vector(vertical);
pixel_col <= std_logic_vector(horizontal);
red_o <= '1' when (red_i = '1' and vidon = '1') else '0';
grn_o <= '1' when (grn_i = '1' and vidon = '1') else '0';
blu_o <= '1' when (blu_i = '1' and vidon = '1') else '0';
end architecture;
|
gpl-3.0
|
8d484a733ab7894360215fa642b1b6e1
| 0.608133 | 3.377953 | false | false | false | false |
electronicvisions/brick
|
test/source/vhdl/counter.vhd
| 2 | 626 |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port( clk: in std_logic;
reset: in std_logic;
enable: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture behav of counter is
signal pre_count: std_logic_vector(3 downto 0);
begin
process(clk, enable, reset)
begin
if reset = '1' then
pre_count <= "0000";
elsif (clk='1' and clk'event) then
if enable = '1' then
pre_count <= pre_count + "1";
end if;
end if;
end process;
count <= pre_count;
end behav;
|
bsd-3-clause
|
0316a43c95934bf9e6c4d869f9b17164
| 0.600639 | 3.226804 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
VHDL/USB/COUNTER_TIMEOUT.vhd
| 2 | 4,580 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: COUNTER_TIMEOUT.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY COUNTER_TIMEOUT IS
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END COUNTER_TIMEOUT;
ARCHITECTURE SYN OF counter_timeout IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (11 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(11 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 12
)
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "12"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER_TIMEOUT.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER_TIMEOUT.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER_TIMEOUT.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER_TIMEOUT.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER_TIMEOUT_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
gpl-2.0
|
2c7559352febbdb7db7e7b08ecc9b0e7
| 0.652183 | 3.672815 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/syndrome_calculator_n_pipe.vhd
| 1 | 19,006 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Syndrome_Calculator_N_Pipe
-- Module Name: Syndrome_Calculator_N_Pipe
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st step in Goppa Code Decoding.
--
-- This circuit computes the syndrome from the ciphertext, support elements and
-- inverted evaluation of support elements into polynomial g, aka g(L)^(-1).
-- This circuit works by computing the syndrome of only the positions where the ciphertext
-- has value 1.
--
-- This is circuit version with a variable number of computation units and a pipeline.
-- A optimized version that loads and analyzes the ciphertext in a pipeline version is
-- syndrome_calculator_n_pipe_v2.
--
-- The circuits parameters
--
-- number_of_units :
--
-- The number of units that compute each syndrome at the same time.
-- This number must be 1 or greater.
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword or in this case the ciphertext. Both the codeword
-- and ciphertext has the same size.
--
-- size_codeword :
--
-- The number of bits necessary to hold the ciphertext/codeword.
-- This is ceil(log2(length_codeword)).
--
-- length_syndrome :
--
-- The size of the syndrome array. This parameter depends of the
-- Goppa code used.
--
-- size_syndrome :
--
-- The number of bits necessary to hold the array syndrome.
-- This is ceil(log2(length_syndrome)).
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- controller_syndrome_calculator_2_pipe Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_decrement_rst_nbits Rev 1.0
-- shift_register_rst_nbits Rev 1.0
-- mult_gf_2_m Rev 1.0
-- adder_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity syndrome_calculator_n_pipe is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- length_syndrome : integer := 54;
-- size_syndrome : integer := 6
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- length_syndrome : integer := 100;
-- size_syndrome : integer := 7
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 64;
-- size_syndrome : integer := 6
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 128;
-- size_syndrome : integer := 7
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3200;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 256;
-- size_syndrome : integer := 8
-- QD-GOPPA [7296, 5632, 128, 13] --
number_of_units : integer := 32;
gf_2_m : integer range 1 to 20 := 15;
length_codeword : integer := 8320;
size_codeword : integer := 14;
length_syndrome : integer := 256;
size_syndrome : integer := 8
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_L : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR(0 downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_h : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_L : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
address_new_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0)
);
end syndrome_calculator_n_pipe;
architecture Behavioral of syndrome_calculator_n_pipe is
component controller_syndrome_calculator_2_pipe
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
almost_units_ready : in STD_LOGIC;
empty_units : in STD_LOGIC;
limit_ctr_codeword_q : in STD_LOGIC;
limit_ctr_syndrome_q : in STD_LOGIC;
reg_first_syndrome_q : in STD_LOGIC_VECTOR(0 downto 0);
reg_codeword_q : in STD_LOGIC_VECTOR(0 downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
control_units_ce : out STD_LOGIC;
control_units_rst : out STD_LOGIC;
int_reg_L_ce : out STD_LOGIC;
int_square_h : out STD_LOGIC;
int_reg_h_ce : out STD_LOGIC;
int_reg_h_rst : out STD_LOGIC;
int_sel_reg_h : out STD_LOGIC;
reg_load_syndrome_ce : out STD_LOGIC;
reg_load_syndrome_rst : out STD_LOGIC;
reg_new_value_syndrome_ce : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_first_syndrome_ce : out STD_LOGIC;
reg_first_syndrome_rst : out STD_LOGIC;
ctr_load_address_syndrome_ce : out STD_LOGIC;
ctr_load_address_syndrome_rst : out STD_LOGIC;
reg_bus_address_syndrome_ce : out STD_LOGIC;
reg_calc_address_syndrome_ce : out STD_LOGIC;
reg_store_address_syndrome_ce : out STD_LOGIC;
ctr_load_address_codeword_ce : out STD_LOGIC;
ctr_load_address_codeword_rst : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_decrement_rst_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component shift_register_rst_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component mult_gf_2_m
Generic (gf_2_m : integer range 1 to 20 := 11);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component adder_gf_2_m
Generic(
gf_2_m : integer := 1;
number_of_elements : integer range 2 to integer'high := 2
);
Port(
a : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_elements) - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal reg_L_d : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal reg_L_ce : STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
signal reg_L_q : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal reg_h_d :STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal reg_h_ce : STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
signal reg_h_rst : STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
constant reg_h_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_h_q : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal sel_reg_h : STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
signal square_h : STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
signal reg_load_syndrome_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_load_syndrome_ce : STD_LOGIC;
signal reg_load_syndrome_rst : STD_LOGIC;
constant reg_load_syndrome_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
signal reg_load_syndrome_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_syndrome_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_syndrome_ce : STD_LOGIC;
signal reg_new_value_syndrome_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_codeword_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_codeword_ce : STD_LOGIC;
signal reg_codeword_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_first_syndrome_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_first_syndrome_ce : STD_LOGIC;
signal reg_first_syndrome_rst : STD_LOGIC;
constant reg_first_syndrome_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "1";
signal reg_first_syndrome_q : STD_LOGIC_VECTOR(0 downto 0);
signal mult_a : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal mult_b : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal mult_o : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal adder_a : STD_LOGIC_VECTOR(((number_of_units+1)*gf_2_m - 1) downto 0);
signal adder_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_load_address_syndrome_ce : STD_LOGIC;
signal ctr_load_address_syndrome_rst : STD_LOGIC;
constant ctr_load_address_syndrome_rst_value : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0) := std_logic_vector(to_unsigned(length_syndrome - 1, size_syndrome));
signal ctr_load_address_syndrome_q : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal reg_bus_address_syndrome_d : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal reg_bus_address_syndrome_ce : STD_LOGIC;
signal reg_bus_address_syndrome_q : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal reg_calc_address_syndrome_d : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal reg_calc_address_syndrome_ce : STD_LOGIC;
signal reg_calc_address_syndrome_q : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal reg_store_address_syndrome_d : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal reg_store_address_syndrome_ce : STD_LOGIC;
signal reg_store_address_syndrome_q : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal ctr_load_address_codeword_ce : STD_LOGIC;
signal ctr_load_address_codeword_rst : STD_LOGIC;
constant ctr_load_address_codeword_rst_value : STD_LOGIC_VECTOR((size_codeword - 1) downto 0) := std_logic_vector(to_unsigned(0, size_codeword));
signal ctr_load_address_codeword_q : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal control_units_ce : STD_LOGIC;
signal control_units_rst : STD_LOGIC;
constant control_units_rst_value0 : STD_LOGIC_VECTOR((number_of_units - 1) downto 0) := (others => '0');
constant control_units_rst_value1 : STD_LOGIC_VECTOR((number_of_units) downto (number_of_units)) := "1";
constant control_units_rst_value : STD_LOGIC_VECTOR((number_of_units) downto 0) := control_units_rst_value1 & control_units_rst_value0;
signal control_units_q : STD_LOGIC_VECTOR((number_of_units) downto 0);
signal control_units_data_out : STD_LOGIC;
signal int_reg_L_ce : STD_LOGIC;
signal int_square_h : STD_LOGIC;
signal int_reg_h_ce : STD_LOGIC;
signal int_reg_h_rst: STD_LOGIC;
signal int_sel_reg_h : STD_LOGIC;
signal almost_units_ready : STD_LOGIC;
signal empty_units : STD_LOGIC;
signal limit_ctr_codeword_q : STD_LOGIC;
signal limit_ctr_syndrome_q : STD_LOGIC;
begin
controller : controller_syndrome_calculator_2_pipe
Port Map(
clk => clk,
rst => rst,
almost_units_ready => almost_units_ready,
empty_units => empty_units,
limit_ctr_codeword_q => limit_ctr_codeword_q,
limit_ctr_syndrome_q => limit_ctr_syndrome_q,
reg_first_syndrome_q => reg_first_syndrome_q,
reg_codeword_q => reg_codeword_q,
syndrome_finalized => syndrome_finalized,
write_enable_new_syndrome => write_enable_new_syndrome,
control_units_ce => control_units_ce,
control_units_rst => control_units_rst,
int_reg_L_ce => int_reg_L_ce,
int_square_h => int_square_h,
int_reg_h_ce => int_reg_h_ce,
int_reg_h_rst => int_reg_h_rst,
int_sel_reg_h => int_sel_reg_h,
reg_load_syndrome_ce => reg_load_syndrome_ce,
reg_load_syndrome_rst => reg_load_syndrome_rst,
reg_new_value_syndrome_ce => reg_new_value_syndrome_ce,
reg_codeword_ce => reg_codeword_ce,
reg_first_syndrome_ce => reg_first_syndrome_ce,
reg_first_syndrome_rst => reg_first_syndrome_rst,
ctr_load_address_syndrome_ce => ctr_load_address_syndrome_ce,
ctr_load_address_syndrome_rst => ctr_load_address_syndrome_rst,
reg_bus_address_syndrome_ce => reg_bus_address_syndrome_ce,
reg_calc_address_syndrome_ce => reg_calc_address_syndrome_ce,
reg_store_address_syndrome_ce => reg_store_address_syndrome_ce,
ctr_load_address_codeword_ce => ctr_load_address_codeword_ce,
ctr_load_address_codeword_rst => ctr_load_address_codeword_rst
);
calculator_units : for I in 0 to (number_of_units - 1) generate
reg_L_I : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_L_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
clk => clk,
ce => reg_L_ce(I),
q => reg_L_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
reg_h_I : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_h_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
clk => clk,
ce => reg_h_ce(I),
rst => reg_h_rst(I),
rst_value => reg_h_rst_value,
q => reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
mult_I : mult_gf_2_m
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => mult_a(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
b => mult_b(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
o => mult_o(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
reg_L_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= value_L;
reg_h_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= mult_o(((I + 1)*gf_2_m - 1) downto I*gf_2_m) when sel_reg_h(I) = '1' else
value_h;
mult_a(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m) when square_h(I) = '1' else
reg_L_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m);
mult_b(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m);
reg_L_ce(I) <= int_reg_L_ce and control_units_q(I);
square_h(I) <= int_square_h and control_units_q(I);
reg_h_ce(I) <= int_reg_h_ce and (control_units_q(I) or (int_sel_reg_h and (not int_square_h)));
reg_h_rst(I) <= int_reg_h_rst and control_units_q(I);
sel_reg_h(I) <= int_sel_reg_h;
end generate;
control_units : shift_register_rst_nbits
Generic Map(
size => number_of_units+1
)
Port Map(
data_in => control_units_data_out,
clk => clk,
ce => control_units_ce,
rst => control_units_rst,
rst_value => control_units_rst_value,
q => control_units_q,
data_out => control_units_data_out
);
adder : adder_gf_2_m
Generic Map(
gf_2_m => gf_2_m,
number_of_elements => number_of_units+1
)
Port Map(
a => adder_a,
o => adder_o
);
reg_load_syndrome : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_load_syndrome_d,
clk => clk,
ce => reg_load_syndrome_ce,
rst => reg_load_syndrome_rst,
rst_value => reg_load_syndrome_rst_value,
q => reg_load_syndrome_q
);
reg_new_value_syndrome : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_syndrome_d,
clk => clk,
ce => reg_new_value_syndrome_ce,
q => reg_new_value_syndrome_q
);
reg_codeword : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_codeword_d,
clk => clk,
ce => reg_codeword_ce,
q => reg_codeword_q
);
reg_first_syndrome : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_first_syndrome_d,
clk => clk,
ce => reg_first_syndrome_ce,
rst => reg_first_syndrome_rst,
rst_value => reg_first_syndrome_rst_value,
q => reg_first_syndrome_q
);
ctr_load_address_syndrome : counter_decrement_rst_nbits
Generic Map(
size => size_syndrome,
decrement_value => 1
)
Port Map(
clk => clk,
ce => ctr_load_address_syndrome_ce,
rst => ctr_load_address_syndrome_rst,
rst_value => ctr_load_address_syndrome_rst_value,
q => ctr_load_address_syndrome_q
);
reg_bus_address_syndrome : register_nbits
Generic Map(
size => size_syndrome
)
Port Map(
d => reg_bus_address_syndrome_d,
clk => clk,
ce => reg_bus_address_syndrome_ce,
q => reg_bus_address_syndrome_q
);
reg_calc_address_syndrome : register_nbits
Generic Map(
size => size_syndrome
)
Port Map(
d => reg_calc_address_syndrome_d,
clk => clk,
ce => reg_calc_address_syndrome_ce,
q => reg_calc_address_syndrome_q
);
reg_store_address_syndrome : register_nbits
Generic Map(
size => size_syndrome
)
Port Map(
d => reg_store_address_syndrome_d,
clk => clk,
ce => reg_store_address_syndrome_ce,
q => reg_store_address_syndrome_q
);
ctr_load_address_codeword : counter_rst_nbits
Generic Map(
size => size_codeword,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_load_address_codeword_ce,
rst => ctr_load_address_codeword_rst,
rst_value => ctr_load_address_codeword_rst_value,
q => ctr_load_address_codeword_q
);
adder_a <= reg_h_q & reg_load_syndrome_q;
reg_load_syndrome_d <= value_syndrome;
reg_codeword_d <= value_codeword;
reg_first_syndrome_d <= "0";
reg_new_value_syndrome_d <= adder_o;
new_value_syndrome <= reg_new_value_syndrome_q;
reg_bus_address_syndrome_d <= ctr_load_address_syndrome_q;
reg_calc_address_syndrome_d <= reg_bus_address_syndrome_q;
reg_store_address_syndrome_d <= reg_calc_address_syndrome_q;
address_h <= ctr_load_address_codeword_q;
address_L <= ctr_load_address_codeword_q;
address_codeword <= ctr_load_address_codeword_q;
address_syndrome <= ctr_load_address_syndrome_q;
address_new_syndrome <= reg_store_address_syndrome_q;
almost_units_ready <= control_units_q(number_of_units - 1);
empty_units <= control_units_q(0);
limit_ctr_codeword_q <= '1' when (ctr_load_address_codeword_q = std_logic_vector(to_unsigned(length_codeword - 1, ctr_load_address_codeword_q'length))) else '0';
limit_ctr_syndrome_q <= '1' when (reg_store_address_syndrome_q = std_logic_vector(to_unsigned(0, ctr_load_address_syndrome_q'length))) else '0';
end Behavioral;
|
bsd-2-clause
|
e937855c10ea6017f2235d8f4fdccc57
| 0.662422 | 2.73271 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/decoBCD/contbcd.vhd
| 3 | 810 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity contBCD is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
s: out std_logic_vector(3 downto 0);
co: out std_logic
);
end;
architecture contBCD_arq of contBCD is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(clk,rst)
variable count: integer range 0 to 10;
begin
if rst = '1' then
s <= (others => '0');
co <= '0';
elsif rising_edge(clk) then
if ena = '1' then
count:=count + 1;
if count = 9 then
co <= '1';
elsif count = 10 then
count := 0;
co <= '0';
else
co <= '0';
end if;
end if;
end if;
s <= std_logic_vector(TO_UNSIGNED(count,4));
end process;
end;
|
gpl-3.0
|
5790ad711a7204e68c000244391218fa
| 0.580247 | 2.87234 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/finite_field/inv_gf_2_m.vhd
| 1 | 49,351 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Inv_GF_2_M
-- Module Name: Inv_GF_2_M
-- Project Name: GF_2_M Arithmetic
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit computes the inversion of a element in GF(2^m)
-- This circuit has a pure combinatorial strategy.
--
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit.
--
-- Dependencies:
-- VHDL-93
--
-- mult_gf_2_m Rev 1.0
-- pow2_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity inv_gf_2_m is
Generic(gf_2_m : integer range 1 to 20);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end inv_gf_2_m;
architecture Behavioral of inv_gf_2_m is
component pow2_gf_2_m
Generic(gf_2_m : integer range 1 to 20);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component mult_gf_2_m
Generic(gf_2_m : integer range 1 to 20);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
type vector is array(integer range <>) of std_logic_vector((gf_2_m - 1) downto 0);
signal intermediate_values : vector(0 to 30);
--for all : pow2_gf_2_m use entity work.pow2_gf_2_m(Software_POLYNOMIAL);
begin
GF_2_1 : if gf_2_m = 1 generate
o <= a;
end generate;
GF_2_2 : if gf_2_m = 2 generate -- x^2 + x^1 + 1
GF_2_2_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => o
);
end generate;
GF_2_3 : if gf_2_m = 3 generate -- x^3 + x^1 + 1
GF_2_3_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_3_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_3_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => o
);
end generate;
GF_2_4 : if gf_2_m = 4 generate -- x^4 + x^1 + 1
GF_2_4_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_4_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_4_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => intermediate_values(2)
);
GF_2_4_op_3 : mult_gf_2_m -- a^7
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(2),
o => intermediate_values(3)
);
GF_2_4_op_4 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^14
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => o
);
end generate;
GF_2_5 : if gf_2_m = 5 generate -- x^5 + x^2 + 1
GF_2_5_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_5_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_5_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => intermediate_values(2)
);
GF_2_5_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(2),
o => intermediate_values(3)
);
GF_2_5_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_5_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => o
);
end generate;
GF_2_6 : if gf_2_m = 6 generate -- x^6 + x^1 + 1
GF_2_6_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_6_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_6_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => intermediate_values(2)
);
GF_2_6_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(2),
o => intermediate_values(3)
);
GF_2_6_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_6_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
GF_2_6_op_6 : mult_gf_2_m -- a^31
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(5),
o => intermediate_values(6)
);
GF_2_6_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^62
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(6),
o => o
);
end generate;
GF_2_7 : if gf_2_m = 7 generate -- x^7 + x^1 + 1
GF_2_7_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_7_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_7_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => intermediate_values(2)
);
GF_2_7_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(2),
o => intermediate_values(3)
);
GF_2_7_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_7_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
GF_2_7_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(5),
o => intermediate_values(6)
);
GF_2_7_op_7 : mult_gf_2_m -- a^63
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_7_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^126
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => o
);
end generate;
GF_2_8 : if gf_2_m = 8 generate -- x^8 + x^4 + x^3 + x^1 + 1
GF_2_8_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_8_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_8_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => intermediate_values(2)
);
GF_2_8_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(2),
o => intermediate_values(3)
);
GF_2_8_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_8_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
GF_2_8_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(5),
o => intermediate_values(6)
);
GF_2_8_op_7 : mult_gf_2_m -- a^63
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_8_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^126
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
GF_2_8_op_9 : mult_gf_2_m -- a^127
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(8),
o => intermediate_values(9)
);
GF_2_8_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^254
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => o
);
end generate;
GF_2_9 : if gf_2_m = 9 generate -- x^9 + x^1 + 1
GF_2_9_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_9_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_9_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => intermediate_values(2)
);
GF_2_9_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(2),
o => intermediate_values(3)
);
GF_2_9_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_9_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
GF_2_9_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(5),
o => intermediate_values(6)
);
GF_2_9_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_9_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
GF_2_9_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
b => intermediate_values(8),
o => intermediate_values(9)
);
GF_2_9_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => o
);
end generate;
GF_2_10 : if gf_2_m = 10 generate -- x^10 + x^3 + 1
GF_2_10_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_10_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_10_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => intermediate_values(2)
);
GF_2_10_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(2),
o => intermediate_values(3)
);
GF_2_10_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_10_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
GF_2_10_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(5),
o => intermediate_values(6)
);
GF_2_10_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_10_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
GF_2_10_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
b => intermediate_values(8),
o => intermediate_values(9)
);
GF_2_10_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_10_op_11 : mult_gf_2_m -- a^511
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_10_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1022
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => o
);
end generate;
GF_2_11 : if gf_2_m = 11 generate -- x^11 + x^2 + 1
GF_2_11_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_11_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_11_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => intermediate_values(2)
);
GF_2_11_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(2),
o => intermediate_values(3)
);
GF_2_11_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_11_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
GF_2_11_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(5),
o => intermediate_values(6)
);
GF_2_11_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_11_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
GF_2_11_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
b => intermediate_values(8),
o => intermediate_values(9)
);
GF_2_11_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_11_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_11_op_12 : mult_gf_2_m -- a^1023
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(11),
o => intermediate_values(12)
);
GF_2_11_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2046
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(12),
o => o
);
end generate;
GF_2_12 : if gf_2_m = 12 generate -- x^12 + x^3 + 1
GF_2_12_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_12_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_12_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => intermediate_values(2)
);
GF_2_12_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(2),
o => intermediate_values(3)
);
GF_2_12_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_12_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
GF_2_12_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(5),
o => intermediate_values(6)
);
GF_2_12_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_12_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
GF_2_12_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
b => intermediate_values(8),
o => intermediate_values(9)
);
GF_2_12_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_12_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_12_op_12 : mult_gf_2_m -- a^1023
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(11),
o => intermediate_values(12)
);
GF_2_12_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2046
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(12),
o => intermediate_values(13)
);
GF_2_12_op_14 : mult_gf_2_m -- a^2047
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_12_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4094
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => o
);
end generate;
GF_2_13 : if gf_2_m = 13 generate -- x^13 + x^4 + x^3 + x^1 + 1
GF_2_13_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_13_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_13_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => intermediate_values(2)
);
GF_2_13_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(2),
o => intermediate_values(3)
);
GF_2_13_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_13_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
GF_2_13_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(5),
o => intermediate_values(6)
);
GF_2_13_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_13_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
GF_2_13_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
b => intermediate_values(8),
o => intermediate_values(9)
);
GF_2_13_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_13_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_13_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2040
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
GF_2_13_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4080
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(12),
o => intermediate_values(13)
);
GF_2_13_op_14 : mult_gf_2_m -- a^4095
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
b => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_13_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^8190
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => o
);
end generate;
GF_2_14 : if gf_2_m = 14 generate -- x^14 + x^5 + 1
GF_2_14_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_14_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_14_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => intermediate_values(2)
);
GF_2_14_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(2),
o => intermediate_values(3)
);
GF_2_14_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_14_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
GF_2_14_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(5),
o => intermediate_values(6)
);
GF_2_14_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_14_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
GF_2_14_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
b => intermediate_values(8),
o => intermediate_values(9)
);
GF_2_14_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_14_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_14_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2040
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
GF_2_14_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4080
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(12),
o => intermediate_values(13)
);
GF_2_14_op_14 : mult_gf_2_m -- a^4095
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
b => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_14_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^8190
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
GF_2_14_op_16 : mult_gf_2_m -- a^8191
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(15),
o => intermediate_values(16)
);
GF_2_14_op_17 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^16382
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(16),
o => o
);
end generate;
GF_2_15 : if gf_2_m = 15 generate -- x^15 + x^1 + 1
GF_2_15_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_15_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_15_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => intermediate_values(2)
);
GF_2_15_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(2),
o => intermediate_values(3)
);
GF_2_15_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_15_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
GF_2_15_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(5),
o => intermediate_values(6)
);
GF_2_15_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_15_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
GF_2_15_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
b => intermediate_values(8),
o => intermediate_values(9)
);
GF_2_15_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_15_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_15_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2040
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
GF_2_15_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4080
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(12),
o => intermediate_values(13)
);
GF_2_15_op_14 : mult_gf_2_m -- a^4095
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
b => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_15_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^8190
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
GF_2_15_op_16 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^16380
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(15),
o => intermediate_values(16)
);
GF_2_15_op_17 : mult_gf_2_m -- a^16383
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(16),
o => intermediate_values(17)
);
GF_2_15_op_18 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^32766
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(17),
o => o
);
end generate;
GF_2_16 : if gf_2_m = 16 generate -- x^16 + x^5 + x^3 + x^1 + 1
GF_2_16_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_16_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_16_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => intermediate_values(2)
);
GF_2_16_op_3 : mult_gf_2_m -- a^7
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(2),
o => intermediate_values(3)
);
GF_2_16_op_4 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^14
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_16_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^28
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
GF_2_16_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^56
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(5),
o => intermediate_values(6)
);
GF_2_16_op_7 : mult_gf_2_m -- a^63
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
b => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_16_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^126
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
GF_2_16_op_9 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^252
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(8),
o => intermediate_values(9)
);
GF_2_16_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^504
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_16_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1008
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_16_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2016
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
GF_2_16_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4032
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(12),
o => intermediate_values(13)
);
GF_2_16_op_14 : mult_gf_2_m -- a^4095
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
b => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_16_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^8190
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
GF_2_16_op_16 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^16380
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(15),
o => intermediate_values(16)
);
GF_2_16_op_17 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^32760
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(16),
o => intermediate_values(17)
);
GF_2_16_op_18 : mult_gf_2_m -- a^32767
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(3),
b => intermediate_values(17),
o => intermediate_values(18)
);
GF_2_16_op_19 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^65534
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(18),
o => o
);
end generate;
GF_2_17 : if gf_2_m = 17 generate -- x^17 + x^3 + 1
GF_2_17_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_17_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_17_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => intermediate_values(2)
);
GF_2_17_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(2),
o => intermediate_values(3)
);
GF_2_17_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_17_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
GF_2_17_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(5),
o => intermediate_values(6)
);
GF_2_17_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_17_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
GF_2_17_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
b => intermediate_values(8),
o => intermediate_values(9)
);
GF_2_17_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_17_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_17_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2040
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
GF_2_17_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4080
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(12),
o => intermediate_values(13)
);
GF_2_17_op_14 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^8160
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_17_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^16320
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
GF_2_17_op_16 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^32640
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(15),
o => intermediate_values(16)
);
GF_2_17_op_17 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^65280
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(16),
o => intermediate_values(17)
);
GF_2_17_op_18 : mult_gf_2_m -- a^65535
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
b => intermediate_values(17),
o => intermediate_values(18)
);
GF_2_17_op_19 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^131070
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(18),
o => o
);
end generate;
GF_2_18 : if gf_2_m = 18 generate -- x^18 + x^3 + 1
GF_2_18_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_18_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_18_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => intermediate_values(2)
);
GF_2_18_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(2),
o => intermediate_values(3)
);
GF_2_18_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_18_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
GF_2_18_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(5),
o => intermediate_values(6)
);
GF_2_18_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_18_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
GF_2_18_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
b => intermediate_values(8),
o => intermediate_values(9)
);
GF_2_18_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_18_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_18_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2040
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
GF_2_18_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4080
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(12),
o => intermediate_values(13)
);
GF_2_18_op_14 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^8160
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_18_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^16320
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
GF_2_18_op_16 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^32640
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(15),
o => intermediate_values(16)
);
GF_2_18_op_17 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^65280
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(16),
o => intermediate_values(17)
);
GF_2_18_op_18 : mult_gf_2_m -- a^65535
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
b => intermediate_values(17),
o => intermediate_values(18)
);
GF_2_18_op_19 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^131070
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(18),
o => intermediate_values(19)
);
GF_2_18_op_20 : mult_gf_2_m -- a^131071
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(19),
o => intermediate_values(20)
);
GF_2_18_op_21 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^262142
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(20),
o => o
);
end generate;
GF_2_19 : if gf_2_m = 19 generate -- x^19 + x^5 + x^2 + x^1 + 1
GF_2_19_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_19_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_19_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => intermediate_values(2)
);
GF_2_19_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(2),
o => intermediate_values(3)
);
GF_2_19_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_19_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
GF_2_19_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(5),
o => intermediate_values(6)
);
GF_2_19_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_19_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
GF_2_19_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
b => intermediate_values(8),
o => intermediate_values(9)
);
GF_2_19_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_19_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_19_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2040
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
GF_2_19_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4080
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(12),
o => intermediate_values(13)
);
GF_2_19_op_14 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^8160
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_19_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^16320
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
GF_2_19_op_16 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^32640
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(15),
o => intermediate_values(16)
);
GF_2_19_op_17 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^65280
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(16),
o => intermediate_values(17)
);
GF_2_19_op_18 : mult_gf_2_m -- a^65535
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
b => intermediate_values(17),
o => intermediate_values(18)
);
GF_2_19_op_19 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^131070
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(18),
o => intermediate_values(19)
);
GF_2_19_op_20 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^262140
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(19),
o => intermediate_values(20)
);
GF_2_19_op_21 : mult_gf_2_m -- a^262143
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(20),
o => intermediate_values(21)
);
GF_2_19_op_22 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^524286
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(21),
o => o
);
end generate;
GF_2_20 : if gf_2_m = 20 generate -- x^20 + x^3 + 1
GF_2_20_op_0 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
o => intermediate_values(0)
);
GF_2_20_op_1 : mult_gf_2_m -- a^3
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(0),
o => intermediate_values(1)
);
GF_2_20_op_2 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^6
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
o => intermediate_values(2)
);
GF_2_20_op_3 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^12
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(2),
o => intermediate_values(3)
);
GF_2_20_op_4 : mult_gf_2_m -- a^15
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(3),
o => intermediate_values(4)
);
GF_2_20_op_5 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^30
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
o => intermediate_values(5)
);
GF_2_20_op_6 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^60
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(5),
o => intermediate_values(6)
);
GF_2_20_op_7 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^120
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(6),
o => intermediate_values(7)
);
GF_2_20_op_8 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^240
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(7),
o => intermediate_values(8)
);
GF_2_20_op_9 : mult_gf_2_m -- a^255
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(4),
b => intermediate_values(8),
o => intermediate_values(9)
);
GF_2_20_op_10 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^510
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
o => intermediate_values(10)
);
GF_2_20_op_11 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1020
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(10),
o => intermediate_values(11)
);
GF_2_20_op_12 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^2040
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(11),
o => intermediate_values(12)
);
GF_2_20_op_13 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^4080
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(12),
o => intermediate_values(13)
);
GF_2_20_op_14 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^8160
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(13),
o => intermediate_values(14)
);
GF_2_20_op_15 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^16320
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(14),
o => intermediate_values(15)
);
GF_2_20_op_16 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^32640
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(15),
o => intermediate_values(16)
);
GF_2_20_op_17 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^65280
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(16),
o => intermediate_values(17)
);
GF_2_20_op_18 : mult_gf_2_m -- a^65535
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(9),
b => intermediate_values(17),
o => intermediate_values(18)
);
GF_2_20_op_19 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^131070
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(18),
o => intermediate_values(19)
);
GF_2_20_op_20 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^262140
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(19),
o => intermediate_values(20)
);
GF_2_20_op_21 : mult_gf_2_m -- a^262143
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(1),
b => intermediate_values(20),
o => intermediate_values(21)
);
GF_2_20_op_22 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^524286
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(21),
o => intermediate_values(22)
);
GF_2_20_op_23 : mult_gf_2_m -- a^524287
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => a,
b => intermediate_values(22),
o => intermediate_values(23)
);
GF_2_20_op_24 : entity work.pow2_gf_2_m(Software_POLYNOMIAL) -- a^1048574
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => intermediate_values(23),
o => o
);
end generate;
end Behavioral;
|
bsd-2-clause
|
bee36596e363df167b405abaab120fc2
| 0.600109 | 2.228439 | false | false | false | false |
pwuertz/digitizer2fw
|
src/rtl/tdc_sample_prep.vhd
| 1 | 6,228 |
-------------------------------------------------------------------------------
-- TDC sample preparation
--
-- This component processes the input signals looking for events, rising edges
-- for digital, maxfind for analog. The module also includes a sample counter
-- which also generates an event on overflow.
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sampling_pkg.all;
use work.maxfinder_pkg.all;
use work.tdc_sample_prep_pkg.all;
entity tdc_sample_prep is
generic (
CNT_BITS: natural := 16
);
port (
clk: in std_logic;
samples_d_in: in din_samples_t(0 to 3);
samples_a_in: in adc_samples_t(0 to 1);
a_threshold: in a_sample_t;
a_invert: in std_logic;
a_average: in std_logic_vector(1 downto 0);
--
samples_d_out: out din_samples_t(0 to 3);
samples_a_out: out a_samples_t(0 to 1);
cnt: out unsigned(CNT_BITS-1 downto 0);
tdc_events: out tdc_events_t
);
end tdc_sample_prep;
architecture tdc_sample_prep_arch of tdc_sample_prep is
-- input filtering
signal samples_a_in_avg, samples_a_in_filt: adc_samples_t(0 to 1);
-- queue samples for sample out alignment after rising/maximum detection
constant D_QUEUE_LEN: natural := 2;
constant A_QUEUE_LEN: natural := 8; -- 8
type samples_d_buf_t is array(0 to D_QUEUE_LEN-1) of din_samples_t(0 to 3);
type samples_a_buf_t is array(0 to A_QUEUE_LEN-1) of a_samples_t(0 to 1);
signal samples_d_buf: samples_d_buf_t := (others => (others => (others => '0')));
signal samples_a_buf: samples_a_buf_t := (others => (others => (others => '0')));
-- sample counter
signal sample_cnt_int: unsigned(CNT_BITS-1 downto 0) := (others => '0');
-- digital processing
component digital_edge_detect
port (
clk: in std_logic;
samples_d: in din_samples_t(0 to 3);
rising_d: out din_samples_t(0 to 3);
falling_d: out din_samples_t(0 to 3)
);
end component;
signal rising_d, falling_d: din_samples_t(0 to 3);
signal d1_rising_int, d1_falling_int: std_logic_vector(3 downto 0) := (others => '0');
signal d2_rising_int, d2_falling_int: std_logic_vector(3 downto 0) := (others => '0');
-- analog processing
component maxfinder_simple
generic (
N_FRAC_BITS: natural := 1;
N_ADIFF_CLIP: natural := 0
);
port (
clk: in std_logic;
samples_in: in a_samples_t(0 to 1);
threshold: in a_sample_t;
max_found: out std_logic;
max_pos: out unsigned(1+N_FRAC_BITS-1 downto 0);
max_height: out a_sample_t
);
end component;
signal max_samples_in: a_samples_t(0 to 1);
signal max_found: std_logic;
signal max_pos: unsigned(1 downto 0) := (others => '0');
signal max_height: a_sample_t := (others => '0');
signal a_maxfound_int: tdc_event_t;
begin
-- input filter
a_filter: entity work.sample_average
port map (
clk => clk,
n => a_average,
samples_a_in => samples_a_in,
samples_a_out => samples_a_in_avg
);
process(clk)
begin
if rising_edge(clk) then
for I in samples_a_in_avg'low to samples_a_in_avg'high loop
samples_a_in_filt(I) <= samples_a_in_avg(I);
if a_invert = '1' then
samples_a_in_filt(I).data <= -samples_a_in_avg(I).data;
end if;
end loop;
end if;
end process;
-- sample counter
proc_sample_counter: process(clk)
constant X: unsigned(CNT_BITS-1 downto 0) := (others => '1');
begin
if rising_edge(clk) then
sample_cnt_int <= sample_cnt_int + 1;
end if;
end process;
-- digital rising edges
digital_edge_detect_inst: digital_edge_detect
port map(
clk => clk,
samples_d => samples_d_in,
rising_d => rising_d,
falling_d => falling_d
);
d1_rising_int <= rising_d(0)(0) & rising_d(1)(0) & rising_d(2)(0) & rising_d(3)(0);
d2_rising_int <= rising_d(0)(1) & rising_d(1)(1) & rising_d(2)(1) & rising_d(3)(1);
d1_falling_int <= falling_d(0)(0) & falling_d(1)(0) & falling_d(2)(0) & falling_d(3)(0);
d2_falling_int <= falling_d(0)(1) & falling_d(1)(1) & falling_d(2)(1) & falling_d(3)(1);
-- analog maximum finder
maxfinder_inst: maxfinder_simple
port map(
clk => clk,
samples_in => max_samples_in,
threshold => a_threshold,
max_found => max_found,
max_pos => max_pos,
max_height => max_height
);
max_samples_in(0) <= samples_a_in_filt(0).data;
max_samples_in(1) <= samples_a_in_filt(1).data;
a_maxfound_int <= (valid => max_found, pos => max_pos);
--------------------------------------------------------------------------------
-- output
-- shift in/out input samples, use queue to align input samples with event outputs
process(clk)
begin
if rising_edge(clk) then
-- digital
samples_d_buf(1 to samples_d_buf'high) <= samples_d_buf(0 to samples_d_buf'high-1);
samples_d_buf(0) <= samples_d_in;
samples_d_out <= samples_d_buf(samples_d_buf'high);
-- analog
samples_a_buf(1 to samples_a_buf'high) <= samples_a_buf(0 to samples_a_buf'high-1);
for I in samples_a_in_filt'low to samples_a_in_filt'high loop
samples_a_buf(0)(I) <= samples_a_in_filt(I).data;
end loop;
samples_a_out <= samples_a_buf(samples_a_buf'high);
end if;
end process;
-- register event outputs
process(clk)
begin
if rising_edge(clk) then
cnt <= sample_cnt_int;
tdc_events <= (
d1_rising => flat_events_to_event_t(d1_rising_int),
d1_falling => flat_events_to_event_t(d1_falling_int),
d2_rising => flat_events_to_event_t(d2_rising_int),
d2_falling => flat_events_to_event_t(d2_falling_int),
a_maxfound => a_maxfound_int,
a_maxvalue => max_height
);
end if;
end process;
end tdc_sample_prep_arch;
|
gpl-3.0
|
a35f8621f95eb52ed0142517cd031d81
| 0.593062 | 3.132294 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/controller_syndrome_computing.vhd
| 1 | 16,438 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Syndrome_Computing
-- Module Name: Controller_Syndrome_Computing
-- Project Name: McEliece Goppa decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st step in Goppa Decoding.
--
-- This circuit is the state machine for polynomial_syndrome_computing_n.
-- This state machine is only active during syndrome computation.
-- During polynomial sigma evaluation and roots search, this circuit is ignored and
-- controlled by controller_polynomial_computing.
--
-- For optimizations in polynomial_syndrome_computing_n_v2 both states machines were joined
-- joined into a single one that can run both algorithms.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_syndrome_computing is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_load_x_values : in STD_LOGIC;
last_store_x_values : in STD_LOGIC;
last_syndrome_value : in STD_LOGIC;
final_syndrome_evaluation : in STD_LOGIC;
pipeline_ready : in STD_LOGIC;
evaluation_data_in : out STD_LOGIC;
reg_write_enable_rst : out STD_LOGIC;
ctr_load_x_address_ce : out STD_LOGIC;
ctr_load_x_address_rst : out STD_LOGIC;
ctr_store_x_address_ce : out STD_LOGIC;
ctr_store_x_address_rst : out STD_LOGIC;
reg_first_values_ce : out STD_LOGIC;
reg_first_values_rst : out STD_LOGIC;
ctr_address_syndrome_ce : out STD_LOGIC;
ctr_address_syndrome_load : out STD_LOGIC;
ctr_address_syndrome_increment_decrement : out STD_LOGIC;
ctr_address_syndrome_rst : out STD_LOGIC;
reg_store_temporary_syndrome_ce : out STD_LOGIC;
reg_final_syndrome_evaluation_ce : out STD_LOGIC;
reg_final_syndrome_evaluation_rst : out STD_LOGIC;
finalize_syndrome : out STD_LOGIC;
shift_polynomial_ce_ce : out STD_LOGIC;
shift_polynomial_ce_rst : out STD_LOGIC;
shift_syndrome_data_in : out STD_LOGIC;
shift_syndrome_mode_rst : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
calculation_finalized : out STD_LOGIC
);
end controller_syndrome_computing;
architecture Behavioral of controller_syndrome_computing is
type State is (reset, load_counter, load_L_syndrome_values, prepare_write_load_L_values, write_load_L_values, prepare_write_L_values, write_L_values, write_syndrome_values, last_write_syndrome_values, final_write_syndrome_values, final_last_write_syndrome_values, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, last_load_x_values, last_store_x_values, last_syndrome_value, final_syndrome_evaluation, pipeline_ready)
begin
case (actual_state) is
when reset =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '1';
ctr_address_syndrome_ce <= '0';
ctr_address_syndrome_load <= '0';
ctr_address_syndrome_increment_decrement <= '0';
ctr_address_syndrome_rst <= '1';
reg_store_temporary_syndrome_ce <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '1';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '1';
shift_syndrome_data_in <= '1';
shift_syndrome_mode_rst <= '1';
write_enable_new_value_syndrome <= '0';
calculation_finalized <= '0';
when load_counter =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '1';
ctr_address_syndrome_ce <= '0';
ctr_address_syndrome_load <= '0';
ctr_address_syndrome_increment_decrement <= '0';
ctr_address_syndrome_rst <= '1';
reg_store_temporary_syndrome_ce <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '1';
shift_syndrome_data_in <= '1';
shift_syndrome_mode_rst <= '1';
write_enable_new_value_syndrome <= '0';
calculation_finalized <= '0';
when load_L_syndrome_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_syndrome_ce <= '0';
ctr_address_syndrome_load <= '0';
ctr_address_syndrome_increment_decrement <= '0';
ctr_address_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
calculation_finalized <= '0';
when prepare_write_load_L_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_syndrome_ce <= '0';
ctr_address_syndrome_load <= '0';
ctr_address_syndrome_increment_decrement <= '0';
ctr_address_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
calculation_finalized <= '0';
when write_load_L_values =>
if(last_load_x_values = '1') then
ctr_load_x_address_ce <= '0';
else
ctr_load_x_address_ce <= '1';
end if;
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_syndrome_ce <= '0';
ctr_address_syndrome_load <= '0';
ctr_address_syndrome_increment_decrement <= '0';
ctr_address_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
calculation_finalized <= '0';
when prepare_write_L_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '1';
reg_first_values_rst <= '0';
ctr_address_syndrome_ce <= '0';
ctr_address_syndrome_load <= '0';
ctr_address_syndrome_increment_decrement <= '0';
ctr_address_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
calculation_finalized <= '0';
when write_L_values =>
if(last_syndrome_value = '1') then
reg_final_syndrome_evaluation_ce <= '1';
else
reg_final_syndrome_evaluation_ce <= '0';
end if;
if(last_store_x_values = '1') then
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
ctr_address_syndrome_ce <= '0';
ctr_address_syndrome_increment_decrement <= '0';
reg_store_temporary_syndrome_ce <= '1';
shift_polynomial_ce_rst <= '1';
else
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
ctr_address_syndrome_ce <= '1';
ctr_address_syndrome_increment_decrement <= '1';
reg_store_temporary_syndrome_ce <= '0';
shift_polynomial_ce_rst <= '0';
end if;
evaluation_data_in <= '1';
ctr_load_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_syndrome_load <= '0';
ctr_address_syndrome_rst <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '0';
shift_polynomial_ce_ce <= '0';
shift_syndrome_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
calculation_finalized <= '0';
when write_syndrome_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_syndrome_ce <= '1';
ctr_address_syndrome_increment_decrement <= '0';
ctr_address_syndrome_load <= '0';
ctr_address_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '1';
calculation_finalized <= '0';
when last_write_syndrome_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_syndrome_ce <= '1';
ctr_address_syndrome_load <= '1';
ctr_address_syndrome_increment_decrement <= '0';
ctr_address_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
calculation_finalized <= '0';
when final_write_syndrome_values =>
if(final_syndrome_evaluation = '1' and last_syndrome_value = '0') then
write_enable_new_value_syndrome <= '0';
else
write_enable_new_value_syndrome <= '1';
end if;
if(last_syndrome_value = '1') then
reg_final_syndrome_evaluation_rst <= '1';
else
reg_final_syndrome_evaluation_rst <= '0';
end if;
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_syndrome_ce <= '1';
ctr_address_syndrome_load <= '0';
ctr_address_syndrome_increment_decrement <= '0';
ctr_address_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_final_syndrome_evaluation_ce <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_data_in <= '1';
shift_syndrome_mode_rst <= '0';
calculation_finalized <= '0';
when final_last_write_syndrome_values =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_syndrome_ce <= '0';
ctr_address_syndrome_load <= '0';
ctr_address_syndrome_increment_decrement <= '0';
ctr_address_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
calculation_finalized <= '0';
when final =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '1';
ctr_address_syndrome_ce <= '0';
ctr_address_syndrome_load <= '0';
ctr_address_syndrome_increment_decrement <= '0';
ctr_address_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '1';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
calculation_finalized <= '1';
when others =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_syndrome_ce <= '0';
ctr_address_syndrome_load <= '0';
ctr_address_syndrome_increment_decrement <= '0';
ctr_address_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
calculation_finalized <= '0';
end case;
end process;
NewState: process (actual_state, last_load_x_values, last_store_x_values, last_syndrome_value, final_syndrome_evaluation, pipeline_ready)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= load_L_syndrome_values;
when load_L_syndrome_values =>
if(pipeline_ready = '1') then
next_state <= prepare_write_load_L_values;
else
next_state <= load_L_syndrome_values;
end if;
when prepare_write_load_L_values =>
next_state <= write_load_L_values;
when write_load_L_values =>
if(last_load_x_values = '1') then
next_state <= prepare_write_L_values;
else
next_state <= write_load_L_values;
end if;
when prepare_write_L_values =>
next_state <= write_L_values;
when write_L_values =>
if(last_store_x_values = '1') then
if(final_syndrome_evaluation = '1' or last_syndrome_value = '1') then
next_state <= final_write_syndrome_values;
else
next_state <= write_syndrome_values;
end if;
else
next_state <= write_L_values;
end if;
when write_syndrome_values =>
if(pipeline_ready = '1') then
next_state <= last_write_syndrome_values;
else
next_state <= write_syndrome_values;
end if;
when last_write_syndrome_values =>
next_state <= write_load_L_values;
when final_write_syndrome_values =>
if(pipeline_ready = '1') then
next_state <= final_last_write_syndrome_values;
else
next_state <= final_write_syndrome_values;
end if;
when final_last_write_syndrome_values =>
next_state <= final;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
b97f6149a1679a361be9d3f969a4feb2
| 0.629821 | 2.857292 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/class_adder/class_adder_tb.vhd
| 1 | 2,417 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity class_adder_tb is
end entity;
architecture class_adder_tb_arq of class_adder_tb is
signal number1_in: std_logic_vector(3 downto 0);
signal number2_in: std_logic_vector(3 downto 0);
signal result: std_logic_vector(3 downto 0);
signal cout: std_logic;
signal cin: std_logic;
component class_adder is
generic(N: integer:= 4);
port(
number1_in: in std_logic_vector(N-1 downto 0);
number2_in: in std_logic_vector(N-1 downto 0);
cin: in std_logic;
result: out std_logic_vector(N-1 downto 0);
cout: out std_logic
);
end component;
for class_adder_0: class_adder use entity work.class_adder;
begin
class_adder_0: class_adder
port map(
number1_in => number1_in,
number2_in => number2_in,
result => result,
cout => cout,
cin => cin
);
process
type pattern_type is record
in1 : std_logic_vector(3 downto 0); --input number
in2 : std_logic_vector(3 downto 0); --output
cin : std_logic;
r: std_logic_vector(3 downto 0); --output mantisa
co : std_logic; --output exponent
end record;
-- The patterns to apply.
type pattern_array is array (natural range<>) of pattern_type;
constant patterns : pattern_array := (
("1111", "1111",'0', "1110", '1'),
("0000", "0000",'1', "0001", '0'),
(std_logic_vector(to_unsigned(2,4)), std_logic_vector(to_unsigned(2,4)),'0', std_logic_vector(to_unsigned(4,4)), '0'),
(std_logic_vector(to_unsigned(4,4)), std_logic_vector(to_unsigned(4,4)),'0', std_logic_vector(to_unsigned(8,4)), '0')
);
begin
for i in patterns'range loop
-- Set the inputs.
number1_in <= patterns(i).in1;
number2_in <= patterns(i).in2;
cin <= patterns(i).cin;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert cout = patterns(i).co report "BAD CARRY: " & std_logic'image(cout) & ", ON " & integer'image(to_integer(unsigned(number1_in))) & " + " & integer'image(to_integer(unsigned(number2_in))) severity error;
assert result = patterns(i).r report "BAD RESULT: " & integer'image(to_integer(unsigned(result))) & ", ON " & integer'image(to_integer(unsigned(number1_in))) & " + " & integer'image(to_integer(unsigned(number2_in))) severity error;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
fabc5f44601624e7da29f44d39398b35
| 0.644187 | 3.002484 | false | false | false | false |
ruygargar/LCSE_lab
|
doc/PIC/ROM.vhd
| 1 | 21,424 |
----------------------------------------------------------------
-- Nombre : ROM.vhd
-- Descripcion : Memoria de programa del PIC
----------------------------------------------------------------
-- Version : 1.0
----------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
entity ROM is
port (
Instruction : out std_logic_vector(11 downto 0); -- Instruction bus
Program_counter : in std_logic_vector(11 downto 0));
end ROM;
architecture AUTOMATIC of ROM is
constant W0 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W1 : std_logic_vector(11 downto 0) := X"003";
constant W2 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W3 : std_logic_vector(11 downto 0) := X"0FF";
constant W4 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPL;
constant W5 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W6 : std_logic_vector(11 downto 0) :=X"000";
constant W7 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W8 : std_logic_vector(11 downto 0) := X"000";
constant W9 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W10 : std_logic_vector(11 downto 0) := X"003";
constant W11 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W12 : std_logic_vector(11 downto 0) := X"000";
constant W13 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W14 : std_logic_vector(11 downto 0) := X"041";
constant W15 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W16 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W17 : std_logic_vector(11 downto 0) :=X"045";
constant W18 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W19 : std_logic_vector(11 downto 0) := X"049";
constant W20 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W21 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W22 : std_logic_vector(11 downto 0) :=X"02E";
constant W23 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W24 : std_logic_vector(11 downto 0) := X"054";
constant W25 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W26 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W27 : std_logic_vector(11 downto 0) :=X"05C";
constant W28 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W29 : std_logic_vector(11 downto 0) := X"053";
constant W30 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W31 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W32 : std_logic_vector(11 downto 0) :=X"07E";
constant W33 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W34 : std_logic_vector(11 downto 0) :=X"0D6";
constant W35 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W36 : std_logic_vector(11 downto 0) := X"04F";
constant W37 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W38 : std_logic_vector(11 downto 0) := X"004";
constant W39 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W40 : std_logic_vector(11 downto 0) := X"04B";
constant W41 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W42 : std_logic_vector(11 downto 0) := X"005";
constant W43 : std_logic_vector(11 downto 0) :=X"0" & TYPE_4 & "000000";
constant W44 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W45 : std_logic_vector(11 downto 0) :=X"000";
constant W46 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W47 : std_logic_vector(11 downto 0) := X"001";
constant W48 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W49 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_INDX;
constant W50 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W51 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W52 : std_logic_vector(11 downto 0) := X"007";
constant W53 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W54 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W55 : std_logic_vector(11 downto 0) :=X"0D6";
constant W56 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W57 : std_logic_vector(11 downto 0) := X"002";
constant W58 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W59 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W60 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W61 : std_logic_vector(11 downto 0) := X"001";
constant W62 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W63 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W64 : std_logic_vector(11 downto 0) :=X"0D6";
constant W65 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_INDXD_MEM;
constant W66 : std_logic_vector(11 downto 0) := X"010";
constant W67 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W68 : std_logic_vector(11 downto 0) :=X"023";
constant W69 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W70 : std_logic_vector(11 downto 0) := X"001";
constant W71 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W72 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W73 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_INDX;
constant W74 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W75 : std_logic_vector(11 downto 0) := X"0FF";
constant W76 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W77 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W78 : std_logic_vector(11 downto 0) :=X"0D6";
constant W79 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W80 : std_logic_vector(11 downto 0) := X"002";
constant W81 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W82 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W83 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W84 : std_logic_vector(11 downto 0) := X"009";
constant W85 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W86 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W87 : std_logic_vector(11 downto 0) :=X"0D6";
constant W88 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_INDXD_MEM;
constant W89 : std_logic_vector(11 downto 0) := X"020";
constant W90 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W91 : std_logic_vector(11 downto 0) :=X"023";
constant W92 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W93 : std_logic_vector(11 downto 0) := X"001";
constant W94 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W95 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W96 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W97 : std_logic_vector(11 downto 0) := X"002";
constant W98 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W99 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W100 : std_logic_vector(11 downto 0) :=X"0D6";
constant W101 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W102 : std_logic_vector(11 downto 0) := X"000";
constant W103 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ADD;
constant W104 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTL;
constant W105 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTL;
constant W106 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTL;
constant W107 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTL;
constant W108 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W109 : std_logic_vector(11 downto 0) := X"041";
constant W110 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W111 : std_logic_vector(11 downto 0) := X"002";
constant W112 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W113 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W114 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W115 : std_logic_vector(11 downto 0) := X"0FF";
constant W116 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W117 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W118 : std_logic_vector(11 downto 0) :=X"0D6";
constant W119 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_B;
constant W120 : std_logic_vector(11 downto 0) := X"041";
constant W121 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ADD;
constant W122 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W123 : std_logic_vector(11 downto 0) := X"031";
constant W124 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W125 : std_logic_vector(11 downto 0) :=X"023";
constant W126 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W127 : std_logic_vector(11 downto 0) := X"001";
constant W128 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W129 : std_logic_vector(11 downto 0) := X"041";
constant W130 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W131 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W132 : std_logic_vector(11 downto 0) :=X"091";
constant W133 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W134 : std_logic_vector(11 downto 0) := X"049";
constant W135 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W136 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W137 : std_logic_vector(11 downto 0) :=X"0A7";
constant W138 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W139 : std_logic_vector(11 downto 0) := X"054";
constant W140 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W141 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W142 : std_logic_vector(11 downto 0) :=X"0BD";
constant W143 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W144 : std_logic_vector(11 downto 0) :=X"0D6";
constant W145 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W146 : std_logic_vector(11 downto 0) := X"002";
constant W147 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W148 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W149 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_INDX;
constant W150 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W151 : std_logic_vector(11 downto 0) := X"009";
constant W152 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W153 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W154 : std_logic_vector(11 downto 0) :=X"0D6";
constant W155 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_INDXD_MEM & DST_A;
constant W156 : std_logic_vector(11 downto 0) := X"020";
constant W157 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_BIN2ASCII;
constant W158 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W159 : std_logic_vector(11 downto 0) := X"005";
constant W160 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W161 : std_logic_vector(11 downto 0) := X"041";
constant W162 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W163 : std_logic_vector(11 downto 0) := X"004";
constant W164 : std_logic_vector(11 downto 0) :=X"0" & TYPE_4 & "000000";
constant W165 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W166 : std_logic_vector(11 downto 0) :=X"000";
constant W167 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W168 : std_logic_vector(11 downto 0) := X"002";
constant W169 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W170 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W171 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_INDX;
constant W172 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W173 : std_logic_vector(11 downto 0) := X"007";
constant W174 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W175 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W176 : std_logic_vector(11 downto 0) :=X"0D6";
constant W177 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_INDXD_MEM & DST_A;
constant W178 : std_logic_vector(11 downto 0) := X"010";
constant W179 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_BIN2ASCII;
constant W180 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W181 : std_logic_vector(11 downto 0) := X"005";
constant W182 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W183 : std_logic_vector(11 downto 0) := X"053";
constant W184 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W185 : std_logic_vector(11 downto 0) := X"004";
constant W186 : std_logic_vector(11 downto 0) :=X"0" & TYPE_4 & "000000";
constant W187 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W188 : std_logic_vector(11 downto 0) :=X"000";
constant W189 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W190 : std_logic_vector(11 downto 0) := X"031";
constant W191 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W192 : std_logic_vector(11 downto 0) :="000011110000";
constant W193 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_AND;
constant W194 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTR;
constant W195 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTR;
constant W196 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTR;
constant W197 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTR;
constant W198 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W199 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_BIN2ASCII;
constant W200 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W201 : std_logic_vector(11 downto 0) := X"004";
constant W202 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W203 : std_logic_vector(11 downto 0) := X"031";
constant W204 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W205 : std_logic_vector(11 downto 0) :="000000001111";
constant W206 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_AND;
constant W207 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W208 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_BIN2ASCII;
constant W209 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W210 : std_logic_vector(11 downto 0) := X"005";
constant W211 : std_logic_vector(11 downto 0) :=X"0" & TYPE_4 & "000000";
constant W212 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W213 : std_logic_vector(11 downto 0) :=X"000";
constant W214 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W215 : std_logic_vector(11 downto 0) := X"045";
constant W216 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W217 : std_logic_vector(11 downto 0) := X"004";
constant W218 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W219 : std_logic_vector(11 downto 0) := X"052";
constant W220 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W221 : std_logic_vector(11 downto 0) := X"005";
constant W222 : std_logic_vector(11 downto 0) :=X"0" & TYPE_4 & "000000";
constant W223 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W224 : std_logic_vector(11 downto 0) :=X"000";
begin -- AUTOMATIC
with Program_counter select
Instruction <=
W0 when X"000",
W1 when X"001",
W2 when X"002",
W3 when X"003",
W4 when X"004",
W5 when X"005",
W6 when X"006",
W7 when X"007",
W8 when X"008",
W9 when X"009",
W10 when X"00A",
W11 when X"00B",
W12 when X"00C",
W13 when X"00D",
W14 when X"00E",
W15 when X"00F",
W16 when X"010",
W17 when X"011",
W18 when X"012",
W19 when X"013",
W20 when X"014",
W21 when X"015",
W22 when X"016",
W23 when X"017",
W24 when X"018",
W25 when X"019",
W26 when X"01A",
W27 when X"01B",
W28 when X"01C",
W29 when X"01D",
W30 when X"01E",
W31 when X"01F",
W32 when X"020",
W33 when X"021",
W34 when X"022",
W35 when X"023",
W36 when X"024",
W37 when X"025",
W38 when X"026",
W39 when X"027",
W40 when X"028",
W41 when X"029",
W42 when X"02A",
W43 when X"02B",
W44 when X"02C",
W45 when X"02D",
W46 when X"02E",
W47 when X"02F",
W48 when X"030",
W49 when X"031",
W50 when X"032",
W51 when X"033",
W52 when X"034",
W53 when X"035",
W54 when X"036",
W55 when X"037",
W56 when X"038",
W57 when X"039",
W58 when X"03A",
W59 when X"03B",
W60 when X"03C",
W61 when X"03D",
W62 when X"03E",
W63 when X"03F",
W64 when X"040",
W65 when X"041",
W66 when X"042",
W67 when X"043",
W68 when X"044",
W69 when X"045",
W70 when X"046",
W71 when X"047",
W72 when X"048",
W73 when X"049",
W74 when X"04A",
W75 when X"04B",
W76 when X"04C",
W77 when X"04D",
W78 when X"04E",
W79 when X"04F",
W80 when X"050",
W81 when X"051",
W82 when X"052",
W83 when X"053",
W84 when X"054",
W85 when X"055",
W86 when X"056",
W87 when X"057",
W88 when X"058",
W89 when X"059",
W90 when X"05A",
W91 when X"05B",
W92 when X"05C",
W93 when X"05D",
W94 when X"05E",
W95 when X"05F",
W96 when X"060",
W97 when X"061",
W98 when X"062",
W99 when X"063",
W100 when X"064",
W101 when X"065",
W102 when X"066",
W103 when X"067",
W104 when X"068",
W105 when X"069",
W106 when X"06A",
W107 when X"06B",
W108 when X"06C",
W109 when X"06D",
W110 when X"06E",
W111 when X"06F",
W112 when X"070",
W113 when X"071",
W114 when X"072",
W115 when X"073",
W116 when X"074",
W117 when X"075",
W118 when X"076",
W119 when X"077",
W120 when X"078",
W121 when X"079",
W122 when X"07A",
W123 when X"07B",
W124 when X"07C",
W125 when X"07D",
W126 when X"07E",
W127 when X"07F",
W128 when X"080",
W129 when X"081",
W130 when X"082",
W131 when X"083",
W132 when X"084",
W133 when X"085",
W134 when X"086",
W135 when X"087",
W136 when X"088",
W137 when X"089",
W138 when X"08A",
W139 when X"08B",
W140 when X"08C",
W141 when X"08D",
W142 when X"08E",
W143 when X"08F",
W144 when X"090",
W145 when X"091",
W146 when X"092",
W147 when X"093",
W148 when X"094",
W149 when X"095",
W150 when X"096",
W151 when X"097",
W152 when X"098",
W153 when X"099",
W154 when X"09A",
W155 when X"09B",
W156 when X"09C",
W157 when X"09D",
W158 when X"09E",
W159 when X"09F",
W160 when X"0A0",
W161 when X"0A1",
W162 when X"0A2",
W163 when X"0A3",
W164 when X"0A4",
W165 when X"0A5",
W166 when X"0A6",
W167 when X"0A7",
W168 when X"0A8",
W169 when X"0A9",
W170 when X"0AA",
W171 when X"0AB",
W172 when X"0AC",
W173 when X"0AD",
W174 when X"0AE",
W175 when X"0AF",
W176 when X"0B0",
W177 when X"0B1",
W178 when X"0B2",
W179 when X"0B3",
W180 when X"0B4",
W181 when X"0B5",
W182 when X"0B6",
W183 when X"0B7",
W184 when X"0B8",
W185 when X"0B9",
W186 when X"0BA",
W187 when X"0BB",
W188 when X"0BC",
W189 when X"0BD",
W190 when X"0BE",
W191 when X"0BF",
W192 when X"0C0",
W193 when X"0C1",
W194 when X"0C2",
W195 when X"0C3",
W196 when X"0C4",
W197 when X"0C5",
W198 when X"0C6",
W199 when X"0C7",
W200 when X"0C8",
W201 when X"0C9",
W202 when X"0CA",
W203 when X"0CB",
W204 when X"0CC",
W205 when X"0CD",
W206 when X"0CE",
W207 when X"0CF",
W208 when X"0D0",
W209 when X"0D1",
W210 when X"0D2",
W211 when X"0D3",
W212 when X"0D4",
W213 when X"0D5",
W214 when X"0D6",
W215 when X"0D7",
W216 when X"0D8",
W217 when X"0D9",
W218 when X"0DA",
W219 when X"0DB",
W220 when X"0DC",
W221 when X"0DD",
W222 when X"0DE",
W223 when X"0DF",
W224 when X"0E0",
X"0" & TYPE_1 & ALU_ADD when others;
end AUTOMATIC;
|
gpl-3.0
|
25f8d39641e8f95de202b5869af59d48
| 0.64017 | 2.481065 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/shift_register_rst_nbits.vhd
| 1 | 1,705 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Shift_Register_rst_n_bits
-- Module Name: Shift_Register_rst_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Shift Register of size bits with reset signal, that only registers when ce equals to 1.
-- The reset is synchronous and the value loaded during reset is defined by reset_value.
--
-- The circuits parameters
--
-- size :
--
-- The size of the register in bits.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shift_register_rst_nbits is
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0);
data_out : out STD_LOGIC
);
end shift_register_rst_nbits;
architecture Behavioral of shift_register_rst_nbits is
signal internal_value : STD_LOGIC_VECTOR((size - 1) downto 0);
begin
process(clk, ce, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= rst_value;
elsif(ce = '1') then
internal_value <= internal_value((size - 2) downto 0) & data_in;
else
null;
end if;
end if;
end process;
data_out <= internal_value(size - 1);
q <= internal_value;
end Behavioral;
|
bsd-2-clause
|
238ad3773a998a9e34c253f38c2d296b
| 0.604106 | 3.369565 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/genericCounter/generic_counter_tb.vhd
| 2 | 916 |
library ieee;
use ieee.std_logic_1164.all;
entity genericCounter_tb is
end;
architecture genericCounter_tb_func of genericCounter_tb is
signal rst_in: std_logic:='1';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal n_out: std_logic_vector(3 downto 0);
signal c_out: std_logic:='0';
component genericCounter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end component;
begin
clk_in <= not(clk_in) after 20 ns;
rst_in <= '0' after 50 ns;
enable_in <= '1' after 60 ns;
genericCounterMap: genericCounter generic map (4,10)
port map(
clk => clk_in,
rst => rst_in,
ena => enable_in,
count => n_out,
carry_o => c_out
);
end architecture;
|
gpl-3.0
|
d90e214deb2b72a40df7a7d86e9fe501
| 0.616812 | 2.898734 | false | false | false | false |
ruygargar/LCSE_lab
|
ram/ram.vhd
| 1 | 3,773 |
-------------------------------------------------------------------------------
-- Author: Aragonés Orellana, Silvia
-- García Garcia, Ruy
-- Project Name: PIC
-- Design Name: ram.vhd
-- Module Name: ram.vhd
-------------------------------------------------------------------------------
library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
entity ram is
PORT (
Clk : in std_logic;
Reset : in std_logic;
WriteEnable : in std_logic;
OutputEnable : in std_logic;
ChipSelect : in std_logic;
Address : in std_logic_vector(7 downto 0);
Databus : inout std_logic_vector(7 downto 0) := (others => 'Z');
Switches : out std_logic_vector(7 downto 0);
Temp_L : out std_logic_vector(6 downto 0);
Temp_H : out std_logic_vector(6 downto 0)
);
end ram;
architecture Behavioral of ram is
-- Declaración del componente Bloque de Ram de 64 Bytes.
COMPONENT bram64
PORT(
Clk : IN std_logic;
WriteEnable : IN std_logic;
OutputEnable : IN std_logic;
Address : IN std_logic_vector(5 downto 0);
Databus : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;
-- Declaración del componente SPR.
COMPONENT spr
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
WriteEnable : IN std_logic;
OutputEnable : IN std_logic;
Address : IN std_logic_vector(5 downto 0);
Databus : INOUT std_logic_vector(7 downto 0);
Switches : OUT std_logic_vector(7 downto 0);
Temp_L : OUT std_logic_vector(6 downto 0);
Temp_h : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
-- Buses de señales procedentes del decodificador "DEC2:4", que controlan
-- las señales WriteEnable y OutputEnable de cada BRAM (Block RAM) y del
-- bloque SPR (Specific Porpouse Registers).
signal WE : std_logic_vector(3 downto 0);
signal OE : std_logic_vector(3 downto 0);
begin
-- Instancia del SPR. En el decodificador "DEC2:4", sus señales de control
-- se corresponden con la salida 0.
spr_0: spr PORT MAP(
Clk => Clk,
Reset => Reset,
WriteEnable => WE(0),
OutputEnable => OE(0),
Address => Address(5 downto 0),
Databus => Databus(7 downto 0),
Switches => Switches,
Temp_L => Temp_L,
Temp_H => Temp_H
);
-- Instancia de BRAM. En el decodificador "DEC2:4", sus señales de control
-- se corresponden con la salida 1.
bram_1: bram64 PORT MAP(
Clk => Clk,
WriteEnable => WE(1),
OutputEnable => OE(1),
Address => Address(5 downto 0),
Databus => Databus(7 downto 0)
);
-- Instancia de BRAM. En el decodificador "DEC2:4", sus señales de control
-- se corresponden con la salida 2.
bram_2: bram64 PORT MAP(
Clk => Clk,
WriteEnable => WE(2),
OutputEnable => OE(2),
Address => Address(5 downto 0),
Databus => Databus(7 downto 0)
);
-- Instancia de BRAM. En el decodificador "DEC2:4", sus señales de control
-- se corresponden con la salida 3.
bram_3: bram64 PORT MAP(
Clk => Clk,
WriteEnable => WE(3),
OutputEnable => OE(3),
Address => Address(5 downto 0),
Databus => Databus(7 downto 0)
);
-- Proceso combinacional que decodifica en función del bus de dirección y
-- las señales ChipSelect, WriteEnable y OutputEnable, las señales de
-- control WE y OE de cada uno de los bloques del sistema de almacenamiento.
-- La escritura predomina sobre la lectura, en caso de tener activadas ambas
-- señales de control.
process(ChipSelect, WriteEnable, OutputEnable, Address(7 downto 6))
begin
WE <= X"0";
OE <= X"0";
if (ChipSelect = '1' and WriteEnable = '1') then
WE(conv_integer(Address(7 downto 6))) <= '1';
elsif (ChipSelect = '1' and OutputEnable = '1') then
OE(conv_integer(Address(7 downto 6))) <= '1';
end if;
end process;
end Behavioral;
|
gpl-3.0
|
56a6cd7136781bb3768302fc73afb780
| 0.636629 | 3.252586 | false | false | false | false |
pwuertz/digitizer2fw
|
src/rtl/communication.vhd
| 1 | 6,301 |
-------------------------------------------------------------------------------
-- Communication Interface
--
-- (De)serializes data to/from a FWFT FIFO interface for register read/writing
--
-- TODO: Document protocol
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.communication_pkg.all;
entity communication is
port (
clk: in std_logic;
rst: in std_logic;
error: out std_logic;
-- application bus interface
slave_addr: out unsigned(5 downto 0);
slave_port: out unsigned(5 downto 0);
comm_to_slave: out comm_to_slave_t;
comm_from_slave: in comm_from_slave_t;
-- fifo interface
fifo_out_wr_en: out std_logic;
fifo_out_full: in std_logic;
fifo_out_data: out std_logic_vector(COMM_BUS_WIDTH-1 downto 0);
fifo_in_rd_en: out std_logic;
fifo_in_empty: in std_logic;
fifo_in_data: in std_logic_vector(COMM_BUS_WIDTH-1 downto 0)
);
end communication;
architecture communication_arch of communication is
-- protocol definitions
constant cmd_reg_read: integer := 1;
constant cmd_reg_write: integer := 2;
constant cmd_reg_read_n: integer := 3;
constant cmd_reg_write_n: integer := 4;
-- state machine
type fsm_state_t is (s_reset, s_idle,
s_write_reg_size, s_write_reg_data,
s_read_reg_size, s_read_reg_data);
signal state, next_state: fsm_state_t;
signal addr_int, next_addr_int: unsigned(5 downto 0);
signal port_int, next_port_int: unsigned(5 downto 0);
signal block_size, next_block_size: unsigned(15 downto 0);
begin
-------------------------------------------------------------------------------
-- register state
sync_proc: process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
state <= s_reset;
else
state <= next_state;
addr_int <= next_addr_int;
port_int <= next_port_int;
block_size <= next_block_size;
end if;
end if;
end process;
-- next state and output logic
next_state_decode: process(state, block_size, addr_int, port_int,
comm_from_slave,
fifo_in_empty, fifo_out_full, fifo_in_data)
variable cmd: integer;
begin
next_state <= state;
next_addr_int <= addr_int;
next_port_int <= port_int;
next_block_size <= block_size;
-- register interface (r/w)
slave_addr <= addr_int;
slave_port <= port_int;
comm_to_slave.wr_req <= '0';
comm_to_slave.rd_req <= '0';
comm_to_slave.data_wr <= fifo_in_data;
fifo_out_data <= comm_from_slave.data_rd;
-- fifo interface (r/w)
fifo_out_wr_en <= '0';
fifo_in_rd_en <= '0';
error <= '0';
case state is
when s_reset =>
next_state <= s_idle;
when s_idle =>
-- wait for next command
if fifo_in_empty = '0' then
-- ack data from fifo
fifo_in_rd_en <= '1';
-- decode command bits
cmd := to_integer(unsigned(fifo_in_data(15 downto 12)));
case cmd is
when cmd_reg_read =>
next_state <= s_read_reg_data;
next_block_size <= to_unsigned(1, 16);
when cmd_reg_write =>
next_state <= s_write_reg_data;
next_block_size <= to_unsigned(1, 16);
when cmd_reg_read_n =>
next_state <= s_read_reg_size;
when cmd_reg_write_n =>
next_state <= s_write_reg_size;
when others =>
error <= '1';
next_state <= s_idle;
end case;
-- store slave address and port
next_addr_int <= unsigned(fifo_in_data(11 downto 6));
next_port_int <= unsigned(fifo_in_data(5 downto 0));
end if;
when s_write_reg_size =>
-- read data block size from fifo
if fifo_in_empty = '0' then
fifo_in_rd_en <= '1';
next_block_size <= unsigned(fifo_in_data);
next_state <= s_write_reg_data;
end if;
when s_write_reg_data =>
if fifo_in_empty = '0' then
-- request write operation if fifo isn't empty
comm_to_slave.wr_req <= '1';
if comm_from_slave.wr_ack = '1' then
-- if accepted, ack data from fifo
fifo_in_rd_en <= '1';
next_block_size <= block_size - 1;
-- return to idle when next_block_size=0
if block_size = 1 then
next_state <= s_idle;
end if;
end if;
end if;
when s_read_reg_size =>
-- read data block size from fifo
if fifo_in_empty = '0' then
fifo_in_rd_en <= '1';
next_block_size <= unsigned(fifo_in_data);
next_state <= s_read_reg_data;
end if;
when s_read_reg_data =>
if fifo_out_full = '0' then
-- request read operation if fifo isn't full
comm_to_slave.rd_req <= '1';
if comm_from_slave.rd_ack = '1' then
-- if accepted, push data to fifo
fifo_out_wr_en <= '1';
next_block_size <= block_size - 1;
-- return to idle when next_block_size=0
if block_size = 1 then
next_state <= s_idle;
end if;
end if;
end if;
when others =>
error <= '1';
end case;
end process;
end communication_arch;
|
gpl-3.0
|
aed982b04460ef1a26530c04bae7e1b8
| 0.490635 | 3.962264 | false | false | false | false |
electronicvisions/brick
|
test/source/vhdl/counter_tb.vhd
| 2 | 1,211 |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity counter_tb is
end;
architecture counter_tb of counter_tb is
component counter
port ( count : out std_logic_vector(3 downto 0);
clk : in std_logic;
enable: in std_logic;
reset : in std_logic);
end component ;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal enable : std_logic := '0';
signal count : std_logic_vector(3 downto 0);
begin
dut : counter
port map (
count => count,
clk => clk,
enable=> enable,
reset => reset );
clock : process
begin
wait for 1 ns; clk <= not clk;
end process clock;
stimulus : process
begin
wait for 5 ns; reset <= '1';
wait for 4 ns; reset <= '0';
wait for 4 ns; enable <= '1';
wait;
end process stimulus;
monitor : process (clk)
variable c_str : line;
begin
if (clk = '1' and clk'event) then
write(c_str,count);
assert false report time'image(now) &
": Current Count Value : " & c_str.all
severity note;
deallocate(c_str);
end if;
end process monitor;
end counter_tb;
|
bsd-3-clause
|
409c333ab4c52fdf647c031a14642079
| 0.609414 | 3.272973 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
VHDL/PLL3.vhd
| 1 | 15,116 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: PLL3.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY PLL3 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END PLL3;
ARCHITECTURE SYN OF pll3 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
locked <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 8,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 28571,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=PLL3",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "280.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "35.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL3.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "28571"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL3.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL3.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL3.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL3_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
gpl-2.0
|
97e6bad7df5c091a18db583aaa74e75f
| 0.69873 | 3.34721 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/pipeline_polynomial_calc_v2.vhd
| 1 | 4,367 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Pipeline_Polynomial_Calc_v2
-- Module Name: Pipeline_Polynomial_Calc_v2
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 3rd step in Goppa Code Decoding.
--
-- This circuit is to be used inside polynomial_evaluator_n_v2 to evaluate polynomials.
-- This circuit is the essential for 1 pipeline, therefor all stages are composed in here.
-- For more than 1 pipeline, only in polynomial_evaluator_n_v2 with the shared components
-- for all pipelines.
--
-- For the computation this circuit applies the Horner scheme, where at each stage
-- an accumulator is multiplied by respective x and then added accumulated with coefficient.
-- In Horner scheme algorithm, it begin from the most significative coefficient until reaches
-- lesser significative coefficient.
--
-- To improve syndrome generation this circuit was adapted to support syndrome generation
-- in pipeline_polynomial_calc_v3
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- size :
--
-- The number of stages the pipeline has. More stages means more values of value_polynomial
-- are tested at once.
--
-- Dependencies:
-- VHDL-93
--
-- stage_polynomial_calc_v2 Rev 1.0
-- register_nbits Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pipeline_polynomial_calc_v2 is
Generic (
gf_2_m : integer range 1 to 20 := 11;
size : integer := 28
);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((((gf_2_m)*size) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
reg_x_rst : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end pipeline_polynomial_calc_v2;
architecture Behavioral of pipeline_polynomial_calc_v2 is
component stage_polynomial_calc_v2
Generic(gf_2_m : integer range 1 to 20 := 11);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial_coefficient : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component register_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
type array_std_logic_vector is array(integer range <>) of STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal acc_d : array_std_logic_vector((size) downto 0);
signal acc_q : array_std_logic_vector((size - 1) downto 0);
signal x_q : array_std_logic_vector((size) downto 0);
constant reg_x_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(1, gf_2_m));
begin
x_q(0) <= value_x;
acc_d(0) <= value_acc;
pipeline : for I in 0 to (size - 1) generate
reg_x_I : register_rst_nbits
Generic Map(size => gf_2_m)
Port Map(
d => x_q(I),
clk => clk,
ce => '1',
rst => reg_x_rst(I),
rst_value => reg_x_rst_value,
q => x_q(I+1)
);
reg_acc_I : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => acc_d(I),
clk => clk,
ce => '1',
q => acc_q(I)
);
stage_I : stage_polynomial_calc_v2
Generic Map(gf_2_m => gf_2_m)
Port Map (
value_x => x_q(I+1),
value_polynomial_coefficient => value_polynomial(((gf_2_m)*(I+1) - 1) downto ((gf_2_m)*(I))),
value_acc => acc_q(I),
new_value_acc => acc_d(I+1)
);
end generate;
new_value_acc <= acc_d(size);
end Behavioral;
|
bsd-2-clause
|
7c00f97dd6ac19469c4087feafbda659
| 0.642317 | 2.982923 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
VHDL/LED/FIFO_LED_PIC.vhd
| 1 | 7,997 |
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo_mixed_widths
-- ============================================================
-- File Name: FIFO_LED_PIC.vhd
-- Megafunction Name(s):
-- dcfifo_mixed_widths
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY FIFO_LED_PIC IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (39 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END FIFO_LED_PIC;
ARCHITECTURE SYN OF fifo_led_pic IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (39 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT dcfifo_mixed_widths
GENERIC (
add_usedw_msb_bit : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
lpm_widthu_r : NATURAL;
lpm_width_r : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (39 DOWNTO 0);
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
rdreq : IN STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(39 DOWNTO 0);
wrusedw <= sub_wire1(6 DOWNTO 0);
rdusedw <= sub_wire2(7 DOWNTO 0);
dcfifo_mixed_widths_component : dcfifo_mixed_widths
GENERIC MAP (
add_usedw_msb_bit => "ON",
intended_device_family => "Cyclone IV E",
lpm_numwords => 64,
lpm_showahead => "OFF",
lpm_type => "dcfifo_mixed_widths",
lpm_width => 80,
lpm_widthu => 7,
lpm_widthu_r => 8,
lpm_width_r => 40,
overflow_checking => "ON",
rdsync_delaypipe => 5,
read_aclr_synch => "ON",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 5
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
q => sub_wire0,
wrusedw => sub_wire1,
rdusedw => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "64"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "80"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "1"
-- Retrieval info: PRIVATE: output_width NUMERIC "40"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_USEDW_MSB_BIT STRING "ON"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "80"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "40"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 80 0 INPUT NODEFVAL "data[79..0]"
-- Retrieval info: USED_PORT: q 0 0 40 0 OUTPUT NODEFVAL "q[39..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: rdusedw 0 0 8 0 OUTPUT NODEFVAL "rdusedw[7..0]"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: USED_PORT: wrusedw 0 0 7 0 OUTPUT NODEFVAL "wrusedw[6..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 80 0 data 0 0 80 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 40 0 @q 0 0 40 0
-- Retrieval info: CONNECT: rdusedw 0 0 8 0 @rdusedw 0 0 8 0
-- Retrieval info: CONNECT: wrusedw 0 0 7 0 @wrusedw 0 0 7 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_LED_PIC.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_LED_PIC.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_LED_PIC.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_LED_PIC.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_LED_PIC_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
76d4d1344de86626dcdc1d296bc2fe6b
| 0.668001 | 3.445498 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/tp1/generic_counter/generic_counter.vhd
| 1 | 994 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity generic_counter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end;
architecture generic_counter_arq of generic_counter is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(clk,rst)
variable tmp_count: integer range 0 to MAX_COUNT+1;
begin
if rst = '1' then
count <= (others => '0');
carry_o <= '0';
elsif rising_edge(clk) then
if ena = '1' then
tmp_count:=tmp_count + 1;
if tmp_count = MAX_COUNT then
carry_o <= '1';
elsif tmp_count = MAX_COUNT+1 then
tmp_count := 0;
carry_o <= '0';
else
carry_o <= '0';
end if;
end if;
end if;
count <= std_logic_vector(TO_UNSIGNED(tmp_count,BITS));
end process;
end;
|
gpl-3.0
|
f8de7908b4ae9e381840dfdd016cd556
| 0.61167 | 2.864553 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/tb_find_correct_errors_n_v3.vhd
| 1 | 26,856 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Find_Correct_Errors_N_v3
-- Module Name: Tb_Find_Correct_Errors_N_v3
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Testbench for polynomial_syndrome_computing_n circuit.
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- number_of_pipelines :
--
-- Number of pipelines used in the circuit to test the support elements and
-- correct the message. Each pipeline needs at least 2 memory ram to store
-- intermediate results.
--
-- pipeline_size :
--
-- The number of stages of the pipeline. More stages means more values of sigma
-- are tested at once.
--
-- size_pipeline_size :
--
-- The number of bits necessary to store the size of the pipeline.
-- This is ceil(log2(pipeline_size))
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- length_support_elements :
--
-- The number of support elements. This parameter depends of the Goppa code used.
--
-- size_support_elements :
--
-- The size of the memory that holds all support elements. This parameter
-- depends of the Goppa code used.
-- This is ceil(log2(length_support_elements))
--
-- x_memory_file :
--
-- File that holds the values to be evaluated on the polynomial. Support elements L.
--
-- sigma_memory_file :
--
-- File that holds polynomial sigma coefficients.
--
-- resp_memory_file :
--
-- File that holds all evaluations of support L on polynomial sigma.
-- This file holds the output of the circuit,
-- it is needed to detect if polynomial evaluator circuit worked properly.
--
-- dump_acc_memory_file :
--
-- File that will hold the output of all support L evaluations on polynomial sigma,
-- that were done by the circuit.
--
-- codeword_memory_file :
--
-- File that holds the ciphertext that will be corrected according to the polynomial
-- sigma roots that were found.
--
-- message_memory_file :
--
-- File that holds the ciphertext already corrected.
-- This file is necessary to detect
-- if the ciphertext correction was performed correctly by the circuit.
--
-- dump_codeword_memory_file :
--
-- File that will hold the ciphertext corrected by the circuit.
--
-- dump_error_memory_file :
--
-- File that will hold the errors found on the ciphertext by the circuit.
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- polynomial_syndrome_computing_n Rev 1.0
-- ram Rev 1.0
-- ram_bank Rev 1.0
-- ram_double_bank Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_find_correct_errors_n_v3 is
Generic(
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 6;
-- sigma_degree : integer := 4;
-- size_sigma_degree : integer := 2;
-- length_support_elements: integer := 52;
-- size_support_elements : integer := 6;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_52_28_4_6.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_52_28_4_6.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_52_28_4_6.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_52_28_4_6.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_52_28_4_6.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_52_28_4_6.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_52_28_4_6.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_52_28_4_6.dat"
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_pipelines : integer := 4;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- sigma_degree : integer := 27;
-- size_sigma_degree : integer := 5;
-- length_support_elements: integer := 2048;
-- size_support_elements : integer := 11;
-- x_memory_file : string := "mceliece/data_tests/L_goppa_2048_1751_27_11.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_2048_1751_27_11.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_goppa_2048_1751_27_11.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_goppa_2048_1751_27_11.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_goppa_2048_1751_27_11.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_goppa_2048_1751_27_11.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_goppa_2048_1751_27_11.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_goppa_2048_1751_27_11.dat"
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 7;
-- size_pipeline_size : integer := 3;
-- gf_2_m : integer range 1 to 20 := 11;
-- sigma_degree : integer := 50;
-- size_sigma_degree : integer := 6;
-- length_support_elements: integer := 2048;
-- size_support_elements : integer := 11;
-- x_memory_file : string := "mceliece/data_tests/L_goppa_2048_1498_50_11.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_2048_1498_50_11.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_goppa_2048_1498_50_11.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_goppa_2048_1498_50_11.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_goppa_2048_1498_50_11.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_goppa_2048_1498_50_11.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_goppa_2048_1498_50_11.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_goppa_2048_1498_50_11.dat"
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 7;
-- size_pipeline_size : integer := 3;
-- gf_2_m : integer range 1 to 20 := 12;
-- sigma_degree : integer := 66;
-- size_sigma_degree : integer := 7;
-- length_support_elements: integer := 3307;
-- size_support_elements : integer := 12;
-- x_memory_file : string := "mceliece/data_tests/L_goppa_3307_2515_66_12.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_3307_2515_66_12.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_goppa_3307_2515_66_12.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_goppa_3307_2515_66_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_goppa_3307_2515_66_12.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_goppa_3307_2515_66_12.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_goppa_3307_2515_66_12.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_goppa_3307_2515_66_12.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
number_of_pipelines : integer := 1;
pipeline_size : integer := 33;
size_pipeline_size : integer := 6;
gf_2_m : integer range 1 to 20 := 12;
sigma_degree : integer := 32;
size_sigma_degree : integer := 6;
length_support_elements: integer := 2528;
size_support_elements : integer := 12;
x_memory_file : string := "mceliece/data_tests/L_qdgoppa_2528_2144_32_12_1.dat";
sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_2528_2144_32_12_1.dat";
resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_2528_2144_32_12_1.dat";
dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_2528_2144_32_12_1.dat";
codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_2528_2144_32_12_1.dat";
message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2528_2144_32_12_1.dat";
dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_2528_2144_32_12_1.dat";
dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_2528_2144_32_12_1.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- sigma_degree : integer := 64;
-- size_sigma_degree : integer := 7;
-- length_support_elements: integer := 2816;
-- size_support_elements : integer := 12;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_2816_2048_64_12.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_2816_2048_64_12.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_2816_2048_64_12.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_2816_2048_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_2816_2048_64_12.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2816_2048_64_12.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_2816_2048_64_12.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- sigma_degree : integer := 64;
-- size_sigma_degree : integer := 7;
-- length_support_elements: integer := 3328;
-- size_support_elements : integer := 12;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_3328_2560_64_12.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_3328_2560_64_12.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_3328_2560_64_12.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_3328_2560_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_3328_2560_64_12.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_3328_2560_64_12.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_3328_2560_64_12.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 129;
-- size_pipeline_size : integer := 8;
-- gf_2_m : integer range 1 to 20 := 13;
-- sigma_degree : integer := 128;
-- size_sigma_degree : integer := 8;
-- length_support_elements: integer := 7296;
-- size_support_elements : integer := 13;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_7296_5632_128_13.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_7296_5632_128_13.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_7296_5632_128_13.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_7296_5632_128_13.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_7296_5632_128_13.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_7296_5632_128_13.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_7296_5632_128_13.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_7296_5632_128_13.dat"
);
end tb_find_correct_errors_n_v3;
architecture Behavioral of tb_find_correct_errors_n_v3 is
component ram
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component ram_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component ram_double_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component polynomial_syndrome_computing_n
Generic (
number_of_pipelines : integer;
pipeline_size : integer;
size_pipeline_size : integer;
gf_2_m : integer range 1 to 20;
number_of_errors : integer;
size_number_of_errors : integer;
number_of_support_elements : integer;
size_number_of_support_elements : integer
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_message : in STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_h : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
computation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
address_value_error : out STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_value_error : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_error : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal value_x : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal value_polynomial : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_message : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal value_h : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal mode_polynomial_syndrome : STD_LOGIC;
signal computation_finalized : STD_LOGIC;
signal address_value_polynomial : STD_LOGIC_VECTOR((size_sigma_degree - 1) downto 0);
signal address_value_x : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_value_acc : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_value_message : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_new_value_message : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_new_value_acc : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_new_value_syndrome : STD_LOGIC_VECTOR((size_sigma_degree) downto 0);
signal address_value_error : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal write_enable_new_value_acc : STD_LOGIC;
signal write_enable_new_value_syndrome : STD_LOGIC;
signal write_enable_new_value_message : STD_LOGIC;
signal write_enable_value_error : STD_LOGIC;
signal new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal new_value_message : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal value_error : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
constant test_codeword_rst_value : std_logic_vector(0 downto 0) := (others => '0');
constant true_codeword_rst_value : std_logic_vector(0 downto 0) := (others => '0');
constant error_rst_value : std_logic_vector(0 downto 0) := (others => '0');
constant x_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
constant sigma_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
constant true_acc_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
constant test_acc_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
signal test_codeword_dump : std_logic := '0';
signal true_codeword_dump : std_logic := '0';
signal x_dump : std_logic := '0';
signal sigma_dump : std_logic := '0';
signal true_acc_dump : std_logic := '0';
signal test_acc_dump : std_logic := '0';
signal error_dump : std_logic := '0';
signal test_acc_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal true_acc_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal true_codeword_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal test_codeword_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal true_acc_value : STD_LOGIC_VECTOR (((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal true_codeword_value : STD_LOGIC_VECTOR ((number_of_pipelines - 1) downto 0);
signal error_acc : STD_LOGIC;
signal error_message : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
for true_codeword : ram_bank use entity work.ram_bank(file_load);
for test_codeword : ram_double_bank use entity work.ram_double_bank(file_load);
for x : ram_bank use entity work.ram_bank(file_load);
for sigma : ram use entity work.ram(file_load);
for true_acc : ram_bank use entity work.ram_bank(file_load);
for test_acc : ram_double_bank use entity work.ram_double_bank(simple);
for error : ram_bank use entity work.ram_bank(simple);
begin
test_codeword : ram_double_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => codeword_memory_file,
dump_file_name => dump_codeword_memory_file
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_message,
rw_a => '0',
rw_b => write_enable_new_value_message,
clk => clk,
rst => rst,
dump => test_codeword_dump,
address_a => test_codeword_address,
address_b => address_new_value_message,
rst_value => test_codeword_rst_value,
data_out_a => value_message,
data_out_b => open
);
error : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => "",
dump_file_name => dump_error_memory_file
)
Port Map(
data_in => value_error,
rw => write_enable_value_error,
clk => clk,
rst => rst,
dump => error_dump,
address => address_value_error,
rst_value => error_rst_value,
data_out => open
);
true_codeword : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => message_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => true_codeword_dump,
address => true_codeword_address,
rst_value => true_codeword_rst_value,
data_out => true_codeword_value
);
x : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => x_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => x_dump,
address => address_value_x,
rst_value => x_rst_value,
data_out => value_x
);
true_acc : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => resp_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => true_acc_dump,
address => true_acc_address,
rst_value => true_acc_rst_value,
data_out => true_acc_value
);
test_acc : ram_double_bank
Generic Map(
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => dump_acc_memory_file
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_acc,
rw_a => '0',
rw_b => write_enable_new_value_acc,
clk => clk,
rst => rst,
dump => test_acc_dump,
address_a => test_acc_address,
address_b => address_new_value_acc,
rst_value => test_acc_rst_value,
data_out_a => value_acc,
data_out_b => open
);
sigma : ram
Generic Map (
ram_address_size => size_sigma_degree,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => sigma_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => sigma_dump,
address => address_value_polynomial,
rst_value => sigma_rst_value,
data_out => value_polynomial
);
poly : polynomial_syndrome_computing_n
Generic Map(
number_of_pipelines => number_of_pipelines,
pipeline_size => pipeline_size,
size_pipeline_size => size_pipeline_size,
gf_2_m => gf_2_m,
number_of_support_elements => length_support_elements,
size_number_of_support_elements => size_support_elements,
number_of_errors => sigma_degree,
size_number_of_errors => size_sigma_degree
)
Port Map(
value_x => value_x,
value_acc => value_acc,
value_polynomial => value_polynomial,
value_message => value_message,
value_h => value_h,
mode_polynomial_syndrome => mode_polynomial_syndrome,
clk => clk,
rst => rst,
computation_finalized => computation_finalized,
address_value_polynomial => address_value_polynomial,
address_value_x => address_value_x,
address_value_acc => address_value_acc,
address_value_message => address_value_message,
address_new_value_message => address_new_value_message,
address_new_value_acc => address_new_value_acc,
address_new_value_syndrome => address_new_value_syndrome,
address_value_error => address_value_error,
write_enable_new_value_acc => write_enable_new_value_acc,
write_enable_new_value_syndrome => write_enable_new_value_syndrome,
write_enable_new_value_message => write_enable_new_value_message,
write_enable_value_error => write_enable_value_error,
new_value_syndrome => new_value_syndrome,
new_value_acc => new_value_acc,
new_value_message => new_value_message,
value_error => value_error
);
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
test_acc_address <= address_value_acc when computation_finalized = '0' else
true_acc_address;
test_codeword_address <= address_value_x when computation_finalized = '0' else
true_codeword_address;
mode_polynomial_syndrome <= '0';
process
variable i : integer;
begin
true_acc_address <= (others => '0');
true_codeword_address <= (others => '0');
rst <= '1';
error_acc <= '0';
error_message <= '0';
wait for PERIOD*2;
rst <= '0';
wait until computation_finalized = '1';
report "Circuit finish = " & integer'image((cycle_count - 2)/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (length_support_elements)) loop
error_message <= '0';
error_acc <= '0';
true_acc_address <= std_logic_vector(to_unsigned(i, true_acc_address'Length));
true_codeword_address <= std_logic_vector(to_unsigned(i, true_codeword_address'Length));
wait for PERIOD*2;
if (true_acc_value = value_acc) then
error_acc <= '0';
else
error_acc <= '1';
report "Computed values do not match expected ones";
end if;
if (true_codeword_value = value_message) then
error_message <= '0';
else
error_message <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
error_acc <= '0';
error_message <= '0';
wait for PERIOD;
i := i + number_of_pipelines;
end loop;
error_message <= '0';
error_acc <= '0';
test_acc_dump <= '1';
test_codeword_dump <= '1';
wait for PERIOD;
test_acc_dump <= '0';
test_codeword_dump <= '0';
test_bench_finish <= '1';
wait;
end process;
end Behavioral;
|
bsd-2-clause
|
c47f9bad2d3f5b15d254c95edb9b9841
| 0.672364 | 2.890228 | false | true | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/expanded_mantissa_adder/expanded_mantissa_adder_tb.vhd
| 1 | 2,269 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity expanded_mantissa_adder_tb is
end entity;
architecture expanded_mantissa_adder_tb_arq of expanded_mantissa_adder_tb is
signal man_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal man_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal result : std_logic_vector(31 downto 0) := (others => '0');
signal cout : std_logic := '0';
component expanded_mantissa_adder is
generic(
BITS : natural := 16
);
port(
man_1_in : in std_logic_vector(BITS - 1 downto 0);
man_2_in : in std_logic_vector(BITS - 1 downto 0);
result : out std_logic_vector(BITS - 1 downto 0);
cout : out std_logic
);
end component;
for expanded_mantissa_adder_0 : expanded_mantissa_adder use entity work.expanded_mantissa_adder;
begin
expanded_mantissa_adder_0 : expanded_mantissa_adder
generic map(BITS => 32)
port map(
man_1_in => man_1_in,
man_2_in => man_2_in,
result => result,
cout => cout
);
process
type pattern_type is record
m1 : std_logic_vector(31 downto 0);
m2 : std_logic_vector(31 downto 0);
r : std_logic_vector(31 downto 0);
co : std_logic;
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000",'0'),
("11111111111111111111111111111111","00000000000000000000000000000000","11111111111111111111111111111111",'0'),
("11111111111111110000000000000000","00000000000000001111111111111111","11111111111111111111111111111111",'0'),
("10000000000000000000000000000000","10000000000000000000000000000000","00000000000000000000000000000000",'1')
);
begin
for i in patterns'range loop
-- Set the inputs.
man_1_in <= patterns(i).m1;
man_2_in <= patterns(i).m2;
wait for 1 ns;
assert patterns(i).r = result report "BAD RESULT, GOT: " & integer'image(to_integer(unsigned(result)));
assert patterns(i).co = cout report "BAD CARRY, GOT: " & std_logic'image(cout);
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
c31ffdb6f761987868e6c072ce7ebd28
| 0.696342 | 3.443096 | false | false | false | false |
pwuertz/digitizer2fw
|
src/rtl/sampling.vhd
| 1 | 7,871 |
-------------------------------------------------------------------------------
-- Sampling module
--
-- This component captures the data from the analog and digital inputs.
-- The data samples are forwarded to the application using the ADC data clock
-- frequency of 250 MHz (2 analog samples per cycle). From this clock a digital
-- sampling clock is synthesized at 1 GHz (4 digital samples per cycle).
--
-- The temporal order of the sample outputs is from left to right.
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sampling_pkg.all;
entity sampling is
port (
-- data in from pins
DIN_P: in std_logic_vector(1 downto 0);
DIN_N: in std_logic_vector(1 downto 0);
ADC_DA_P: in std_logic_vector(12 downto 0);
ADC_DA_N: in std_logic_vector(12 downto 0);
ADC_DACLK_P: in std_logic;
ADC_DACLK_N: in std_logic;
-- data in to device
app_clk: out std_logic;
samples_d: out din_samples_t(0 to 3);
samples_a: out adc_samples_t(0 to 1);
-- control
rst: in std_logic
);
end sampling;
architecture sampling_arch of sampling is
constant SAMPLES_A_PER_CLK: natural := 2;
constant SAMPLES_D_PER_CLK: natural := 4;
constant sampling_enable: std_logic := '1';
signal rst_int: std_logic_vector(2 downto 0) := (others => '0');
attribute ASYNC_REG: string;
attribute SHREG_EXTRACT: string;
attribute ASYNC_REG of rst_int: signal is "true";
attribute SHREG_EXTRACT of rst_int: signal is "no";
component sampling_daclk_core
port (
adc_daclk_in: in std_logic;
adc_daclk: out std_logic
);
end component;
signal adc_daclk_in, clk_da: std_logic;
constant ADC_DA_INV_MAP: std_logic_vector(ADC_DA_P'range) := "1111110000000";
signal ADC_DA_int, ADC_DA_int_inv: std_logic_vector(ADC_DA_P'range);
type adc_da_arr_t is array (natural range <>) of std_logic_vector(ADC_DA_P'range);
signal adc_da_arr: adc_da_arr_t(0 to SAMPLES_A_PER_CLK-1);
component sampling_din_core
port (
clk_dsample_in: in std_logic;
clk_dsample_fb: out std_logic;
clk_dsample: out std_logic;
clk_dsample_div: out std_logic
);
end component;
signal clk_dsample_fb: std_logic;
signal clk_dsample, clk_dsample_bufio, clk_dsample_bufio_inv: std_logic;
signal clk_dsample_div, clk_dsample_div_bufr: std_logic;
signal DIN_int, DIN_int_inv: std_logic_vector(DIN_P'range);
type din_arr_t is array (natural range <>) of std_logic_vector(DIN_P'range);
signal din_arr, din_arr_buf: din_arr_t(0 to SAMPLES_D_PER_CLK-1);
begin
-- register reset signal in sample clock domain
process(clk_da)
begin
if rising_edge(clk_da) then
rst_int <= rst_int(rst_int'high-1 downto 0) & rst;
end if;
end process;
-------------------------------------------------------------------------------
-- analog capture
-------------------------------------------------------------------------------
-- generate 0-phase clk_da from input ADC_DACLK (remove clock input delay)
ADC_DACLK_IBUFDS: IBUFDS
port map (
I => ADC_DACLK_P,
IB => ADC_DACLK_N,
O => adc_daclk_in
);
sampling_daclk_core_inst: sampling_daclk_core
port map (
adc_daclk_in => adc_daclk_in,
adc_daclk => clk_da
);
app_clk <= clk_da;
-- capture ADC_DA signals to adc_da_arr
GEN_ADC_IN: for I in ADC_DA_P'low to ADC_DA_P'high generate
-- for each DA signal, generate IBUFDS and IDDR
-- flip bits from inverted LVDS pairs (ADC_DA_INV_MAP)
IBUFDS_inst: IBUFDS
port map (
I => ADC_DA_P(I),
IB => ADC_DA_N(I),
O => ADC_DA_int(I)
);
ADC_DA_int_inv(I) <= not ADC_DA_int(I);
NORMAL: if ADC_DA_INV_MAP(I) = '0' generate
IDDR_inst: IDDR
generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map (
Q1 => adc_da_arr(0)(I),
Q2 => adc_da_arr(1)(I),
C => clk_da, CE => sampling_enable,
D => ADC_DA_int(I),
R => '0', S => '0'
);
end generate NORMAL;
INVERTED: if ADC_DA_INV_MAP(I) = '1' generate
IDDR_inst: IDDR
generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map (
Q1 => adc_da_arr(0)(I),
Q2 => adc_da_arr(1)(I),
C => clk_da, CE => sampling_enable,
D => ADC_DA_int_inv(I),
R => '0', S => '0'
);
end generate INVERTED;
end generate GEN_ADC_IN;
-- typecast and register analog output
process(clk_da)
begin
if rising_edge(clk_da) then
for I in 0 to SAMPLES_A_PER_CLK-1 loop
samples_a(I) <= to_adc_sample_t(adc_da_arr(I));
end loop;
end if;
end process;
-------------------------------------------------------------------------------
-- digital capture
-------------------------------------------------------------------------------
-- generate digital capture clocks from analog clock (fixed phase)
sampling_din_core_inst: sampling_din_core
port map (
clk_dsample_in => adc_daclk_in,
clk_dsample_fb => clk_dsample_fb,
clk_dsample => clk_dsample,
clk_dsample_div => clk_dsample_div
);
-- route digital capture clocks through BUFIO/BUFR
CLK_DSAMPLE_BUFIO_INST: BUFIO
port map (I => clk_dsample, O => clk_dsample_bufio);
clk_dsample_bufio_inv <= not clk_dsample_bufio;
CLK_DSAMPLE_DIV_BUFR_INST: BUFR
generic map (BUFR_DIVIDE => "1", SIM_DEVICE => "7SERIES")
port map (I => clk_dsample_div, CE => '1', CLR => '0', O => clk_dsample_div_bufr);
-- capture DIN signals to din_arr
GEN_DIG_IN: for I in DIN_P'low to DIN_P'high generate
-- for each DIN signal, generate IBUFDS and ISERDESE2
-- account for inverted LVDS pairs
IBUFDS_inst: IBUFDS
port map (
I => DIN_P(I),
IB => DIN_N(I),
O => DIN_int(I)
);
DIN_int_inv(I) <= not DIN_int(I);
ISERDESE2_inst: ISERDESE2
generic map (
DATA_RATE => "DDR", DATA_WIDTH => 4, INTERFACE_TYPE => "NETWORKING",
IOBDELAY => "NONE", NUM_CE => 2, OFB_USED => "FALSE", SERDES_MODE => "MASTER"
)
port map (
-- Q1 - Q8: 1-bit (each) output: Registered data outputs
Q1 => din_arr(3)(I), -- newest
Q2 => din_arr(2)(I),
Q3 => din_arr(1)(I),
Q4 => din_arr(0)(I), -- oldest
Q5 => open, Q6 => open, Q7 => open, Q8 => open,
-- Clocks: 1-bit (each) input: ISERDESE2 clock input ports
CLK => clk_dsample_bufio,
CLKB => clk_dsample_bufio_inv,
CLKDIV => clk_dsample_div_bufr,
CLKDIVP => '0',
-- Input Data: 1-bit (each) input: ISERDESE2 data input ports
D => DIN_int_inv(I),
DDLY => '0',
-- control
CE1 => sampling_enable, CE2 => sampling_enable,
RST => rst_int(rst_int'high),
BITSLIP => '0',
-- unused
DYNCLKDIVSEL => '0', DYNCLKSEL => '0',
SHIFTIN1 => '0', SHIFTIN2 => '0',
SHIFTOUT1 => open, SHIFTOUT2 => open,
O => open, OFB => '0',
OCLK => '0', OCLKB => '0'
);
end generate GEN_DIG_IN;
-- recapture din_arr in clk_div domain
process (clk_dsample_div_bufr)
begin
if rising_edge(clk_dsample_div_bufr) then
din_arr_buf <= din_arr;
end if;
end process;
-- register digital output in analog clock domain
process(clk_da)
begin
if rising_edge(clk_da) then
for I in 0 to SAMPLES_D_PER_CLK-1 loop
samples_d(I) <= din_arr_buf(I);
end loop;
end if;
end process;
end sampling_arch;
|
gpl-3.0
|
f8092813128dca5f36df17010b78c128
| 0.567217 | 3.432185 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/registry/registry_tb.vhd
| 1 | 2,045 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity registry_tb is
end entity;
architecture registry_tb_arq of registry_tb is
signal d_in : std_logic_vector(31 downto 0) := (others => '0');
signal rst_in: std_logic:='0';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal q_out: std_logic_vector(31 downto 0) := (others => '0');
component registry is
generic(TOTAL_BITS : integer := 32);
port(
enable: in std_logic;
reset: in std_logic;
clk: in std_logic;
D: in std_logic_vector(TOTAL_BITS - 1 downto 0);
Q: out std_logic_vector(TOTAL_BITS - 1 downto 0)
);
end component;
for registry_0: registry use entity work.registry;
begin
registry_0: registry
port map(
enable => enable_in,
reset => rst_in,
clk => clk_in,
D => d_in,
Q => q_out
);
process
type pattern_type is record
en : std_logic;
r: std_logic;
clk: std_logic;
d: std_logic_vector(31 downto 0);
q: std_logic_vector(31 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range<>) of pattern_type;
constant patterns : pattern_array := (
('1', '0','1', "00000000000000000000000000000001", "00000000000000000000000000000001"),
('0', '0','1', "00000000000000000000000000000000", "00000000000000000000000000000001"),
('0', '1','0', "00000000000111111000000000111111", "00000000000000000000000000000000"),
('0', '1','1', "00000000000111111000000000111111", "00000000000000000000000000000000")
);
begin
for i in patterns'range loop
d_in <= patterns(i).d;
enable_in <= patterns(i).en;
rst_in <= patterns(i).r;
clk_in <= patterns(i).clk;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert q_out = patterns(i).q report "BAD Q: " & integer'image(to_integer(unsigned(q_out)));
clk_in <= '0'; --reset clock
wait for 1 ns;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
bf50b02a22509048c7e9a9f9b19c3e6f
| 0.640098 | 3.225552 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/tps-Gaston/tp1/generic_counter_tb.vhd
| 2 | 917 |
library ieee;
use ieee.std_logic_1164.all;
entity generic_counter_tb is
end;
architecture generic_counter_tb_func of generic_counter_tb is
signal rst_in: std_logic:='1';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal n_out: std_logic_vector(3 downto 0);
signal c_out: std_logic:='0';
component generic_counter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end component;
begin
clk_in <= not(clk_in) after 20 ns;
rst_in <= '0' after 50 ns;
enable_in <= '1' after 60 ns;
generic_counter_map: generic_counter generic map (4,19)
port map(
clk => clk_in,
rst => rst_in,
ena => enable_in,
count => n_out,
carry_o => c_out
);
end architecture;
|
gpl-3.0
|
0866268e18485273f2da81e2080ac327
| 0.61614 | 2.795732 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/TP1-Contador/led_enabler.vhd
| 1 | 1,231 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity led_enabler is
port(
enabler_input : in std_logic_vector(3 downto 0);
enabler_output : out std_logic_vector(7 downto 0)
);
end led_enabler;
architecture led_enabler_arq of led_enabler is
begin
process (enabler_input) is
begin
case enabler_input is
when "0000" => enabler_output <= not b"11111100"; ---a->g
when "0001" => enabler_output <= not b"01100000";
when "0010" => enabler_output <= not b"11011010";
when "0011" => enabler_output <= not b"11110010";
when "0100" => enabler_output <= not b"01100110";
when "0101" => enabler_output <= not b"10110110";
when "0110" => enabler_output <= not b"10111110";
when "0111" => enabler_output <= not b"11100000";
when "1000" => enabler_output <= not b"11111110";
when "1001" => enabler_output <= not b"11100110";
when others => enabler_output <= not b"01111100"; ---u
end case;
end process;
end led_enabler_arq;
|
gpl-3.0
|
558875e0fd303dab6eed4f5eb7314d2d
| 0.528838 | 3.920382 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/stage_polynomial_calc_v2.vhd
| 1 | 2,556 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Stage_Polynomial_Calc_v2
-- Module Name: Stage_Polynomial_Calc_v2
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 3rd step in Goppa Code Decoding.
--
-- This circuit is the stage for pipeline_polynomial_calc_v2. The pipeline is composed of
-- an arbitrary number of this stages.
--
-- For the computation this circuit applies the Horner scheme, where at each stage
-- an accumulator is multiplied by respective x and then added accumulated with coefficient.
-- In Horner scheme algorithm, it begin from the most significative coefficient until reaches
-- lesser significative coefficient.
--
-- To improve syndrome generation this circuit was adapted to support syndrome generation
-- in stage_polynomial_calc_v3
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- Dependencies:
-- VHDL-93
--
-- mult_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity stage_polynomial_calc_v2 is
Generic(gf_2_m : integer range 1 to 20 := 11);
Port (
value_x : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
value_polynomial_coefficient : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0)
);
end stage_polynomial_calc_v2;
architecture Behavioral of stage_polynomial_calc_v2 is
component mult_gf_2_m
Generic(gf_2_m : integer range 1 to 20 := 11);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal mult_x_a : STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
signal mult_x_b : STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
signal mult_x_o : STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
begin
mult_x : mult_gf_2_m
Generic Map (gf_2_m => gf_2_m)
Port Map (
a => mult_x_a,
b => mult_x_b,
o => mult_x_o
);
mult_x_a <= value_x;
mult_x_b <= value_acc xor value_polynomial_coefficient;
new_value_acc <= mult_x_o;
end Behavioral;
|
bsd-2-clause
|
8417a05cf597fd5326f40c9815b25271
| 0.637324 | 3.175155 | false | false | false | false |
rajvinjamuri/ECE385_VHDL
|
logic_unit.vhd
| 1 | 5,919 |
---------------------------------------------------------------------------
-- logic_unit.vhd --
-- Sai Koppula --
-- 3-13 --
-- --
-- Purpose/Description --
-- Takes in make_code and outputs the right direction --
-- --
-- --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
-- --
-- --
--Updates --
-- --
-- >fixed 11 downto 0 --
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity logic_unit is
Port (
SR_In : in std_logic_vector(10 downto 0);
PR_In : in std_logic_vector(10 downto 0);
-- Up, Do, Le, Ri : out std_logic;
WW, SS, AA, DD : out std_logic;
QQ, EE, RR : out std_logic;
One, Two, Three, Four, Five, Six, Seven, Eight, Nine, Zero : out std_logic;
Plus, Minus : out std_logic;
Spacebar : out std_logic);
end logic_unit;
architecture Behavioral of logic_unit is
signal break_code : std_logic_vector(7 downto 0);
begin
break_code <= "11110000"; --set the break code (supposed to be F0) to F8 here
decideMove: process(SR_In, PR_In)
begin
if (SR_In(8 downto 1) = "00011101") --W
then
if (PR_In(8 downto 1) /= break_code)
then WW <= '1';
else WW <= '0';
end if;
else WW <= '0';
end if;
if (SR_In(8 downto 1) = "00011011") --S
then
if (PR_In(8 downto 1) /= break_code)
then SS <= '1';
else SS <= '0';
end if;
else SS <= '0';
end if;
if (SR_In(8 downto 1) = "00011100") --A
then
if (PR_In(8 downto 1) /= break_code) -- THIS WAS HACKED, FIND BETTER SOLUTION (Break code was coming out as F8 instead of F0)
then AA <= '1';
else AA <= '0';
end if;
else AA <= '0';
end if;
if (SR_In(8 downto 1) = "00100011") --D
then
if (PR_In(8 downto 1) /= break_code) -- THIS WAS HACKED, FIND BETTER SOLUTION
then DD <= '1';
else DD <= '0';
end if;
else DD <= '0';
end if;
--------------------------------------------
if (SR_In(8 downto 1) = "00010110") --1
then
if (PR_In(8 downto 1) /= break_code)
then One <= '1';
else One <= '0';
end if;
else One <= '0';
end if;
if (SR_In(8 downto 1) = "00011110") --2
then
if (PR_In(8 downto 1) /= break_code)
then Two <= '1';
else Two <= '0';
end if;
else Two <= '0';
end if;
if (SR_In(8 downto 1) = "00100110") --3
then
if (PR_In(8 downto 1) /= break_code)
then Three <= '1';
else Three <= '0';
end if;
else Three <= '0';
end if;
if (SR_In(8 downto 1) = "00100101") --4
then
if (PR_In(8 downto 1) /= break_code)
then Four <= '1';
else Four <= '0';
end if;
else Four <= '0';
end if;
if (SR_In(8 downto 1) = "00101110") --5
then
if (PR_In(8 downto 1) /= break_code)
then Five <= '1';
else Five <= '0';
end if;
else Five <= '0';
end if;
if (SR_In(8 downto 1) = "00100110") --6
then
if (PR_In(8 downto 1) /= break_code)
then Six <= '1';
else Six <= '0';
end if;
else Six <= '0';
end if;
if (SR_In(8 downto 1) = "00111101") --7
then
if (PR_In(8 downto 1) /= break_code)
then Seven <= '1';
else Seven <= '0';
end if;
else Seven <= '0';
end if;
if (SR_In(8 downto 1) = "00111110") --8
then
if (PR_In(8 downto 1) /= break_code)
then Eight <= '1';
else Eight <= '0';
end if;
else Eight <= '0';
end if;
if (SR_In(8 downto 1) = "01000110") --9
then
if (PR_In(8 downto 1) /= break_code)
then Nine <= '1';
else Nine <= '0';
end if;
else Nine <= '0';
end if;
if (SR_In(8 downto 1) = "01000101") --0
then
if (PR_In(8 downto 1) /= break_code)
then Zero <= '1';
else Zero <= '0';
end if;
else Zero <= '0';
end if;
--------------------------------------------
if (SR_In(8 downto 1) = "00010101") --Q
then
if (PR_In(8 downto 1) /= break_code)
then QQ <= '1';
else QQ <= '0';
end if;
else QQ <= '0';
end if;
if (SR_In(8 downto 1) = "00100100") --E
then
if (PR_In(8 downto 1) /= break_code)
then EE <= '1';
else EE <= '0';
end if;
else EE <= '0';
end if;
if (SR_In(8 downto 1) = "00101101") --R
then
if (PR_In(8 downto 1) /= break_code)
then RR <= '1';
else RR <= '0';
end if;
else RR <= '0';
end if;
--------------------------------------------
if (SR_In(8 downto 1) = "01010101") --Plus
then
if (PR_In(8 downto 1) /= break_code)
then Plus <= '1';
else Plus <= '0';
end if;
else Plus <= '0';
end if;
if (SR_In(8 downto 1) = "01001110") --Minus
then
if (PR_In(8 downto 1) /= break_code)
then Minus <= '1';
else Minus <= '0';
end if;
else Minus <= '0';
end if;
if (SR_In(8 downto 1) = "00101001") --Spacebar
then
if (PR_In(8 downto 1) /= break_code)
then Spacebar <= '1';
else Spacebar <= '0';
end if;
else Spacebar <= '0';
end if;
end process;
end Behavioral;
|
mit
|
d96289d48ed360a75f10cc99b2a462c0
| 0.418652 | 3.241512 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/result_complementer/result_complementer_tb.vhd
| 1 | 2,298 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity result_complementer_tb is
end entity;
architecture result_complementer_tb_arq of result_complementer_tb is
signal result_in : std_logic_vector(5 downto 0) := (others => '0');
signal sign_1_in : std_logic := '0';
signal sign_2_in : std_logic := '0';
signal result_cout : std_logic := '0';
signal result_out : std_logic_vector(5 downto 0) := (others => '0');
component result_complementer is
generic(
BITS : natural := 16
);
port(
in_result : in std_logic_vector(BITS - 1 downto 0) := (others => '0');
sign_1_in : in std_logic := '0';
sign_2_in : in std_logic := '0';
result_cout : in std_logic := '0';
out_result : out std_logic_vector(BITS - 1 downto 0) := (others => '0')
);
end component;
for result_complementer_0 : result_complementer use entity work.result_complementer;
begin
result_complementer_0 : result_complementer
generic map(BITS => 6)
port map(
in_result => result_in,
sign_1_in => sign_1_in,
sign_2_in => sign_2_in,
result_cout => result_cout,
out_result => result_out
);
process
type pattern_type is record
ir : std_logic_vector(5 downto 0);
s1 : std_logic;
s2 : std_logic;
rco : std_logic;
r : std_logic_vector(5 downto 0);
end record;
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("000000",'0', '0', '0',"000000"),
("000000",'1', '1', '0',"000000"),
("000000",'0', '0', '1',"000000"),
("000000",'1', '1', '1',"000000"),
("000000",'0', '1', '1',"000000"),
("000000",'1', '0', '1',"000000"),
("000000",'0', '1', '0',"000000"),
("000000",'1', '0', '0',"000000"),
("111111",'0', '1', '0',"000001"),
("111111",'1', '0', '0',"000001")
);
begin
for i in patterns'range loop
result_in <= patterns(i).ir;
sign_1_in <= patterns(i).s1;
sign_2_in <= patterns(i).s2;
result_cout <= patterns(i).rco;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert result_out = patterns(i).r report "BAD RESULT: " & integer'image(to_integer(unsigned(result_out)));
end loop;
assert false report "end of test" severity note;
wait;
end process;
end result_complementer_tb_arq;
|
gpl-3.0
|
ab4051a93f8f82b1569854d5d2baee77
| 0.602698 | 2.868914 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/polynomial_evaluator_n_v2.vhd
| 1 | 18,265 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Polynomial_Evaluator_N_v2
-- Module Name: Polynomial_Evaluator_N_v2
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 3rd step in Goppa Code Decoding.
--
-- This circuit is to be used together with find_correct_erros_n to find the roots
-- of polynomial sigma. This circuit can also be alone to evaluate a polynomial withing
-- a range of values.
--
-- For the computation this circuit applies the Horner scheme, where at each stage
-- an accumulator is multiplied by respective x and then added accumulated with coefficient.
-- In Horner scheme algorithm, it begin from the most significative coefficient until reaches
-- lesser significative coefficient.
--
-- To improve syndrome generation this circuit were joined with find_correct_errors in
-- polynomial_syndrome_computing_n.
--
-- The circuits parameters
--
-- number_of_pipelines :
--
-- Number of pipelines used in the circuit to test the support elements and
-- correct the message. Each pipeline needs at least 2 memory ram to store
-- intermediate results.
--
-- pipeline_size :
--
-- The number of stages the pipeline has. More stages means more values of value_sigma
-- are tested at once.
--
-- size_pipeline_size :
--
-- The number of bits necessary to store the pipeline_size.
-- This number is ceil(log2(pipeline_size))
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- polynomial_degree :
--
-- The polynomial degree to be evaluated. Therefore the polynomial has
-- polynomial_degree+1 coefficients. This parameters depends of the Goppa code used.
--
-- size_polynomial_degree :
--
-- The number of bits necessary to store polynomial_degree.
-- This number is ceil(log2(polynomial_degree+1))
--
-- number_of_values_x :
--
-- The size of the memory that holds all support elements. This parameter
-- depends of the Goppa code used.
--
-- size_number_of_values_x :
-- The number of bits necessary to store all support elements.
-- this number is ceil(log2(number_of_values_x)).
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- pipeline_polynomial_calc_v2 Rev 1.0
-- shift_register_rst_nbits Rev 1.0
-- shift_register_nbits Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_decrement_rst_nbits Rev 1.0
-- controller_polynomial_evaluator Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity polynomial_evaluator_n_v2 is
Generic (
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 28;
-- size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 11;
-- polynomial_degree : integer := 27;
-- size_polynomial_degree : integer := 5;
-- number_of_values_x: integer := 2048;
-- size_number_of_values_x : integer := 11
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 51;
-- size_pipeline_size : integer := 6;
-- gf_2_m : integer range 1 to 20 := 11;
-- polynomial_degree : integer := 50;
-- size_polynomial_degree : integer := 6;
-- number_of_values_x: integer := 2048;
-- size_number_of_values_x : integer := 11
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 67;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- polynomial_degree : integer := 66;
-- size_polynomial_degree : integer := 7;
-- number_of_values_x: integer := 3307;
-- size_number_of_values_x : integer := 12
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 33;
-- size_pipeline_size : integer := 6;
-- gf_2_m : integer range 1 to 20 := 12;
-- polynomial_degree : integer := 32;
-- size_polynomial_degree : integer := 6;
-- number_of_values_x: integer := 2528;
-- size_number_of_values_x : integer := 12
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- polynomial_degree : integer := 64;
-- size_polynomial_degree : integer := 7;
-- number_of_values_x: integer := 2816;
-- size_number_of_values_x : integer := 12
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- polynomial_degree : integer := 64;
-- size_polynomial_degree : integer := 7;
-- number_of_values_x: integer := 3328;
-- size_number_of_values_x : integer := 12
-- QD-GOPPA [7296, 5632, 128, 13] --
number_of_pipelines : integer := 1;
pipeline_size : integer := 2;
size_pipeline_size : integer := 2;
gf_2_m : integer range 1 to 20 := 13;
polynomial_degree : integer := 128;
size_polynomial_degree : integer := 8;
number_of_values_x: integer := 7296;
size_number_of_values_x : integer := 13
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_evaluations : out STD_LOGIC;
evaluation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_polynomial_degree - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0)
);
end polynomial_evaluator_n_v2;
architecture RTL of polynomial_evaluator_n_v2 is
component pipeline_polynomial_calc_v2
Generic (
gf_2_m : integer range 1 to 20 := 11;
size : integer := 2
);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((((gf_2_m)*size) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
reg_x_rst : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component shift_register_rst_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component shift_register_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component register_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_decrement_rst_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component controller_polynomial_evaluator
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_load_x_values : in STD_LOGIC;
last_store_x_values : in STD_LOGIC;
limit_polynomial_degree : in STD_LOGIC;
pipeline_ready : in STD_LOGIC;
evaluation_data_in : out STD_LOGIC;
reg_write_enable_rst : out STD_LOGIC;
ctr_load_x_address_ce : out STD_LOGIC;
ctr_load_x_address_rst : out STD_LOGIC;
ctr_store_x_address_ce : out STD_LOGIC;
ctr_store_x_address_rst : out STD_LOGIC;
reg_first_values_ce : out STD_LOGIC;
reg_first_values_rst : out STD_LOGIC;
ctr_address_polynomial_ce : out STD_LOGIC;
ctr_address_polynomial_rst : out STD_LOGIC;
reg_x_rst_rst : out STD_LOGIC;
shift_polynomial_ce_ce : out STD_LOGIC;
shift_polynomial_ce_rst : out STD_LOGIC;
last_coefficients : out STD_LOGIC;
evaluation_finalized : out STD_LOGIC
);
end component;
signal pipeline_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal pipeline_value_x_pow : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
constant coefficient_zero : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
constant first_acc : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
constant first_x_pow : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(1, gf_2_m));
signal reg_polynomial_coefficients_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_polynomial_coefficients_ce : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal reg_polynomial_coefficients_q : STD_LOGIC_VECTOR((((gf_2_m)*pipeline_size) - 1) downto 0);
signal reg_x_rst_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_x_rst_ce : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal reg_x_rst_rst : STD_LOGIC;
signal reg_x_rst_q : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal reg_x_rst : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal shift_polynomial_ce_data_in : STD_LOGIC;
signal shift_polynomial_ce_ce : STD_LOGIC;
signal shift_polynomial_ce_rst : STD_LOGIC;
constant shift_polynomial_ce_rst_value : STD_LOGIC_VECTOR(pipeline_size downto 0) := std_logic_vector(to_unsigned(1, pipeline_size+1));
signal shift_polynomial_ce_q : STD_LOGIC_VECTOR(pipeline_size downto 0);
signal ctr_address_polynomial_ce : STD_LOGIC;
signal ctr_address_polynomial_rst : STD_LOGIC;
constant ctr_address_polynomial_rst_value : STD_LOGIC_VECTOR((size_polynomial_degree) downto 0) := std_logic_vector(to_signed(polynomial_degree, size_polynomial_degree+1));
signal ctr_address_polynomial_q : STD_LOGIC_VECTOR((size_polynomial_degree) downto 0);
signal ctr_load_x_address_ce : STD_LOGIC;
signal ctr_load_x_address_rst : STD_LOGIC;
constant ctr_load_x_address_rst_value : STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0) := std_logic_vector(to_unsigned(0, size_number_of_values_x));
signal ctr_load_x_address_q : STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
signal ctr_store_x_address_ce : STD_LOGIC;
signal ctr_store_x_address_rst : STD_LOGIC;
constant ctr_store_x_message_address_rst_value : STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0) := std_logic_vector(to_unsigned(0, size_number_of_values_x));
signal ctr_store_x_address_q : STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
signal reg_first_values_ce : STD_LOGIC;
signal reg_first_values_rst : STD_LOGIC;
constant reg_first_values_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "1";
signal reg_first_values_q : STD_LOGIC_VECTOR(0 downto 0);
signal evaluation_data_in : STD_LOGIC;
signal evaluation_data_out : STD_LOGIC;
signal reg_write_enable_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_write_enable_rst : STD_LOGIC;
constant reg_write_enable_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_write_enable_q : STD_LOGIC_VECTOR(0 downto 0);
signal pipeline_ready : STD_LOGIC;
signal limit_polynomial_degree : STD_LOGIC;
signal last_coefficients : STD_LOGIC;
signal last_load_x_values : STD_LOGIC;
signal last_store_x_values : STD_LOGIC;
begin
pipelines : for I in 0 to (number_of_pipelines - 1) generate
pipeline_I : pipeline_polynomial_calc_v2
Generic Map (
gf_2_m => gf_2_m,
size => pipeline_size
)
Port Map(
value_x => value_x(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
value_polynomial => reg_polynomial_coefficients_q,
value_acc => pipeline_value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
reg_x_rst => reg_x_rst,
clk => clk,
new_value_acc => new_value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)))
);
pipeline_value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= first_acc when reg_first_values_q = "1" else
value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)));
end generate;
polynomial : for I in 0 to (pipeline_size - 1) generate
reg_polynomial_coefficients_I : register_nbits
Generic Map (size => gf_2_m)
Port Map(
d => reg_polynomial_coefficients_d,
clk => clk,
ce => reg_polynomial_coefficients_ce(I),
q => reg_polynomial_coefficients_q(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)))
);
reg_x_rst_I : register_rst_nbits
Generic Map (size => 1)
Port Map(
d => reg_x_rst_d,
clk => clk,
ce => reg_x_rst_ce(I),
rst => reg_x_rst_rst,
rst_value => "0",
q => reg_x_rst_q(I downto I)
);
reg_x_rst(I) <= (reg_x_rst_q(I) or (limit_polynomial_degree and shift_polynomial_ce_q(I)));
end generate;
controller : controller_polynomial_evaluator
Port Map(
clk => clk,
rst => rst,
last_load_x_values => last_load_x_values,
last_store_x_values => last_store_x_values,
limit_polynomial_degree => limit_polynomial_degree,
pipeline_ready => pipeline_ready,
evaluation_data_in => evaluation_data_in,
reg_write_enable_rst => reg_write_enable_rst,
ctr_load_x_address_ce => ctr_load_x_address_ce,
ctr_load_x_address_rst => ctr_load_x_address_rst,
ctr_store_x_address_ce => ctr_store_x_address_ce,
ctr_store_x_address_rst => ctr_store_x_address_rst,
reg_first_values_ce => reg_first_values_ce,
reg_first_values_rst => reg_first_values_rst,
ctr_address_polynomial_ce => ctr_address_polynomial_ce,
ctr_address_polynomial_rst => ctr_address_polynomial_rst,
reg_x_rst_rst => reg_x_rst_rst,
shift_polynomial_ce_ce => shift_polynomial_ce_ce,
shift_polynomial_ce_rst => shift_polynomial_ce_rst,
last_coefficients => last_coefficients,
evaluation_finalized => evaluation_finalized
);
shift_polynomial_ce : shift_register_rst_nbits
Generic Map(
size => pipeline_size + 1
)
Port Map(
data_in => shift_polynomial_ce_data_in,
clk => clk,
ce => shift_polynomial_ce_ce,
rst => shift_polynomial_ce_rst,
rst_value => shift_polynomial_ce_rst_value,
q => shift_polynomial_ce_q,
data_out => shift_polynomial_ce_data_in
);
evaluation : shift_register_nbits
Generic Map(
size => pipeline_size - 1
)
Port Map(
data_in => evaluation_data_in,
clk => clk,
ce => '1',
q => open,
data_out => evaluation_data_out
);
reg_write_enable : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_write_enable_d,
clk => clk,
ce => '1',
rst => reg_write_enable_rst,
rst_value => reg_write_enable_rst_value,
q => reg_write_enable_q
);
ctr_address_polynomial : counter_decrement_rst_nbits
Generic Map(
size => size_polynomial_degree+1,
decrement_value => 1
)
Port Map(
clk => clk,
ce => ctr_address_polynomial_ce,
rst => ctr_address_polynomial_rst,
rst_value => ctr_address_polynomial_rst_value,
q => ctr_address_polynomial_q
);
ctr_load_x_address : counter_rst_nbits
Generic Map(
size => size_number_of_values_x,
increment_value => number_of_pipelines
)
Port Map(
clk => clk,
ce => ctr_load_x_address_ce,
rst => ctr_load_x_address_rst,
rst_value => ctr_load_x_address_rst_value,
q => ctr_load_x_address_q
);
ctr_store_x_address : counter_rst_nbits
Generic Map(
size => size_number_of_values_x,
increment_value => number_of_pipelines
)
Port Map(
clk => clk,
ce => ctr_store_x_address_ce,
rst => ctr_store_x_address_rst,
rst_value => ctr_store_x_message_address_rst_value,
q => ctr_store_x_address_q
);
reg_first_values : register_rst_nbits
Generic Map(size => 1)
Port Map(
d => "0",
clk => clk,
ce => reg_first_values_ce,
rst => reg_first_values_rst,
rst_value => reg_first_values_rst_value,
q => reg_first_values_q
);
reg_x_rst_d(0) <= limit_polynomial_degree;
reg_x_rst_ce <= shift_polynomial_ce_q((pipeline_size - 1) downto 0);
reg_polynomial_coefficients_d <= coefficient_zero when last_coefficients = '1' else
value_polynomial;
reg_polynomial_coefficients_ce <= shift_polynomial_ce_q((pipeline_size - 1) downto 0);
address_value_polynomial <= ctr_address_polynomial_q((size_polynomial_degree - 1) downto 0);
address_value_x <= ctr_load_x_address_q;
address_value_acc <= ctr_load_x_address_q;
address_new_value_acc <= ctr_store_x_address_q;
pipeline_ready <= shift_polynomial_ce_q(pipeline_size-1);
limit_polynomial_degree <= '1' when (signed(ctr_address_polynomial_q) = to_signed(-1, ctr_address_polynomial_q'length)) else '0';
last_evaluations <= limit_polynomial_degree and shift_polynomial_ce_q(pipeline_size);
reg_write_enable_d(0) <= evaluation_data_out;
write_enable_new_value_acc <= reg_write_enable_q(0);
last_load_x_values <= '1' when ctr_load_x_address_q = std_logic_vector(to_unsigned(((number_of_values_x - 1)/number_of_pipelines)*number_of_pipelines, ctr_load_x_address_q'Length)) else '0';
last_store_x_values <= '1' when ctr_store_x_address_q = std_logic_vector(to_unsigned(((number_of_values_x - 1)/number_of_pipelines)*number_of_pipelines, ctr_load_x_address_q'Length)) else '0';
end RTL;
|
bsd-2-clause
|
f24d0b74bfe485f090efc810e3351f18
| 0.668218 | 2.875925 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/ram.vhd
| 1 | 3,364 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: RAM
-- Module Name: RAM
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavioral of a memory RAM. Only used for tests.
--
-- The circuits parameters
--
-- ram_address_size :
--
-- Address size of the RAM used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word on the RAM.
--
-- file_ram_word_size :
--
-- The size of the word used in the file to be loaded on the RAM.(ARCH: FILE_LOAD)
--
-- load_file_name :
--
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
--
-- The name of the file to be used to dump the memory.(ARCH: FILE_LOAD)
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
entity ram is
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end ram;
architecture simple of ram is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
for I in 0 to (2**ram_address_size - 1) loop
memory_ram(I) <= rst_value;
end loop;
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw = '1' then
memory_ram(to_integer(unsigned(address))) <= data_in;
end if;
data_out <= memory_ram(to_integer(unsigned(address)));
end if;
end process;
end simple;
|
bsd-2-clause
|
b4b1adb0ecb26d358fcfc9f19f7dabe5
| 0.504459 | 3.676503 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/bit_xor/bit_xor_tb.vhd
| 1 | 1,226 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bit_xor_tb is
end entity;
architecture bit_xor_tb_arq of bit_xor_tb is
signal bit1 : std_logic;
signal bit2 : std_logic;
signal result : std_logic;
component bit_xor is
port (
bit1_in: in std_logic := '0';
bit2_in: in std_logic := '0';
result: out std_logic := '0'
);
end component;
begin
bit_xor_0 : bit_xor
port map(
bit1_in => bit1,
bit2_in => bit2,
result => result
);
process
type pattern_type is record
b1 : std_logic;
b2 : std_logic;
r : std_logic;
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
('0','0','0'),
('0','1','1'),
('1','0','1'),
('1','1','0')
);
begin
for i in patterns'range loop
-- Set the inputs.
bit1 <= patterns(i).b1;
bit2 <= patterns(i).b2;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert result = patterns(i).r report "BAD RESULT: " & std_logic'image(result);
end loop;
assert false report "end of test" severity note;
wait;
end process;
end bit_xor_tb_arq;
|
gpl-3.0
|
431e2f845f38d40a57e09e285998fdd5
| 0.59217 | 2.755056 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/tps-Gaston/tp1/cont_bcd_tb.vhd
| 2 | 754 |
library ieee;
use ieee.std_logic_1164.all;
entity cont_bcd_tb is
end;
architecture cont_bcd_tb_func of cont_bcd_tb is
signal rst_in: std_logic:='1';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal n_out: std_logic_vector(3 downto 0);
signal c_out: std_logic:='0';
component cont_bcd is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
s: out std_logic_vector(3 downto 0);
co: out std_logic
);
end component;
begin
clk_in <= not(clk_in) after 20 ns;
rst_in <= '0' after 50 ns;
enable_in <= '1' after 60 ns;
contadorBCDMap: cont_bcd port map(
clk => clk_in,
rst => rst_in,
ena => enable_in,
s => n_out,
co => c_out
);
end architecture;
|
gpl-3.0
|
6fbd85e48d947a8e48c262befcb780bb
| 0.607427 | 2.608997 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/Gen_Ena/gen_ena_tb.vhd
| 2 | 644 |
library ieee;
use ieee.std_logic_1164.all;
entity gen_ena_tb is
end;
architecture gen_ena_tb_func of gen_ena_tb is
signal rst_in: std_logic:='1';
signal enable_out: std_logic:='0';
signal clk_in: std_logic:='0';
component generic_enabler is
generic(PERIOD:natural := 1000000 ); --1MHz
port(
clk: in std_logic;
rst: in std_logic;
ena_out: out std_logic
);
end component;
begin
clk_in <= not(clk_in) after 1 ns;
rst_in <= '0' after 50 ns;
genEnaMap: generic_enabler generic map(4)
port map(
clk => clk_in,
rst => rst_in,
ena_out => enable_out
);
end architecture;
|
gpl-3.0
|
7992c4bae430550a361583d2483a3629
| 0.613354 | 2.8 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/TP1-Contador/led_display_controller.vhd
| 1 | 2,850 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity led_display_controller is
port (
clk_in: in std_logic;
bcd0: in std_logic_vector(3 downto 0);
bcd1: in std_logic_vector(3 downto 0);
bcd2: in std_logic_vector(3 downto 0);
bcd3: in std_logic_vector(3 downto 0);
anode_output: out std_logic_vector(3 downto 0);
led_output : out std_logic_vector(7 downto 0)
);
end;
architecture led_display_controller_arq of led_display_controller is
signal counter_enabler: std_logic:= '1';
signal counter_output: std_logic_vector(1 downto 0);
signal multiplex_output: std_logic_vector(3 downto 0);
component generic_counter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15
);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
counter_out: out std_logic_vector(BITS-1 downto 0);
carry_out: out std_logic
);
end component;
component generic_enabler is
generic(
PERIOD:natural := 1000000 --1MHz
);
port(
clk: in std_logic;
rst: in std_logic;
enabler_out: out std_logic
);
end component;
component bcd_multiplexer IS
port(
bcd0_input : in std_logic_vector(3 downto 0);
bcd1_input : in std_logic_vector(3 downto 0);
bcd2_input : in std_logic_vector(3 downto 0);
bcd3_input : in std_logic_vector(3 downto 0);
mux_selector : in std_logic_vector (1 downto 0);
mux_output : out std_logic_vector (3 downto 0)
);
end component;
component anode_selector is
port(
selector_in : in std_logic_vector (1 downto 0);
selector_out : out std_logic_vector (3 downto 0)
);
end component;
component led_enabler is
port(
enabler_input : in std_logic_vector(3 downto 0);
enabler_output : out std_logic_vector(7 downto 0)
);
end component;
begin
genericCounterMap: generic_counter
generic map (2,4)
port map(
clk => clk_in,
rst => '0',
ena => counter_enabler,
counter_out => counter_output
);
generic_enabler_map: generic_enabler
generic map (500000)
port map(
clk => clk_in,
rst => '0',
enabler_out => counter_enabler
);
bcd_multiplexerMap: bcd_multiplexer
port map(
bcd0_input => bcd0,
bcd1_input => bcd1,
bcd2_input => bcd2,
bcd3_input => bcd3,
mux_selector => counter_output,
mux_output => multiplex_output
);
anode_selMap: anode_selector
port map(
selector_in => counter_output,
selector_out => anode_output
);
led_enablerMap: led_enabler
port map(
enabler_input => multiplex_output,
enabler_output => led_output
);
end;
|
gpl-3.0
|
e00dd9d351dcacfe095a08010dea6c1d
| 0.598596 | 3.413174 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/mceliece_qd_goppa_decrypt_v4.vhd
| 1 | 26,259 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: McEliece_QD-Goppa_Decrypt_v4
-- Module Name: McEliece_QD-Goppa_Decrypt_v4
-- Project Name: McEliece Goppa Decryption
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit implements McEliece decryption algorithm for binary Goppa codes.
-- The circuit is divided into 3 phases : Syndrome computation, Solving Key Equation and
-- Finding Root.
-- Each circuits waits for the next one to begin computation. All circuits share some
-- input and output memories, therefore is not possible to make a pipeline of this 3 phases.
-- First circuit, polynomial_syndrome_computing_n_v2, computes the syndrome from the ciphertext
-- and private keys, support L and polynomial g(x) (In this case g(L)^-1).
-- Second circuit, solving_key_equation_5, computes polynomial sigma through
-- the syndrome computed by first circuit.
-- Third circuit, polynomial_syndrome_computing_n_v2, find the roots of polynomial sigma
-- and correct respective errors in the ciphertext and obtains plaintext array.
-- Inversion circuit, inv_gf_2_m_pipeline, is only used during solving_key_equation_5.
-- This circuit was made outside of solving_key_equation_5 so it can be used by other circuits.
--
-- The circuits parameters
--
-- number_of_polynomial_evaluator_syndrome_pipelines :
--
-- The number of pipelines in polynomial_syndrome_computing_n_v2 circuit.
-- This number can be 1 or greater.
--
-- polynomial_evaluator_syndrome_pipeline_size :
--
-- This is the number of stages on polynomial_syndrome_computing_n_v2 circuit.
-- This number can be 2 or greater.
--
-- polynomial_evaluator_syndrome_size_pipeline_size :
--
-- The number of bits necessary to hold the number of stages on the pipeline.
-- This is ceil(log2(polynomial_evaluator_syndrome_pipeline_size))
--
-- gf_2_m :
--
-- The size of the finite field extension used in this circuit.
-- This values depends of the Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword in this Goppa code.
-- This values depends of the Goppa code used.
--
-- size_codeword :
--
-- The number of bits necessary to store an array of codeword lengths.
-- This is ceil(log2(length_codeword))
--
-- number_of_errors :
--
-- The number of errors the Goppa code is able to decode.
-- This values depends of the Goppa code used.
--
-- size_number_of_errors :
--
-- The number of bits necessary to store an array of number of errors + 1 length.
-- This is ceil(log2(number_of_errors+1))
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- polynomial_syndrome_computing_n_v2 Rev 1.0
-- solving_key_equation_5 Rev 1.0
-- inv_gf_2_m_pipeline Rev 1.0
-- register_rst_nbits Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mceliece_qd_goppa_decrypt_v4 is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 4;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 28;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 27;
-- size_number_of_errors : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 50;
-- size_number_of_errors : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3307;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 66;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 32;
-- size_number_of_errors : integer := 6
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [7296, 5632, 128, 13] --
number_of_polynomial_evaluator_syndrome_pipelines : integer := 4;
polynomial_evaluator_syndrome_pipeline_size : integer := 7;
polynomial_evaluator_syndrome_size_pipeline_size : integer := 3;
gf_2_m : integer range 1 to 20 := 13;
length_codeword : integer := 7296;
size_codeword : integer := 13;
number_of_errors : integer := 128;
size_number_of_errors : integer := 8
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_L : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
value_s : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_v : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma_evaluated : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
syndrome_generation_finalized : out STD_LOGIC;
key_equation_finalized : out STD_LOGIC;
decryption_finalized : out STD_LOGIC;
address_value_h : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_L : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_codeword : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_s : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_v : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_s : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_v : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_sigma : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_error : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_s : out STD_LOGIC;
write_enable_new_value_v : out STD_LOGIC;
write_enable_new_value_sigma : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_new_value_error : out STD_LOGIC;
write_enable_new_value_sigma_evaluated : out STD_LOGIC;
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_s : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_v : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_error : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0)
);
end mceliece_qd_goppa_decrypt_v4;
architecture Behavioral of mceliece_qd_goppa_decrypt_v4 is
component polynomial_syndrome_computing_n_v2
Generic (
number_of_pipelines : integer := 1;
pipeline_size : integer := 2;
size_pipeline_size : integer := 2;
gf_2_m : integer range 1 to 20 := 13;
number_of_errors : integer := 128;
size_number_of_errors : integer := 8;
number_of_support_elements: integer := 7296;
size_number_of_support_elements : integer := 13
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_message : in STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_h : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
computation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
address_value_error : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_value_error : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR(((gf_2_m) - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_error : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0)
);
end component;
component solving_key_equation_5
Generic(
gf_2_m : integer range 1 to 20;
final_degree : integer;
size_final_degree : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_s : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_r : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_v : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_u : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_s : out STD_LOGIC;
write_enable_r : out STD_LOGIC;
write_enable_v : out STD_LOGIC;
write_enable_u : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_s : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_v : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_r : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_u : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_value_s : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_r : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_v : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_u : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_s : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_r : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_v : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_u : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end component;
component inv_gf_2_m_pipeline
Generic(gf_2_m : integer range 1 to 20 := 13);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
flag : in STD_LOGIC;
clk : in STD_LOGIC;
oflag : out STD_LOGIC;
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component register_rst_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
signal polynomial_evaluator_syndrome_value_x : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_value_polynomial : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal polynomial_evaluator_syndrome_value_message : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal polynomial_evaluator_syndrome_value_h : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_mode_polynomial_syndrome : STD_LOGIC;
signal polynomial_evaluator_syndrome_rst : STD_LOGIC;
signal polynomial_evaluator_syndrome_computation_finalized : STD_LOGIC;
signal polynomial_evaluator_syndrome_address_value_polynomial : STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
signal polynomial_evaluator_syndrome_address_value_x : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_value_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_value_message : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_new_value_message : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_new_value_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_new_value_syndrome : STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
signal polynomial_evaluator_syndrome_address_value_error : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_write_enable_new_value_acc : STD_LOGIC;
signal polynomial_evaluator_syndrome_write_enable_new_value_syndrome : STD_LOGIC;
signal polynomial_evaluator_syndrome_write_enable_new_value_message : STD_LOGIC;
signal polynomial_evaluator_syndrome_write_enable_value_error : STD_LOGIC;
signal polynomial_evaluator_syndrome_new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal polynomial_evaluator_syndrome_new_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_new_value_message : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal polynomial_evaluator_syndrome_value_error : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal syndrome_finalized : STD_LOGIC;
signal solving_key_equation_rst : STD_LOGIC;
signal solving_key_equation_value_F : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_C : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_key_equation_found : STD_LOGIC;
signal solving_key_equation_write_enable_F : STD_LOGIC;
signal solving_key_equation_write_enable_G : STD_LOGIC;
signal solving_key_equation_write_enable_B : STD_LOGIC;
signal solving_key_equation_write_enable_C : STD_LOGIC;
signal solving_key_equation_new_value_F : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_C : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_address_value_F : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_C : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_F : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_C : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal inv_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal inv_flag : STD_LOGIC;
signal inv_oflag : STD_LOGIC;
signal inv_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
begin
polynomial_evaluator_syndrome : polynomial_syndrome_computing_n_v2
Generic Map(
number_of_pipelines => number_of_polynomial_evaluator_syndrome_pipelines,
pipeline_size => polynomial_evaluator_syndrome_pipeline_size,
size_pipeline_size => polynomial_evaluator_syndrome_size_pipeline_size,
gf_2_m => gf_2_m,
number_of_errors => number_of_errors,
size_number_of_errors => size_number_of_errors,
number_of_support_elements => length_codeword,
size_number_of_support_elements => size_codeword
)
Port Map(
value_x => polynomial_evaluator_syndrome_value_x,
value_acc => polynomial_evaluator_syndrome_value_acc,
value_polynomial => polynomial_evaluator_syndrome_value_polynomial,
value_message => polynomial_evaluator_syndrome_value_message,
value_h => polynomial_evaluator_syndrome_value_h,
mode_polynomial_syndrome => polynomial_evaluator_syndrome_mode_polynomial_syndrome,
clk => clk,
rst => polynomial_evaluator_syndrome_rst,
computation_finalized => polynomial_evaluator_syndrome_computation_finalized,
address_value_polynomial => polynomial_evaluator_syndrome_address_value_polynomial,
address_value_x => polynomial_evaluator_syndrome_address_value_x,
address_value_acc => polynomial_evaluator_syndrome_address_value_acc,
address_value_message => polynomial_evaluator_syndrome_address_value_message,
address_new_value_message => polynomial_evaluator_syndrome_address_new_value_message,
address_new_value_acc => polynomial_evaluator_syndrome_address_new_value_acc,
address_new_value_syndrome => polynomial_evaluator_syndrome_address_new_value_syndrome,
address_value_error => polynomial_evaluator_syndrome_address_value_error,
write_enable_new_value_acc => polynomial_evaluator_syndrome_write_enable_new_value_acc,
write_enable_new_value_syndrome => polynomial_evaluator_syndrome_write_enable_new_value_syndrome,
write_enable_new_value_message => polynomial_evaluator_syndrome_write_enable_new_value_message,
write_enable_value_error => polynomial_evaluator_syndrome_write_enable_value_error,
new_value_syndrome => polynomial_evaluator_syndrome_new_value_syndrome,
new_value_acc => polynomial_evaluator_syndrome_new_value_acc,
new_value_message => polynomial_evaluator_syndrome_new_value_message,
value_error => polynomial_evaluator_syndrome_value_error
);
solving_key_equation : solving_key_equation_5
Generic Map(
gf_2_m => gf_2_m,
final_degree => number_of_errors,
size_final_degree => size_number_of_errors
)
Port Map(
clk => clk,
rst => solving_key_equation_rst,
ready_inv => inv_oflag,
value_s => solving_key_equation_value_F,
value_r => solving_key_equation_value_G,
value_v => solving_key_equation_value_B,
value_u => solving_key_equation_value_C,
value_inv => inv_o,
signal_inv => inv_flag,
key_equation_found => solving_key_equation_key_equation_found,
write_enable_s => solving_key_equation_write_enable_F,
write_enable_r => solving_key_equation_write_enable_G,
write_enable_v => solving_key_equation_write_enable_B,
write_enable_u => solving_key_equation_write_enable_C,
new_value_inv => inv_a,
new_value_s => solving_key_equation_new_value_F,
new_value_v => solving_key_equation_new_value_B,
new_value_r => solving_key_equation_new_value_G,
new_value_u => solving_key_equation_new_value_C,
address_value_s => solving_key_equation_address_value_F,
address_value_r => solving_key_equation_address_value_G,
address_value_v => solving_key_equation_address_value_B,
address_value_u => solving_key_equation_address_value_C,
address_new_value_s => solving_key_equation_address_new_value_F,
address_new_value_r => solving_key_equation_address_new_value_G,
address_new_value_v => solving_key_equation_address_new_value_B,
address_new_value_u => solving_key_equation_address_new_value_C
);
inverter : inv_gf_2_m_pipeline
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => inv_a,
flag => inv_flag,
clk => clk,
oflag => inv_oflag,
o => inv_o
);
reg_syndrome_finalized : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => "1",
clk => clk,
ce => polynomial_evaluator_syndrome_computation_finalized,
rst => rst,
rst_value => "0",
q(0) => syndrome_finalized
);
polynomial_evaluator_syndrome_value_x <= value_L;
polynomial_evaluator_syndrome_value_acc <= value_sigma_evaluated;
polynomial_evaluator_syndrome_value_polynomial <= value_sigma;
polynomial_evaluator_syndrome_value_message <= value_codeword;
polynomial_evaluator_syndrome_value_h <= value_h;
polynomial_evaluator_syndrome_mode_polynomial_syndrome <= not syndrome_finalized;
polynomial_evaluator_syndrome_rst <= ( (rst) or (syndrome_finalized and (not solving_key_equation_key_equation_found)));
solving_key_equation_rst <= not syndrome_finalized;
solving_key_equation_value_G <= value_syndrome;
solving_key_equation_value_F <= value_s;
solving_key_equation_value_B <= value_v;
solving_key_equation_value_C <= value_sigma;
syndrome_generation_finalized <= syndrome_finalized or polynomial_evaluator_syndrome_computation_finalized;
key_equation_finalized <= solving_key_equation_key_equation_found;
decryption_finalized <= polynomial_evaluator_syndrome_computation_finalized and solving_key_equation_key_equation_found;
address_value_h <= polynomial_evaluator_syndrome_address_value_acc;
address_value_L <= polynomial_evaluator_syndrome_address_value_x;
address_value_syndrome <= solving_key_equation_address_value_G when syndrome_finalized = '1' else
"0" & polynomial_evaluator_syndrome_address_new_value_syndrome;
address_value_codeword <= polynomial_evaluator_syndrome_address_value_message;
address_value_s <= solving_key_equation_address_value_F;
address_value_v <= solving_key_equation_address_value_B;
address_value_sigma <= "00" & polynomial_evaluator_syndrome_address_value_polynomial when solving_key_equation_key_equation_found = '1' else
solving_key_equation_address_value_C;
address_value_sigma_evaluated <= polynomial_evaluator_syndrome_address_value_acc;
new_value_syndrome <= solving_key_equation_new_value_G when syndrome_finalized = '1' else
polynomial_evaluator_syndrome_new_value_syndrome;
new_value_s <= solving_key_equation_new_value_F;
new_value_v <= solving_key_equation_new_value_B;
new_value_sigma <= solving_key_equation_new_value_C;
new_value_message <= polynomial_evaluator_syndrome_new_value_message;
new_value_error <= polynomial_evaluator_syndrome_value_error;
new_value_sigma_evaluated <= polynomial_evaluator_syndrome_new_value_acc;
write_enable_new_value_syndrome <= solving_key_equation_write_enable_G when syndrome_finalized = '1' else
polynomial_evaluator_syndrome_write_enable_new_value_syndrome;
write_enable_new_value_s <= solving_key_equation_write_enable_F;
write_enable_new_value_v <= solving_key_equation_write_enable_B;
write_enable_new_value_sigma <= solving_key_equation_write_enable_C;
write_enable_new_value_message <= polynomial_evaluator_syndrome_write_enable_new_value_message;
write_enable_new_value_error <= polynomial_evaluator_syndrome_write_enable_value_error;
write_enable_new_value_sigma_evaluated <= polynomial_evaluator_syndrome_write_enable_new_value_acc;
address_new_value_syndrome <= solving_key_equation_address_new_value_G when syndrome_finalized = '1' else
"0" & polynomial_evaluator_syndrome_address_new_value_syndrome;
address_new_value_s <= solving_key_equation_address_new_value_F;
address_new_value_v <= solving_key_equation_address_new_value_B;
address_new_value_sigma <= solving_key_equation_address_new_value_C;
address_new_value_message <= polynomial_evaluator_syndrome_address_new_value_message;
address_new_value_error <= polynomial_evaluator_syndrome_address_value_error;
address_new_value_sigma_evaluated <= polynomial_evaluator_syndrome_address_new_value_acc;
end Behavioral;
|
bsd-2-clause
|
dad007dbd05c09c7d809d6f24fe00f21
| 0.721277 | 3.145167 | false | false | false | false |
jgibbard/fir_filter
|
mac_module.vhd
| 1 | 2,064 |
---------------------------------------------------------------------------
-- Project : FIR Filter
-- Author : James Gibbard ([email protected])
-- Date : 2017-03-25
-- File : mac_module.vhd
-- Module : mac_module
---------------------------------------------------------------------------
-- Description : Multiply accumulate unit.
-- Both multiply and sum results registered
---------------------------------------------------------------------------
-- Change Log
-- Version 0.0.1 : Initial version
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity mac_module is
generic (
--Max for Xilinx DSP48E1 slice is 25 x 18 multiply with 48bit accumulator
--Max for Cyclon/Arria V is 27 x 27 (or dual 18x19) multiply with 64bit accumulator
a_in_size : integer := 16;
b_in_size : integer := 16;
accumulator_size : integer := 48
);
port (
clk : in std_logic;
rst : in std_logic;
en_in : in std_logic;
a_in : in signed(a_in_size - 1 downto 0);
b_in : in signed(b_in_size - 1 downto 0);
accum_out : out signed(accumulator_size - 1 downto 0)
);
end mac_module;
architecture behavioural of mac_module is
signal accum : signed(accumulator_size - 1 downto 0);
signal multi_res : signed(a_in_size + b_in_size - 1 downto 0);
begin
mac_p : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
accum <= (others => '0');
multi_res <= (others => '0');
else
if en_in = '1' then
--Register multiply operation
multi_res <= a_in * b_in;
--Also register sum operation
accum <= accum + multi_res;
end if;
end if;
end if;
end process;
accum_out <= accum;
end behavioural;
|
unlicense
|
176d7cb26635167364f6ec792ccc314e
| 0.456395 | 4.273292 | false | false | false | false |
alainmarcel/Surelog
|
third_party/tests/ariane/fpga/src/apb_uart/src/uart_interrupt.vhd
| 5 | 4,147 |
--
-- UART interrupt control
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- History: 1.0 - Initial version
-- 1.1 - Automatic flow control
--
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART interrupt control
entity uart_interrupt is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
IER : in std_logic_vector(3 downto 0); -- IER 3:0
LSR : in std_logic_vector(4 downto 0); -- LSR 4:0
THI : in std_logic; -- Transmitter holding register empty interrupt
RDA : in std_logic; -- Receiver data available
CTI : in std_logic; -- Character timeout indication
AFE : in std_logic; -- Automatic flow control enable
MSR : in std_logic_vector(3 downto 0); -- MSR 3:0
IIR : out std_logic_vector(3 downto 0); -- IIR 3:0
INT : out std_logic -- Interrupt
);
end uart_interrupt;
architecture rtl of uart_interrupt is
-- Signals
signal iRLSInterrupt : std_logic; -- Receiver line status interrupt
signal iRDAInterrupt : std_logic; -- Received data available interrupt
signal iCTIInterrupt : std_logic; -- Character timeout indication interrupt
signal iTHRInterrupt : std_logic; -- Transmitter holding register empty interrupt
signal iMSRInterrupt : std_logic; -- Modem status interrupt
signal iIIR : std_logic_vector(3 downto 0); -- IIR register
begin
-- Priority 1: Receiver line status interrupt on: Overrun error, parity error, framing error or break interrupt
iRLSInterrupt <= IER(2) and (LSR(1) or LSR(2) or LSR(3) or LSR(4));
-- Priority 2: Received data available or trigger level reached in FIFO mode
iRDAInterrupt <= IER(0) and RDA;
-- Priority 2: Character timeout indication
iCTIInterrupt <= IER(0) and CTI;
-- Priority 3: Transmitter holding register empty
iTHRInterrupt <= IER(1) and THI;
-- Priority 4: Modem status interrupt: dCTS (when AFC is disabled), dDSR, TERI, dDCD
iMSRInterrupt <= IER(3) and ((MSR(0) and not AFE) or MSR(1) or MSR(2) or MSR(3));
-- IIR
IC_IIR: process (CLK, RST)
begin
if (RST = '1') then
iIIR <= "0001"; -- TODO: Invert later
elsif (CLK'event and CLK = '1') then
-- IIR register
if (iRLSInterrupt = '1') then
iIIR <= "0110";
elsif (iCTIInterrupt = '1') then
iIIR <= "1100";
elsif (iRDAInterrupt = '1') then
iIIR <= "0100";
elsif (iTHRInterrupt = '1') then
iIIR <= "0010";
elsif (iMSRInterrupt = '1') then
iIIR <= "0000";
else
iIIR <= "0001";
end if;
end if;
end process;
-- Outputs
IIR <= iIIR;
INT <= not iIIR(0);
end rtl;
|
apache-2.0
|
c94662db7b22c68b351245efb3c2b853
| 0.545213 | 4.46875 | false | false | false | false |
ruygargar/LCSE_lab
|
dma/dma.vhd
| 1 | 5,671 |
-------------------------------------------------------------------------------
-- Author: Aragonés Orellana, Silvia
-- García Garcia, Ruy
-- Project Name: PIC
-- Design Name: dma.vhd
-- Module Name: dma.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dma is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Databus : inout STD_LOGIC_VECTOR (7 downto 0);
Address : out STD_LOGIC_VECTOR (7 downto 0);
ChipSelect : out STD_LOGIC;
WriteEnable : out STD_LOGIC;
OutputEnable : out STD_LOGIC;
Send : in STD_LOGIC;
Ready : out STD_LOGIC;
DMA_RQ : out STD_LOGIC;
DMA_ACK : in STD_LOGIC;
TX_data : out STD_LOGIC_VECTOR (7 downto 0);
Valid_D : out STD_LOGIC;
Ack_out : in STD_LOGIC;
TX_RDY : in STD_LOGIC;
RCVD_data : in STD_LOGIC_VECTOR (7 downto 0);
Data_read : out STD_LOGIC;
RX_Full : in STD_LOGIC;
RX_empty : in STD_LOGIC);
end dma;
architecture Behavioral of dma is
-- Declaración del componente Controlador de Bus.
COMPONENT dma_bus_controller
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
Send : IN std_logic;
DMA_ACK : IN std_logic;
RX_empty : IN std_logic;
RX_Databus : IN std_logic_vector(7 downto 0);
RX_Address : IN std_logic_vector(7 downto 0);
RX_ChipSelect : IN std_logic;
RX_WriteEnable : IN std_logic;
RX_OutputEnable : IN std_logic;
RX_end : IN std_logic;
TX_Address : IN std_logic_vector(7 downto 0);
TX_ChipSelect : IN std_logic;
TX_WriteEnable : IN std_logic;
TX_OutputEnable : IN std_logic;
TX_ready : IN std_logic;
TX_end : IN std_logic;
Databus : INOUT std_logic_vector(7 downto 0);
Address : OUT std_logic_vector(7 downto 0);
ChipSelect : OUT std_logic;
WriteEnable : OUT std_logic;
OutputEnable : OUT std_logic;
Ready : OUT std_logic;
DMA_RQ : OUT std_logic;
RX_start : OUT std_logic;
TX_Databus : OUT std_logic_vector(7 downto 0);
TX_start : OUT std_logic
);
END COMPONENT;
-- Declaración del componente Transmisor.
COMPONENT dma_tx
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
Databus : IN std_logic_vector(7 downto 0);
Start_TX : IN std_logic;
Ack_DO : IN std_logic;
Address : OUT std_logic_vector(7 downto 0);
ChipSelect : OUT std_logic;
WriteEnable : OUT std_logic;
OutputEnable : OUT std_logic;
Ready_TX : OUT std_logic;
End_TX : OUT std_logic;
DataOut : OUT std_logic_vector(7 downto 0);
Valid_DO : OUT std_logic
);
END COMPONENT;
-- Declaración del componente Receptor.
COMPONENT dma_rx
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
Start_RX : IN std_logic;
DataIn : IN std_logic_vector(7 downto 0);
Empty : IN std_logic;
Databus : OUT std_logic_vector(7 downto 0);
Address : OUT std_logic_vector(7 downto 0);
ChipSelect : OUT std_logic;
WriteEnable : OUT std_logic;
OutputEnable : OUT std_logic;
End_RX : OUT std_logic;
Read_DI : OUT std_logic
);
END COMPONENT;
-- Buses y señales internas, procedentes del Transmisor, empleadas para la
-- interconexión entre el subsistema Transmisor y el Controlador de bus.
signal TX_Databus_i : std_logic_vector(7 downto 0);
signal TX_Address_i : std_logic_vector(7 downto 0);
signal TX_ChipSelect_i : std_logic;
signal TX_WriteEnable_i : std_logic;
signal TX_OutputEnable_i : std_logic;
signal TX_start_i : std_logic;
signal TX_ready_i : std_logic;
signal TX_end_i : std_logic;
-- Buses y señales internas, procedentes del Receptor, empleadas para la
-- interconexión entre el subsistema Receptor y el Controlador de bus.
signal RX_Databus_i : std_logic_vector(7 downto 0);
signal RX_Address_i : std_logic_vector(7 downto 0);
signal RX_ChipSelect_i : std_logic;
signal RX_WriteEnable_i : std_logic;
signal RX_OutputEnable_i : std_logic;
signal RX_start_i : std_logic;
signal RX_end_i : std_logic;
begin
-- Instancia del Controlador de Bus.
bus_controller: dma_bus_controller PORT MAP(
Clk => Clk,
Reset => Reset,
Databus => Databus,
Address => Address,
ChipSelect => ChipSelect,
WriteEnable => WriteEnable,
OutputEnable => OutputEnable,
Send => Send,
Ready => Ready,
DMA_RQ => DMA_RQ,
DMA_ACK => DMA_ACK,
RX_empty => RX_empty,
RX_Databus => RX_Databus_i,
RX_Address => RX_Address_i,
RX_ChipSelect => RX_ChipSelect_i,
RX_WriteEnable => RX_WriteEnable_i,
RX_OutputEnable => RX_OutputEnable_i,
RX_start => RX_start_i,
RX_end => RX_end_i,
TX_Databus => TX_Databus_i,
TX_Address => TX_Address_i,
TX_ChipSelect => TX_ChipSelect_i,
TX_WriteEnable => TX_WriteEnable_i,
TX_OutputEnable => TX_OutputEnable_i,
TX_start => TX_start_i,
TX_ready => TX_ready_i,
TX_end => TX_end_i
);
-- Instancia del Transmisor.
tx: dma_tx PORT MAP(
Clk => Clk,
Reset => Reset,
Databus => TX_Databus_i,
Address => TX_Address_i,
ChipSelect => TX_ChipSelect_i,
WriteEnable => TX_WriteEnable_i,
OutputEnable => TX_OutputEnable_i,
Start_TX => TX_start_i,
Ready_TX => TX_ready_i,
End_TX => TX_end_i,
DataOut => TX_data,
Valid_DO => Valid_D,
Ack_DO => Ack_out
);
-- Instancia del Receptor.
rx: dma_rx PORT MAP(
Clk => Clk,
Reset => Reset,
Databus => RX_Databus_i,
Address => RX_Address_i,
ChipSelect => RX_ChipSelect_i,
WriteEnable => RX_WriteEnable_i,
OutputEnable => RX_OutputEnable_i,
Start_RX => RX_start_i,
End_RX => RX_end_i,
DataIn => RCVD_data,
Read_DI => Data_read,
Empty => RX_empty
);
end Behavioral;
|
gpl-3.0
|
cd14e20259249dedbef742ca2dad3375
| 0.627403 | 3.077048 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/counter_increment_decrement_rst_nbits.vhd
| 1 | 2,225 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_increment_decrement_rst_n_bits
-- Module Name: Counter_increment_decrement_rst_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Counter of size bits with reset signal, that can increment or decrements
-- when ce equals to 1.
-- The reset is synchronous and the value loaded during reset is defined by reset_value.
--
-- The circuits parameters
--
-- size :
--
-- The size of the counter in bits.
--
-- increment_value :
--
-- The amount will be incremented each cycle, when increment_decrement = 0.
--
-- decrement_value :
--
-- The amount will be decremented each cycle, when increment_decrement = 1.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_increment_decrement_rst_nbits is
Generic(
size : integer;
increment_value : integer;
decrement_value : integer
);
Port(
clk : in STD_LOGIC;
ce : in STD_LOGIC;
increment_decrement : STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end counter_increment_decrement_rst_nbits;
architecture Behavioral of counter_increment_decrement_rst_nbits is
signal internal_value : unsigned((size - 1) downto 0);
begin
process(clk, ce, increment_decrement, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= unsigned(rst_value);
elsif(ce = '1') then
if(increment_decrement = '1') then
internal_value <= internal_value - to_unsigned(decrement_value, internal_value'Length);
else
internal_value <= internal_value + to_unsigned(increment_value, internal_value'Length);
end if;
else
null;
end if;
end if;
end process;
q <= std_logic_vector(internal_value);
end Behavioral;
|
bsd-2-clause
|
32c08bdba394d47f3ebf35b46db92100
| 0.642247 | 3.52057 | false | false | false | false |
rajvinjamuri/ECE385_VHDL
|
paddle.vhd
| 1 | 4,941 |
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Paddle.vhd (Ball.vhd) --
-- --
-- Modeled off ball.vhd version by Stephen Kempf and Viral Mehta --
-- --
-- by Raj Vinjamuri and Sai Koppula --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
---------------------------------------------------------------------------
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity paddle is
Port ( Up, Do, Le, Ri : in std_logic; --added direction signals to modify direction
Reset : in std_logic;
frame_clk : in std_logic;
PaddleX : out std_logic_vector(10 downto 0);
PaddleY : out std_logic_vector(10 downto 0);
PaddleS : out std_logic_vector(10 downto 0));
end paddle;
architecture Behavioral of paddle is
signal U, D, L, R : std_logic_vector (0 downto 0); --added signals to use for math needed to change motion vars
signal Paddle_X_Pos, Paddle_Y_Pos, Paddle_Y_motion, Paddle_X_motion : std_logic_vector(10 downto 0);
signal Paddle_Size : std_logic_vector(10 downto 0);
constant Paddle_X_Start : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(320, 11); --Center position on the X axis
constant Paddle_Y_Start : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(460, 11); --Center position on the Y axis
constant Paddle_X_Min : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(0, 11); --Leftmost point on the X axis
constant Paddle_X_Max : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(639, 11); --Rightmost point on the X axis
constant Paddle_Y_Min : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(0, 11); --Topmost point on the Y axis
constant Paddle_Y_Max : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(479, 11); --Bottommost point on the Y axis
constant Paddle_X_Step : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(1, 11); --Step size on the X axis (modified)
constant Paddle_Y_Step : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(1, 11); --Step size on the Y axis
begin
Paddle_Size <= CONV_STD_LOGIC_VECTOR(4, 11); -- assigns the value 4 as a 10-digit binary number, ie "0000000100"
U(0) <= Up; --set internal signal/vars
D(0) <= Do;
L(0) <= Le;
R(0) <= Ri;
Move_Paddle: process(Reset, frame_clk, Paddle_Size)
begin
if(Reset = '1') then --Asynchronous Reset
Paddle_Y_motion <= "00000000000"; --all the initial movement settings
Paddle_X_motion <= "00000000000";
Paddle_Y_Pos <= Paddle_Y_Start;
Paddle_X_Pos <= Paddle_X_Start;
elsif(rising_edge(frame_clk)) then
if ((R(0) or L(0)) = '1') then --see notes on up/down/y-direction
if (R(0) = '1')then
Paddle_X_Pos <= Paddle_X_Pos + "00000000011"; --Verify this works.
if (Paddle_X_Pos + ("00000000110"*Paddle_size) >= Paddle_X_Max) then
Paddle_X_Pos <= Paddle_X_Max - (Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size);
end if;
elsif (L(0) = '1') then
Paddle_X_Pos <= Paddle_X_Pos - "00000000011"; --Verify this works. update: this KINDA works
if (Paddle_X_Pos - ("00000000110"*Paddle_size) <= Paddle_X_Min ) then --change here to fix going off screen
Paddle_X_Pos <= Paddle_X_Min + (Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size);--Paddle_X_Min + (Paddle_Size + Paddle_Size);
end if;
--Paddle_X_Pos <= Paddle_X_Pos + "1111111101"; --Verify this works. update: this KINDA works
else Paddle_X_Pos <= Paddle_X_Pos;
end if;
end if;
--if (Paddle_X_Pos - ("00000000110"*Paddle_size) <= Paddle_X_Min + ("00000000110"*Paddle_size)) then --change here to fix going off screen
--Paddle_X_Pos <= Paddle_X_Min + (Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size);--Paddle_X_Min + (Paddle_Size + Paddle_Size);
-- if (Paddle_X_Pos + ("00000000110"*Paddle_size) >= Paddle_X_Max - ("00000000110"*Paddle_size)) then
--Paddle_X_Pos <= Paddle_X_Max - (Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size + Paddle_Size); --if this were real I would take a steaming poop on it
--cant get this to work. Keeps showing up on the other side
--end if;
--Ball_Y_pos <= Ball_Y_pos + Ball_Y_Motion; -- Update ball position
--Ball_X_pos <= Ball_X_pos + Ball_X_Motion;
end if;
end process Move_Paddle;
PaddleX <= Paddle_X_Pos;
PaddleY <= Paddle_Y_Start;
PaddleS <= Paddle_Size;
end Behavioral;
|
mit
|
87b4a85d1fa1f28e1b00a1a6957e505b
| 0.592997 | 3.393544 | false | false | false | false |
laurivosandi/hdl
|
arithmetic/src/moving_average_filter.vhd
| 1 | 4,124 |
library ieee;
use ieee.std_logic_1164.all;
entity moving_average_filter is
port (
sin : in std_logic_vector (10 downto 0);
clk : in std_logic;
sout : out std_logic_vector (10 downto 0);
rst : in std_logic
);
end moving_average_filter;
architecture behavioral of moving_average_filter is
-- Registers
type tregisters is array (0 to 15) of std_logic_vector(14 downto 0);
signal r : tregisters;
-- Padded input value
signal first : std_logic_vector(14 downto 0);
-- First stage
signal s11 : std_logic_vector(14 downto 0);
signal s12 : std_logic_vector(14 downto 0);
signal s13 : std_logic_vector(14 downto 0);
signal s14 : std_logic_vector(14 downto 0);
signal c11 : std_logic_vector(14 downto 0);
signal c12 : std_logic_vector(14 downto 0);
signal c13 : std_logic_vector(14 downto 0);
signal c14 : std_logic_vector(14 downto 0);
-- Second stage
signal s21 : std_logic_vector(14 downto 0);
signal s22 : std_logic_vector(14 downto 0);
signal c21 : std_logic_vector(14 downto 0);
signal c22 : std_logic_vector(14 downto 0);
signal s22s : std_logic_vector(14 downto 0);
signal c21s : std_logic_vector(14 downto 0);
signal c22s : std_logic_vector(14 downto 0);
-- Third stage
signal s3 : std_logic_vector(14 downto 0);
signal c3 : std_logic_vector(14 downto 0);
signal c3s : std_logic_vector(14 downto 0);
-- Final sum
signal s : std_logic_vector(14 downto 0);
signal c : std_logic_vector(15 downto 0);
component counter42 is
Port ( a : in std_logic_vector (14 downto 0);
b : in std_logic_vector (14 downto 0);
c : in std_logic_vector (14 downto 0);
d : in std_logic_vector (14 downto 0);
s : out std_logic_vector (14 downto 0);
co : out std_logic_vector (14 downto 0));
end component;
component carry_lookahead_adder is
Port ( a : in std_logic_vector (14 downto 0);
b : in std_logic_vector (14 downto 0);
ci : in std_logic;
s : out std_logic_vector (14 downto 0);
co : out std_logic);
end component;
begin
process (sin, clk)
begin
if rst = '1' then
-- Reset register
for i in 0 to 15 loop
r(i) <= "000000000000000";
end loop;
elsif rising_edge(clk) then
-- Shift operands
for i in 15 downto 1 loop
r(i) <= r(i-1);
end loop;
-- Store first operand
r(0) <= first;
end if;
end process;
-- Sign extension
sign_extension_loop: for i in 14 downto 11 generate
first(i) <= sin(10);
end generate;
-- Connect lower 11-bits
input_loop: for i in 10 downto 0 generate
first(i) <= sin(i);
end generate;
-- First stage
stg11: counter42 port map(a=>first, b=>r( 0), c=>r( 1), d=>r( 2), s=>s11, co=>c11);
stg12: counter42 port map(a=>r( 3), b=>r( 4), c=>r( 5), d=>r( 6), s=>s12, co=>c12);
stg13: counter42 port map(a=>r( 7), b=>r( 8), c=>r( 9), d=>r(10), s=>s13, co=>c13);
stg14: counter42 port map(a=>r(11), b=>r(12), c=>r(13), d=>r(14), s=>s14, co=>c14);
-- Second stage: Sum shifted carries & sums
stg21: counter42 port map(a=>s11, b=>s12, c=>s13, d=>s14, s => s21, co => c21);
stg22: counter42 port map(a=>c11, b=>c12, c=>c13, d=>c14, s => s22, co => c22);
s22s <= s22(13 downto 0) & "0"; -- s22 is shifted by 1
c21s <= c21(13 downto 0) & "0"; -- c21 is shifted by 1
c22s <= c22(12 downto 0) & "00"; -- c22 is shifted by 2
-- Third stage
stg3: counter42 port map(a=>s21, b=>s22s, c=>c21s, d=>c22s, s=>s3, co => c3);
c3s <= c3(13 downto 0) & "0"; -- c3 is shifted by 1
-- Final addition
stg4: carry_lookahead_adder port map(a=>s3, b=>c3s, ci=>'0', s=>s);
-- Write output
division_loop: for i in 10 downto 0 generate
sout(i) <= s(i+4);
end generate;
end Behavioral;
|
mit
|
e728b0a4be0438f494f2391767b385af
| 0.563773 | 3.194423 | false | false | false | false |
pwuertz/digitizer2fw
|
src/rtl/slow_cdc.vhdl
| 1 | 1,650 |
-------------------------------------------------------------------------------
-- Clock domain crossing circuit for slowly changing signals
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity slow_cdc_bit is
port (
clk: in std_logic;
din: in std_logic;
dout: out std_logic
);
end slow_cdc_bit;
library ieee;
use ieee.std_logic_1164.all;
entity slow_cdc_bits is
port (
clk: in std_logic;
din: in std_logic_vector;
dout: out std_logic_vector
);
end slow_cdc_bits;
---
architecture slow_cdc_bit_arch of slow_cdc_bit is
signal d_async: std_logic := '0';
signal d_meta: std_logic := '0';
signal d_sync: std_logic := '0';
attribute ASYNC_REG : string;
attribute ASYNC_REG of d_async : signal is "TRUE";
attribute ASYNC_REG of d_meta : signal is "TRUE";
attribute ASYNC_REG of d_sync : signal is "TRUE";
begin
d_async <= din;
process(clk)
begin
if rising_edge(clk) then
d_meta <= d_async;
d_sync <= d_meta;
end if;
end process;
dout <= d_sync;
end slow_cdc_bit_arch;
architecture slow_cdc_bits_arch of slow_cdc_bits is
begin
gen: for I in din'low to din'high generate
sync_bit : entity work.slow_cdc_bit
port map (
clk => clk,
din => din(I),
dout => dout(I)
);
end generate;
end slow_cdc_bits_arch;
|
gpl-3.0
|
fab4b1826d8c2118825a0c7b7b2187d1
| 0.574287 | 3.584783 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
USB_TEST/PLL.vhd
| 1 | 21,007 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: PLL.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY PLL IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END PLL;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire9_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire9_bv(0 DOWNTO 0) <= "0";
sub_wire9 <= To_stdlogicvector(sub_wire9_bv);
sub_wire6 <= sub_wire0(4);
sub_wire5 <= sub_wire0(2);
sub_wire4 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
locked <= sub_wire3;
c0 <= sub_wire4;
c2 <= sub_wire5;
c4 <= sub_wire6;
sub_wire7 <= inclk0;
sub_wire8 <= sub_wire9(0 DOWNTO 0) & sub_wire7;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 5,
clk0_duty_cycle => 50,
clk0_multiply_by => 4,
clk0_phase_shift => "0",
clk1_divide_by => 5,
clk1_duty_cycle => 50,
clk1_multiply_by => 4,
clk1_phase_shift => "6250",
clk2_divide_by => 5,
clk2_duty_cycle => 50,
clk2_multiply_by => 4,
clk2_phase_shift => "12500",
clk3_divide_by => 5,
clk3_duty_cycle => 50,
clk3_multiply_by => 4,
clk3_phase_shift => "18750",
clk4_divide_by => 5,
clk4_duty_cycle => 50,
clk4_multiply_by => 16,
clk4_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=PLL",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_USED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire8,
clk => sub_wire0,
locked => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "40.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "40.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "160.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "40.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "40.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "160.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "90.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "270.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "6250"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "12500"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "18750"
-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
gpl-2.0
|
420180169373dff383f70d1cd0009c4e
| 0.700386 | 3.245828 | false | false | false | false |
achan1989/In64
|
FPGA/SD_card_test.srcs/sources_1/ip/mig_v3_92_0/ATLYS_DDR/user_design/sim/memc3_tb_top.vhd
| 2 | 29,443 |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end memc3_tb_top;
architecture arc of memc3_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p0_DWIDTH : integer := 32;
constant p2_DWIDTH : integer := 32;
constant p0_PORT_MODE : string := "BI_MODE";
constant p2_PORT_MODE : string := "RD_MODE";
--p0 Signal declarations
signal p0_tg_run_traffic : std_logic;
signal p0_tg_start_addr : std_logic_vector(31 downto 0);
signal p0_tg_end_addr : std_logic_vector(31 downto 0);
signal p0_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p0_tg_data_seed : std_logic_vector(31 downto 0);
signal p0_tg_load_seed : std_logic;
signal p0_tg_addr_mode : std_logic_vector(2 downto 0);
signal p0_tg_instr_mode : std_logic_vector(3 downto 0);
signal p0_tg_bl_mode : std_logic_vector(1 downto 0);
signal p0_tg_data_mode : std_logic_vector(3 downto 0);
signal p0_tg_mode_load : std_logic;
signal p0_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p0_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p0_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p0_error_status : std_logic_vector(64 + (2*p0_DWIDTH - 1) downto 0);
signal p0_error : std_logic;
signal p0_cmp_error : std_logic;
signal p0_cmp_data : std_logic_vector(p0_DWIDTH-1 downto 0);
signal p0_cmp_data_valid : std_logic;
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p0_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p2 Signal declarations
signal p2_tg_run_traffic : std_logic;
signal p2_tg_start_addr : std_logic_vector(31 downto 0);
signal p2_tg_end_addr : std_logic_vector(31 downto 0);
signal p2_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p2_tg_data_seed : std_logic_vector(31 downto 0);
signal p2_tg_load_seed : std_logic;
signal p2_tg_addr_mode : std_logic_vector(2 downto 0);
signal p2_tg_instr_mode : std_logic_vector(3 downto 0);
signal p2_tg_bl_mode : std_logic_vector(1 downto 0);
signal p2_tg_data_mode : std_logic_vector(3 downto 0);
signal p2_tg_mode_load : std_logic;
signal p2_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p2_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p2_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p2_error_status : std_logic_vector(64 + (2*p2_DWIDTH - 1) downto 0);
signal p2_error : std_logic;
signal p2_cmp_error : std_logic;
signal p2_cmp_data : std_logic_vector(p2_DWIDTH-1 downto 0);
signal p2_cmp_data_valid : std_logic;
signal p2_mcb_cmd_en_o_int : std_logic;
signal p2_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p2_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p2_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p2_mcb_wr_en_o_int : std_logic;
signal p2_mcb_wr_en_o : std_logic;
signal p2_mcb_wr_full_i : std_logic;
signal p2_mcb_wr_data_o : std_logic_vector(31 downto 0);
signal p2_mcb_wr_mask_o : std_logic_vector(3 downto 0);
signal p2_mcb_wr_fifo_counts : std_logic_vector(6 downto 0);
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p0_cmp_error or p2_cmp_error;
error <= p0_error or p2_error;
error_status <= p0_error_status;
cmp_data <= p0_cmp_data(31 downto 0);
cmp_data_valid <= p0_cmp_data_valid;
p0_mcb_cmd_en_o <= p0_mcb_cmd_en_o_int;
p0_mcb_cmd_instr_o <= p0_mcb_cmd_instr_o_int;
p0_mcb_cmd_bl_o <= p0_mcb_cmd_bl_o_int;
p0_mcb_cmd_addr_o <= p0_mcb_cmd_addr_o_int;
p0_mcb_wr_en_o <= p0_mcb_wr_en_o_int;
init_mem_pattern_ctr_p0 :init_mem_pattern_ctr
generic map
(
DWIDTH => p0_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS,
END_ADDRESS => C_p0_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p0_DATA_MODE,
PORT_MODE => p0_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int,
mcb_wr_en_i => p0_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p0_error,
run_traffic_o => p0_tg_run_traffic,
start_addr_o => p0_tg_start_addr,
end_addr_o => p0_tg_end_addr ,
cmd_seed_o => p0_tg_cmd_seed ,
data_seed_o => p0_tg_data_seed ,
load_seed_o => p0_tg_load_seed ,
addr_mode_o => p0_tg_addr_mode ,
instr_mode_o => p0_tg_instr_mode ,
bl_mode_o => p0_tg_bl_mode ,
data_mode_o => p0_tg_data_mode ,
mode_load_o => p0_tg_mode_load ,
fixed_bl_o => p0_tg_fixed_bl ,
fixed_instr_o => p0_tg_fixed_instr,
fixed_addr_o => p0_tg_fixed_addr
);
m_traffic_gen_p0 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p0_PORT_MODE,
DWIDTH => p0_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p0_BEGIN_ADDRESS,
PRBS_EADDR => C_p0_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p0_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p0_tg_start_addr ,
end_addr_i => p0_tg_end_addr ,
cmd_seed_i => p0_tg_cmd_seed ,
data_seed_i => p0_tg_data_seed ,
load_seed_i => p0_tg_load_seed,
addr_mode_i => p0_tg_addr_mode,
instr_mode_i => p0_tg_instr_mode ,
bl_mode_i => p0_tg_bl_mode ,
data_mode_i => p0_tg_data_mode ,
mode_load_i => p0_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p0_tg_fixed_bl,
fixed_instr_i => p0_tg_fixed_instr,
fixed_addr_i => p0_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p0_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p0_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p0_mcb_cmd_full_i,
mcb_wr_en_o => p0_mcb_wr_en_o_int,
mcb_wr_mask_o => p0_mcb_wr_mask_o,
mcb_wr_data_o => p0_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p0_mcb_wr_full_i,
mcb_wr_fifo_counts => p0_mcb_wr_fifo_counts,
mcb_rd_en_o => p0_mcb_rd_en_o,
mcb_rd_data_i => p0_mcb_rd_data_i,
mcb_rd_empty_i => p0_mcb_rd_empty_i,
mcb_rd_fifo_counts => p0_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p0_cmp_data,
cmp_data_valid => p0_cmp_data_valid,
cmp_error => p0_cmp_error,
error => p0_error,
error_status => p0_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p2_mcb_cmd_en_o <= p2_mcb_cmd_en_o_int;
p2_mcb_cmd_instr_o <= p2_mcb_cmd_instr_o_int;
p2_mcb_cmd_bl_o <= p2_mcb_cmd_bl_o_int;
p2_mcb_cmd_addr_o <= p2_mcb_cmd_addr_o_int;
p2_mcb_wr_en_o <= p2_mcb_wr_en_o_int;
init_mem_pattern_ctr_p2 :init_mem_pattern_ctr
generic map
(
DWIDTH => p2_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS,
END_ADDRESS => C_p0_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p0_DATA_MODE,
PORT_MODE => p2_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int,
mcb_wr_en_i => p0_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p2_error,
run_traffic_o => p2_tg_run_traffic,
start_addr_o => p2_tg_start_addr,
end_addr_o => p2_tg_end_addr ,
cmd_seed_o => p2_tg_cmd_seed ,
data_seed_o => p2_tg_data_seed ,
load_seed_o => p2_tg_load_seed ,
addr_mode_o => p2_tg_addr_mode ,
instr_mode_o => p2_tg_instr_mode ,
bl_mode_o => p2_tg_bl_mode ,
data_mode_o => p2_tg_data_mode ,
mode_load_o => p2_tg_mode_load ,
fixed_bl_o => p2_tg_fixed_bl ,
fixed_instr_o => p2_tg_fixed_instr,
fixed_addr_o => p2_tg_fixed_addr
);
m_traffic_gen_p2 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p2_PORT_MODE,
DWIDTH => p2_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p0_BEGIN_ADDRESS,
PRBS_EADDR => C_p0_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p2_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p2_tg_start_addr ,
end_addr_i => p2_tg_end_addr ,
cmd_seed_i => p2_tg_cmd_seed ,
data_seed_i => p2_tg_data_seed ,
load_seed_i => p2_tg_load_seed,
addr_mode_i => p2_tg_addr_mode,
instr_mode_i => p2_tg_instr_mode ,
bl_mode_i => p2_tg_bl_mode ,
data_mode_i => p2_tg_data_mode ,
mode_load_i => p2_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p2_tg_fixed_bl,
fixed_instr_i => p2_tg_fixed_instr,
fixed_addr_i => p2_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p2_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p2_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p2_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p2_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p2_mcb_cmd_full_i,
mcb_wr_en_o => p2_mcb_wr_en_o_int,
mcb_wr_mask_o => p2_mcb_wr_mask_o,
mcb_wr_data_o => p2_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p2_mcb_wr_full_i,
mcb_wr_fifo_counts => p2_mcb_wr_fifo_counts,
mcb_rd_en_o => p2_mcb_rd_en_o,
mcb_rd_data_i => p2_mcb_rd_data_i,
mcb_rd_empty_i => p2_mcb_rd_empty_i,
mcb_rd_fifo_counts => p2_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p2_cmp_data,
cmp_data_valid => p2_cmp_data_valid,
cmp_error => p2_cmp_error,
error => p2_error,
error_status => p2_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
|
lgpl-3.0
|
4c52426b7329dad5efefa48a7436dc53
| 0.499236 | 3.299305 | false | false | false | false |
ruygargar/LCSE_lab
|
peripherics/tb_peripherics.vhd
| 1 | 6,992 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04:24:24 01/12/2014
-- Design Name:
-- Module Name: C:/Users/Ruy/Desktop/LCSE_lab/peripherics/tb_peripherics.vhd
-- Project Name: peripherics
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: peripherics
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.PIC_pkg.all;
use work.RS232_test.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_peripherics IS
END tb_peripherics;
ARCHITECTURE behavior OF tb_peripherics IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT peripherics
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
TX : OUT std_logic;
RX : IN std_logic;
Databus : INOUT std_logic_vector(7 downto 0);
Address : INOUT std_logic_vector(7 downto 0);
ChipSelect : INOUT std_logic;
WriteEnable : INOUT std_logic;
OutputEnable : INOUT std_logic;
Send : IN std_logic;
Ready : OUT std_logic;
DMA_RQ : OUT std_logic;
DMA_ACK : IN std_logic;
Switches : OUT std_logic_vector(7 downto 0);
Temp_L : OUT std_logic_vector(6 downto 0);
Temp_H : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal RX : std_logic := '1';
signal Send : std_logic := '0';
signal DMA_ACK : std_logic := '0';
--BiDirs
signal Databus : std_logic_vector(7 downto 0) := (others => 'Z');
signal Address : std_logic_vector(7 downto 0) := (others => 'Z');
signal ChipSelect : std_logic := 'Z';
signal WriteEnable : std_logic := 'Z';
signal OutputEnable : std_logic := 'Z';
--Outputs
signal TX : std_logic;
signal Ready : std_logic;
signal DMA_RQ : std_logic;
signal Switches : std_logic_vector(7 downto 0);
signal Temp_L : std_logic_vector(6 downto 0);
signal Temp_H : std_logic_vector(6 downto 0);
-- Clock period definitions
constant Clk_period : time := 25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: peripherics PORT MAP (
Clk => Clk,
Reset => Reset,
TX => TX,
RX => RX,
Databus => Databus,
Address => Address,
ChipSelect => ChipSelect,
WriteEnable => WriteEnable,
OutputEnable => OutputEnable,
Send => Send,
Ready => Ready,
DMA_RQ => DMA_RQ,
DMA_ACK => DMA_ACK,
Switches => Switches,
Temp_L => Temp_L,
Temp_H => Temp_H
);
-- Clock process definitions
Clk <= not Clk after Clk_period;
Reset <= '1' after 100 ns;
Databus <= X"55" after 102 ns, X"AA" after 127 ns, -- Write TX Buffers
X"00" after 177 ns, -- Send handshake
(others => 'Z') after 227 ns, -- Free bus (Send)
X"00" after 377 ns, -- Catch bus again
(others => 'Z') after 89977 ns, -- Free bus (1º DMA_ACK)
X"00" after 90127 ns, -- Catch bus again
(others => 'Z') after 256627 ns, -- Free bus (2º DMA_ACK)
X"00" after 256827 ns, -- Catch bus
X"00" after 300027 ns, -- Clean NEW_INST flag
X"00" after 300077 ns, -- Catch bus
(others => 'Z') after 610027 ns, -- Free bus (3º DMA_ACK)
X"00" after 610477 ns; -- Catch bus
Address <= DMA_TX_BUFFER_MSB after 102 ns, DMA_TX_BUFFER_LSB after 127 ns, -- Write TX Buffers
X"FF" after 177 ns, -- Send handshake
(others => 'Z') after 227 ns, -- Free bus (Send)
X"FF" after 377 ns, -- Catch bus again
(others => 'Z') after 89977 ns, -- Free bus (1º DMA_ACK)
X"FF" after 90127 ns, -- Catch bus
(others => 'Z') after 256627 ns, -- Free bus (2º DMA_ACK)
X"FF" after 256827 ns, -- Catch bus
NEW_INST after 300027 ns, -- Clean NEW_INST flag
X"FF" after 300077 ns, -- Catch bus
(others => 'Z') after 610027 ns, -- Free bus (3º DMA_ACK)
X"FF" after 610477 ns; -- Catch bus
ChipSelect <= '1' after 102 ns, '0' after 177 ns, -- Write TX Buffers
'Z' after 227 ns, -- Free bus (Send)
'0' after 377 ns, -- Catch bus again
'Z' after 89977 ns, -- Free bus (1º DMA_ACK)
'0' after 90127 ns, -- Catch bus again
'Z' after 256627 ns, -- Free bus (2º DMA_ACK)
'0' after 256827 ns, -- Catch bus again
'1' after 300027 ns, -- Clean NEW_INST flag
'0' after 300077 ns, -- Catch bus again
'Z' after 610027 ns, -- Free bus (3º DMA_ACK)
'0' after 610477 ns; -- Catch bus again
WriteEnable <= '1' after 102 ns, '0' after 177 ns, -- Write TX Buffers
'Z' after 227 ns, -- Free bus (Send)
'0' after 377 ns, -- Catch bus again
'Z' after 89977 ns, -- Free bus (1º DMA_ACK)
'0' after 90127 ns, -- Catch bus again
'Z' after 256627 ns, -- Free bus (2º DMA_ACK)
'0' after 256827 ns, -- Catch bus again
'1' after 300027 ns, -- Clean NEW_INST flag
'0' after 300077 ns, -- Catch bus again
'Z' after 610027 ns, -- Free bus
'0' after 610477 ns; -- Catch bus again
OutputEnable <= '0' after 102 ns, -- Write TX Buffers
'Z' after 227 ns, -- Free bus (Send)
'0' after 377 ns, -- Catch bus again
'Z' after 89977 ns, -- Free bus (1º DMA_ACK)
'0' after 90127 ns, -- Catch bus again
'Z' after 256627 ns, -- Free bus (2º DMA_ACK)
'0' after 256827 ns, -- Catch bus again
'0' after 300027 ns, -- Clean NEW_INST flag
'0' after 300077 ns, -- Catch bus again
'Z' after 610027 ns, -- Free bus (3º DMA_ACK)
'0' after 610477 ns; -- Catch bus again
Send <= '1' after 177 ns, '0' after 327 ns; -- Send handshake
DMA_ACK <= '1' after 89927 ns, '0' after 90077 ns, -- 1º DMA-ACK handshake
'1' after 256577 ns, '0' after 256777 ns, -- 2º DMA-ACK handshake
'1' after 609977 ns, '0' after 610427 ns; -- 3º DMA-ACK handshake
-- Stimulus process
RX_process: process -- Data received from RS232 RX
begin
wait for 200 ns;
Transmit(RX, X"01");
Transmit(RX, X"02");
Transmit(RX, X"03");
Transmit(RX, X"04");
Transmit(RX, X"05");
Transmit(RX, X"06");
Transmit(RX, X"07");
wait;
end process;
END;
|
gpl-3.0
|
ea9e1b86fbe71f1bdd2f7a1c5e8ea7d8
| 0.577946 | 3.412396 | false | false | false | false |
rodrigoazs/-7-5-Reed-Solomon
|
code/read_file.vhd
| 1 | 1,412 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity read_file is
Port (Clock: in std_logic;
Qout: out std_logic_vector(2 downto 0)
);
end read_file;
architecture Behavioral of read_file is
signal bin_value : std_logic_vector(2 downto 0):="000";
begin
process
file file_pointer : text;
variable line_content : string(1 to 15);
variable line_num : line;
variable j, i : integer := 0;
variable char : character:='0';
begin
file_open(file_pointer,"read.txt",READ_MODE);
bin_value <= "UUU";
wait for 1 ps;
while not endfile(file_pointer) loop
readline (file_pointer,line_num);
READ (line_num,line_content);
for j in 1 to 15 loop
i := i + 1;
char := line_content(16-j);
if(char = '0') then
bin_value(i-1) <= '0';
else
bin_value(i-1) <= '1';
end if;
if (i = 3) then
i := 0;
wait for 2 ps;
end if;
end loop;
bin_value <= "UUU";
wait for 4 ps;
end loop;
file_close(file_pointer);
wait;
end process;
Qout <= bin_value;
end Behavioral;
|
mit
|
c63502a25e11ed9f961eae26000d0bec
| 0.577195 | 3.418886 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-LuGus/TP2-Voltimetro/ones_generator.vhd
| 1 | 636 |
library IEEE;
use IEEE.std_logic_1164.all;
entity ones_generator is
generic (
PERIOD: natural := 33000;
COUNT: natural := 15500
);
port(
clk: in std_logic;
count_o: out std_logic
);
end;
architecture ones_generator_arq of ones_generator is
begin
process(clk)
variable tmp_count: integer := 0;
begin
if rising_edge(clk) then
tmp_count:=tmp_count + 1;
if tmp_count < COUNT then
count_o <= '1';
end if;
if tmp_count > COUNT then
count_o <= '0';
end if;
if tmp_count >= PERIOD then
tmp_count := 0;
end if;
end if;
end process;
end;
|
gpl-3.0
|
b44ed53f6db00ebf73a3a3cb7545a343
| 0.584906 | 2.930876 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/Contador_vector.vhd
| 2 | 983 |
library IEEE;
use IEEE.std_logic_1164.all;
entity contador_vector is
port(
rst_c: in std_logic;
clk_c: in std_logic;
enable_c: in std_logic;
Q: out std_logic_vector(1 downto 0)
);
end;
architecture contador_func of contador_vector is
component FFD is
port(
enable: in std_logic;
reset: in std_logic;
clk: in std_logic;
Q: out std_logic;
D: in std_logic
);
end component;
signal q0_c_aux,q1_c_aux,d0_c_aux,d1_c_aux:std_logic;
begin
ffd0: FFD port map( --nombres del FFD : enable,reset,clk,Q,D
clk => clk_c,
enable => enable_c,
reset => rst_c, --Siempre van a la izquierda los puertos de los componentes
D => d0_c_aux,
Q => q0_c_aux
);
Q(0) <= q0_c_aux;
ffd1: FFD port map(
clk=> clk_c,
enable => enable_c,
reset => rst_c,
D => d1_c_aux,
Q => q1_c_aux
);
Q(1) <= q1_c_aux;
d0_c_aux <= not(q0_c_aux);
d1_c_aux <= q1_c_aux xor q0_c_aux;
end architecture;
|
gpl-3.0
|
da74954c7581cf53cff69c0a2e2f85ca
| 0.582909 | 2.403423 | false | false | false | false |
alainmarcel/Surelog
|
third_party/tests/YosysTests/verific/vhdl/top.vhd
| 2 | 862 |
library ieee;
use ieee.std_logic_1164.all;
library foo;
use foo.foo_m;
library bar;
use bar.bar_m;
entity top is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end entity;
architecture rtl of top is
component foo_m is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end component;
component bar_m is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end component;
signal t1, t2 : std_logic;
begin
foo_inst : foo_m port map (
clock => clock,
a => a,
b => b,
x => t1,
y => t2
);
bar_inst : bar_m port map (
clock => clock,
a => t1,
b => t2,
x => x,
y => y
);
end architecture;
|
apache-2.0
|
bad0877bcc6472eb59e93b01cca0bdc5
| 0.554524 | 2.435028 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/bcd_controller/contbcd.vhd
| 1 | 827 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity contBCD is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
s: out std_logic_vector(3 downto 0);
co: out std_logic
);
end;
architecture contBCD_arq of contBCD is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(clk,rst)
variable count: integer range 0 to 10;
begin
if rst = '1' then
s <= (others => '0');
co <= '0';
count := 0;
elsif rising_edge(clk) then
if ena = '1' then
count:=count + 1;
if count = 9 then
co <= '1';
elsif count = 10 then
count := 0;
co <= '0';
else
co <= '0';
end if;
end if;
s <= std_logic_vector(TO_UNSIGNED(count,4));
end if;
end process;
end;
|
gpl-3.0
|
2c114381e36f19b2221d1a3c86410c73
| 0.575574 | 2.871528 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/controller_codeword_generator_1.vhd
| 1 | 34,681 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Codeword_Generator_1
-- Module Name: Controller_Codeword_Generator_1
-- Project Name: McEliece QD-Goppa Encoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The first and only step in QD-Goppa Code encoding.
--
-- This circuit is the state machine controller for Codeword_Generator_1 and
-- Codeword_Generator_n_m. The state machine is composed of a step to copy the
-- original message and another for multiplying the message by matrix A.
-- This matrix multiplication is designed for matrices composed of dyadic blocks.
-- The algorithm computes one dyadic matrix at time.
-- Each dyadic matrix is computed in a column wise strategy.
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.00
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_codeword_generator_1 is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_ctr_dyadic_column_q : in STD_LOGIC;
limit_ctr_dyadic_row_q : in STD_LOGIC;
limit_ctr_address_message_q : in STD_LOGIC;
limit_ctr_address_codeword_q : in STD_LOGIC;
write_enable_new_codeword : out STD_LOGIC;
message_into_new_codeword : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_codeword_rst : out STD_LOGIC;
reg_message_ce : out STD_LOGIC;
reg_matrix_ce : out STD_LOGIC;
ctr_dyadic_column_ce : out STD_LOGIC;
ctr_dyadic_column_rst : out STD_LOGIC;
ctr_dyadic_row_ce : out STD_LOGIC;
ctr_dyadic_row_rst : out STD_LOGIC;
ctr_dyadic_matrices_ce : out STD_LOGIC;
ctr_dyadic_matrices_rst : out STD_LOGIC;
ctr_address_base_message_ce : out STD_LOGIC;
ctr_address_base_message_rst : out STD_LOGIC;
ctr_address_base_codeword_ce : out STD_LOGIC;
ctr_address_base_codeword_rst : out STD_LOGIC;
ctr_address_base_codeword_set : out STD_LOGIC;
internal_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC
);
end controller_codeword_generator_1;
architecture Behavioral of controller_codeword_generator_1 is
type State is (reset, load_counter, prepare_message, load_message, copy_message, last_message, write_last_message, prepare_counters_a, new_acc, calc_codeword_a, last_column_value_a, write_last_column_value_a, last_row_value_a, write_last_row_value_a, last_value_a, write_last_value_a, prepare_counters_b, load_acc, calc_codeword_b, last_column_value_b, write_last_column_value_b, last_row_value_b, write_last_row_value_b, last_value_b, write_last_value_b, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, limit_ctr_dyadic_column_q, limit_ctr_dyadic_row_q, limit_ctr_address_message_q, limit_ctr_address_codeword_q)
begin
case (actual_state) is
when reset =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when load_counter =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when prepare_message =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when load_message =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when copy_message =>
if(limit_ctr_dyadic_row_q = '1' and limit_ctr_dyadic_column_q = '1') then
write_enable_new_codeword <= '1';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '1';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
elsif(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '1';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
elsif(limit_ctr_dyadic_column_q = '1') then
write_enable_new_codeword <= '1';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '1';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '1';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when last_message =>
if(limit_ctr_dyadic_column_q = '1') then
write_enable_new_codeword <= '1';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '1';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when write_last_message =>
write_enable_new_codeword <= '1';
message_into_new_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '1';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when prepare_counters_a =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
end if;
when new_acc =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
end if;
when calc_codeword_a =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
end if;
when last_row_value_a =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_row_value_a =>
write_enable_new_codeword <= '1';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when last_column_value_a =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_column_value_a =>
write_enable_new_codeword <= '1';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '1';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '1';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when last_value_a =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_value_a =>
write_enable_new_codeword <= '1';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '1';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '1';
internal_codeword <= '1';
codeword_finalized <= '0';
when prepare_counters_b =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when load_acc =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when calc_codeword_b =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
end if;
when last_row_value_b =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_row_value_b =>
write_enable_new_codeword <= '1';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when last_column_value_b =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_column_value_b =>
if(limit_ctr_address_codeword_q = '1') then
write_enable_new_codeword <= '1';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '1';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '1';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '1';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '1';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '1';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when last_value_b =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_value_b =>
write_enable_new_codeword <= '1';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when final =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '1';
when others =>
write_enable_new_codeword <= '0';
message_into_new_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end case;
end process;
NewState : process(actual_state, limit_ctr_dyadic_column_q, limit_ctr_dyadic_row_q, limit_ctr_address_message_q, limit_ctr_address_codeword_q)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= prepare_message;
when prepare_message =>
next_state <= load_message;
when load_message =>
next_state <= copy_message;
when copy_message =>
if(limit_ctr_address_message_q = '1') then
next_state <= last_message;
else
next_state <= copy_message;
end if;
when last_message =>
next_state <= write_last_message;
when write_last_message =>
next_state <= prepare_counters_a;
when prepare_counters_a =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value_a;
else
next_state <= last_column_value_a;
end if;
else
next_state <= last_row_value_a;
end if;
else
next_state <= new_acc;
end if;
when new_acc =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value_a;
else
next_state <= last_column_value_a;
end if;
else
next_state <= last_row_value_a;
end if;
else
next_state <= calc_codeword_a;
end if;
when calc_codeword_a =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value_a;
else
next_state <= last_column_value_a;
end if;
else
next_state <= last_row_value_a;
end if;
else
next_state <= calc_codeword_a;
end if;
when last_column_value_a =>
next_state <= write_last_column_value_a;
when write_last_column_value_a =>
next_state <= prepare_counters_a;
when last_row_value_a =>
next_state <= write_last_row_value_a;
when write_last_row_value_a =>
next_state <= prepare_counters_a;
when last_value_a =>
next_state <= write_last_value_a;
when write_last_value_a =>
next_state <= prepare_counters_b;
when prepare_counters_b =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_message_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value_b;
else
next_state <= last_column_value_b;
end if;
else
next_state <= last_column_value_b;
end if;
else
next_state <= last_row_value_b;
end if;
else
next_state <= load_acc;
end if;
when load_acc =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_message_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value_b;
else
next_state <= last_column_value_b;
end if;
else
next_state <= last_column_value_b;
end if;
else
next_state <= last_row_value_b;
end if;
else
next_state <= calc_codeword_b;
end if;
when calc_codeword_b =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_message_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value_b;
else
next_state <= last_column_value_b;
end if;
else
next_state <= last_column_value_b;
end if;
else
next_state <= last_row_value_b;
end if;
else
next_state <= calc_codeword_b;
end if;
when last_column_value_b =>
next_state <= write_last_column_value_b;
when write_last_column_value_b =>
next_state <= prepare_counters_b;
when last_row_value_b =>
next_state <= write_last_row_value_b;
when write_last_row_value_b =>
next_state <= prepare_counters_b;
when last_value_b =>
next_state <= write_last_value_b;
when write_last_value_b =>
next_state <= final;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
62956eae81a237709cdcca516c37332f
| 0.590035 | 2.72821 | false | false | false | false |
rodrigoazs/-7-5-Reed-Solomon
|
code/error_guessing.vhd
| 1 | 3,030 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity ErrorGuessing is
Port ( Syndrome: in std_logic_vector(5 downto 0);
Error: out std_logic_vector(20 downto 0));
end ErrorGuessing;
architecture Behavioral of ErrorGuessing is
begin
process ( Syndrome )
begin
case Syndrome is
when "010011"=> Error <="000000000000000000100";
when "010111"=> Error <="000000000000000100000";
when "110111"=> Error <="000000000000100000000";
when "100100"=> Error <="000000000100000000000";
when "110011"=> Error <="000000100000000000000";
when "000100"=> Error <="000100000000000000000";
when "100000"=> Error <="100000000000000000000";
when "001111"=> Error <="000000000000000000010";
when "001101"=> Error <="000000000000000010000";
when "011101"=> Error <="000000000000010000000";
when "010010"=> Error <="000000000010000000000";
when "011111"=> Error <="000000010000000000000";
when "000010"=> Error <="000010000000000000000";
when "010000"=> Error <="010000000000000000000";
when "110101"=> Error <="000000000000000000001";
when "110100"=> Error <="000000000000000001000";
when "111100"=> Error <="000000000000001000000";
when "001001"=> Error <="000000000001000000000";
when "111101"=> Error <="000000001000000000000";
when "000001"=> Error <="000001000000000000000";
when "001000"=> Error <="001000000000000000000";
when "011100"=> Error <="000000000000000000110";
when "011010"=> Error <="000000000000000110000";
when "101010"=> Error <="000000000000110000000";
when "110110"=> Error <="000000000110000000000";
when "101100"=> Error <="000000110000000000000";
when "000110"=> Error <="000110000000000000000";
when "110000"=> Error <="110000000000000000000";
when "111010"=> Error <="000000000000000000011";
when "111001"=> Error <="000000000000000011000";
when "100001"=> Error <="000000000000011000000";
when "011011"=> Error <="000000000011000000000";
when "100010"=> Error <="000000011000000000000";
when "000011"=> Error <="000011000000000000000";
when "011000"=> Error <="011000000000000000000";
when "101001"=> Error <="000000000000000000111";
when "101110"=> Error <="000000000000000111000";
when "010110"=> Error <="000000000000111000000";
when "111111"=> Error <="000000000111000000000";
when "010001"=> Error <="000000111000000000000";
when "000111"=> Error <="000111000000000000000";
when "111000"=> Error <="111000000000000000000";
when "100110"=> Error <="000000000000000000101";
when "100011"=> Error <="000000000000000101000";
when "001011"=> Error <="000000000000101000000";
when "101101"=> Error <="000000000101000000000";
when "001110"=> Error <="000000101000000000000";
when "000101"=> Error <="000101000000000000000";
when "101000"=> Error <="101000000000000000000";
when OTHERS => Error <="000000000000000000000";
end case;
end process;
end Behavioral;
|
mit
|
3e62792150da93c550f53fc9243f4ffa
| 0.733993 | 4.712286 | false | false | false | false |
achan1989/In64
|
FPGA/SD_card_test.srcs/sources_1/new/main.vhd
| 1 | 9,206 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.08.2013 20:08:06
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity main is
Port ( clk : in std_ulogic;
reset_switch : in std_ulogic;
uart_tx : out std_ulogic;
sd_cs_out : out std_ulogic;
sd_clk_out : out std_ulogic;
sd_mosi : out std_ulogic;
sd_miso : in std_ulogic;
sd_power : out std_ulogic;
read_strobe_dbg : out std_ulogic);
end main;
architecture Behavioral of main is
component kcpsm6
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
component test_program
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end component;
component uart_tx6 is
Port ( data_in : in std_logic_vector(7 downto 0);
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_write : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end component;
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal bram_enable : std_logic;
signal in_port : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal k_write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic;
signal interrupt_ack : std_logic;
signal kcpsm6_sleep : std_logic;
signal kcpsm6_reset : std_logic;
signal sd_cs : std_ulogic := '1';
signal sd_clk : std_ulogic := '0';
-- Signals for UART_TX6
signal uart_tx_data_in : std_logic_vector(7 downto 0);
signal write_to_uart_tx : std_ulogic;
signal uart_tx_full : std_ulogic;
signal uart_tx_reset : std_ulogic;
-- Signals used to define baud rate
signal baud_count : integer range 0 to 53 := 0;
signal en_16_x_baud : std_ulogic := '0';
begin
cpu: kcpsm6
generic map ( hwbuild => X"00",
interrupt_vector => X"3FF",
scratch_pad_memory_size => 64)
port map( address => address,
instruction => instruction,
bram_enable => bram_enable,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
sleep => kcpsm6_sleep,
reset => kcpsm6_reset or (not reset_switch),
clk => clk);
kcpsm6_sleep <= '0';
interrupt <= '0';
read_strobe_dbg <= read_strobe;
programRom: test_program
generic map( C_FAMILY => "S6", --Family 'S6', 'V6' or '7S'
C_RAM_SIZE_KWORDS => 1, --Program size '1', '2' or '4'
C_JTAG_LOADER_ENABLE => 1) --Include JTAG Loader when set to '1'
port map( address => address,
instruction => instruction,
enable => bram_enable,
rdl => kcpsm6_reset,
clk => clk);
tx: uart_tx6
port map ( data_in => uart_tx_data_in,
en_16_x_baud => en_16_x_baud,
serial_out => uart_tx,
buffer_write => write_to_uart_tx,
buffer_data_present => open,
buffer_half_full => open,
buffer_full => uart_tx_full,
buffer_reset => uart_tx_reset,
clk => clk);
in_port <= (7 => sd_miso, 2 => uart_tx_full, others => '-');
--input_ports: process(clk)
--begin
-- if rising_edge(clk) then
-- case port_id(0) is
-- when '0' => in_port <= (7 => sd_miso, 6 downto 0 => '-');
-- when '1' => in_port(2) <= uart_tx_full;
-- when others => null;
-- end case;
-- end if;
--end process;
-- Always send CPU output to the UART...
uart_tx_data_in <= out_port;
-- But don't trigger a write unless the CPU output was actually meant for the UART (OUT on port 3).
write_to_uart_tx <= '1' when (write_strobe = '1' and port_id(0) = '1') else '0';
output_ports: process(clk)
begin
if rising_edge(clk) then
if write_strobe = '1' then
case port_id(0) is
when '0' =>
sd_clk <= out_port(0);
sd_cs <= out_port(1);
sd_mosi <= out_port(7);
--when '1' =>
-- write_to_uart_tx <= '1';
-- uart_tx_data_in <= out_port;
when others => null;
end case;
--else
-- write_to_uart_tx <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------------------
-- RS232 (UART) baud rate
-----------------------------------------------------------------------------------------
--
-- To set serial communication baud rate to 115,200 then en_16_x_baud must pulse
-- High at 1,843,200Hz which is every 54.28 cycles at 100MHz. In this implementation
-- a pulse is generated every 54 cycles resulting is a baud rate of 115,741 baud which
-- is only 0.5% high and well within limits.
--
baud_rate: process(clk)
begin
if rising_edge(clk) then
if baud_count = 53 then -- counts 54 states including zero
baud_count <= 0;
en_16_x_baud <= '1'; -- single cycle enable pulse
else
baud_count <= baud_count + 1;
en_16_x_baud <= '0';
end if;
end if;
end process baud_rate;
-----------------------------------------------------------------------------------------
-- Constant-Optimised Output Ports
-----------------------------------------------------------------------------------------
--
-- One constant-optimised output port is used to facilitate resetting of the UART macros.
--
constant_output_ports: process(clk)
begin
if rising_edge(clk) then
if k_write_strobe = '1' then
uart_tx_reset <= out_port(0);
sd_power <= out_port(7);
end if;
end if;
end process constant_output_ports;
sd_cs_out <= sd_cs;
sd_clk_out <= sd_clk;
end Behavioral;
|
lgpl-3.0
|
12266545eb30f6bd5cd18515f718c7d9
| 0.463719 | 4.234591 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/controller_codeword_generator_2.vhd
| 1 | 25,771 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Codeword_Generator_2
-- Module Name: Controller_Codeword_Generator_2
-- Project Name: 1st Step - Codeword Generation
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The first and only step in QD-Goppa Code encoding.
-- This circuit is the state machine controller for Codeword_Generator_n_m_v2.
-- The state machine is composed of a step to copy the
-- original message and another for multiplying the message by matrix A.
-- This matrix multiplication is designed for matrices composed of dyadic blocks.
-- The algorithm computes one dyadic matrix at time.
-- Each dyadic matrix is computed in a column wise strategy.
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.00
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_codeword_generator_2 is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_ctr_dyadic_column_q : in STD_LOGIC;
limit_ctr_dyadic_row_q : in STD_LOGIC;
limit_ctr_address_message_q : in STD_LOGIC;
limit_ctr_address_codeword_q : in STD_LOGIC;
zero_ctr_address_message_q : in STD_LOGIC;
write_enable_new_codeword : out STD_LOGIC;
external_matrix_ce : out STD_LOGIC;
message_added_to_codeword : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_codeword_rst : out STD_LOGIC;
reg_message_ce : out STD_LOGIC;
reg_matrix_ce : out STD_LOGIC;
ctr_dyadic_column_ce : out STD_LOGIC;
ctr_dyadic_column_rst : out STD_LOGIC;
ctr_dyadic_row_ce : out STD_LOGIC;
ctr_dyadic_row_rst : out STD_LOGIC;
ctr_dyadic_matrices_ce : out STD_LOGIC;
ctr_dyadic_matrices_rst : out STD_LOGIC;
ctr_address_base_message_ce : out STD_LOGIC;
ctr_address_base_message_rst : out STD_LOGIC;
ctr_address_base_codeword_ce : out STD_LOGIC;
ctr_address_base_codeword_rst : out STD_LOGIC;
ctr_address_base_codeword_set : out STD_LOGIC;
internal_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC
);
end controller_codeword_generator_2;
architecture Behavioral of controller_codeword_generator_2 is
type State is (reset, load_counter, prepare_message, load_message, copy_message, last_message, write_last_message, prepare_counters_a, load_acc, load_acc_entire_matrix, calc_codeword, last_column_value, write_last_column_value, last_row_value, write_last_row_value, last_value, write_last_value, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, limit_ctr_dyadic_column_q, limit_ctr_dyadic_row_q, limit_ctr_address_message_q, limit_ctr_address_codeword_q, zero_ctr_address_message_q)
begin
case (actual_state) is
when reset =>
write_enable_new_codeword <= '0';
external_matrix_ce <= '0';
message_added_to_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when load_counter =>
write_enable_new_codeword <= '0';
external_matrix_ce <= '0';
message_added_to_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when prepare_message =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
external_matrix_ce <= '0';
message_added_to_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
external_matrix_ce <= '0';
message_added_to_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when load_message =>
if(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '0';
external_matrix_ce <= '0';
message_added_to_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
external_matrix_ce <= '0';
message_added_to_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when copy_message =>
if(limit_ctr_dyadic_row_q = '1' and limit_ctr_dyadic_column_q = '1') then
write_enable_new_codeword <= '1';
external_matrix_ce <= '0';
message_added_to_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '1';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
elsif(limit_ctr_dyadic_row_q = '1') then
write_enable_new_codeword <= '1';
external_matrix_ce <= '0';
message_added_to_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
elsif(limit_ctr_dyadic_column_q = '1') then
write_enable_new_codeword <= '1';
external_matrix_ce <= '0';
message_added_to_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '1';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '1';
external_matrix_ce <= '0';
message_added_to_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when last_message =>
if(limit_ctr_dyadic_column_q = '1') then
write_enable_new_codeword <= '1';
external_matrix_ce <= '0';
message_added_to_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '1';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '1';
external_matrix_ce <= '0';
message_added_to_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when write_last_message =>
write_enable_new_codeword <= '1';
external_matrix_ce <= '0';
message_added_to_codeword <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '1';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when prepare_counters_a =>
write_enable_new_codeword <= '0';
external_matrix_ce <= '1';
message_added_to_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when load_acc =>
if(zero_ctr_address_message_q = '1') then
write_enable_new_codeword <= '0';
external_matrix_ce <= '0';
message_added_to_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
external_matrix_ce <= '0';
message_added_to_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when load_acc_entire_matrix =>
if(zero_ctr_address_message_q = '1') then
write_enable_new_codeword <= '0';
external_matrix_ce <= '0';
message_added_to_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '1';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
external_matrix_ce <= '0';
message_added_to_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '1';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when calc_codeword =>
write_enable_new_codeword <= '0';
external_matrix_ce <= '0';
message_added_to_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when last_row_value =>
write_enable_new_codeword <= '0';
external_matrix_ce <= '0';
message_added_to_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_row_value =>
write_enable_new_codeword <= '1';
external_matrix_ce <= '0';
message_added_to_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when last_column_value =>
write_enable_new_codeword <= '0';
external_matrix_ce <= '0';
message_added_to_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '1';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_column_value =>
if(limit_ctr_address_codeword_q = '1') then
write_enable_new_codeword <= '1';
external_matrix_ce <= '0';
message_added_to_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '1';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '1';
external_matrix_ce <= '0';
message_added_to_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '1';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when last_value =>
write_enable_new_codeword <= '0';
external_matrix_ce <= '0';
message_added_to_codeword <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_value =>
write_enable_new_codeword <= '1';
external_matrix_ce <= '0';
message_added_to_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when final =>
write_enable_new_codeword <= '0';
external_matrix_ce <= '0';
message_added_to_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '1';
when others =>
write_enable_new_codeword <= '0';
external_matrix_ce <= '0';
message_added_to_codeword <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
ctr_address_base_codeword_set <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end case;
end process;
NewState : process(actual_state, limit_ctr_dyadic_column_q, limit_ctr_dyadic_row_q, limit_ctr_address_message_q, limit_ctr_address_codeword_q)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= prepare_message;
when prepare_message =>
next_state <= load_message;
when load_message =>
next_state <= copy_message;
when copy_message =>
if(limit_ctr_address_message_q = '1') then
next_state <= last_message;
else
next_state <= copy_message;
end if;
when last_message =>
next_state <= write_last_message;
when write_last_message =>
next_state <= prepare_counters_a;
when prepare_counters_a =>
if(limit_ctr_dyadic_row_q = '1') then
next_state <= load_acc_entire_matrix;
else
next_state <= load_acc;
end if;
when load_acc =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_message_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value;
else
next_state <= last_column_value;
end if;
else
next_state <= last_column_value;
end if;
else
next_state <= last_row_value;
end if;
else
next_state <= calc_codeword;
end if;
when load_acc_entire_matrix =>
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_message_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= write_last_value;
else
next_state <= write_last_column_value;
end if;
else
next_state <= write_last_column_value;
end if;
else
next_state <= write_last_row_value;
end if;
when calc_codeword =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_message_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value;
else
next_state <= last_column_value;
end if;
else
next_state <= last_column_value;
end if;
else
next_state <= last_row_value;
end if;
else
next_state <= calc_codeword;
end if;
when last_column_value =>
next_state <= write_last_column_value;
when write_last_column_value =>
next_state <= prepare_counters_a;
when last_row_value =>
next_state <= write_last_row_value;
when write_last_row_value =>
next_state <= prepare_counters_a;
when last_value =>
next_state <= write_last_value;
when write_last_value =>
next_state <= final;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
85dffc38dd7b211f350e0f60ed8f05c5
| 0.59404 | 2.766613 | false | false | false | false |
laurivosandi/hdl
|
zynq/src/ov7670_capture/ov7670_capture.vhd
| 1 | 2,524 |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Captures the pixels coming from the OV7670 camera and
-- Stores them in block RAM
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.NUMERIC_STD.ALL;
entity ov7670_capture is
port (
pclk : in std_logic;
vsync : in std_logic;
href : in std_logic;
d : in std_logic_vector ( 7 downto 0);
addr : out std_logic_vector (17 downto 0);
dout : out std_logic_vector (11 downto 0);
we : out std_logic
);
end ov7670_capture;
architecture behavioral of ov7670_capture is
signal d_latch : std_logic_vector(15 downto 0) := (others => '0');
signal address : std_logic_vector(18 downto 0) := (others => '0');
signal address_next : std_logic_vector(18 downto 0) := (others => '0');
signal wr_hold : std_logic_vector( 1 downto 0) := (others => '0');
begin
addr <= address(18 downto 1);
process(pclk)
begin
if rising_edge(pclk) then
-- This is a bit tricky href starts a pixel transfer that takes 3 cycles
-- Input | state after clock tick
-- href | wr_hold d_latch d we address address_next
-- cycle -1 x | xx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx x xxxx xxxx
-- cycle 0 1 | x1 xxxxxxxxRRRRRGGG xxxxxxxxxxxxxxxx x xxxx addr
-- cycle 1 0 | 10 RRRRRGGGGGGBBBBB xxxxxxxxRRRRRGGG x addr addr
-- cycle 2 x | 0x GGGBBBBBxxxxxxxx RRRRRGGGGGGBBBBB 1 addr addr+1
if vsync = '1' then
address <= (others => '0');
address_next <= (others => '0');
wr_hold <= (others => '0');
else
-- This should be a different order, but seems to be GRB!
dout <= d_latch(15 downto 12) & d_latch(10 downto 7) & d_latch(4 downto 1);
address <= address_next;
we <= wr_hold(1);
wr_hold <= wr_hold(0) & (href and not wr_hold(0));
d_latch <= d_latch( 7 downto 0) & d;
if wr_hold(1) = '1' then
address_next <= std_logic_vector(unsigned(address_next)+1);
end if;
end if;
end if;
end process;
end behavioral;
|
mit
|
a7188ff891808cc532980e7369280733
| 0.5 | 3.824242 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/mceliece_qd_goppa_encrypt.vhd
| 1 | 10,294 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: McEliece_QD-Goppa_Encrypt
-- Module Name: McEliece_QD-Goppa_Encrypt
-- Project Name: McEliece QD-Goppa Encryption
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit does the McEliece encryption with two circuits.
-- First circuit, codeword_generator_n_m_v3, computes the codeword from a given message.
-- Second circuit, error_adder, computes the ciphertext from a given error and codeword.
-- Where the codeword is generated by the previously circuit.
-- Both circuits work independently, but the entire circuit cannot work as a pipeline,
-- where is possible to compute a different codeword and adding the error in previously one.
--
-- The circuits parameters
--
-- number_of_units :
--
-- The square root of total number of units the codeword_generator will have and the total
-- units the error adder has.
-- The codeword generator has a total number of units = number_of_units^2.
-- This number must be a power of 2 and equal or greater than 1.
--
-- length_message :
--
-- Length in bits of message size and also part of matrix size.
--
-- size_message :
--
-- The number of bits necessary to store the message. The ceil(log2(lenght_message))
--
-- length_codeword :
--
-- Length in bits of codeword size and also part of matrix size.
--
-- size_codeword :
--
-- The number of bits necessary to store the codeword. The ceil(log2(legth_codeword))
--
-- size_dyadic_matrix :
--
-- The number of bits necessary to store one row of the dyadic matrix.
-- It is also the ceil(log2(number of errors in the code))
--
-- number_dyadic_matrices :
--
-- The number of dyadic matrices present in matrix A.
--
-- size_number_dyadic_matrices :
--
-- The number of bits necessary to store the number of dyadic matrices.
-- The ceil(log2(number_dyadic_matrices))
--
-- Dependencies:
--
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- codeword_generator_n_m_v3 Rev 1.0
-- error_adder Rev 1.0
--
-- Revision:
-- Revision 1.00 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mceliece_qd_goppa_encrypt is
Generic(
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_units : integer := 32;
-- length_message : integer := 2144;
-- size_message : integer := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- size_number_of_errors : integer := 5;
-- number_dyadic_matrices : integer := 804;
-- size_number_dyadic_matrices : integer := 10
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_units : integer := 1;
-- length_message : integer := 2048;
-- size_message : integer := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- size_number_of_errors : integer := 6;
-- number_dyadic_matrices : integer := 384;
-- size_number_dyadic_matrices : integer := 9
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_units : integer := 1;
-- length_message : integer := 2560;
-- size_message : integer := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- size_number_of_errors : integer := 6;
-- number_dyadic_matrices : integer := 480;
-- size_number_dyadic_matrices : integer := 9
-- QD-GOPPA [7296, 5632, 128, 13] --
number_of_units : integer := 2;
length_message : integer := 5632;
size_message : integer := 13;
length_codeword : integer := 7296;
size_codeword : integer := 13;
size_number_of_errors : integer := 7;
number_dyadic_matrices : integer := 572;
size_number_dyadic_matrices : integer := 10
);
Port(
message : in STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
matrix : in STD_LOGIC_VECTOR((2**size_number_of_errors - 1) downto 0);
codeword : in STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
error : in STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
encryption_finalized : out STD_LOGIC;
write_enable_ciphertext_1 : out STD_LOGIC;
write_enable_ciphertext_2 : out STD_LOGIC;
ciphertext_1 : out STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
ciphertext_2 : out STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
address_matrix : out STD_LOGIC_VECTOR((size_number_of_errors + size_number_dyadic_matrices - 1) downto 0);
address_message : out STD_LOGIC_VECTOR((size_message - 1) downto 0);
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_error : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_ciphertext_2 : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0)
);
end mceliece_qd_goppa_encrypt;
architecture RTL of mceliece_qd_goppa_encrypt is
component codeword_generator_n_m_v3
Generic(
number_of_multipliers_per_acc : integer;
number_of_accs : integer;
length_vector : integer;
size_vector : integer;
length_acc : integer;
size_acc : integer;
size_dyadic_matrix : integer;
number_dyadic_matrices : integer;
size_number_dyadic_matrices : integer
);
Port(
acc : in STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
matrix : in STD_LOGIC_VECTOR((2**size_dyadic_matrix - 1) downto 0);
vector : in STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
new_acc : out STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
new_acc_copy : out STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
write_enable_new_acc : out STD_LOGIC;
write_enable_new_acc_copy : out STD_LOGIC;
codeword_finalized : out STD_LOGIC;
address_acc : out STD_LOGIC_VECTOR((size_acc - 1) downto 0);
address_new_acc_copy : out STD_LOGIC_VECTOR((size_acc - 1) downto 0);
address_vector : out STD_LOGIC_VECTOR((size_vector - 1) downto 0);
address_matrix : out STD_LOGIC_VECTOR((size_dyadic_matrix + size_number_dyadic_matrices - 1) downto 0)
);
end component;
component error_adder
Generic(
number_of_units : integer;
length_codeword : integer;
size_codeword : integer
);
Port(
codeword : in STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
error : in STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
error_added : out STD_LOGIC;
write_enable_ciphertext : out STD_LOGIC;
ciphertext : out STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_error : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_ciphertext : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0)
);
end component;
signal rst_error : STD_LOGIC;
signal generator_ciphertext_1 : STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
signal generator_ciphertext_2 : STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
signal generator_write_enable_ciphertext_1 : STD_LOGIC;
signal generator_write_enable_ciphertext_2 : STD_LOGIC;
signal codeword_finalized : STD_LOGIC;
signal generator_address_codeword : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal generator_address_ciphertext_2 : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal generator_address_message : STD_LOGIC_VECTOR((size_message - 1) downto 0);
signal generator_address_matrix : STD_LOGIC_VECTOR((size_number_of_errors + size_number_dyadic_matrices - 1) downto 0);
signal error_added : STD_LOGIC;
signal error_write_enable_ciphertext : STD_LOGIC;
signal error_ciphertext_2 : STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
signal error_address_codeword : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal error_address_error : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal error_address_ciphertext_2 : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
begin
generator : codeword_generator_n_m_v3
Generic Map(
number_of_multipliers_per_acc => number_of_units,
number_of_accs => number_of_units,
length_vector => length_message,
size_vector => size_message,
length_acc => length_codeword,
size_acc => size_codeword,
size_dyadic_matrix => size_number_of_errors,
number_dyadic_matrices => number_dyadic_matrices,
size_number_dyadic_matrices => size_number_dyadic_matrices
)
Port Map(
acc => codeword,
matrix => matrix,
vector => message,
clk => clk,
rst => rst,
new_acc => generator_ciphertext_1,
new_acc_copy => generator_ciphertext_2,
write_enable_new_acc => generator_write_enable_ciphertext_1,
write_enable_new_acc_copy => generator_write_enable_ciphertext_2,
codeword_finalized => codeword_finalized,
address_acc => generator_address_codeword,
address_new_acc_copy => generator_address_ciphertext_2,
address_vector => generator_address_message,
address_matrix => generator_address_matrix
);
error_add : error_adder
Generic Map(
number_of_units => number_of_units,
length_codeword => length_codeword,
size_codeword => size_codeword
)
Port Map(
codeword => codeword,
error => error,
clk => clk,
rst => rst_error,
error_added => error_added,
write_enable_ciphertext => error_write_enable_ciphertext,
ciphertext => error_ciphertext_2,
address_codeword => error_address_codeword,
address_error => error_address_error,
address_ciphertext => error_address_ciphertext_2
);
rst_error <= not codeword_finalized;
encryption_finalized <= error_added and codeword_finalized;
write_enable_ciphertext_1 <= '0' when codeword_finalized = '1' else
generator_write_enable_ciphertext_1;
write_enable_ciphertext_2 <= error_write_enable_ciphertext when codeword_finalized = '1' else
generator_write_enable_ciphertext_2;
ciphertext_1 <= generator_ciphertext_1;
ciphertext_2 <= error_ciphertext_2 when codeword_finalized = '1' else
generator_ciphertext_2;
address_matrix <= generator_address_matrix;
address_message <= generator_address_message;
address_codeword <= error_address_codeword when codeword_finalized = '1' else
generator_address_codeword;
address_error <= error_address_error;
address_ciphertext_2 <= error_address_ciphertext_2 when codeword_finalized = '1' else
generator_address_ciphertext_2;
end RTL;
|
bsd-2-clause
|
655c22cb644c4949a3a8d591c30fd504
| 0.691956 | 3.285669 | false | false | false | false |
alainmarcel/Surelog
|
third_party/tests/ariane/fpga/src/apb_uart/src/slib_counter.vhd
| 5 | 2,883 |
--
-- Counter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.2
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Counter
entity slib_counter is
generic (
WIDTH : natural := 4 -- Counter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear counter register
LOAD : in std_logic; -- Load counter register
ENABLE : in std_logic; -- Enable count operation
DOWN : in std_logic; -- Count direction down
D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input
Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output
OVERFLOW : out std_logic -- Counter overflow
);
end slib_counter;
architecture rtl of slib_counter is
signal iCounter : unsigned(WIDTH downto 0); -- Counter register
begin
-- Counter process
COUNT_SHIFT: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= (others => '0'); -- Reset counter register
elsif (CLK'event and CLK='1') then
if (CLEAR = '1') then
iCounter <= (others => '0'); -- Clear counter register
elsif (LOAD = '1') then -- Load counter register
iCounter <= unsigned('0' & D);
elsif (ENABLE = '1') then -- Enable counter
if (DOWN = '0') then -- Count up
iCounter <= iCounter + 1;
else -- Count down
iCounter <= iCounter - 1;
end if;
end if;
if (iCounter(WIDTH) = '1') then -- Clear overflow
iCounter(WIDTH) <= '0';
end if;
end if;
end process;
-- Output ports
Q <= std_logic_vector(iCounter(WIDTH-1 downto 0));
OVERFLOW <= iCounter(WIDTH);
end rtl;
|
apache-2.0
|
64161601f2dea72f662c5f6debcf516e
| 0.546306 | 4.394817 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/tb_codeword_generator_n_m_v3.vhd
| 1 | 16,339 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Codeword Generator_n_m_v3
-- Module Name: Tb_Codeword_Generator_n_m_v3
-- Project Name: McEliece QD-Goppa Encoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Test bench for codeword_generator_n_m_v2 circuit.
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- number_of_multipliers_per_acc :
--
-- The number of matrix rows and message values calculate at once in one or more accumulators.
-- On this implementation this value, must be the same of number_of_accs,
-- because of copy message. When copying message message values loaded must be same stored in codeword.
-- This value also must be power of 2.
--
-- number_of_accs :
--
-- The number of matrix columns and codeword values calculate at once.
-- On this implementation this value, must be the same of number_of_multipliers_per_acc,
-- because of copy message. When copying message message values loaded must be same stored in codeword.
-- This value also must be power of 2.
--
-- length_message :
--
-- Length in bits of message size and also part of matrix size.
--
-- size_message :
--
-- The number of bits necessary to store the message. The ceil(log2(lenght_message))
--
-- length_codeword :
--
-- Length in bits of codeword size and also part of matrix size.
--
-- size_codeword :
--
-- The number of bits necessary to store the codeword. The ceil(log2(length_codeword))
--
-- size_dyadic_matrix :
--
-- The number of bits necessary to store one row of the dyadic matrix.
-- It is also the ceil(log2(number of errors in the code))
--
-- number_dyadic_matrices :
--
-- The number of dyadic matrices present in matrix A.
--
-- size_number_dyadic_matrices :
--
-- The number of bits necessary to store the number of dyadic matrices.
-- The ceil(log2(number_dyadic_matrices))
--
-- message_memory_file :
--
-- File that holds the message to be encoded.
--
-- codeword_memory_file :
--
-- File that holds the encoded message.
-- This will be used to verify if the circuit worked correctly.
--
-- generator_matrix_memory_file :
--
-- File that holds the public key, matrix A, in a reduced form.
--
-- dump_test_codeword_file :
--
-- File that will hold the encoded message computed by the circuit.
--
--
-- Dependencies:
--
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- codeword_generator_n_m_v3 Rev 1.0
-- ram_bank Rev 1.0
-- ram_double Rev 1.0
-- ram_double_bank Rev 1.0
--
-- Revision:
-- Revision 1.00 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_codeword_generator_n_m_v3 is
Generic (
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
-- number_of_multipliers_per_acc : integer := 1;
-- number_of_accs : integer := 1;
-- length_message : integer := 28;
-- size_message : integer := 5;
-- length_codeword : integer := 52;
-- size_codeword : integer := 6;
-- size_dyadic_matrix : integer := 2;
-- number_dyadic_matrices : integer := 42;
-- size_number_dyadic_matrices : integer := 6;
-- message_memory_file : string := "mceliece/data_tests/message_qdgoppa_52_28_4_6.dat";
-- codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_52_28_4_6.dat";
-- generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_52_28_4_6.dat";
-- dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_52_28_4_6.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
number_of_multipliers_per_acc : integer := 1;
number_of_accs : integer := 1;
length_message : integer := 2144;
size_message : integer := 12;
length_codeword : integer := 2528;
size_codeword : integer := 12;
size_dyadic_matrix : integer := 5;
number_dyadic_matrices : integer := 804;
size_number_dyadic_matrices : integer := 10;
message_memory_file : string := "mceliece/data_tests/message_qdgoppa_2528_2144_32_12.dat";
codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2528_2144_32_12.dat";
generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_2528_2144_32_12.dat";
dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_2528_2144_32_12.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_multipliers_per_acc : integer := 64;
-- number_of_accs : integer := 64;
-- length_message : integer := 2048;
-- size_message : integer := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 384;
-- size_number_dyadic_matrices : integer := 9;
-- message_memory_file : string := "mceliece/data_tests/message_qdgoppa_2816_2048_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2816_2048_64_12.dat";
-- generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_2816_2048_64_12.dat";
-- dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_multipliers_per_acc : integer := 64;
-- number_of_accs : integer := 64;
-- length_message : integer := 2560;
-- size_message : integer := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 480;
-- size_number_dyadic_matrices : integer := 9;
-- message_memory_file : string := "mceliece/data_tests/message_qdgoppa_3328_2560_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_3328_2560_64_12.dat";
-- generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_3328_2560_64_12.dat";
-- dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_multipliers_per_acc : integer := 1;
-- number_of_accs : integer := 1;
-- length_message : integer := 5632;
-- size_message : integer := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- size_dyadic_matrix : integer := 7;
-- number_dyadic_matrices : integer := 572;
-- size_number_dyadic_matrices : integer := 10;
-- message_memory_file : string := "mceliece/data_tests/message_qdgoppa_7296_5632_128_13.dat";
-- codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_7296_5632_128_13.dat";
-- generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_7296_5632_128_13.dat";
-- dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_7296_5632_128_13.dat"
);
end tb_codeword_generator_n_m_v3;
architecture Behavioral of tb_codeword_generator_n_m_v3 is
component codeword_generator_n_m_v3 is
Generic(
number_of_multipliers_per_acc : integer;
number_of_accs : integer;
length_message : integer;
size_message : integer;
length_codeword : integer;
size_codeword : integer;
size_dyadic_matrix : integer;
number_dyadic_matrices : integer;
size_number_dyadic_matrices : integer
);
Port(
codeword : in STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
matrix : in STD_LOGIC_VECTOR((2**size_dyadic_matrix - 1) downto 0);
message : in STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
new_codeword : out STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
new_codeword_copy : out STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
write_enable_new_codeword : out STD_LOGIC;
write_enable_new_codeword_copy : out STD_LOGIC;
codeword_finalized : out STD_LOGIC;
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_new_codeword_copy : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_message : out STD_LOGIC_VECTOR((size_message - 1) downto 0);
address_matrix : out STD_LOGIC_VECTOR(((size_dyadic_matrix + size_number_dyadic_matrices) - 1) downto 0)
);
end component;
component ram_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component ram_double
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component ram_double_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal codeword : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal matrix : STD_LOGIC_VECTOR((2**size_dyadic_matrix - 1) downto 0);
signal message : STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
signal new_codeword : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal new_codeword_copy : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal write_enable_new_codeword : STD_LOGIC;
signal write_enable_new_codeword_copy : STD_LOGIC;
signal codeword_finalized : STD_LOGIC;
signal address_codeword : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal address_new_codeword_copy : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal address_message : STD_LOGIC_VECTOR((size_message - 1) downto 0);
signal address_matrix : STD_LOGIC_VECTOR(((size_dyadic_matrix + size_number_dyadic_matrices) - 1) downto 0);
signal test_address_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal final_address_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal true_codeword : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal test_error : STD_LOGIC;
signal dump_test_codeword : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
for mem_message : ram_bank use entity work.ram_bank(file_load);
for mem_test_codeword : ram_double_bank use entity work.ram_double_bank(simple);
for mem_true_codeword : ram_bank use entity work.ram_bank(file_load);
begin
test : codeword_generator_n_m_v3
Generic Map(
number_of_multipliers_per_acc => number_of_multipliers_per_acc,
number_of_accs => number_of_accs,
length_message => length_message,
size_message => size_message,
length_codeword => length_codeword,
size_codeword => size_codeword,
size_dyadic_matrix => size_dyadic_matrix,
number_dyadic_matrices => number_dyadic_matrices,
size_number_dyadic_matrices => size_number_dyadic_matrices
)
Port Map(
codeword => codeword,
matrix => matrix,
message => message,
clk => clk,
rst => rst,
new_codeword => new_codeword,
new_codeword_copy => new_codeword_copy,
write_enable_new_codeword => write_enable_new_codeword,
write_enable_new_codeword_copy => write_enable_new_codeword_copy,
codeword_finalized => codeword_finalized,
address_codeword => address_codeword,
address_new_codeword_copy => address_new_codeword_copy,
address_message => address_message,
address_matrix => address_matrix
);
mem_generator_matrix : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => 2**size_dyadic_matrix,
ram_address_size => size_dyadic_matrix + size_number_dyadic_matrices,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => generator_matrix_memory_file,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_matrix,
rst_value => "0",
data_out => matrix
);
mem_message : ram_bank
Generic Map(
number_of_memories => number_of_multipliers_per_acc,
ram_address_size => size_message,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => message_memory_file,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_message,
rst_value => "0",
data_out => message
);
mem_test_codeword : ram_double_bank
Generic Map(
number_of_memories => number_of_accs,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => "",
dump_file_name => dump_test_codeword_file
)
Port Map(
data_in_a => new_codeword,
data_in_b => new_codeword_copy,
rw_a => write_enable_new_codeword,
rw_b => write_enable_new_codeword_copy,
clk => clk,
rst => rst,
dump => dump_test_codeword,
address_a => final_address_acc,
address_b => address_new_codeword_copy,
rst_value => "0",
data_out_a => codeword,
data_out_b => open
);
mem_true_codeword : ram_bank
Generic Map(
number_of_memories => number_of_accs,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => codeword_memory_file,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => final_address_acc,
rst_value => "0",
data_out => true_codeword
);
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
final_address_acc <= address_codeword when codeword_finalized = '0' else test_address_acc;
process
variable i : integer;
begin
test_address_acc <= (others => '0');
rst <= '1';
test_error <= '0';
dump_test_codeword <= '0';
wait for PERIOD*2;
rst <= '0';
wait until codeword_finalized = '1';
report "Circuit finish = " & integer'image((cycle_count - 2)/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (length_codeword)) loop
test_address_acc <= std_logic_vector(to_unsigned(i, test_address_acc'Length));
wait for PERIOD*2;
if (true_codeword = codeword) then
test_error <= '0';
else
test_error <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
test_error <= '0';
wait for PERIOD;
i := i + number_of_accs;
end loop;
dump_test_codeword <= '1';
wait for PERIOD;
dump_test_codeword <= '0';
test_bench_finish <= '1';
wait;
end process;
end Behavioral;
|
bsd-2-clause
|
a6f0372658f2b60329f81c4cbe5ce5cd
| 0.668646 | 2.984292 | false | true | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/display/display_tb.vhd
| 1 | 3,311 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity display_tb is
end entity;
architecture display_tb_arq of display_tb is
constant MIN_X : natural := 145; -- front guard: 1.89 us
constant MIN_Y : natural := 65; -- front guard: 1.02 ms
signal clk: std_logic := '0';
signal r,g,b: std_logic := '0';
signal v : std_logic := '0';
signal h : std_logic := '0';
component display is
port (
clk: in std_logic := '0';
rst: in std_logic := '0';
ena: in std_logic := '0';
hs: out std_logic := '0';
vs: out std_logic := '0';
red_o: out std_logic := '0';
grn_o: out std_logic := '0';
blu_o: out std_logic := '0'
);
end component;
begin
display_0 : display
port map(
clk => clk,
rst => '0',
ena => '1',
hs => h,
vs => v,
red_o => r,
grn_o => g,
blu_o => b
);
clk_process: process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
process (clk)
file file_pointer: text is out "../VGASimulator/pixels.txt";
--file file_pointer: text open WRITE_MODE is out "write.txt";
variable line_el: line;
variable last_h,last_v,last_r,last_g,last_b : std_logic;
variable x,y,last_y,h_changes,v_changes : integer := 0;
variable enter,updated_y,logger : boolean := false;
begin
if rising_edge(clk) then
if (enter = true) then
enter := false;
if(x >= MIN_X and x < 350 + MIN_X and y >= MIN_Y and y < 350 + MIN_Y) then
--report integer'image(x - MIN_X) & ":" & integer'image(y - MIN_Y) & " " & std_logic'image(r) & std_logic'image(g) & std_logic'image(b);
write(line_el, integer'image(x - MIN_X));
write(line_el, string'(" "));
write(line_el, integer'image(y - MIN_Y));
write(line_el, string'(" "));
write(line_el, std_logic'image(r));
write(line_el, string'(" "));
write(line_el, std_logic'image(g));
write(line_el, string'(" "));
write(line_el, std_logic'image(b));
writeline(file_pointer, line_el); -- write the contents into the file.
last_r := r;
last_g := g;
last_b := b;
last_y := y;
end if;
x := x + 1;
updated_y := false;
if(x = 800) then
if(not updated_y) then
y := y + 1;
x := 0;
updated_y := true;
end if;
end if;
if(y = 525) then
x := 0;
y := 0;
end if;
else
enter := true;
end if;
end if;
end process;
end;
|
gpl-3.0
|
455ba5a03056dd23ec364402d9ef0d64
| 0.423739 | 3.85 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/polynomial_syndrome_computing_n.vhd
| 1 | 36,590 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Polynomial_Syndrome_Computing_N
-- Module Name: Polynomial_Syndrome_Computing_N
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st and 3rd step in Goppa Decoding.
--
-- This circuit can find the roots of polynomial sigma and compute the syndrome from
-- the received ciphertext. The algorithm run by the circuit is chosen from one of the inputs.
-- Both circuits were joined into the same, because several computing parts are reused in
-- the computations, therefore this circuit needs less area than two apart.
--
-- For the computation this circuit applies the Horner scheme during finding roots, where at each stage
-- an accumulator is multiplied by respective x and then added accumulated with coefficient.
-- In Horner scheme algorithm, it begin from the most significative coefficient until reaches
-- lesser significative coefficient.
--
-- In syndrome generation it is applied alternant syndrome generation, where at each pipeline
-- stage is computed one syndrome iteration. A syndrome iteration is the multiplication of
-- one powering element by one support element.
--
-- For area reduction this circuit were optimized in version polynomial_syndrome_computing_n_v2.
--
-- The circuits parameters
--
-- number_of_pipelines :
--
-- Number of pipelines used in the circuit to test the support elements and
-- correct the message. Each pipeline needs at least 2 memory ram to store
-- intermediate results.
--
-- pipeline_size :
--
-- The number of stages the pipeline has. More stages means more values of value_sigma
-- are tested at once.
--
-- size_pipeline_size :
--
-- The number of bits necessary to store the pipeline_size.
-- This number is ceil(log2(pipeline_size))
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- polynomial_degree :
--
-- The polynomial degree to be evaluated. Therefore the polynomial has
-- polynomial_degree+1 coefficients. This parameters depends of the Goppa code used.
--
-- size_polynomial_degree :
--
-- The number of bits necessary to store polynomial_degree.
-- This number is ceil(log2(polynomial_degree+1))
--
-- number_of_values_x :
--
-- The size of the memory that holds all support elements. This parameter
-- depends of the Goppa code used.
--
-- size_number_of_values_x :
-- The number of bits necessary to store all support elements.
-- this number is ceil(log2(number_of_values_x)).
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- pipeline_polynomial_calc_v3 Rev 1.0
-- controller_polynomial_computing Rev 1.0
-- controller_syndrome_computing Rev 1.0
-- pow2_gf_2_m Rev 1.0
-- shift_register_rst_nbits Rev 1.0
-- shift_register_nbits Rev 1.0
-- register_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_increment_decrement_load_rst_nbits Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity polynomial_syndrome_computing_n is
Generic (
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 28;
-- size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 11;
-- number_of_errors : integer := 27;
-- size_number_of_errors : integer := 5;
-- number_of_support_elements: integer := 2048;
-- size_number_of_support_elements : integer := 11
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 51;
-- size_pipeline_size : integer := 6;
-- gf_2_m : integer range 1 to 20 := 11;
-- number_of_errors : integer := 50;
-- size_number_of_errors : integer := 6;
-- number_of_support_elements: integer := 2048;
-- size_number_of_support_elements : integer := 11
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 67;
-- size_pipeline_size : integer := 6;
-- gf_2_m : integer range 1 to 20 := 12;
-- number_of_errors : integer := 66;
-- size_number_of_errors : integer := 7;
-- number_of_support_elements : integer := 3307;
-- size_number_of_support_elements : integer := 12;
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 33;
-- size_pipeline_size : integer := 6;
-- gf_2_m : integer range 1 to 20 := 12;
-- number_of_errors : integer := 32;
-- size_number_of_errors : integer := 6;
-- number_of_support_elements: integer := 2528;
-- size_number_of_support_elements : integer := 12
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7;
-- number_of_support_elements: integer := 2816;
-- size_number_of_support_elements : integer := 12
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7;
-- number_of_support_elements: integer := 3328;
-- size_number_of_support_elements : integer := 12
-- QD-GOPPA [7296, 5632, 128, 13] --
number_of_pipelines : integer := 1;
pipeline_size : integer := 2;
size_pipeline_size : integer := 2;
gf_2_m : integer range 1 to 20 := 13;
number_of_errors : integer := 128;
size_number_of_errors : integer := 8;
number_of_support_elements: integer := 7296;
size_number_of_support_elements : integer := 13
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_message : in STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_h : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
computation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
address_value_error : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_value_error : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_error : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0)
);
end polynomial_syndrome_computing_n;
architecture RTL of polynomial_syndrome_computing_n is
component pipeline_polynomial_calc_v3
Generic (
gf_2_m : integer range 1 to 20;
size : integer
);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((((gf_2_m)*size) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((size - 1) downto 0);
reg_x_rst : in STD_LOGIC_VECTOR((size - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((((gf_2_m)*size) - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component pow2_gf_2_m
Generic(
gf_2_m : integer range 1 to 20
);
Port(
a : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0)
);
end component;
component shift_register_rst_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component shift_register_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component register_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_increment_decrement_load_rst_nbits
Generic (
size : integer;
increment_value : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
increment_decrement : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component controller_polynomial_computing
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_load_x_values : in STD_LOGIC;
last_store_x_values : in STD_LOGIC;
limit_polynomial_degree : in STD_LOGIC;
pipeline_ready : in STD_LOGIC;
evaluation_data_in : out STD_LOGIC;
reg_write_enable_rst : out STD_LOGIC;
ctr_load_x_address_ce : out STD_LOGIC;
ctr_load_x_address_rst : out STD_LOGIC;
ctr_store_x_address_ce : out STD_LOGIC;
ctr_store_x_address_rst : out STD_LOGIC;
reg_first_values_ce : out STD_LOGIC;
reg_first_values_rst : out STD_LOGIC;
ctr_address_polynomial_ce : out STD_LOGIC;
ctr_address_polynomial_rst : out STD_LOGIC;
reg_x_rst_rst : out STD_LOGIC;
shift_polynomial_ce_ce : out STD_LOGIC;
shift_polynomial_ce_rst : out STD_LOGIC;
last_coefficients : out STD_LOGIC;
evaluation_finalized : out STD_LOGIC
);
end component;
component controller_syndrome_computing
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_load_x_values : in STD_LOGIC;
last_store_x_values : in STD_LOGIC;
last_syndrome_value : in STD_LOGIC;
final_syndrome_evaluation : in STD_LOGIC;
pipeline_ready : in STD_LOGIC;
evaluation_data_in : out STD_LOGIC;
reg_write_enable_rst : out STD_LOGIC;
ctr_load_x_address_ce : out STD_LOGIC;
ctr_load_x_address_rst : out STD_LOGIC;
ctr_store_x_address_ce : out STD_LOGIC;
ctr_store_x_address_rst : out STD_LOGIC;
reg_first_values_ce : out STD_LOGIC;
reg_first_values_rst : out STD_LOGIC;
ctr_address_syndrome_ce : out STD_LOGIC;
ctr_address_syndrome_load : out STD_LOGIC;
ctr_address_syndrome_increment_decrement : out STD_LOGIC;
ctr_address_syndrome_rst : out STD_LOGIC;
reg_store_temporary_syndrome_ce : out STD_LOGIC;
reg_final_syndrome_evaluation_ce : out STD_LOGIC;
reg_final_syndrome_evaluation_rst : out STD_LOGIC;
finalize_syndrome : out STD_LOGIC;
shift_polynomial_ce_ce : out STD_LOGIC;
shift_polynomial_ce_rst : out STD_LOGIC;
shift_syndrome_data_in : out STD_LOGIC;
shift_syndrome_mode_rst : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
calculation_finalized : out STD_LOGIC
);
end component;
signal pipeline_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal pipeline_value_polynomial : STD_LOGIC_VECTOR(((gf_2_m)*(pipeline_size)*(number_of_pipelines) - 1) downto 0);
signal pipeline_value_codeword : STD_LOGIC_VECTOR(((pipeline_size)*(number_of_pipelines) - 1) downto 0);
signal square_value_h : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal new_value_intermediate_syndrome : STD_LOGIC_VECTOR(((gf_2_m)*(pipeline_size)*(number_of_pipelines) - 1) downto 0);
constant coefficient_zero : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
constant first_acc : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
constant first_x_pow : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(1, gf_2_m));
signal reg_polynomial_coefficients_d : STD_LOGIC_VECTOR((((gf_2_m)*pipeline_size) - 1) downto 0);
signal reg_polynomial_coefficients_ce : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal reg_polynomial_coefficients_q : STD_LOGIC_VECTOR((((gf_2_m)*pipeline_size) - 1) downto 0);
signal reg_x_rst_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_x_rst_ce : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal reg_x_rst_rst : STD_LOGIC;
signal reg_x_rst_q : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal reg_x_rst : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal shift_polynomial_ce_data_in : STD_LOGIC;
signal shift_polynomial_ce_ce : STD_LOGIC;
signal shift_polynomial_ce_rst : STD_LOGIC;
constant shift_polynomial_ce_rst_value : STD_LOGIC_VECTOR(pipeline_size downto 0) := std_logic_vector(to_unsigned(1, pipeline_size+1));
signal shift_polynomial_ce_q : STD_LOGIC_VECTOR(pipeline_size downto 0);
signal finalize_syndrome : STD_LOGIC;
signal shift_syndrome_mode_data_in : STD_LOGIC;
signal shift_syndrome_mode_rst : STD_LOGIC;
constant shift_syndrome_mode_rst_value : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0) := std_logic_vector(to_unsigned(1, pipeline_size));
signal shift_syndrome_mode_q : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal ctr_load_x_address_ce : STD_LOGIC;
signal ctr_load_x_address_rst : STD_LOGIC;
constant ctr_load_x_address_rst_value : STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0) := std_logic_vector(to_unsigned(0, size_number_of_support_elements));
signal ctr_load_x_address_q : STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
signal ctr_store_x_address_ce : STD_LOGIC;
signal ctr_store_x_address_rst : STD_LOGIC;
constant ctr_store_x_address_rst_value : STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0) := std_logic_vector(to_unsigned(0, size_number_of_support_elements));
signal ctr_store_x_address_q : STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
signal ctr_address_polynomial_syndrome_d : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0);
signal ctr_address_polynomial_syndrome_ce : STD_LOGIC;
signal ctr_address_polynomial_syndrome_load : STD_LOGIC;
signal ctr_address_polynomial_syndrome_increment_decrement : STD_LOGIC;
signal ctr_address_polynomial_syndrome_rst : STD_LOGIC;
signal ctr_address_polynomial_syndrome_rst_value : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0) := std_logic_vector(to_unsigned(number_of_errors*2, size_number_of_errors+1));
signal ctr_address_polynomial_syndrome_q : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0);
signal reg_store_temporary_syndrome_d : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0);
signal reg_store_temporary_syndrome_ce : STD_LOGIC;
signal reg_store_temporary_syndrome_q : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0);
signal reg_first_values_ce : STD_LOGIC;
signal reg_first_values_rst : STD_LOGIC;
constant reg_first_values_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "1";
signal reg_first_values_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_final_syndrome_evaluation_ce : STD_LOGIC;
signal reg_final_syndrome_evaluation_rst : STD_LOGIC;
constant reg_final_syndrome_evaluation_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_final_syndrome_evaluation_q : STD_LOGIC_VECTOR(0 downto 0);
signal evaluation_data_in : STD_LOGIC;
signal evaluation_data_out : STD_LOGIC;
signal reg_write_enable_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_write_enable_rst : STD_LOGIC;
constant reg_write_enable_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_write_enable_q : STD_LOGIC_VECTOR(0 downto 0);
signal pipeline_ready : STD_LOGIC;
signal limit_polynomial_degree : STD_LOGIC;
signal last_syndrome_value : STD_LOGIC;
signal final_syndrome_evaluation : STD_LOGIC;
signal last_coefficients : STD_LOGIC;
signal last_load_x_values : STD_LOGIC;
signal last_store_x_values : STD_LOGIC;
signal value_evaluated : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal last_evaluations : STD_LOGIC;
signal is_error_position : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
constant error_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal message_data_in : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal message_data_q : STD_LOGIC_VECTOR((((number_of_pipelines)*(pipeline_size+1)) - 1) downto 0);
signal message_data_out : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal poly_reg_polynomial_coefficients_d : STD_LOGIC_VECTOR(((gf_2_m)*(pipeline_size) - 1) downto 0);
constant poly_ctr_address_polynomial_rst_value : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0) := std_logic_vector(to_unsigned(number_of_errors, size_number_of_errors+1));
signal poly_evaluation_data_in : STD_LOGIC;
signal poly_reg_write_enable_rst : STD_LOGIC;
signal poly_ctr_load_x_address_ce : STD_LOGIC;
signal poly_ctr_load_x_address_rst : STD_LOGIC;
signal poly_ctr_store_x_address_ce : STD_LOGIC;
signal poly_ctr_store_x_address_rst : STD_LOGIC;
signal poly_reg_first_values_ce : STD_LOGIC;
signal poly_reg_first_values_rst : STD_LOGIC;
signal poly_ctr_address_polynomial_ce : STD_LOGIC;
signal poly_ctr_address_polynomial_rst : STD_LOGIC;
signal poly_reg_x_rst_rst : STD_LOGIC;
signal poly_shift_polynomial_ce_ce : STD_LOGIC;
signal poly_shift_polynomial_ce_rst : STD_LOGIC;
signal poly_last_coefficients : STD_LOGIC;
signal poly_evaluation_finalized : STD_LOGIC;
signal synd_reg_polynomial_coefficients_d : STD_LOGIC_VECTOR(((gf_2_m)*(pipeline_size) - 1) downto 0);
constant synd_ctr_address_syndrome_rst_value : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0) := std_logic_vector(to_unsigned(number_of_errors*2, size_number_of_errors+1));
signal synd_evaluation_data_in : STD_LOGIC;
signal synd_reg_write_enable_rst : STD_LOGIC;
signal synd_ctr_load_x_address_ce : STD_LOGIC;
signal synd_ctr_load_x_address_rst : STD_LOGIC;
signal synd_ctr_store_x_address_ce : STD_LOGIC;
signal synd_ctr_store_x_address_rst : STD_LOGIC;
signal synd_reg_first_values_ce : STD_LOGIC;
signal synd_reg_first_values_rst : STD_LOGIC;
signal synd_ctr_address_syndrome_load : STD_LOGIC;
signal synd_ctr_address_syndrome_ce : STD_LOGIC;
signal synd_ctr_address_syndrome_increment_decrement : STD_LOGIC;
signal synd_ctr_address_syndrome_rst : STD_LOGIC;
signal synd_reg_store_temporary_syndrome_ce : STD_LOGIC;
signal synd_reg_final_syndrome_evaluation_ce : STD_LOGIC;
signal synd_reg_final_syndrome_evaluation_rst : STD_LOGIC;
signal synd_finalize_syndrome : STD_LOGIC;
signal synd_shift_polynomial_ce_ce : STD_LOGIC;
signal synd_shift_polynomial_ce_rst : STD_LOGIC;
signal synd_shift_syndrome_mode_data_in : STD_LOGIC;
signal synd_shift_syndrome_mode_rst : STD_LOGIC;
signal synd_write_enable_new_value_syndrome : STD_LOGIC;
signal synd_calculation_finalized : STD_LOGIC;
begin
pipelines : for I in 0 to (number_of_pipelines - 1) generate
square_I : entity work.pow2_gf_2_m(Software_POLYNOMIAL)
Generic Map(gf_2_m => gf_2_m)
Port Map(
a => value_h(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
o => square_value_h(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)))
);
pipeline_I : pipeline_polynomial_calc_v3
Generic Map (
gf_2_m => gf_2_m,
size => pipeline_size
)
Port Map(
value_x => value_x(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
value_polynomial => pipeline_value_polynomial((((gf_2_m)*pipeline_size*(I + 1)) - 1) downto (((gf_2_m)*pipeline_size*(I)))),
value_acc => pipeline_value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
value_codeword => pipeline_value_codeword(((pipeline_size)*(I + 1) - 1) downto ((pipeline_size)*(I))),
reg_x_rst => reg_x_rst,
mode_polynomial_syndrome => mode_polynomial_syndrome,
clk => clk,
new_value_acc => value_evaluated(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
new_value_syndrome => new_value_intermediate_syndrome((((gf_2_m)*pipeline_size*(I + 1)) - 1) downto (((gf_2_m)*pipeline_size*(I))))
);
pipeline_value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) when (reg_first_values_q(0) = '0') else
square_value_h(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) when (mode_polynomial_syndrome = '1') else
first_acc;
shift_message : shift_register_nbits
Generic Map(size => pipeline_size + 1)
Port Map(
data_in => message_data_in(I),
clk => clk,
ce => '1',
q => message_data_q(((pipeline_size + 1)*(I + 1) - 1) downto ((pipeline_size + 1)*(I))),
data_out => message_data_out(I)
);
pipeline_value_codeword(((pipeline_size)*(I + 1) - 1) downto ((pipeline_size)*(I))) <= message_data_q(((pipeline_size + 1)*(I + 1) - 2) downto ((pipeline_size + 1)*(I)));
is_error_position(I) <= '1' when value_evaluated(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) = error_value else '0';
message_data_in(I) <= value_message(I);
new_value_message(I) <= (not message_data_out(I)) when is_error_position(I) = '1' else message_data_out(I);
value_error(I) <= is_error_position(I);
first_case : if I = 0 generate
pipeline_value_polynomial((((gf_2_m)*pipeline_size*(I+1)) - 1) downto (((gf_2_m)*pipeline_size*I))) <= reg_polynomial_coefficients_q;
end generate first_case;
other_cases : if I > 0 generate
pipeline_value_polynomial((((gf_2_m)*pipeline_size*(I+1)) - 1) downto (((gf_2_m)*pipeline_size*I))) <= new_value_intermediate_syndrome((((gf_2_m)*pipeline_size*(I)) - 1) downto (((gf_2_m)*pipeline_size*(I - 1)))) when mode_polynomial_syndrome = '1' else
reg_polynomial_coefficients_q;
end generate other_cases;
end generate;
polynomial : for I in 0 to (pipeline_size - 1) generate
reg_polynomial_coefficients_I : register_nbits
Generic Map (size => gf_2_m)
Port Map(
d => reg_polynomial_coefficients_d(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
clk => clk,
ce => reg_polynomial_coefficients_ce(I),
q => reg_polynomial_coefficients_q(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)))
);
reg_x_rst_I : register_rst_nbits
Generic Map (size => 1)
Port Map(
d => reg_x_rst_d,
clk => clk,
ce => reg_x_rst_ce(I),
rst => reg_x_rst_rst,
rst_value => "0",
q => reg_x_rst_q(I downto I)
);
reg_x_rst(I) <= (reg_x_rst_q(I) or (limit_polynomial_degree and shift_polynomial_ce_q(I)));
poly_reg_polynomial_coefficients_d(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= coefficient_zero when (last_coefficients = '1') else
value_polynomial;
first_case : if I = 0 generate
synd_reg_polynomial_coefficients_d(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= coefficient_zero when (shift_polynomial_ce_q(I) = '1') else
new_value_intermediate_syndrome(((number_of_pipelines-1)*(pipeline_size)*(gf_2_m)+(gf_2_m)*(I + 1) - 1) downto ((number_of_pipelines-1)*(pipeline_size)*(gf_2_m)+(gf_2_m)*(I)));
end generate first_case;
other_cases : if I > 0 generate
synd_reg_polynomial_coefficients_d(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= coefficient_zero when (shift_polynomial_ce_q(I) = '1') else
reg_polynomial_coefficients_q(((gf_2_m)*(I) - 1) downto ((gf_2_m)*(I - 1))) when (shift_syndrome_mode_q(I) = '0') else
new_value_intermediate_syndrome(((number_of_pipelines-1)*(pipeline_size)*(gf_2_m)+(gf_2_m)*(I + 1) - 1) downto ((number_of_pipelines-1)*(pipeline_size)*(gf_2_m)+(gf_2_m)*(I)));
end generate other_cases;
reg_polynomial_coefficients_ce(I) <= ((shift_syndrome_mode_q(I)) or finalize_syndrome) when mode_polynomial_syndrome = '1' else
shift_polynomial_ce_q(I);
end generate;
controller_poly : controller_polynomial_computing
Port Map(
clk => clk,
rst => rst,
last_load_x_values => last_load_x_values,
last_store_x_values => last_store_x_values,
limit_polynomial_degree => limit_polynomial_degree,
pipeline_ready => pipeline_ready,
evaluation_data_in => poly_evaluation_data_in,
reg_write_enable_rst => poly_reg_write_enable_rst,
ctr_load_x_address_ce => poly_ctr_load_x_address_ce,
ctr_load_x_address_rst => poly_ctr_load_x_address_rst,
ctr_store_x_address_ce => poly_ctr_store_x_address_ce,
ctr_store_x_address_rst => poly_ctr_store_x_address_rst,
reg_first_values_ce => poly_reg_first_values_ce,
reg_first_values_rst => poly_reg_first_values_rst,
ctr_address_polynomial_ce => poly_ctr_address_polynomial_ce,
ctr_address_polynomial_rst => poly_ctr_address_polynomial_rst,
reg_x_rst_rst => poly_reg_x_rst_rst,
shift_polynomial_ce_ce => poly_shift_polynomial_ce_ce,
shift_polynomial_ce_rst => poly_shift_polynomial_ce_rst,
last_coefficients => poly_last_coefficients,
evaluation_finalized => poly_evaluation_finalized
);
controller_synd : controller_syndrome_computing
Port Map(
clk => clk,
rst => rst,
last_load_x_values => last_load_x_values,
last_store_x_values => last_store_x_values,
last_syndrome_value => last_syndrome_value,
final_syndrome_evaluation => final_syndrome_evaluation,
pipeline_ready => pipeline_ready,
evaluation_data_in => synd_evaluation_data_in,
reg_write_enable_rst => synd_reg_write_enable_rst,
ctr_load_x_address_ce => synd_ctr_load_x_address_ce,
ctr_load_x_address_rst => synd_ctr_load_x_address_rst,
ctr_store_x_address_ce => synd_ctr_store_x_address_ce,
ctr_store_x_address_rst => synd_ctr_store_x_address_rst,
reg_first_values_ce => synd_reg_first_values_ce,
reg_first_values_rst => synd_reg_first_values_rst,
ctr_address_syndrome_ce => synd_ctr_address_syndrome_ce,
ctr_address_syndrome_load => synd_ctr_address_syndrome_load,
ctr_address_syndrome_increment_decrement => synd_ctr_address_syndrome_increment_decrement,
ctr_address_syndrome_rst => synd_ctr_address_syndrome_rst,
reg_store_temporary_syndrome_ce => synd_reg_store_temporary_syndrome_ce,
reg_final_syndrome_evaluation_ce => synd_reg_final_syndrome_evaluation_ce,
reg_final_syndrome_evaluation_rst => synd_reg_final_syndrome_evaluation_rst,
finalize_syndrome => synd_finalize_syndrome,
shift_polynomial_ce_ce => synd_shift_polynomial_ce_ce,
shift_polynomial_ce_rst => synd_shift_polynomial_ce_rst,
shift_syndrome_data_in => synd_shift_syndrome_mode_data_in,
shift_syndrome_mode_rst => synd_shift_syndrome_mode_rst,
write_enable_new_value_syndrome => synd_write_enable_new_value_syndrome,
calculation_finalized => synd_calculation_finalized
);
shift_polynomial_ce : shift_register_rst_nbits
Generic Map(
size => pipeline_size + 1
)
Port Map(
data_in => shift_polynomial_ce_data_in,
clk => clk,
ce => shift_polynomial_ce_ce,
rst => shift_polynomial_ce_rst,
rst_value => shift_polynomial_ce_rst_value,
q => shift_polynomial_ce_q,
data_out => shift_polynomial_ce_data_in
);
shift_syndrome_mode : shift_register_rst_nbits
Generic Map(
size => pipeline_size
)
Port Map(
data_in => shift_syndrome_mode_data_in,
clk => clk,
ce => '1',
rst => shift_syndrome_mode_rst,
rst_value => shift_syndrome_mode_rst_value,
q => shift_syndrome_mode_q,
data_out => open
);
evaluation : shift_register_nbits
Generic Map(
size => pipeline_size
)
Port Map(
data_in => evaluation_data_in,
clk => clk,
ce => '1',
q => open,
data_out => evaluation_data_out
);
reg_write_enable : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_write_enable_d,
clk => clk,
ce => '1',
rst => reg_write_enable_rst,
rst_value => reg_write_enable_rst_value,
q => reg_write_enable_q
);
ctr_address_polynomial_syndrome : counter_increment_decrement_load_rst_nbits
Generic Map(
size => size_number_of_errors+1,
increment_value => 1,
decrement_value => 1
)
Port Map(
d => ctr_address_polynomial_syndrome_d,
clk => clk,
ce => ctr_address_polynomial_syndrome_ce,
load => ctr_address_polynomial_syndrome_load,
increment_decrement => ctr_address_polynomial_syndrome_increment_decrement,
rst => ctr_address_polynomial_syndrome_rst,
rst_value => ctr_address_polynomial_syndrome_rst_value,
q => ctr_address_polynomial_syndrome_q
);
reg_store_temporary_syndrome : register_nbits
Generic Map(
size => size_number_of_errors+1
)
Port Map(
d => reg_store_temporary_syndrome_d,
clk => clk,
ce => reg_store_temporary_syndrome_ce,
q => reg_store_temporary_syndrome_q
);
ctr_load_x_address : counter_rst_nbits
Generic Map(
size => size_number_of_support_elements,
increment_value => number_of_pipelines
)
Port Map(
clk => clk,
ce => ctr_load_x_address_ce,
rst => ctr_load_x_address_rst,
rst_value => ctr_load_x_address_rst_value,
q => ctr_load_x_address_q
);
ctr_store_x_address : counter_rst_nbits
Generic Map(
size => size_number_of_support_elements,
increment_value => number_of_pipelines
)
Port Map(
clk => clk,
ce => ctr_store_x_address_ce,
rst => ctr_store_x_address_rst,
rst_value => ctr_store_x_address_rst_value,
q => ctr_store_x_address_q
);
reg_first_values : register_rst_nbits
Generic Map(size => 1)
Port Map(
d => "0",
clk => clk,
ce => reg_first_values_ce,
rst => reg_first_values_rst,
rst_value => reg_first_values_rst_value,
q => reg_first_values_q
);
reg_final_syndrome_evaluation : register_rst_nbits
Generic Map(size => 1)
Port Map(
d => "1",
clk => clk,
ce => reg_final_syndrome_evaluation_ce,
rst => reg_final_syndrome_evaluation_rst,
rst_value => reg_final_syndrome_evaluation_rst_value,
q => reg_final_syndrome_evaluation_q
);
new_value_acc <= value_evaluated;
evaluation_data_in <= synd_evaluation_data_in when mode_polynomial_syndrome = '1' else
poly_evaluation_data_in;
reg_write_enable_rst <= synd_reg_write_enable_rst when mode_polynomial_syndrome = '1' else
poly_reg_write_enable_rst;
ctr_load_x_address_ce <= synd_ctr_load_x_address_ce when mode_polynomial_syndrome = '1' else
poly_ctr_load_x_address_ce;
ctr_load_x_address_rst <= synd_ctr_load_x_address_rst when mode_polynomial_syndrome = '1' else
poly_ctr_load_x_address_rst;
ctr_store_x_address_ce <= synd_ctr_store_x_address_ce when mode_polynomial_syndrome = '1' else
poly_ctr_store_x_address_ce;
ctr_store_x_address_rst <= synd_ctr_store_x_address_rst when mode_polynomial_syndrome = '1' else
poly_ctr_store_x_address_rst;
reg_first_values_ce <= synd_reg_first_values_ce when mode_polynomial_syndrome = '1' else
poly_reg_first_values_ce;
reg_first_values_rst <= synd_reg_first_values_rst when mode_polynomial_syndrome = '1' else
poly_reg_first_values_rst;
ctr_address_polynomial_syndrome_ce <= synd_ctr_address_syndrome_ce when mode_polynomial_syndrome = '1' else
poly_ctr_address_polynomial_ce;
ctr_address_polynomial_syndrome_load <= synd_ctr_address_syndrome_load when mode_polynomial_syndrome = '1' else
'0';
ctr_address_polynomial_syndrome_increment_decrement <= synd_ctr_address_syndrome_increment_decrement when mode_polynomial_syndrome = '1' else
'1';
ctr_address_polynomial_syndrome_rst <= synd_ctr_address_syndrome_rst when mode_polynomial_syndrome = '1' else
poly_ctr_address_polynomial_rst;
ctr_address_polynomial_syndrome_rst_value <= synd_ctr_address_syndrome_rst_value when mode_polynomial_syndrome = '1' else
poly_ctr_address_polynomial_rst_value;
reg_store_temporary_syndrome_ce <= synd_reg_store_temporary_syndrome_ce when mode_polynomial_syndrome = '1' else
'0';
reg_x_rst_rst <= '1' when mode_polynomial_syndrome = '1' else
poly_reg_x_rst_rst;
reg_final_syndrome_evaluation_ce <= synd_reg_final_syndrome_evaluation_ce when mode_polynomial_syndrome = '1' else
'0';
reg_final_syndrome_evaluation_rst <= synd_reg_final_syndrome_evaluation_rst when mode_polynomial_syndrome = '1' else
'0';
finalize_syndrome <= synd_finalize_syndrome when mode_polynomial_syndrome = '1' else
'1';
shift_polynomial_ce_ce <= synd_shift_polynomial_ce_ce when mode_polynomial_syndrome = '1' else
poly_shift_polynomial_ce_ce;
shift_polynomial_ce_rst <= synd_shift_polynomial_ce_rst when mode_polynomial_syndrome = '1' else
poly_shift_polynomial_ce_rst;
shift_syndrome_mode_data_in <= synd_shift_syndrome_mode_data_in when mode_polynomial_syndrome = '1' else
'0';
shift_syndrome_mode_rst <= synd_shift_syndrome_mode_rst when mode_polynomial_syndrome = '1' else
'0';
last_coefficients <= '0' when mode_polynomial_syndrome = '1' else
poly_last_coefficients;
computation_finalized <= synd_calculation_finalized when mode_polynomial_syndrome = '1' else
poly_evaluation_finalized;
reg_x_rst_d(0) <= limit_polynomial_degree;
reg_x_rst_ce <= shift_polynomial_ce_q((pipeline_size - 1) downto 0);
reg_polynomial_coefficients_d <= synd_reg_polynomial_coefficients_d when mode_polynomial_syndrome = '1' else
poly_reg_polynomial_coefficients_d;
write_enable_new_value_syndrome <= synd_write_enable_new_value_syndrome when mode_polynomial_syndrome = '1' else
'0';
address_value_polynomial <= ctr_address_polynomial_syndrome_q((size_number_of_errors - 1) downto 0);
address_value_x <= ctr_load_x_address_q;
address_value_acc <= ctr_load_x_address_q;
address_value_message <= ctr_load_x_address_q;
address_new_value_acc <= ctr_store_x_address_q;
address_new_value_message <= ctr_store_x_address_q;
address_value_error <= ctr_store_x_address_q;
address_new_value_syndrome <= ctr_address_polynomial_syndrome_q;
reg_store_temporary_syndrome_d <= ctr_address_polynomial_syndrome_q;
ctr_address_polynomial_syndrome_d <= reg_store_temporary_syndrome_q;
pipeline_ready <= shift_polynomial_ce_q(pipeline_size-1);
limit_polynomial_degree <= '1' when (signed(ctr_address_polynomial_syndrome_q) = to_signed(-1, ctr_address_polynomial_syndrome_q'length)) else '0';
last_syndrome_value <= '1' when (ctr_address_polynomial_syndrome_q = std_logic_vector(to_signed(0, ctr_address_polynomial_syndrome_q'Length))) else '0';
last_evaluations <= limit_polynomial_degree and shift_polynomial_ce_q(pipeline_size);
final_syndrome_evaluation <= reg_final_syndrome_evaluation_q(0);
reg_write_enable_d(0) <= evaluation_data_out;
new_value_syndrome <= reg_polynomial_coefficients_q(((gf_2_m)*(pipeline_size) - 1) downto ((gf_2_m)*(pipeline_size - 1)));
write_enable_new_value_acc <= reg_write_enable_q(0);
write_enable_new_value_message <= '0' when mode_polynomial_syndrome = '1' else
reg_write_enable_q(0) and last_evaluations;
write_enable_value_error <= '0' when mode_polynomial_syndrome = '1' else
reg_write_enable_q(0) and last_evaluations;
last_load_x_values <= '1' when ctr_load_x_address_q = std_logic_vector(to_unsigned(((number_of_support_elements - 1)/number_of_pipelines)*number_of_pipelines, ctr_load_x_address_q'Length)) else '0';
last_store_x_values <= '1' when ctr_store_x_address_q = std_logic_vector(to_unsigned(((number_of_support_elements - 1)/number_of_pipelines)*number_of_pipelines, ctr_load_x_address_q'Length)) else '0';
end RTL;
|
bsd-2-clause
|
578e058d97128b8b36f9b68f80edba6e
| 0.688631 | 2.961794 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-LuGus/TP2-Voltimetro/char_rom.vhd
| 1 | 6,741 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Char_ROM is
generic(
N: integer:= 6;
M: integer:= 3;
W: integer:= 8
);
port(
char_address: in std_logic_vector(5 downto 0);
font_row, font_col: in std_logic_vector(M-1 downto 0);
rom_out: out std_logic
);
end;
architecture p of Char_ROM is
subtype tipoLinea is std_logic_vector(0 to W-1);
type char is array(0 to W-1) of tipoLinea;
constant A: char:= (
"00011000",
"00111100",
"01100110",
"01100110",
"01111110",
"01100110",
"01100110",
"00000000"
);
constant B: char:= (
"01111100",
"01100110",
"01100110",
"01111100",
"01100110",
"01100110",
"01111100",
"00000000"
);
constant C: char:= (
"00111110",
"01100011",
"01100000",
"01100000",
"01100000",
"01100011",
"00111110",
"00000000"
);
constant D: char:= (
"01111100",
"01100110",
"01100011",
"01100011",
"01100011",
"01100110",
"01111100",
"00000000"
);
constant E: char:= (
"01111110",
"01100000",
"01100000",
"01111000",
"01100000",
"01100000",
"01111110",
"00000000"
);
constant F: char:= (
"01111110",
"01100000",
"01100000",
"01111000",
"01100000",
"01100000",
"01100000",
"00000000"
);
constant G: char:= (
"00111100",
"01100010",
"01100000",
"01101110",
"01100110",
"01100110",
"00111100",
"00000000"
);
constant H: char:= (
"01100110",
"01100110",
"01100110",
"01111110",
"01100110",
"01100110",
"01100110",
"00000000"
);
constant N_Char: char:= (
"01100110",
"01100110",
"01110110",
"01110110",
"01101110",
"01101110",
"01100110",
"00000000"
);
constant O: char:= ("00111100",
"01111110",
"11000111",
"11001011",
"11010011",
"11100011",
"01111110",
"00111100"
);
constant ZERO: char:= (
"00111100",
"01111110",
"11000111",
"11001011",
"11010011",
"11100011",
"01111110",
"00111100"
);
constant ONE: char:= (
"00001000",
"00011000",
"00111000",
"00011000",
"00011000",
"00011000",
"01111110",
"00000000");
constant TWO: char:= (
"00111100",
"01100110",
"01100110",
"00001110",
"00011100",
"00111000",
"01110110",
"01111110"
);
constant THREE: char:= (
"01111110",
"01111110",
"00000110",
"01111110",
"01111110",
"00000110",
"01111110",
"01111110"
);
constant FOUR: char:= (
"00100110",
"01100110",
"01100110",
"01111110",
"00000110",
"00000110",
"00000110",
"00000110"
);
constant FIVE: char:= (
"01111110",
"01000110",
"01000000",
"01111100",
"01111110",
"00000010",
"01100010",
"01111110"
);
constant SIX: char:= (
"01111110",
"01000110",
"01000000",
"01000000",
"01111110",
"01100010",
"01100010",
"01111110"
);
constant SEVEN: char:= (
"01111110",
"01100010",
"00000110",
"00001100",
"00011000",
"00011000",
"00011000",
"00011000"
);
constant EIGHT: char:= (
"01111110",
"01000010",
"01000010",
"01000010",
"01111110",
"01000010",
"01000010",
"01111110"
);
constant NINE: char:= (
"01111110",
"01100010",
"01100010",
"00111110",
"00011110",
"00000110",
"00000110",
"00000110"
);
constant COMMA: char:= (
"00000000",
"00000000",
"00000000",
"00000000",
"00011000",
"00011000",
"00001000",
"00010000"
);
constant Err: char:= (
"00000000",
"01111110",
"01111110",
"01100110",
"01100110",
"01111110",
"01111110",
"00000000"
);
constant SPACE: char:= (
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000",
"00000000"
);
constant V: char:= (
"11000011",
"11000011",
"01100110",
"01100110",
"00100100",
"00011000",
"00011000",
"00000000"
);
type memo is array(0 to 255) of tipoLinea;
signal RAM: memo:= (
0 => ZERO(0), 1 => ZERO(1), 2 => ZERO(2), 3 => ZERO(3), 4 => ZERO(4), 5 => ZERO(5), 6 => ZERO(6), 7 => ZERO(7),
8 => ONE(0), 9 => ONE(1), 10 => ONE(2), 11 => ONE(3), 12 => ONE(4), 13 => ONE(5), 14 => ONE(6), 15 => ONE(7),
16 => TWO(0), 17 => TWO(1), 18 => TWO(2), 19 => TWO(3), 20 => TWO(4), 21 => TWO(5), 22 => TWO(6), 23 => TWO(7),
24 => THREE(0), 25 => THREE(1), 26 => THREE(2), 27 => THREE(3), 28 => THREE(4), 29 => THREE(5), 30 => THREE(6), 31 => THREE(7),
32 => FOUR(0), 33 => FOUR(1), 34 => FOUR(2), 35 => FOUR(3), 36 => FOUR(4), 37 => FOUR(5), 38 => FOUR(6), 39 => FOUR(7),
40 => FIVE(0), 41 => FIVE(1), 42 => FIVE(2), 43 => FIVE(3), 44 => FIVE(4), 45 => FIVE(5), 46 => FIVE(6), 47 => FIVE(7),
48 => SIX(0), 49 => SIX(1), 50 => SIX(2), 51 => SIX(3), 52 => SIX(4), 53 => SIX(5), 54 => SIX(6), 55 => SIX(7),
56 => SEVEN(0), 57 => SEVEN(1), 58 => SEVEN(2), 59 => SEVEN(3), 60 => SEVEN(4), 61 => SEVEN(5), 62 => SEVEN(6), 63 => SEVEN(7),
64 => EIGHT(0), 65 => EIGHT(1), 66 => EIGHT(2), 67 => EIGHT(3), 68 => EIGHT(4), 69 => EIGHT(5), 70 => EIGHT(6), 71 => EIGHT(7),
72 => NINE(0), 73 => NINE(1), 74 => NINE(2), 75 => NINE(3), 76 => NINE(4), 77 => NINE(5), 78 => NINE(6), 79 => NINE(7),
80 => COMMA(0), 81 => COMMA(1), 82 => COMMA(2), 83 => COMMA(3), 84 => COMMA(4), 85 => COMMA(5), 86 => COMMA(6), 87 => COMMA(7),
88 => SPACE(0), 89 => SPACE(1), 90 => SPACE(2), 91 => SPACE(3), 92 => SPACE(4), 93 => SPACE(5), 94 => SPACE(6), 95 => SPACE(7),
96 => V(0), 97 => V(1), 98 => V(2), 99 => V(3), 100 => V(4), 101 => V(5), 102 => V(6), 103 => V(7),
104 to 255 => "00000000"
);
signal char_addr_aux: std_logic_vector(8 downto 0);
begin
char_addr_aux <= char_address & font_row;
rom_out <= RAM(conv_integer(char_addr_aux))(conv_integer(font_col));
end;
|
gpl-3.0
|
3431928e2e873cbaa8c36cfe4254617b
| 0.461801 | 3.112188 | false | false | false | false |
rajvinjamuri/ECE385_VHDL
|
ball.vhd
| 1 | 34,537 |
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Ball.vhd --
-- --
-- Modeled off ball.vhd version by Stephen Kempf and Viral Mehta --
-- --
-- by Raj Vinjamuri and Sai Koppula --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
---------------------------------------------------------------------------
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ball is
Port ( Le, Ri : in std_logic; --same as keyboard input. Used to dictate ball reaction
--Up, Do, Le, Ri : in std_logic;
clk : in std_logic;
Reset : in std_logic;
frame_clk : in std_logic;
StartMove : in std_logic;
seedIn : in std_logic_vector(17 downto 0);
BallX : out std_logic_vector(10 downto 0);
BallY : out std_logic_vector(10 downto 0);
BallS : out std_logic_vector(10 downto 0);
PaddleX : in std_logic_vector(10 downto 0);
PaddleY : in std_logic_vector(10 downto 0);
PaddleS : in std_logic_vector(10 downto 0);
BricksX : in std_logic_vector(219 downto 0);
BricksY : in std_logic_vector(219 downto 0);
BricksOn : in std_logic_vector(19 downto 0);
paddle_loss_status : out std_logic_vector(1 downto 0));
end ball;
architecture Behavioral of ball is
--signal L, R : std_logic_vector (0 downto 0); --added signals to use for math needed to change motion vars
signal paddle_loss_statusSig : std_logic_vector(1 downto 0);
signal Ball_X_pos, Ball_X_motion, Ball_Y_pos, Ball_Y_motion : std_logic_vector(10 downto 0);
signal Ball_Size : std_logic_vector(10 downto 0);
constant Ball_X_Center : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(320, 11); --Center position on the X axis
constant Ball_Y_Center : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(240, 11); --Center position on the Y axis
constant Ball_Y_Set : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(450, 11); --Center position on the Y axis
constant Ball_X_Min : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(0, 11); --Leftmost point on the X axis
constant Ball_X_Max : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(639, 11); --Rightmost point on the X axis
constant Ball_Y_Min : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(0, 11); --Topmost point on the Y axis
constant Ball_Y_Max : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(470, 11); --Bottommost point on the Y axis
signal Ball_X_Step : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(1, 11); --Step size on the X axis (modified)
signal Ball_Y_Step : std_logic_vector(10 downto 0) := CONV_STD_LOGIC_VECTOR(2, 11); --Step size on the Y axis (modified)
signal Brick_Width, Brick_Height : std_logic_vector(10 downto 0);
signal BrickX, BrickY : std_logic_vector(10 downto 0);
signal BrickOn : std_logic;
begin
Ball_Size <= CONV_STD_LOGIC_VECTOR(4, 11); -- assigns the value 4 as a 10-digit binary number, ie "0000000100"
-- Ball_Y_Step <= not(Ball_Y_Step) + '1';
--U(0) <= Up; --set internal signal/vars
--D(0) <= Do;
--L(0) <= Le;
--R(0) <= Ri;
Move_Ball: process(Reset, frame_clk, Ball_Size)
begin
--Temp Brick info
Brick_Width <= CONV_STD_LOGIC_VECTOR(60, 11);
Brick_Height <= CONV_STD_LOGIC_VECTOR(20, 11);
-------Randomizing y-step value with seed---------------
if (seedIn(2) = '1') then
Ball_X_Step <= "00000000010";
else
Ball_X_Step <= "00000000001";
end if;
-------[START] Reset and Initial Conditions--------------
if(Reset = '1') then --Asynchronous Reset
Ball_Y_Motion <= "00000000000"; --changed
Ball_X_Motion <= "00000000000";
-- if (StartMove = '1') then
-- if (seedIn(3) = '1') then
-- Ball_Y_Motion <= not(Ball_Y_Step) + '1'; --all the initial movement settings
-- Ball_X_Motion <= Ball_X_Step;
-- else
-- Ball_Y_Motion <= not(Ball_Y_Step) + '1'; --all the initial movement settings
-- Ball_X_Motion <= not(Ball_X_Step) + '1';
-- end if;
-- end if;
paddle_loss_statusSig <= "00";
Ball_Y_pos <= Ball_Y_Set;
Ball_X_pos <= Ball_X_Center;
-------[END] Reset and Initial Conditions--------------
elsif(rising_edge(frame_clk)) then
paddle_loss_statusSig(1) <= '0'; --change paddle-hit back to zero on next interaction-cycle
if (StartMove = '1') then
if (seedIn(3) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1'; --all the initial movement settings
Ball_X_Motion <= Ball_X_Step;
else
Ball_Y_Motion <= not(Ball_Y_Step) + '1'; --all the initial movement settings
Ball_X_Motion <= not(Ball_X_Step) + '1';
end if;
else
Ball_Y_Motion <= Ball_Y_Motion;
Ball_X_Motion <= Ball_X_Motion;
end if;
-------Wall Interactions Below (X-axis change in ball movement)---------------
if ((Ball_X_Pos - Ball_Size - "00000000100" <= Ball_X_Min) OR (Ball_X_Pos - Ball_Size - "00000000100" >= Ball_X_Max) ) then --change here to fix going off screen
Ball_X_Pos <= Ball_X_Min + Ball_Size;
Ball_X_Motion <= Ball_X_Step;
elsif (Ball_X_Pos + Ball_Size >= Ball_X_Max) then
Ball_X_Pos <= Ball_X_Max - Ball_Size;
Ball_X_Motion <= not(Ball_X_Step) + '1'; --change here to fix going off screen
--redundancy in wall conditions:
elsif (Ball_X_pos + Ball_Size >= Ball_X_Max) then -- Ball is at the right edge, BOUNCE!
Ball_X_Motion <= not(Ball_X_Step) + '1'; --2's complement.
elsif((Ball_X_Pos - Ball_Size - "00000000100" <= Ball_X_Min) OR (Ball_X_Pos - Ball_Size - "00000000100" >= Ball_X_Max) )then -- Ball is at the left edge, BOUNCE!
Ball_X_Motion <= Ball_X_Step;
-- end if;
-------Wall Interactions Below (Y-axis change in ball movement)---------------
elsif (Ball_Y_Pos - Ball_Size - Ball_Y_Step <= Ball_Y_Min) then --change here to fix going off screen
Ball_Y_Pos <= Ball_Y_Min + Ball_Size;
Ball_Y_Motion <= Ball_Y_Step;
--elsif (Ball_Y_Pos + Ball_Size >= Ball_Y_Max) then
--Ball_Y_Pos <= Ball_Y_Max - Ball_Size;
--Ball_Y_Motion <= not(Ball_Y_Step) + '1'; --change here to fix going off screen
--elsif(Ball_Y_pos - Ball_Size <= Ball_Y_Min) then -- Ball is at the top edge, BOUNCE! If at bottom then dealt with in loss conditions
--Ball_Y_Motion <= Ball_Y_Step;
-- end if;
-------Losing Condition Check/Set (Ball Movement and Game_Status change)---------------
elsif (Ball_Y_pos + Ball_Size >= Ball_Y_Max) then -- Ball is at the bottom edge, go to the right
if (Ball_X_Motion < 0) then --if going left then go right
Ball_X_Motion <= not(Ball_X_Step) + '1'; --2's complement.
end if;
if (paddle_loss_statusSig(0) = '1') then Ball_Y_Motion <= "00000000000"; --soon after the bounce, make it zero
end if;
paddle_loss_statusSig <= "01"; --indicate loss
-------Difficulty Change Below (Various change in ball movement)---------------
--elsif (U(0) = '1') then Ball_Y_Motion <= Ball_Y_Step + "0000000001"; --change difficulty up on "W"
--elsif (D(0) = '1') then Ball_Y_Motion <= Ball_Y_Step - "0000000001"; --change difficulty down on "S"
-------Paddle Interactions Below (Y-axis and X-axis change in ball movement)---------------
elsif((Ball_Y_Pos + Ball_Size >= PaddleY - (PaddleS)) AND ((Ball_X_Pos + Ball_Size >= PaddleX - ("00000000110" * PaddleS) AND Ball_X_Pos + Ball_Size <= PaddleX + ("00000000110"*PaddleS))
OR (Ball_X_Pos - Ball_Size >= PaddleX - ("00000000110" * PaddleS) AND Ball_X_Pos - Ball_Size <= PaddleX + ("00000000110"*PaddleS)))) then
if (Le = '1') then --depending on paddle movement, have ball go in according X-direction
Ball_X_Motion <= not(Ball_X_Step) + '1'; --go left
elsif (Ri = '1') then
Ball_X_Motion <= Ball_X_Step; --go right
end if;
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
paddle_loss_statusSig(1) <= '1'; --indicate paddle hit
elsif(Ball_X_Pos - Ball_Size <= PaddleX + ("00000000110"*PaddleS) AND Ball_X_Pos - Ball_Size >= PaddleX - ("0000000110"*PaddleS) AND Ball_Y_Pos - Ball_Size >= PaddleY - PaddleS AND Ball_Y_Pos + Ball_Size >= PaddleY + PaddleS) then
Ball_X_Motion <= Ball_X_Step;
paddle_loss_statusSig(1) <= '1'; --indicate paddle hit
elsif(Ball_X_Pos + Ball_Size <= PaddleX + ("00000000110"*PaddleS) AND Ball_X_Pos + Ball_Size >= PaddleX - ("0000000110"*PaddleS) AND Ball_Y_Pos - Ball_Size >= PaddleY - PaddleS AND Ball_Y_Pos + Ball_Size >= PaddleY + PaddleS) then
Ball_X_Motion <= not(Ball_X_Step) + '1';
paddle_loss_statusSig(1) <= '1'; --indicate paddle hit
end if;
------Brick Interactions Below (Y-axis change in ball movement)----------------
if(Ball_Y_Pos - Ball_Size <= BricksY(10 downto 0) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(10 downto 0) AND Ball_X_Pos + Ball_Size >= BricksX(10 downto 0) AND Ball_X_Pos - Ball_Size <= BricksX(10 downto 0) + Brick_Width AND BricksOn(0) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(10 downto 0) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(10 downto 0) AND Ball_X_Pos + Ball_Size >= BricksX(10 downto 0) AND Ball_X_Pos - Ball_Size <= BricksX(10 downto 0) + Brick_Width AND BricksOn(0) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(21 downto 11) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(21 downto 11) AND Ball_X_Pos + Ball_Size >= BricksX(21 downto 11) AND Ball_X_Pos - Ball_Size <= BricksX(21 downto 11) + Brick_Width AND BricksOn(1) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(21 downto 11) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(21 downto 11) AND Ball_X_Pos + Ball_Size >= BricksX(21 downto 11) AND Ball_X_Pos - Ball_Size <= BricksX(21 downto 11) + Brick_Width AND BricksOn(1) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(32 downto 22) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(32 downto 22) AND Ball_X_Pos + Ball_Size >= BricksX(32 downto 22) AND Ball_X_Pos - Ball_Size <= BricksX(32 downto 22) + Brick_Width AND BricksOn(2) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(32 downto 22) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(32 downto 22) AND Ball_X_Pos + Ball_Size >= BricksX(32 downto 22) AND Ball_X_Pos - Ball_Size <= BricksX(32 downto 22) + Brick_Width AND BricksOn(2) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(43 downto 33) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(43 downto 33) AND Ball_X_Pos + Ball_Size >= BricksX(43 downto 33) AND Ball_X_Pos - Ball_Size <= BricksX(43 downto 33) + Brick_Width AND BricksOn(3) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(43 downto 33) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(43 downto 33) AND Ball_X_Pos + Ball_Size >= BricksX(43 downto 33) AND Ball_X_Pos - Ball_Size <= BricksX(43 downto 33) + Brick_Width AND BricksOn(3) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(54 downto 44) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(54 downto 44) AND Ball_X_Pos + Ball_Size >= BricksX(54 downto 44) AND Ball_X_Pos - Ball_Size <= BricksX(54 downto 44) + Brick_Width AND BricksOn(4) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(54 downto 44) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(54 downto 44) AND Ball_X_Pos + Ball_Size >= BricksX(54 downto 44) AND Ball_X_Pos - Ball_Size <= BricksX(54 downto 44) + Brick_Width AND BricksOn(4) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(65 downto 55) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(65 downto 55) AND Ball_X_Pos + Ball_Size >= BricksX(65 downto 55) AND Ball_X_Pos - Ball_Size <= BricksX(65 downto 55) + Brick_Width AND BricksOn(5) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(65 downto 55) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(65 downto 55) AND Ball_X_Pos + Ball_Size >= BricksX(65 downto 55) AND Ball_X_Pos - Ball_Size <= BricksX(65 downto 55) + Brick_Width AND BricksOn(5) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(76 downto 66) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(76 downto 66) AND Ball_X_Pos + Ball_Size >= BricksX(76 downto 66) AND Ball_X_Pos - Ball_Size <= BricksX(76 downto 66) + Brick_Width AND BricksOn(6) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(76 downto 66) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(76 downto 66) AND Ball_X_Pos + Ball_Size >= BricksX(76 downto 66) AND Ball_X_Pos - Ball_Size <= BricksX(76 downto 66) + Brick_Width AND BricksOn(6) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(87 downto 77) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(87 downto 77) AND Ball_X_Pos + Ball_Size >= BricksX(87 downto 77) AND Ball_X_Pos - Ball_Size <= BricksX(87 downto 77) + Brick_Width AND BricksOn(7) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(87 downto 77) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(87 downto 77) AND Ball_X_Pos + Ball_Size >= BricksX(87 downto 77) AND Ball_X_Pos - Ball_Size <= BricksX(87 downto 77) + Brick_Width AND BricksOn(7) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(98 downto 88) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(98 downto 88) AND Ball_X_Pos + Ball_Size >= BricksX(98 downto 88) AND Ball_X_Pos - Ball_Size <= BricksX(98 downto 88) + Brick_Width AND BricksOn(8) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(98 downto 88) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(98 downto 88) AND Ball_X_Pos + Ball_Size >= BricksX(98 downto 88) AND Ball_X_Pos - Ball_Size <= BricksX(98 downto 88) + Brick_Width AND BricksOn(8) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(109 downto 99) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(109 downto 99) AND Ball_X_Pos + Ball_Size >= BricksX(109 downto 99) AND Ball_X_Pos - Ball_Size <= BricksX(109 downto 99) + Brick_Width AND BricksOn(9) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(109 downto 99) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(109 downto 99) AND Ball_X_Pos + Ball_Size >= BricksX(109 downto 99) AND Ball_X_Pos - Ball_Size <= BricksX(109 downto 99) + Brick_Width AND BricksOn(9) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(120 downto 110) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(120 downto 110) AND Ball_X_Pos + Ball_Size >= BricksX(120 downto 110) AND Ball_X_Pos - Ball_Size <= BricksX(120 downto 110) + Brick_Width AND BricksOn(10) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(120 downto 110) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(120 downto 110) AND Ball_X_Pos + Ball_Size >= BricksX(120 downto 110) AND Ball_X_Pos - Ball_Size <= BricksX(120 downto 110) + Brick_Width AND BricksOn(10) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(131 downto 121) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(131 downto 121) AND Ball_X_Pos + Ball_Size >= BricksX(131 downto 121) AND Ball_X_Pos - Ball_Size <= BricksX(131 downto 121) + Brick_Width AND BricksOn(11) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(131 downto 121) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(131 downto 121) AND Ball_X_Pos + Ball_Size >= BricksX(131 downto 121) AND Ball_X_Pos - Ball_Size <= BricksX(131 downto 121) + Brick_Width AND BricksOn(11) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(142 downto 132) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(142 downto 132) AND Ball_X_Pos + Ball_Size >= BricksX(142 downto 132) AND Ball_X_Pos - Ball_Size <= BricksX(142 downto 132) + Brick_Width AND BricksOn(12) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(142 downto 132) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(142 downto 132) AND Ball_X_Pos + Ball_Size >= BricksX(142 downto 132) AND Ball_X_Pos - Ball_Size <= BricksX(142 downto 132) + Brick_Width AND BricksOn(12) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(153 downto 143) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(153 downto 143) AND Ball_X_Pos + Ball_Size >= BricksX(153 downto 143) AND Ball_X_Pos - Ball_Size <= BricksX(153 downto 143) + Brick_Width AND BricksOn(13) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(153 downto 143) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(153 downto 143) AND Ball_X_Pos + Ball_Size >= BricksX(153 downto 143) AND Ball_X_Pos - Ball_Size <= BricksX(153 downto 143) + Brick_Width AND BricksOn(13) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(164 downto 154) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(164 downto 154) AND Ball_X_Pos + Ball_Size >= BricksX(164 downto 154) AND Ball_X_Pos - Ball_Size <= BricksX(164 downto 154) + Brick_Width AND BricksOn(14) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(164 downto 154) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(164 downto 154) AND Ball_X_Pos + Ball_Size >= BricksX(164 downto 154) AND Ball_X_Pos - Ball_Size <= BricksX(164 downto 154) + Brick_Width AND BricksOn(14) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(175 downto 165) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(175 downto 165) AND Ball_X_Pos + Ball_Size >= BricksX(175 downto 165) AND Ball_X_Pos - Ball_Size <= BricksX(175 downto 165) + Brick_Width AND BricksOn(15) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(175 downto 165) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(175 downto 165) AND Ball_X_Pos + Ball_Size >= BricksX(175 downto 165) AND Ball_X_Pos - Ball_Size <= BricksX(175 downto 165) + Brick_Width AND BricksOn(15) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(186 downto 176) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(186 downto 176) AND Ball_X_Pos + Ball_Size >= BricksX(186 downto 176) AND Ball_X_Pos - Ball_Size <= BricksX(186 downto 176) + Brick_Width AND BricksOn(16) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(186 downto 176) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(186 downto 176) AND Ball_X_Pos + Ball_Size >= BricksX(186 downto 176) AND Ball_X_Pos - Ball_Size <= BricksX(186 downto 176) + Brick_Width AND BricksOn(16) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(197 downto 187) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(197 downto 187) AND Ball_X_Pos + Ball_Size >= BricksX(197 downto 187) AND Ball_X_Pos - Ball_Size <= BricksX(197 downto 187) + Brick_Width AND BricksOn(17) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(197 downto 187) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(197 downto 187) AND Ball_X_Pos + Ball_Size >= BricksX(197 downto 187) AND Ball_X_Pos - Ball_Size <= BricksX(197 downto 187) + Brick_Width AND BricksOn(17) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(208 downto 198) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(208 downto 198) AND Ball_X_Pos + Ball_Size >= BricksX(208 downto 198) AND Ball_X_Pos - Ball_Size <= BricksX(208 downto 198) + Brick_Width AND BricksOn(18) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(208 downto 198) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(208 downto 198) AND Ball_X_Pos + Ball_Size >= BricksX(208 downto 198) AND Ball_X_Pos - Ball_Size <= BricksX(208 downto 198) + Brick_Width AND BricksOn(18) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
elsif(Ball_Y_Pos - Ball_Size <= BricksY(219 downto 209) + Brick_Height AND Ball_Y_Pos - Ball_Size >= BricksY(219 downto 209) AND Ball_X_Pos + Ball_Size >= BricksX(219 downto 209) AND Ball_X_Pos - Ball_Size <= BricksX(219 downto 209) + Brick_Width AND BricksOn(19) = '1') then
Ball_Y_Motion <= Ball_Y_Step;
elsif(Ball_Y_Pos + Ball_Size <= BricksY(219 downto 209) + Brick_Height AND Ball_Y_Pos + Ball_Size >= BricksY(219 downto 209) AND Ball_X_Pos + Ball_Size >= BricksX(219 downto 209) AND Ball_X_Pos - Ball_Size <= BricksX(219 downto 209) + Brick_Width AND BricksOn(19) = '1') then
Ball_Y_Motion <= not(Ball_Y_Step) + '1';
--end if;
-------Brick Interactions Below (X-axis change in ball movement)---------------
elsif(Ball_X_Pos - Ball_Size <= BricksX(10 downto 0) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(10 downto 0) AND Ball_Y_Pos + Ball_Size >= BricksY(10 downto 0) AND Ball_Y_Pos - Ball_Size <= BricksY(10 downto 0) + Brick_Height AND BricksOn(0) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(10 downto 0) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(10 downto 0) AND Ball_Y_Pos + Ball_Size >= BricksY(10 downto 0) AND Ball_Y_Pos - Ball_Size <= BricksY(10 downto 0) + Brick_Height AND BricksOn(0) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(21 downto 11) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(21 downto 11) AND Ball_Y_Pos + Ball_Size >= BricksY(21 downto 11) AND Ball_Y_Pos - Ball_Size <= BricksY(21 downto 11) + Brick_Height AND BricksOn(1) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(21 downto 11) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(21 downto 11) AND Ball_Y_Pos + Ball_Size >= BricksY(21 downto 11) AND Ball_Y_Pos - Ball_Size <= BricksY(21 downto 11) + Brick_Height AND BricksOn(1) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(32 downto 22) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(32 downto 22) AND Ball_Y_Pos + Ball_Size >= BricksY(32 downto 22) AND Ball_Y_Pos - Ball_Size <= BricksY(32 downto 22) + Brick_Height AND BricksOn(2) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(32 downto 22) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(32 downto 22) AND Ball_Y_Pos + Ball_Size >= BricksY(32 downto 22) AND Ball_Y_Pos - Ball_Size <= BricksY(32 downto 22) + Brick_Height AND BricksOn(2) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(43 downto 33) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(43 downto 33) AND Ball_Y_Pos + Ball_Size >= BricksY(43 downto 33) AND Ball_Y_Pos - Ball_Size <= BricksY(43 downto 33) + Brick_Height AND BricksOn(3) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(43 downto 33) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(43 downto 33) AND Ball_Y_Pos + Ball_Size >= BricksY(43 downto 33) AND Ball_Y_Pos - Ball_Size <= BricksY(43 downto 33) + Brick_Height AND BricksOn(3) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(54 downto 44) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(54 downto 44) AND Ball_Y_Pos + Ball_Size >= BricksY(54 downto 44) AND Ball_Y_Pos - Ball_Size <= BricksY(54 downto 44) + Brick_Height AND BricksOn(4) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(54 downto 44) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(54 downto 44) AND Ball_Y_Pos + Ball_Size >= BricksY(54 downto 44) AND Ball_Y_Pos - Ball_Size <= BricksY(54 downto 44) + Brick_Height AND BricksOn(4) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(65 downto 55) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(65 downto 55) AND Ball_Y_Pos + Ball_Size >= BricksY(65 downto 55) AND Ball_Y_Pos - Ball_Size <= BricksY(65 downto 55) + Brick_Height AND BricksOn(5) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(65 downto 55) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(65 downto 55) AND Ball_Y_Pos + Ball_Size >= BricksY(65 downto 55) AND Ball_Y_Pos - Ball_Size <= BricksY(65 downto 55) + Brick_Height AND BricksOn(5) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(76 downto 66) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(76 downto 66) AND Ball_Y_Pos + Ball_Size >= BricksY(76 downto 66) AND Ball_Y_Pos - Ball_Size <= BricksY(76 downto 66) + Brick_Height AND BricksOn(6) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(76 downto 66) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(76 downto 66) AND Ball_Y_Pos + Ball_Size >= BricksY(76 downto 66) AND Ball_Y_Pos - Ball_Size <= BricksY(76 downto 66) + Brick_Height AND BricksOn(6) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(87 downto 77) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(87 downto 77) AND Ball_Y_Pos + Ball_Size >= BricksY(87 downto 77) AND Ball_Y_Pos - Ball_Size <= BricksY(87 downto 77) + Brick_Height AND BricksOn(7) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(87 downto 77) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(87 downto 77) AND Ball_Y_Pos + Ball_Size >= BricksY(87 downto 77) AND Ball_Y_Pos - Ball_Size <= BricksY(87 downto 77) + Brick_Height AND BricksOn(7) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(98 downto 88) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(98 downto 88) AND Ball_Y_Pos + Ball_Size >= BricksY(98 downto 88) AND Ball_Y_Pos - Ball_Size <= BricksY(98 downto 88) + Brick_Height AND BricksOn(8) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(98 downto 88) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(98 downto 88) AND Ball_Y_Pos + Ball_Size >= BricksY(98 downto 88) AND Ball_Y_Pos - Ball_Size <= BricksY(98 downto 88) + Brick_Height AND BricksOn(8) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(109 downto 99) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(109 downto 99) AND Ball_Y_Pos + Ball_Size >= BricksY(109 downto 99) AND Ball_Y_Pos - Ball_Size <= BricksY(109 downto 99) + Brick_Height AND BricksOn(9) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(109 downto 99) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(109 downto 99) AND Ball_Y_Pos + Ball_Size >= BricksY(109 downto 99) AND Ball_Y_Pos - Ball_Size <= BricksY(109 downto 99) + Brick_Height AND BricksOn(9) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(120 downto 110) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(120 downto 110) AND Ball_Y_Pos + Ball_Size >= BricksY(120 downto 110) AND Ball_Y_Pos - Ball_Size <= BricksY(120 downto 110) + Brick_Height AND BricksOn(10) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(120 downto 110) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(120 downto 110) AND Ball_Y_Pos + Ball_Size >= BricksY(120 downto 110) AND Ball_Y_Pos - Ball_Size <= BricksY(120 downto 110) + Brick_Height AND BricksOn(10) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(131 downto 121) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(131 downto 121) AND Ball_Y_Pos + Ball_Size >= BricksY(131 downto 121) AND Ball_Y_Pos - Ball_Size <= BricksY(131 downto 121) + Brick_Height AND BricksOn(11) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(131 downto 121) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(131 downto 121) AND Ball_Y_Pos + Ball_Size >= BricksY(131 downto 121) AND Ball_Y_Pos - Ball_Size <= BricksY(131 downto 121) + Brick_Height AND BricksOn(11) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(142 downto 132) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(142 downto 132) AND Ball_Y_Pos + Ball_Size >= BricksY(142 downto 132) AND Ball_Y_Pos - Ball_Size <= BricksY(142 downto 132) + Brick_Height AND BricksOn(12) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(142 downto 132) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(142 downto 132) AND Ball_Y_Pos + Ball_Size >= BricksY(142 downto 132) AND Ball_Y_Pos - Ball_Size <= BricksY(142 downto 132) + Brick_Height AND BricksOn(12) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(153 downto 143) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(153 downto 143) AND Ball_Y_Pos + Ball_Size >= BricksY(153 downto 143) AND Ball_Y_Pos - Ball_Size <= BricksY(153 downto 143) + Brick_Height AND BricksOn(13) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(153 downto 143) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(153 downto 143) AND Ball_Y_Pos + Ball_Size >= BricksY(153 downto 143) AND Ball_Y_Pos - Ball_Size <= BricksY(153 downto 143) + Brick_Height AND BricksOn(13) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(164 downto 154) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(164 downto 154) AND Ball_Y_Pos + Ball_Size >= BricksY(164 downto 154) AND Ball_Y_Pos - Ball_Size <= BricksY(164 downto 154) + Brick_Height AND BricksOn(14) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(164 downto 154) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(164 downto 154) AND Ball_Y_Pos + Ball_Size >= BricksY(164 downto 154) AND Ball_Y_Pos - Ball_Size <= BricksY(164 downto 154) + Brick_Height AND BricksOn(14) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(175 downto 165) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(175 downto 165) AND Ball_Y_Pos + Ball_Size >= BricksY(175 downto 165) AND Ball_Y_Pos - Ball_Size <= BricksY(175 downto 165) + Brick_Height AND BricksOn(15) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(175 downto 165) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(175 downto 165) AND Ball_Y_Pos + Ball_Size >= BricksY(175 downto 165) AND Ball_Y_Pos - Ball_Size <= BricksY(175 downto 165) + Brick_Height AND BricksOn(15) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(186 downto 176) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(186 downto 176) AND Ball_Y_Pos + Ball_Size >= BricksY(186 downto 176) AND Ball_Y_Pos - Ball_Size <= BricksY(186 downto 176) + Brick_Height AND BricksOn(16) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(186 downto 176) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(186 downto 176) AND Ball_Y_Pos + Ball_Size >= BricksY(186 downto 176) AND Ball_Y_Pos - Ball_Size <= BricksY(186 downto 176) + Brick_Height AND BricksOn(16) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(197 downto 187) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(197 downto 187) AND Ball_Y_Pos + Ball_Size >= BricksY(197 downto 187) AND Ball_Y_Pos - Ball_Size <= BricksY(197 downto 187) + Brick_Height AND BricksOn(17) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(197 downto 187) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(197 downto 187) AND Ball_Y_Pos + Ball_Size >= BricksY(197 downto 187) AND Ball_Y_Pos - Ball_Size <= BricksY(197 downto 187) + Brick_Height AND BricksOn(17) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(208 downto 198) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(208 downto 198) AND Ball_Y_Pos + Ball_Size >= BricksY(208 downto 198) AND Ball_Y_Pos - Ball_Size <= BricksY(208 downto 198) + Brick_Height AND BricksOn(18) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(208 downto 198) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(208 downto 198) AND Ball_Y_Pos + Ball_Size >= BricksY(208 downto 198) AND Ball_Y_Pos - Ball_Size <= BricksY(208 downto 198) + Brick_Height AND BricksOn(18) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
elsif(Ball_X_Pos - Ball_Size <= BricksX(219 downto 209) + Brick_Width AND Ball_X_Pos - Ball_Size >= BricksX(219 downto 209) AND Ball_Y_Pos + Ball_Size >= BricksY(219 downto 209) AND Ball_Y_Pos - Ball_Size <= BricksY(219 downto 209) + Brick_Height AND BricksOn(19) = '1') then
Ball_X_Motion <= Ball_X_Motion;
elsif(Ball_X_Pos + Ball_Size <= BricksX(219 downto 209) + Brick_Width AND Ball_X_Pos + Ball_Size >= BricksX(219 downto 209) AND Ball_Y_Pos + Ball_Size >= BricksY(219 downto 209) AND Ball_Y_Pos - Ball_Size <= BricksY(219 downto 209) + Brick_Height AND BricksOn(19) = '1') then
Ball_X_Motion <= not(Ball_X_Step) + '1';
end if;
Ball_Y_pos <= Ball_Y_pos + Ball_Y_Motion; -- Update ball position
Ball_X_pos <= Ball_X_pos + Ball_X_Motion;
end if;
end process Move_Ball;
BallX <= Ball_X_pos;
BallY <= Ball_Y_pos;
BallS <= Ball_Size;
paddle_loss_status <= paddle_loss_statusSig;
end Behavioral;
|
mit
|
96fa664a1e8422c4929e7a918fc12627
| 0.650838 | 3.016595 | false | false | false | false |
rajvinjamuri/ECE385_VHDL
|
vga_controller.vhd
| 1 | 5,281 |
---------------------------------------------------------------------------
-- VGA controller --
-- Kyle Kloepper --
-- 4-05-2005 --
-- --
-- Modified by Stephen Kempf 04-08-2005 --
-- 10-05-2006 --
-- 03-12-2007 --
-- Fall 2009 Distribution --
-- --
-- Used standard 640x480 vga found at epanorama --
-- --
-- reference: http://www.xilinx.com/bvdocs/userguides/ug130.pdf --
-- http://www.epanorama.net/documents/pc/vga_timing.html --
-- --
-- note: The standard is changed slightly because of 25 mhz instead --
-- of 25.175 mhz pixel clock. Refresh rate drops slightly. --
-- --
-- For use with ECE 385 Lab 9 and Final Project --
-- ECE Department @ UIUC --
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_controller is
Port ( clk : in std_logic; -- 50 MHz clock
reset : in std_logic; -- reset signal
hs : out std_logic; -- Horizontal sync pulse. Active low
vs : out std_logic; -- Vertical sync pulse. Active low
pixel_clk : out std_logic; -- 25 MHz pixel clock output
blank : out std_logic; -- Blanking interval indicator. Active low.
sync : out std_logic; -- Composite Sync signal. Active low. We don't use it in this lab,
-- but the video DAC on the DE2 board requires an input for it.
DrawX : out std_logic_vector(10 downto 0); -- horizontal coordinate
DrawY : out std_logic_vector(10 downto 0) ); -- vertical coordinate
end vga_controller;
architecture Behavioral of vga_controller is
--800 horizontal pixels indexed 0 to 799
--525 vertical pixels indexed 0 to 524
constant hpixels : std_logic_vector(9 downto 0) := "1100011111";
constant vlines : std_logic_vector(9 downto 0) := "1000001100";
--horizontal pixel and vertical line counters
signal hc, vc : std_logic_vector(10 downto 0);
signal clkdiv : std_logic;
--signal indicates if ok to display color for a pixel
signal display : std_logic;
begin
-- Disable Composite Sync
sync <= '0';
--This cuts the 50 Mhz clock in half to generate a 25 MHz pixel clock
process(clk, reset)
begin
if (reset = '1') then
clkdiv <= '0';
elsif (rising_edge(clk)) then
clkdiv <= not clkdiv;
end if;
end process;
--Runs the horizontal counter when it resets vertical counter is incremented
counter_proc : process(clkdiv, reset)
begin
if (reset = '1') then
hc <= "00000000000";
vc <= "00000000000";
elsif (rising_edge(clkdiv)) then
if (hc = hpixels) then --If hc has reached the end of pixel count
hc <= "00000000000";
if (vc = vlines) then -- if vc has reached end of line count
vc <= "00000000000";
else
vc <= vc + 1;
end if;
else
hc <= hc + 1; -- no statement about vc, implied vc <= vc;
end if;
end if;
end process;
DrawX <= hc;
DrawY <= vc;
-- horizontal sync pulse is 96 pixels long at pixels 656-752
-- (signal is registered to ensure clean output waveform)
hsync_proc : process (reset, clkdiv, hc)
begin
if (reset = '1') then
hs <= '0';
elsif (rising_edge(clkdiv)) then
if ((hc + 1) >= "1010010000" and (hc + 1) < "1011110000") then -- must check next value of hc
hs <= '0';
else
hs <= '1';
end if;
end if;
end process;
-- vertical sync pulse is 2 lines(800 pixels) long at line 490-491
-- (signal is registered to ensure clean output waveform)
vsync_proc : process(reset, clkdiv, vc)
begin
if (reset = '1') then
vs <= '0';
elsif (rising_edge(clkdiv)) then
if ((vc + 1) = "111101010" or (vc + 1) = "111101011") then -- must check next value of vc
vs <= '0';
else
vs <= '1';
end if;
end if;
end process;
-- only display pixels between horizontal 0-639 and vertical 0-479 (640x480)
-- (This signal is registered within the DAC chip, so we can leave it as pure combinational logic here)
blank_proc : process(hc, vc)
begin
if ((hc >= "1010000000") or (vc >= "0111100000")) then
display <= '0';
else
display <= '1';
end if;
end process;
blank <= display;
pixel_clk <= clkdiv;
end Behavioral;
|
mit
|
4ac809df35c9fe433a788fe4a7553f22
| 0.490437 | 4.460304 | false | false | false | false |
alainmarcel/Surelog
|
third_party/tests/ariane/fpga/src/apb_uart/src/apb_uart.vhd
| 2 | 51,558 |
--
-- UART 16750
--
-- Author: Sebastian Witt
-- Date: 29.01.2008
-- Version: 1.5
--
-- History: 1.0 - Initial version
-- 1.1 - THR empty interrupt register connected to RST
-- 1.2 - Registered outputs
-- 1.3 - Automatic flow control
-- 1.4 - De-assert IIR FIFO64 when FIFO is disabled
-- 1.5 - Inverted low active outputs when RST is active
--
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART
entity apb_uart is
port (
CLK : in std_logic; -- Clock
RSTN : in std_logic; -- Reset negated
PSEL : in std_logic; -- APB psel signal
PENABLE : in std_logic; -- APB penable signal
PWRITE : in std_logic; -- APB pwrite signal
PADDR : in std_logic_vector(2 downto 0); -- APB paddr signal
PWDATA : in std_logic_vector(31 downto 0); -- APB pwdata signal
PRDATA : out std_logic_vector(31 downto 0); -- APB prdata signal
PREADY : out std_logic; -- APB pready signal
PSLVERR : out std_logic; -- APB pslverr signal
INT : out std_logic; -- Interrupt output
OUT1N : out std_logic; -- Output 1
OUT2N : out std_logic; -- Output 2
RTSN : out std_logic; -- RTS output
DTRN : out std_logic; -- DTR output
CTSN : in std_logic; -- CTS input
DSRN : in std_logic; -- DSR input
DCDN : in std_logic; -- DCD input
RIN : in std_logic; -- RI input
SIN : in std_logic; -- Receiver input
SOUT : out std_logic -- Transmitter output
);
end apb_uart;
architecture rtl of apb_uart is
-- UART transmitter
component uart_transmitter is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
TXCLK : in std_logic; -- Transmitter clock (2x baudrate)
TXSTART : in std_logic; -- Start transmitter
CLEAR : in std_logic; -- Clear transmitter state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
BC : in std_logic; -- Break control
DIN : in std_logic_vector(7 downto 0); -- Input data
TXFINISHED : out std_logic; -- Transmitter operation finished
SOUT : out std_logic -- Transmitter output
);
end component;
-- UART receiver
component uart_receiver is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
RXCLK : in std_logic; -- Receiver clock (16x baudrate)
RXCLEAR : in std_logic; -- Reset receiver state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
SIN : in std_logic; -- Receiver input
PE : out std_logic; -- Parity error
FE : out std_logic; -- Framing error
BI : out std_logic; -- Break interrupt
DOUT : out std_logic_vector(7 downto 0); -- Output data
RXFINISHED : out std_logic -- Receiver operation finished
);
end component;
-- UART interrupt control
component uart_interrupt is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
IER : in std_logic_vector(3 downto 0); -- IER 3:0
LSR : in std_logic_vector(4 downto 0); -- LSR 4:0
THI : in std_logic; -- Transmitter holding register empty interrupt
RDA : in std_logic; -- Receiver data available
CTI : in std_logic; -- Character timeout indication
AFE : in std_logic; -- Automatic flow control enable
MSR : in std_logic_vector(3 downto 0); -- MSR 3:0
IIR : out std_logic_vector(3 downto 0); -- IIR 3:0
INT : out std_logic -- Interrupt
);
end component;
-- UART baudrate generator
component uart_baudgen is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
CLEAR : in std_logic; -- Reset generator (synchronization)
DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider
BAUDTICK : out std_logic -- 16xBaudrate tick
);
end component;
-- UART FIFO
component slib_fifo is
generic (
WIDTH : integer := 8; -- FIFO width
SIZE_E : integer := 6 -- FIFO size (2^SIZE_E)
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear FIFO
WRITE : in std_logic; -- Write to FIFO
READ : in std_logic; -- Read from FIFO
D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input
Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output
EMPTY : out std_logic; -- FIFO is empty
FULL : out std_logic; -- FIFO is full
USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage
);
end component;
-- Edge detect
component slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end component;
-- Input synchronization
component slib_input_sync is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end component;
-- Input filter
component slib_input_filter is
generic (
SIZE : natural := 4 -- Filter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end component;
-- Clock enable generation
component slib_clock_div is
generic (
RATIO : integer := 8 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end component;
-- Global device signals
signal iWrite : std_logic; -- Write to UART
signal iRead : std_logic; -- Read from UART
signal iRST : std_logic; -- RST negated
-- UART registers read/write signals
signal iRBRRead : std_logic; -- Read from RBR
signal iTHRWrite : std_logic; -- Write to THR
signal iDLLWrite : std_logic; -- Write to DLL
signal iDLMWrite : std_logic; -- Write to DLM
signal iIERWrite : std_logic; -- Write to IER
signal iIIRRead : std_logic; -- Read from IIR
signal iFCRWrite : std_logic; -- Write to FCR
signal iLCRWrite : std_logic; -- Write to LCR
signal iMCRWrite : std_logic; -- Write to MCR
signal iLSRRead : std_logic; -- Read from LSR
signal iMSRRead : std_logic; -- Read from MSR
signal iSCRWrite : std_logic; -- Write to SCR
-- UART registers
signal iTSR : std_logic_vector(7 downto 0); -- Transmitter holding register
signal iRBR : std_logic_vector(7 downto 0); -- Receiver buffer register
signal iDLL : std_logic_vector(7 downto 0); -- Divisor latch LSB
signal iDLM : std_logic_vector(7 downto 0); -- Divisor latch MSB
signal iIER : std_logic_vector(7 downto 0); -- Interrupt enable register
signal iIIR : std_logic_vector(7 downto 0); -- Interrupt identification register
signal iFCR : std_logic_vector(7 downto 0); -- FIFO control register
signal iLCR : std_logic_vector(7 downto 0); -- Line control register
signal iMCR : std_logic_vector(7 downto 0); -- Modem control register
signal iLSR : std_logic_vector(7 downto 0); -- Line status register
signal iMSR : std_logic_vector(7 downto 0); -- Modem status register
signal iSCR : std_logic_vector(7 downto 0); -- Scratch register
-- IER register signals
signal iIER_ERBI : std_logic; -- IER: Enable received data available interrupt
signal iIER_ETBEI : std_logic; -- IER: Enable transmitter holding register empty interrupt
signal iIER_ELSI : std_logic; -- IER: Enable receiver line status interrupt
signal iIER_EDSSI : std_logic; -- IER: Enable modem status interrupt
-- IIR register signals
signal iIIR_PI : std_logic; -- IIR: Pending interrupt
signal iIIR_ID0 : std_logic; -- IIR: Interrupt ID0
signal iIIR_ID1 : std_logic; -- IIR: Interrupt ID1
signal iIIR_ID2 : std_logic; -- IIR: Interrupt ID2
signal iIIR_FIFO64 : std_logic; -- IIR: 64 byte FIFO enabled
-- FCR register signals
signal iFCR_FIFOEnable : std_logic; -- FCR: FIFO enable
signal iFCR_RXFIFOReset : std_logic; -- FCR: Receiver FIFO reset
signal iFCR_TXFIFOReset : std_logic; -- FCR: Transmitter FIFO reset
signal iFCR_DMAMode : std_logic; -- FCR: DMA mode select
signal iFCR_FIFO64E : std_logic; -- FCR: 64 byte FIFO enable
signal iFCR_RXTrigger : std_logic_vector(1 downto 0); -- FCR: Receiver trigger
-- LCR register signals
signal iLCR_WLS : std_logic_vector(1 downto 0); -- LCR: Word length select
signal iLCR_STB : std_logic; -- LCR: Number of stop bits
signal iLCR_PEN : std_logic; -- LCR: Parity enable
signal iLCR_EPS : std_logic; -- LCR: Even parity select
signal iLCR_SP : std_logic; -- LCR: Sticky parity
signal iLCR_BC : std_logic; -- LCR: Break control
signal iLCR_DLAB : std_logic; -- LCR: Divisor latch access bit
-- MCR register signals
signal iMCR_DTR : std_logic; -- MCR: Data terminal ready
signal iMCR_RTS : std_logic; -- MCR: Request to send
signal iMCR_OUT1 : std_logic; -- MCR: OUT1
signal iMCR_OUT2 : std_logic; -- MCR: OUT2
signal iMCR_LOOP : std_logic; -- MCR: Loop
signal iMCR_AFE : std_logic; -- MCR: Auto flow control enable
-- LSR register signals
signal iLSR_DR : std_logic; -- LSR: Data ready
signal iLSR_OE : std_logic; -- LSR: Overrun error
signal iLSR_PE : std_logic; -- LSR: Parity error
signal iLSR_FE : std_logic; -- LSR: Framing error
signal iLSR_BI : std_logic; -- LSR: Break Interrupt
signal iLSR_THRE : std_logic; -- LSR: Transmitter holding register empty
signal iLSR_THRNF : std_logic; -- LSR: Transmitter holding register not full
signal iLSR_TEMT : std_logic; -- LSR: Transmitter empty
signal iLSR_FIFOERR : std_logic; -- LSR: Error in receiver FIFO
-- MSR register signals
signal iMSR_dCTS : std_logic; -- MSR: Delta CTS
signal iMSR_dDSR : std_logic; -- MSR: Delta DSR
signal iMSR_TERI : std_logic; -- MSR: Trailing edge ring indicator
signal iMSR_dDCD : std_logic; -- MSR: Delta DCD
signal iMSR_CTS : std_logic; -- MSR: CTS
signal iMSR_DSR : std_logic; -- MSR: DSR
signal iMSR_RI : std_logic; -- MSR: RI
signal iMSR_DCD : std_logic; -- MSR: DCD
-- UART MSR signals
signal iCTSNs : std_logic; -- Synchronized CTSN input
signal iDSRNs : std_logic; -- Synchronized DSRN input
signal iDCDNs : std_logic; -- Synchronized DCDN input
signal iRINs : std_logic; -- Synchronized RIN input
signal iCTSn : std_logic; -- Filtered CTSN input
signal iDSRn : std_logic; -- Filtered DSRN input
signal iDCDn : std_logic; -- Filtered DCDN input
signal iRIn : std_logic; -- Filtered RIN input
signal iCTSnRE : std_logic; -- CTSn rising edge
signal iCTSnFE : std_logic; -- CTSn falling edge
signal iDSRnRE : std_logic; -- DSRn rising edge
signal iDSRnFE : std_logic; -- DSRn falling edge
signal iDCDnRE : std_logic; -- DCDn rising edge
signal iDCDnFE : std_logic; -- DCDn falling edge
signal iRInRE : std_logic; -- RIn rising edge
signal iRInFE : std_logic; -- RIn falling edge
-- UART baudrate generation signals
signal iBaudgenDiv : std_logic_vector(15 downto 0); -- Baudrate divider
signal iBaudtick16x : std_logic; -- 16x Baudrate output from baudrate generator
signal iBaudtick2x : std_logic; -- 2x Baudrate for transmitter
signal iRCLK : std_logic; -- 16x Baudrate for receiver
signal iBAUDOUTN : std_logic;
-- UART FIFO signals
signal iTXFIFOClear : std_logic; -- Clear TX FIFO
signal iTXFIFOWrite : std_logic; -- Write to TX FIFO
signal iTXFIFORead : std_logic; -- Read from TX FIFO
signal iTXFIFOEmpty : std_logic; -- TX FIFO is empty
signal iTXFIFOFull : std_logic; -- TX FIFO is full
signal iTXFIFO16Full : std_logic; -- TX FIFO 16 byte mode is full
signal iTXFIFO64Full : std_logic; -- TX FIFO 64 byte mode is full
signal iTXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage
signal iTXFIFOQ : std_logic_vector(7 downto 0); -- TX FIFO output
signal iRXFIFOClear : std_logic; -- Clear RX FIFO
signal iRXFIFOWrite : std_logic; -- Write to RX FIFO
signal iRXFIFORead : std_logic; -- Read from RX FIFO
signal iRXFIFOEmpty : std_logic; -- RX FIFO is empty
signal iRXFIFOFull : std_logic; -- RX FIFO is full
signal iRXFIFO16Full : std_logic; -- RX FIFO 16 byte mode is full
signal iRXFIFO64Full : std_logic; -- RX FIFO 64 byte mode is full
signal iRXFIFOD : std_logic_vector(10 downto 0); -- RX FIFO input
signal iRXFIFOQ : std_logic_vector(10 downto 0); -- RX FIFO output
signal iRXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage
signal iRXFIFOTrigger : std_logic; -- FIFO trigger level reached
signal iRXFIFO16Trigger : std_logic; -- FIFO 16 byte mode trigger level reached
signal iRXFIFO64Trigger : std_logic; -- FIFO 64 byte mode trigger level reached
signal iRXFIFOPE : std_logic; -- Parity error from FIFO
signal iRXFIFOFE : std_logic; -- Frame error from FIFO
signal iRXFIFOBI : std_logic; -- Break interrupt from FIFO
-- UART transmitter signals
signal iSOUT : std_logic; -- Transmitter output
signal iTXStart : std_logic; -- Start transmitter
signal iTXClear : std_logic; -- Clear transmitter status
signal iTXFinished : std_logic; -- TX finished, character transmitted
signal iTXRunning : std_logic; -- TX in progress
-- UART receiver signals
signal iSINr : std_logic; -- Synchronized SIN input
signal iSIN : std_logic; -- Receiver input
signal iRXFinished : std_logic; -- RX finished, character received
signal iRXClear : std_logic; -- Clear receiver status
signal iRXData : std_logic_vector(7 downto 0); -- RX data
signal iRXPE : std_logic; -- RX parity error
signal iRXFE : std_logic; -- RX frame error
signal iRXBI : std_logic; -- RX break interrupt
-- UART control signals
signal iFERE : std_logic; -- Frame error detected
signal iPERE : std_logic; -- Parity error detected
signal iBIRE : std_logic; -- Break interrupt detected
signal iFECounter : integer range 0 to 64; -- FIFO error counter
signal iFEIncrement : std_logic; -- FIFO error counter increment
signal iFEDecrement : std_logic; -- FIFO error counter decrement
signal iRDAInterrupt : std_logic; -- Receiver data available interrupt (DA or FIFO trigger level)
signal iTimeoutCount : unsigned(5 downto 0); -- Character timeout counter (FIFO mode)
signal iCharTimeout : std_logic; -- Character timeout indication (FIFO mode)
signal iLSR_THRERE : std_logic; -- LSR THRE rising edge for interrupt generation
signal iTHRInterrupt : std_logic; -- Transmitter holding register empty interrupt
signal iTXEnable : std_logic; -- Transmitter enable signal
signal iRTS : std_logic; -- Internal RTS signal with/without automatic flow control
begin
-- Global device signals
iWrite <= '1' when PSEL = '1' and PENABLE = '1' and PWRITE = '1' else '0';
iRead <= '1' when PSEL = '1' and PENABLE = '1' and PWRITE = '0' else '0';
iRST <= '1' when RSTN = '0' else '0';
-- UART registers read/write signals
iRBRRead <= '1' when iRead = '1' and PADDR = "000" and iLCR_DLAB = '0' else '0';
iTHRWrite <= '1' when iWrite = '1' and PADDR = "000" and iLCR_DLAB = '0' else '0';
iDLLWrite <= '1' when iWrite = '1' and PADDR = "000" and iLCR_DLAB = '1' else '0';
iDLMWrite <= '1' when iWrite = '1' and PADDR = "001" and iLCR_DLAB = '1' else '0';
iIERWrite <= '1' when iWrite = '1' and PADDR = "001" and iLCR_DLAB = '0' else '0';
iIIRRead <= '1' when iRead = '1' and PADDR = "010" else '0';
iFCRWrite <= '1' when iWrite = '1' and PADDR = "010" else '0';
iLCRWrite <= '1' when iWrite = '1' and PADDR = "011" else '0';
iMCRWrite <= '1' when iWrite = '1' and PADDR = "100" else '0';
iLSRRead <= '1' when iRead = '1' and PADDR = "101" else '0';
iMSRRead <= '1' when iRead = '1' and PADDR = "110" else '0';
iSCRWrite <= '1' when iWrite = '1' and PADDR = "111" else '0';
-- Async. input synchronization
UART_IS_SIN: slib_input_sync port map (CLK, iRST, SIN, iSINr);
UART_IS_CTS: slib_input_sync port map (CLK, iRST, CTSN, iCTSNs);
UART_IS_DSR: slib_input_sync port map (CLK, iRST, DSRN, iDSRNs);
UART_IS_DCD: slib_input_sync port map (CLK, iRST, DCDN, iDCDNs);
UART_IS_RI: slib_input_sync port map (CLK, iRST, RIN, iRINs);
-- Input filter for UART control signals
UART_IF_CTS: slib_input_filter generic map (SIZE => 2) port map (CLK, iRST, iBaudtick2x, iCTSNs, iCTSn);
UART_IF_DSR: slib_input_filter generic map (SIZE => 2) port map (CLK, iRST, iBaudtick2x, iDSRNs, iDSRn);
UART_IF_DCD: slib_input_filter generic map (SIZE => 2) port map (CLK, iRST, iBaudtick2x, iDCDNs, iDCDn);
UART_IF_RI: slib_input_filter generic map (SIZE => 2) port map (CLK, iRST, iBaudtick2x, iRINs, iRIn);
-- Divisor latch register
UART_DLR: process (CLK, iRST)
begin
if (iRST = '1') then
iDLL <= (others => '0');
iDLM <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iDLLWrite = '1') then
iDLL <= PWDATA(7 downto 0);
end if;
if (iDLMWrite = '1') then
iDLM <= PWDATA(7 downto 0);
end if;
end if;
end process;
-- Interrupt enable register
UART_IER: process (CLK, iRST)
begin
if (iRST = '1') then
iIER(3 downto 0) <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iIERWrite = '1') then
iIER(3 downto 0) <= PWDATA(3 downto 0);
end if;
end if;
end process;
iIER_ERBI <= iIER(0);
iIER_ETBEI <= iIER(1);
iIER_ELSI <= iIER(2);
iIER_EDSSI <= iIER(3);
iIER(7 downto 4) <= (others => '0');
-- Interrupt control and IIR
UART_IIC: uart_interrupt port map (CLK => CLK,
RST => iRST,
IER => iIER(3 downto 0),
LSR => iLSR(4 downto 0),
THI => iTHRInterrupt,
RDA => iRDAInterrupt,
CTI => iCharTimeout,
AFE => iMCR_AFE,
MSR => iMSR(3 downto 0),
IIR => iIIR(3 downto 0),
INT => INT
);
-- THR empty interrupt
UART_IIC_THRE_ED: slib_edge_detect port map (CLK => CLK, RST => iRST, D => iLSR_THRE, RE => iLSR_THRERE);
UART_IIC_THREI: process (CLK, iRST)
begin
if (iRST = '1') then
iTHRInterrupt <= '0';
elsif (CLK'event and CLK = '1') then
if (iLSR_THRERE = '1' or iFCR_TXFIFOReset = '1' or (iIERWrite = '1' and PWDATA(1) = '1' and iLSR_THRE = '1')) then
iTHRInterrupt <= '1'; -- Set on THRE, TX FIFO reset (FIFO enable) or ETBEI enable
elsif ((iIIRRead = '1' and iIIR(3 downto 1) = "001") or iTHRWrite = '1') then
iTHRInterrupt <= '0'; -- Clear on IIR read (if source of interrupt) or THR write
end if;
end if;
end process;
iRDAInterrupt <= '1' when (iFCR_FIFOEnable = '0' and iLSR_DR = '1') or
(iFCR_FIFOEnable = '1' and iRXFIFOTrigger = '1') else '0';
iIIR_PI <= iIIR(0);
iIIR_ID0 <= iIIR(1);
iIIR_ID1 <= iIIR(2);
iIIR_ID2 <= iIIR(3);
iIIR_FIFO64 <= iIIR(5);
iIIR(4) <= '0';
iIIR(5) <= iFCR_FIFO64E when iFCR_FIFOEnable = '1' else '0';
iIIR(6) <= iFCR_FIFOEnable;
iIIR(7) <= iFCR_FIFOEnable;
-- Character timeout indication
UART_CTI: process (CLK, iRST)
begin
if (iRST = '1') then
iTimeoutCount <= (others => '0');
iCharTimeout <= '0';
elsif (CLK'event and CLK = '1') then
if (iRXFIFOEmpty = '1' or iRBRRead = '1' or iRXFIFOWrite = '1') then
iTimeoutCount <= (others => '0');
elsif (iRXFIFOEmpty = '0' and iBaudtick2x = '1' and iTimeoutCount(5) = '0') then
iTimeoutCount <= iTimeoutCount + 1;
end if;
-- Timeout indication
if (iFCR_FIFOEnable = '1') then
if (iRBRRead = '1') then
iCharTimeout <= '0';
elsif (iTimeoutCount(5) = '1') then
iCharTimeout <= '1';
end if;
else
iCharTimeout <= '0';
end if;
end if;
end process;
-- FIFO control register
UART_FCR: process (CLK, iRST)
begin
if (iRST = '1') then
iFCR_FIFOEnable <= '0';
iFCR_RXFIFOReset <= '0';
iFCR_TXFIFOReset <= '0';
iFCR_DMAMode <= '0';
iFCR_FIFO64E <= '0';
iFCR_RXTrigger <= (others => '0');
elsif (CLK'event and CLK = '1') then
-- FIFO reset pulse only
iFCR_RXFIFOReset <= '0';
iFCR_TXFIFOReset <= '0';
if (iFCRWrite = '1') then
iFCR_FIFOEnable <= PWDATA(0);
iFCR_DMAMode <= PWDATA(3);
iFCR_RXTrigger <= PWDATA(7 downto 6);
if (iLCR_DLAB = '1') then
iFCR_FIFO64E <= PWDATA(5);
end if;
-- RX FIFO reset control, reset on FIFO enable/disable
if (PWDATA(1) = '1' or (iFCR_FIFOEnable = '0' and PWDATA(0) = '1') or (iFCR_FIFOEnable = '1' and PWDATA(0) = '0')) then
iFCR_RXFIFOReset <= '1';
end if;
-- TX FIFO reset control, reset on FIFO enable/disable
if (PWDATA(2) = '1' or (iFCR_FIFOEnable = '0' and PWDATA(0) = '1') or (iFCR_FIFOEnable = '1' and PWDATA(0) = '0')) then
iFCR_TXFIFOReset <= '1';
end if;
end if;
end if;
end process;
iFCR(0) <= iFCR_FIFOEnable;
iFCR(1) <= iFCR_RXFIFOReset;
iFCR(2) <= iFCR_TXFIFOReset;
iFCR(3) <= iFCR_DMAMode;
iFCR(4) <= '0';
iFCR(5) <= iFCR_FIFO64E;
iFCR(7 downto 6) <= iFCR_RXTrigger;
-- Line control register
UART_LCR: process (CLK, iRST)
begin
if (iRST = '1') then
iLCR <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iLCRWrite = '1') then
iLCR <= PWDATA(7 downto 0);
end if;
end if;
end process;
iLCR_WLS <= iLCR(1 downto 0);
iLCR_STB <= iLCR(2);
iLCR_PEN <= iLCR(3);
iLCR_EPS <= iLCR(4);
iLCR_SP <= iLCR(5);
iLCR_BC <= iLCR(6);
iLCR_DLAB <= iLCR(7);
-- Modem control register
UART_MCR: process (CLK, iRST)
begin
if (iRST = '1') then
iMCR(5 downto 0) <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iMCRWrite = '1') then
iMCR(5 downto 0) <= PWDATA(5 downto 0);
end if;
end if;
end process;
iMCR_DTR <= iMCR(0);
iMCR_RTS <= iMCR(1);
iMCR_OUT1 <= iMCR(2);
iMCR_OUT2 <= iMCR(3);
iMCR_LOOP <= iMCR(4);
iMCR_AFE <= iMCR(5);
iMCR(6) <= '0';
iMCR(7) <= '0';
-- Line status register
UART_LSR: process (CLK, iRST)
begin
if (iRST = '1') then
iLSR_OE <= '0';
iLSR_PE <= '0';
iLSR_FE <= '0';
iLSR_BI <= '0';
iFECounter <= 0;
iLSR_FIFOERR <= '0';
elsif (CLK'event and CLK = '1') then
-- Overrun error
if ((iFCR_FIFOEnable = '0' and iLSR_DR = '1' and iRXFinished = '1') or
(iFCR_FIFOEnable = '1' and iRXFIFOFull = '1' and iRXFinished = '1')) then
iLSR_OE <= '1';
elsif (iLSRRead = '1') then
iLSR_OE <= '0';
end if;
-- Parity error
if (iPERE = '1') then
iLSR_PE <= '1';
elsif (iLSRRead = '1') then
iLSR_PE <= '0';
end if;
-- Frame error
if (iFERE = '1') then
iLSR_FE <= '1';
elsif (iLSRRead = '1') then
iLSR_FE <= '0';
end if;
-- Break interrupt
if (iBIRE = '1') then
iLSR_BI <= '1';
elsif (iLSRRead = '1') then
iLSR_BI <= '0';
end if;
-- FIFO error
-- Datasheet: Cleared by LSR read when no subsequent errors in FIFO
-- Observed: Cleared when no subsequent errors in FIFO
if (iFECounter /= 0) then
iLSR_FIFOERR <= '1';
--elsif (iLSRRead = '1' and iFECounter = 0 and not (iRXFIFOEmpty = '0' and iRXFIFOQ(10 downto 8) /= "000")) then
elsif (iRXFIFOEmpty = '1' or iRXFIFOQ(10 downto 8) = "000") then
iLSR_FIFOERR <= '0';
end if;
-- FIFO error counter
if (iRXFIFOClear = '1') then
iFECounter <= 0;
else
if (iFEIncrement = '1' and iFEDecrement = '0') then
iFECounter <= iFECounter + 1;
elsif (iFEIncrement = '0' and iFEDecrement = '1') then
iFECounter <= iFECounter - 1;
end if;
end if;
end if;
end process;
iRXFIFOPE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(8) = '1' else '0';
iRXFIFOFE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(9) = '1' else '0';
iRXFIFOBI <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(10) = '1' else '0';
UART_PEDET: slib_edge_detect port map (CLK, iRST, iRXFIFOPE, iPERE);
UART_FEDET: slib_edge_detect port map (CLK, iRST, iRXFIFOFE, iFERE);
UART_BIDET: slib_edge_detect port map (CLK, iRST, iRXFIFOBI, iBIRE);
iFEIncrement <= '1' when iRXFIFOWrite = '1' and iRXFIFOD(10 downto 8) /= "000" else '0';
iFEDecrement <= '1' when iFECounter /= 0 and iRXFIFOEmpty = '0' and (iPERE = '1' or iFERE = '1' or iBIRE = '1') else '0';
iLSR(0) <= iLSR_DR;
iLSR(1) <= iLSR_OE;
iLSR(2) <= iLSR_PE;
iLSR(3) <= iLSR_FE;
iLSR(4) <= iLSR_BI;
iLSR(5) <= iLSR_THRNF;
iLSR(6) <= iLSR_TEMT;
iLSR(7) <= '1' when iFCR_FIFOEnable = '1' and iLSR_FIFOERR = '1' else '0';
iLSR_DR <= '1' when iRXFIFOEmpty = '0' or iRXFIFOWrite = '1' else '0';
iLSR_THRE <= '1' when iTXFIFOEmpty = '1' else '0';
iLSR_TEMT <= '1' when iTXRunning = '0' and iLSR_THRE = '1' else '0';
iLSR_THRNF <= '1' when ((iFCR_FIFOEnable = '0' and iTXFIFOEmpty = '1') or (iFCR_FIFOEnable = '1' and iTXFIFOFull = '0')) else '0';
-- Modem status register
iMSR_CTS <= '1' when (iMCR_LOOP = '1' and iRTS = '1') or (iMCR_LOOP = '0' and iCTSn = '0') else '0';
iMSR_DSR <= '1' when (iMCR_LOOP = '1' and iMCR_DTR = '1') or (iMCR_LOOP = '0' and iDSRn = '0') else '0';
iMSR_RI <= '1' when (iMCR_LOOP = '1' and iMCR_OUT1 = '1') or (iMCR_LOOP = '0' and iRIn = '0') else '0';
iMSR_DCD <= '1' when (iMCR_LOOP = '1' and iMCR_OUT2 = '1') or (iMCR_LOOP = '0' and iDCDn = '0') else '0';
-- Edge detection for CTS, DSR, DCD and RI
UART_ED_CTS: slib_edge_detect port map (CLK => CLK, RST => iRST, D => iMSR_CTS, RE => iCTSnRE, FE => iCTSnFE);
UART_ED_DSR: slib_edge_detect port map (CLK => CLK, RST => iRST, D => iMSR_DSR, RE => iDSRnRE, FE => iDSRnFE);
UART_ED_RI: slib_edge_detect port map (CLK => CLK, RST => iRST, D => iMSR_RI, RE => iRInRE, FE => iRInFE);
UART_ED_DCD: slib_edge_detect port map (CLK => CLK, RST => iRST, D => iMSR_DCD, RE => iDCDnRE, FE => iDCDnFE);
UART_MSR: process (CLK, iRST)
begin
if (iRST = '1') then
iMSR_dCTS <= '0';
iMSR_dDSR <= '0';
iMSR_TERI <= '0';
iMSR_dDCD <= '0';
elsif (CLK'event and CLK = '1') then
-- Delta CTS
if (iCTSnRE = '1' or iCTSnFE = '1') then
iMSR_dCTS <= '1';
elsif (iMSRRead = '1') then
iMSR_dCTS <= '0';
end if;
-- Delta DSR
if (iDSRnRE = '1' or iDSRnFE = '1') then
iMSR_dDSR <= '1';
elsif (iMSRRead = '1') then
iMSR_dDSR <= '0';
end if;
-- Trailing edge RI
if (iRInFE = '1') then
iMSR_TERI <= '1';
elsif (iMSRRead = '1') then
iMSR_TERI <= '0';
end if;
-- Delta DCD
if (iDCDnRE = '1' or iDCDnFE = '1') then
iMSR_dDCD <= '1';
elsif (iMSRRead = '1') then
iMSR_dDCD <= '0';
end if;
end if;
end process;
iMSR(0) <= iMSR_dCTS;
iMSR(1) <= iMSR_dDSR;
iMSR(2) <= iMSR_TERI;
iMSR(3) <= iMSR_dDCD;
iMSR(4) <= iMSR_CTS;
iMSR(5) <= iMSR_DSR;
iMSR(6) <= iMSR_RI;
iMSR(7) <= iMSR_DCD;
-- Scratch register
UART_SCR: process (CLK, iRST)
begin
if (iRST = '1') then
iSCR <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iSCRWrite = '1') then
iSCR <= PWDATA(7 downto 0);
end if;
end if;
end process;
-- Baudrate generator
iBaudgenDiv <= iDLM & iDLL;
UART_BG16: uart_baudgen port map (CLK => CLK,
RST => iRST,
CE => '1',
CLEAR => '0',
DIVIDER => iBaudgenDiv,
BAUDTICK => iBaudtick16x
);
UART_BG2: slib_clock_div generic map (RATIO => 8)
port map (CLK => CLK,
RST => iRST,
CE => iBaudtick16x,
Q => iBaudtick2x
);
UART_RCLK: slib_edge_detect port map (CLK => CLK,
RST => iRST,
D => iBAUDOUTN,
RE => iRCLK
);
-- Transmitter FIFO
UART_TXFF: slib_fifo generic map (WIDTH => 8, SIZE_E => 6)
port map (CLK => CLK,
RST => iRST,
CLEAR => iTXFIFOClear,
WRITE => iTXFIFOWrite,
READ => iTXFIFORead,
D => PWDATA(7 downto 0),
Q => iTXFIFOQ,
EMPTY => iTXFIFOEmpty,
FULL => iTXFIFO64Full,
USAGE => iTXFIFOUsage
);
-- Transmitter FIFO inputs
iTXFIFO16Full <= iTXFIFOUsage(4);
iTXFIFOFull <= iTXFIFO16Full when iFCR_FIFO64E = '0' else iTXFIFO64Full;
iTXFIFOWrite <= '1' when ((iFCR_FIFOEnable = '0' and iTXFIFOEmpty = '1') or (iFCR_FIFOEnable = '1' and iTXFIFOFull = '0')) and iTHRWrite = '1' else '0';
iTXFIFOClear <= '1' when iFCR_TXFIFOReset = '1' else '0';
-- Receiver FIFO
UART_RXFF: slib_fifo generic map (WIDTH => 11, SIZE_E => 6)
port map (CLK => CLK,
RST => iRST,
CLEAR => iRXFIFOClear,
WRITE => iRXFIFOWrite,
READ => iRXFIFORead,
D => iRXFIFOD,
Q => iRXFIFOQ,
EMPTY => iRXFIFOEmpty,
FULL => iRXFIFO64Full,
USAGE => iRXFIFOUsage
);
-- Receiver FIFO inputs
iRXFIFORead <= '1' when iRBRRead = '1' else '0';
iRXFIFO16Full <= iRXFIFOUsage(4);
iRXFIFOFull <= iRXFIFO16Full when iFCR_FIFO64E = '0' else iRXFIFO64Full;
-- Receiver FIFO outputs
iRBR <= iRXFIFOQ(7 downto 0);
-- FIFO trigger level: 1, 4, 8, 14
iRXFIFO16Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or
(iFCR_RXTrigger = "01" and (iRXFIFOUsage(2) = '1' or iRXFIFOUsage(3) = '1')) or
(iFCR_RXTrigger = "10" and iRXFIFOUsage(3) = '1') or
(iFCR_RXTrigger = "11" and iRXFIFOUsage(3) = '1' and iRXFIFOUsage(2) = '1' and iRXFIFOUsage(1) = '1') or
iRXFIFO16Full = '1' else '0';
-- FIFO 64 trigger level: 1, 16, 32, 56
iRXFIFO64Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or
(iFCR_RXTrigger = "01" and (iRXFIFOUsage(4) = '1' or iRXFIFOUsage(5) = '1')) or
(iFCR_RXTrigger = "10" and iRXFIFOUsage(5) = '1') or
(iFCR_RXTrigger = "11" and iRXFIFOUsage(5) = '1' and iRXFIFOUsage(4) = '1' and iRXFIFOUsage(3) = '1') or
iRXFIFO64Full = '1' else '0';
iRXFIFOTrigger <= iRXFIFO16Trigger when iFCR_FIFO64E = '0' else iRXFIFO64Trigger;
-- Transmitter
UART_TX: uart_transmitter port map (CLK => CLK,
RST => iRST,
TXCLK => iBaudtick2x,
TXSTART => iTXStart,
CLEAR => iTXClear,
WLS => iLCR_WLS,
STB => iLCR_STB,
PEN => iLCR_PEN,
EPS => iLCR_EPS,
SP => iLCR_SP,
BC => iLCR_BC,
DIN => iTSR,
TXFINISHED => iTXFinished,
SOUT => iSOUT
);
iTXClear <= '0';
-- Receiver
UART_RX: uart_receiver port map (CLK => CLK,
RST => iRST,
RXCLK => iRCLK,
RXCLEAR => iRXClear,
WLS => iLCR_WLS,
STB => iLCR_STB,
PEN => iLCR_PEN,
EPS => iLCR_EPS,
SP => iLCR_SP,
SIN => iSIN,
PE => iRXPE,
FE => iRXFE,
BI => iRXBI,
DOUT => iRXData,
RXFINISHED => iRXFinished
);
iRXClear <= '0';
iSIN <= iSINr when iMCR_LOOP = '0' else iSOUT;
-- Transmitter enable signal
-- TODO: Use iCTSNs instead of iMSR_CTS? Input filter increases delay for Auto-CTS recognition.
iTXEnable <= '1' when iTXFIFOEmpty = '0' and (iMCR_AFE = '0' or (iMCR_AFE = '1' and iMSR_CTS = '1')) else '0';
-- Transmitter process
UART_TXPROC: process (CLK, iRST)
type state_type is (IDLE, TXSTART, TXRUN, TXEND);
variable State : state_type;
begin
if (iRST = '1') then
State := IDLE;
iTSR <= (others => '0');
iTXStart <= '0';
iTXFIFORead <= '0';
iTXRunning <= '0';
elsif (CLK'event and CLK = '1') then
-- Defaults
iTXStart <= '0';
iTXFIFORead <= '0';
iTXRunning <= '0';
case State is
when IDLE => if (iTXEnable = '1') then
iTXStart <= '1'; -- Start transmitter
State := TXSTART;
else
State := IDLE;
end if;
when TXSTART => iTSR <= iTXFIFOQ;
iTXStart <= '1'; -- Start transmitter
iTXFIFORead <= '1'; -- Increment TX FIFO read counter
State := TXRUN;
when TXRUN => if (iTXFinished = '1') then -- TX finished
State := TXEND;
else
State := TXRUN;
end if;
iTXRunning <= '1';
iTXStart <= '1';
when TXEND => State := IDLE;
when others => State := IDLE;
end case;
end if;
end process;
-- Receiver process
UART_RXPROC: process (CLK, iRST)
type state_type is (IDLE, RXSAVE);
variable State : state_type;
begin
if (iRST = '1') then
State := IDLE;
iRXFIFOWrite <= '0';
iRXFIFOClear <= '0';
iRXFIFOD <= (others => '0');
elsif (CLK'event and CLK = '1') then
-- Defaults
iRXFIFOWrite <= '0';
iRXFIFOClear <= iFCR_RXFIFOReset;
case State is
when IDLE => if (iRXFinished = '1') then -- Receive finished
iRXFIFOD <= iRXBI & iRXFE & iRXPE & iRXData;
if (iFCR_FIFOEnable = '0') then
iRXFIFOClear <= '1'; -- Non-FIFO mode
end if;
State := RXSAVE;
else
State := IDLE;
end if;
when RXSAVE => if (iFCR_FIFOEnable = '0') then
iRXFIFOWrite <= '1'; -- Non-FIFO mode: Overwrite
elsif (iRXFIFOFull = '0') then
iRXFIFOWrite <= '1'; -- FIFO mode
end if;
State := IDLE;
when others => State := IDLE;
end case;
end if;
end process;
-- Automatic flow control
UART_AFC: process (CLK, iRST)
begin
if (iRST = '1') then
iRTS <= '0';
elsif (CLK'event and CLK = '1') then
if (iMCR_RTS = '0' or (iMCR_AFE = '1' and iRXFIFOTrigger = '1')) then
-- Deassert when MCR_RTS is not set or AFC is enabled and the RX FIFO trigger level is reached
iRTS <= '0';
elsif (iMCR_RTS = '1' and (iMCR_AFE = '0' or (iMCR_AFE = '1' and iRXFIFOEmpty = '1'))) then
-- Assert when MCR_RTS is set and AFC is disabled or when AFC is enabled and the RX FIFO is empty
iRTS <= '1';
end if;
end if;
end process;
-- Output registers
UART_OUTREGS: process (CLK, iRST)
begin
if (iRST = '1') then
iBAUDOUTN <= '1';
OUT1N <= '1';
OUT2N <= '1';
RTSN <= '1';
DTRN <= '1';
SOUT <= '1';
elsif (CLK'event and CLK = '1') then
-- Default values
iBAUDOUTN <= '0';
OUT1N <= '0';
OUT2N <= '0';
RTSN <= '0';
DTRN <= '0';
SOUT <= '0';
-- BAUDOUTN
if (iBaudtick16x = '0') then
iBAUDOUTN <= '1';
end if;
-- OUT1N
if (iMCR_LOOP = '1' or iMCR_OUT1 = '0') then
OUT1N <= '1';
end if;
-- OUT2N
if (iMCR_LOOP = '1' or iMCR_OUT2 = '0') then
OUT2N <= '1';
end if;
-- RTS
if (iMCR_LOOP = '1' or iRTS = '0') then
RTSN <= '1';
end if;
-- DTR
if (iMCR_LOOP = '1' or iMCR_DTR = '0') then
DTRN <= '1';
end if;
-- SOUT
if (iMCR_LOOP = '1' or iSOUT = '1') then
SOUT <= '1';
end if;
end if;
end process;
-- UART data output
UART_DOUT: process (PADDR, iLCR_DLAB, iRBR, iDLL, iDLM, iIER, iIIR, iLCR, iMCR, iLSR, iMSR, iSCR)
begin
case PADDR is
when "000" => if (iLCR_DLAB = '0') then
PRDATA(7 downto 0) <= iRBR;
else
PRDATA(7 downto 0) <= iDLL;
end if;
when "001" => if (iLCR_DLAB = '0') then
PRDATA(7 downto 0) <= iIER;
else
PRDATA(7 downto 0) <= iDLM;
end if;
when "010" => PRDATA(7 downto 0) <= iIIR;
when "011" => PRDATA(7 downto 0) <= iLCR;
when "100" => PRDATA(7 downto 0) <= iMCR;
when "101" => PRDATA(7 downto 0) <= iLSR;
when "110" => PRDATA(7 downto 0) <= iMSR;
when "111" => PRDATA(7 downto 0) <= iSCR;
when others => PRDATA(7 downto 0) <= iRBR;
end case;
end process;
PRDATA(31 downto 8) <= (others => '0');
PREADY <= '1';
PSLVERR <= '0';
end rtl;
|
apache-2.0
|
4ada3b5119bb012dee5a2e337931b2fc
| 0.430699 | 4.680283 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/ram_double_bank.vhd
| 1 | 4,666 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Essentials
-- Module Name: RAM Double Bank
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavior of a RAM Double Bank behavioral, where it can output
-- number_of_memories at once and have 2 interfaces, so it can read and write on the same cycle
-- Only used for tests.
--
-- The circuits parameters
--
-- number_of_memories :
--
-- Number of memories in the RAM Double Bank
--
-- ram_address_size :
-- Address size of the RAM Double Bank used on the circuit.
--
-- ram_word_size :
-- The size of internal word on the RAM Double Bank.
--
-- file_ram_word_size :
-- The size of the word used in the file to be loaded on the RAM Double Bank.(ARCH: FILE_LOAD)
--
-- load_file_name :
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
-- The name of the file to be used to dump the memory.
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
entity ram_double_bank is
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end ram_double_bank;
architecture simple of ram_double_bank is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
for I in ramtype'range loop
memory_ram(I) <= rst_value;
end loop;
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw_a = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address_a) + index)) <= data_in_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
if rw_b = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address_b) + index)) <= data_in_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
for index in 0 to (number_of_memories - 1) loop
data_out_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_a)) + index);
data_out_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_b)) + index);
end loop;
end if;
end process;
end simple;
|
bsd-2-clause
|
f20486f4e3ce8fe9bf2ec4432b802560
| 0.546078 | 3.495131 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/pipeline_polynomial_calc.vhd
| 1 | 4,316 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Pipeline_Polynomial_Calc
-- Module Name: Pipeline_Polynomial_Calc
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 3rd step in Goppa Code Decoding.
--
-- This circuit is to be used inside polynomial_evaluator_n to evaluate polynomials.
-- This circuit is the essential for 1 pipeline, therefor all stages are composed in here.
-- For more than 1 pipeline, only in polynomial_evaluator_n with the shared components
-- for all pipelines.
--
-- For the computation this circuit applies the school book algorithm of powering x
-- and multiplying by the respective polynomial coefficient and adding into the accumulator.
-- This method is not appropriate for this computation, so in pipeline_polynomial_calc_v2
-- Horner scheme is applied to reduce circuits costs.
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- size :
--
-- The number of stages the pipeline has. More stages means more values of value_polynomial
-- are tested at once.
--
-- Dependencies:
-- VHDL-93
--
-- stage_polynomial_calc Rev 1.0
-- register_nbits Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pipeline_polynomial_calc is
Generic (
gf_2_m : integer range 1 to 20 := 11;
size : integer := 28
);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((((gf_2_m)*size) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_x_pow : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
clk : in STD_LOGIC;
new_value_x_pow : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end pipeline_polynomial_calc;
architecture Behavioral of pipeline_polynomial_calc is
component stage_polynomial_calc
Generic(gf_2_m : integer range 1 to 20 := 11);
Port (
value_x : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
value_x_pow : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
value_polynomial_coefficient : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
new_value_x_pow : out STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0)
);
end component;
component register_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
type array_std_logic_vector is array(integer range <>) of std_logic_vector((gf_2_m - 1) downto 0);
signal acc_d : array_std_logic_vector((size) downto 0);
signal acc_q : array_std_logic_vector((size - 1) downto 0);
signal x_pow_d : array_std_logic_vector((size) downto 0);
signal x_pow_q : array_std_logic_vector((size - 1) downto 0);
signal x_q : array_std_logic_vector((size) downto 0);
begin
x_q(0) <= value_x;
x_pow_d(0) <= value_x_pow;
acc_d(0) <= value_acc;
pipeline : for I in 0 to (size - 1) generate
reg_x_I : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => x_q(I),
clk => clk,
ce => '1',
q => x_q(I+1)
);
reg_x_pow_I : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => x_pow_d(I),
clk => clk,
ce => '1',
q => x_pow_q(I)
);
reg_acc_I : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => acc_d(I),
clk => clk,
ce => '1',
q => acc_q(I)
);
stage_I : stage_polynomial_calc
Generic Map(gf_2_m => gf_2_m)
Port Map (
value_x => x_q(I+1),
value_x_pow => x_pow_q(I),
value_polynomial_coefficient => value_polynomial(((gf_2_m)*(I+1) - 1) downto ((gf_2_m)*(I))),
value_acc => acc_q(I),
new_value_x_pow => x_pow_d(I+1),
new_value_acc => acc_d(I+1)
);
end generate;
new_value_x_pow <= x_pow_d(size);
new_value_acc <= acc_d(size);
end Behavioral;
|
bsd-2-clause
|
6e7be68a74d09fe76cde96867ab2a0ea
| 0.629286 | 2.890824 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/controller_solving_key_equation_5.vhd
| 1 | 30,771 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_FG_Solving_Key_Equation_5
-- Module Name: Controller_FG_Solving_Key_Equation_5
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 2nd step in Goppa Code Decoding.
--
-- This is a state machine circuit that controls solving_key_equation_5 circuit.
-- This state machine have 3 phases: first phase variable initialization,
-- second computation of polynomial sigma, third step writing the polynomial sigma
-- on a specific memory position.
--
-- Dependencies:
--
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_solving_key_equation_5 is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_number_of_iterations : in STD_LOGIC;
last_polynomial_coefficient : in STD_LOGIC;
is_inv_zero : in STD_LOGIC;
is_r0_zero : in STD_LOGIC;
is_delta_less_than_0 : in STD_LOGIC;
is_rho_zero : in STD_LOGIC;
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_s : out STD_LOGIC;
write_enable_r : out STD_LOGIC;
write_enable_v : out STD_LOGIC;
write_enable_u : out STD_LOGIC;
sel_mult_r_inv : out STD_LOGIC;
last_u_value : out STD_LOGIC;
change_s_v : out STD_LOGIC;
change_r_u : out STD_LOGIC;
shift_r_u : out STD_LOGIC;
reg_value_s_rst : out STD_LOGIC;
reg_value_s_ce : out STD_LOGIC;
reg_value_r_rst : out STD_LOGIC;
reg_value_r_ce : out STD_LOGIC;
reg_value_v_rst : out STD_LOGIC;
reg_value_v_ce : out STD_LOGIC;
reg_value_u_rst : out STD_LOGIC;
reg_value_u_ce : out STD_LOGIC;
sel_reg_rho_rst_value : out STD_LOGIC;
reg_rho_rst : out STD_LOGIC;
reg_rho_ce : out STD_LOGIC;
ctr_delta_ce : out STD_LOGIC;
ctr_delta_load : out STD_LOGIC;
ctr_delta_rst : out STD_LOGIC;
reg_new_value_s_rst : out STD_LOGIC;
reg_new_value_s_ce : out STD_LOGIC;
reg_new_value_r_rst : out STD_LOGIC;
reg_new_value_r_ce : out STD_LOGIC;
reg_new_value_v_ce : out STD_LOGIC;
reg_new_value_u_rst : out STD_LOGIC;
reg_new_value_u_ce : out STD_LOGIC;
reg_new_value_u0_ce : out STD_LOGIC;
ctr_load_value_ce : out STD_LOGIC;
ctr_load_value_rst : out STD_LOGIC;
ctr_store_value_ce : out STD_LOGIC;
ctr_store_value_rst : out STD_LOGIC;
ctr_number_of_iterations_ce : out STD_LOGIC;
ctr_number_of_iterations_rst : out STD_LOGIC
);
end controller_solving_key_equation_5;
architecture Behavioral of controller_solving_key_equation_5 is
type State is (reset, load_counters, prepare_inital_s_r_v_u, prepare_inital_s_r_v_u_2, prepare_inital_s_r_v_u_3, load_inital_s_r_v_u, last_load_inital_s_r_v_u, load_first_values, compute_rho, compute_u0, prepare_compute_new_polynomials, prepare_compute_new_polynomials_2, compute_new_polynomials, last_compute_new_polynomials, update_delta, prepare_last_swap, prepare_last_swap_2, last_swap, finalize_swap, final);
signal actual_state, next_state : State;
begin
Clock : process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output : process (actual_state, limit_number_of_iterations, last_polynomial_coefficient, is_inv_zero, is_r0_zero, is_delta_less_than_0, is_rho_zero)
begin
case (actual_state) is
when reset =>
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '0';
write_enable_r <= '0';
write_enable_v <= '0';
write_enable_u <= '0';
sel_mult_r_inv <= '0';
last_u_value <= '0';
change_s_v <= '0';
change_r_u <= '0';
shift_r_u <= '0';
reg_value_s_rst <= '1';
reg_value_s_ce <= '0';
reg_value_r_rst <= '1';
reg_value_r_ce <= '0';
reg_value_v_rst <= '1';
reg_value_v_ce <= '0';
reg_value_u_rst <= '1';
reg_value_u_ce <= '0';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '1';
reg_new_value_s_rst <= '1';
reg_new_value_s_ce <= '0';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '0';
reg_new_value_v_ce <= '0';
reg_new_value_u_rst <= '1';
reg_new_value_u_ce <= '0';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '0';
ctr_load_value_rst <= '1';
ctr_store_value_ce <= '0';
ctr_store_value_rst <= '1';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '1';
when load_counters =>
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '0';
write_enable_r <= '0';
write_enable_v <= '0';
write_enable_u <= '0';
sel_mult_r_inv <= '0';
last_u_value <= '0';
change_s_v <= '0';
change_r_u <= '0';
shift_r_u <= '0';
reg_value_s_rst <= '0';
reg_value_s_ce <= '0';
reg_value_r_rst <= '0';
reg_value_r_ce <= '0';
reg_value_v_rst <= '0';
reg_value_v_ce <= '0';
reg_value_u_rst <= '0';
reg_value_u_ce <= '0';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '0';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '0';
reg_new_value_v_ce <= '0';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '0';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '1';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '0';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when prepare_inital_s_r_v_u =>
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '0';
write_enable_r <= '0';
write_enable_v <= '0';
write_enable_u <= '0';
sel_mult_r_inv <= '0';
last_u_value <= '0';
change_s_v <= '0';
change_r_u <= '0';
shift_r_u <= '0';
reg_value_s_rst <= '1';
reg_value_s_ce <= '0';
reg_value_r_rst <= '0';
reg_value_r_ce <= '1';
reg_value_v_rst <= '1';
reg_value_v_ce <= '0';
reg_value_u_rst <= '1';
reg_value_u_ce <= '0';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '0';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '0';
reg_new_value_v_ce <= '0';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '0';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '1';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '0';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when prepare_inital_s_r_v_u_2 =>
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '0';
write_enable_r <= '0';
write_enable_v <= '0';
write_enable_u <= '0';
sel_mult_r_inv <= '0';
last_u_value <= '0';
change_s_v <= '0';
change_r_u <= '0';
shift_r_u <= '0';
reg_value_s_rst <= '1';
reg_value_s_ce <= '0';
reg_value_r_rst <= '0';
reg_value_r_ce <= '1';
reg_value_v_rst <= '1';
reg_value_v_ce <= '0';
reg_value_u_rst <= '1';
reg_value_u_ce <= '0';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '1';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '1';
reg_new_value_v_ce <= '1';
reg_new_value_u_rst <= '1';
reg_new_value_u_ce <= '0';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '1';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '0';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when prepare_inital_s_r_v_u_3 =>
signal_inv <= '1';
key_equation_found <= '0';
write_enable_s <= '1';
write_enable_r <= '1';
write_enable_v <= '1';
write_enable_u <= '1';
sel_mult_r_inv <= '0';
last_u_value <= '0';
change_s_v <= '0';
change_r_u <= '0';
shift_r_u <= '0';
reg_value_s_rst <= '1';
reg_value_s_ce <= '0';
reg_value_r_rst <= '0';
reg_value_r_ce <= '1';
reg_value_v_rst <= '1';
reg_value_v_ce <= '0';
reg_value_u_rst <= '1';
reg_value_u_ce <= '0';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '1';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '1';
reg_new_value_v_ce <= '1';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '1';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '1';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '1';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when load_inital_s_r_v_u =>
if(last_polynomial_coefficient = '1') then
reg_new_value_s_rst <= '1';
reg_new_value_s_ce <= '0';
reg_new_value_r_rst <= '1';
reg_new_value_r_ce <= '0';
ctr_load_value_ce <= '0';
ctr_load_value_rst <= '1';
else
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '1';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '1';
ctr_load_value_ce <= '1';
ctr_load_value_rst <= '0';
end if;
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '1';
write_enable_r <= '1';
write_enable_v <= '1';
write_enable_u <= '1';
sel_mult_r_inv <= '0';
last_u_value <= '0';
change_s_v <= '0';
change_r_u <= '0';
shift_r_u <= '0';
reg_value_s_rst <= '1';
reg_value_s_ce <= '0';
reg_value_r_rst <= '0';
reg_value_r_ce <= '1';
reg_value_v_rst <= '1';
reg_value_v_ce <= '0';
reg_value_u_rst <= '1';
reg_value_u_ce <= '0';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_v_ce <= '1';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '1';
reg_new_value_u0_ce <= '0';
ctr_store_value_ce <= '1';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when last_load_inital_s_r_v_u =>
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '1';
write_enable_r <= '1';
write_enable_v <= '1';
write_enable_u <= '1';
sel_mult_r_inv <= '0';
last_u_value <= '0';
change_s_v <= '0';
change_r_u <= '0';
shift_r_u <= '0';
reg_value_s_rst <= '0';
reg_value_s_ce <= '0';
reg_value_r_rst <= '0';
reg_value_r_ce <= '0';
reg_value_v_rst <= '0';
reg_value_v_ce <= '0';
reg_value_u_rst <= '0';
reg_value_u_ce <= '0';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '0';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '0';
reg_new_value_v_ce <= '0';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '0';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '0';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '0';
ctr_store_value_rst <= '1';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when load_first_values =>
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '0';
write_enable_r <= '0';
write_enable_v <= '0';
write_enable_u <= '0';
sel_mult_r_inv <= '0';
last_u_value <= '0';
change_s_v <= '0';
change_r_u <= '0';
shift_r_u <= '1';
reg_value_s_rst <= '0';
reg_value_s_ce <= '1';
reg_value_r_rst <= '0';
reg_value_r_ce <= '1';
reg_value_v_rst <= '0';
reg_value_v_ce <= '1';
reg_value_u_rst <= '0';
reg_value_u_ce <= '1';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '0';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '0';
reg_new_value_v_ce <= '0';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '0';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '1';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '0';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when compute_rho =>
if(is_r0_zero = '1') then
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '1';
reg_rho_ce <= '0';
elsif(is_inv_zero = '1') then
sel_reg_rho_rst_value <= '1';
reg_rho_rst <= '1';
reg_rho_ce <= '0';
else
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '1';
end if;
if(is_delta_less_than_0 = '1' and is_r0_zero = '0') then
change_s_v <= '1';
else
change_s_v <= '0';
end if;
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '0';
write_enable_r <= '0';
write_enable_v <= '0';
write_enable_u <= '0';
sel_mult_r_inv <= '1';
last_u_value <= '0';
change_r_u <= '0';
shift_r_u <= '1';
reg_value_s_rst <= '0';
reg_value_s_ce <= '1';
reg_value_r_rst <= '0';
reg_value_r_ce <= '1';
reg_value_v_rst <= '0';
reg_value_v_ce <= '1';
reg_value_u_rst <= '0';
reg_value_u_ce <= '1';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '0';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '0';
reg_new_value_v_ce <= '0';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '0';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '1';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '0';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when compute_u0 =>
if(is_delta_less_than_0 = '1' and is_r0_zero = '0') then
change_s_v <= '1';
else
change_s_v <= '0';
end if;
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '0';
write_enable_r <= '0';
write_enable_v <= '0';
write_enable_u <= '0';
sel_mult_r_inv <= '0';
last_u_value <= '0';
change_r_u <= '0';
shift_r_u <= '1';
reg_value_s_rst <= '0';
reg_value_s_ce <= '1';
reg_value_r_rst <= '0';
reg_value_r_ce <= '1';
reg_value_v_rst <= '0';
reg_value_v_ce <= '1';
reg_value_u_rst <= '0';
reg_value_u_ce <= '1';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '1';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '1';
reg_new_value_v_ce <= '1';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '1';
reg_new_value_u0_ce <= '1';
ctr_load_value_ce <= '1';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '0';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when prepare_compute_new_polynomials =>
if(is_delta_less_than_0 = '1' and is_rho_zero = '0') then
change_s_v <= '1';
else
change_s_v <= '0';
end if;
signal_inv <= '1';
key_equation_found <= '0';
write_enable_s <= '1';
write_enable_r <= '0';
write_enable_v <= '1';
write_enable_u <= '0';
sel_mult_r_inv <= '0';
last_u_value <= '0';
change_r_u <= '0';
shift_r_u <= '1';
reg_value_s_rst <= '0';
reg_value_s_ce <= '1';
reg_value_r_rst <= '0';
reg_value_r_ce <= '1';
reg_value_v_rst <= '0';
reg_value_v_ce <= '1';
reg_value_u_rst <= '0';
reg_value_u_ce <= '1';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '1';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '1';
reg_new_value_v_ce <= '1';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '1';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '1';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '1';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when prepare_compute_new_polynomials_2 =>
if(is_delta_less_than_0 = '1' and is_rho_zero = '0') then
change_s_v <= '1';
else
change_s_v <= '0';
end if;
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '1';
write_enable_r <= '1';
write_enable_v <= '1';
write_enable_u <= '1';
sel_mult_r_inv <= '0';
last_u_value <= '0';
change_r_u <= '0';
shift_r_u <= '1';
reg_value_s_rst <= '0';
reg_value_s_ce <= '1';
reg_value_r_rst <= '0';
reg_value_r_ce <= '1';
reg_value_v_rst <= '0';
reg_value_v_ce <= '1';
reg_value_u_rst <= '0';
reg_value_u_ce <= '1';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '1';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '1';
reg_new_value_v_ce <= '1';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '1';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '1';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '1';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when compute_new_polynomials =>
if(last_polynomial_coefficient = '1') then
reg_value_u_rst <= '1';
reg_value_u_ce <= '0';
else
reg_value_u_rst <= '0';
reg_value_u_ce <= '1';
end if;
if(is_delta_less_than_0 = '1' and is_rho_zero = '0') then
change_s_v <= '1';
else
change_s_v <= '0';
end if;
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '1';
write_enable_r <= '1';
write_enable_v <= '1';
write_enable_u <= '1';
sel_mult_r_inv <= '0';
last_u_value <= '0';
change_r_u <= '0';
shift_r_u <= '1';
reg_value_s_rst <= '0';
reg_value_s_ce <= '1';
reg_value_r_rst <= '0';
reg_value_r_ce <= '1';
reg_value_v_rst <= '0';
reg_value_v_ce <= '1';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '1';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '1';
reg_new_value_v_ce <= '1';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '1';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '1';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '1';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when last_compute_new_polynomials =>
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '1';
write_enable_r <= '1';
write_enable_v <= '1';
write_enable_u <= '1';
sel_mult_r_inv <= '0';
last_u_value <= '1';
change_s_v <= '0';
change_r_u <= '0';
shift_r_u <= '1';
reg_value_s_rst <= '0';
reg_value_s_ce <= '0';
reg_value_r_rst <= '0';
reg_value_r_ce <= '0';
reg_value_v_rst <= '0';
reg_value_v_ce <= '0';
reg_value_u_rst <= '0';
reg_value_u_ce <= '0';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '0';
reg_new_value_r_rst <= '1';
reg_new_value_r_ce <= '0';
reg_new_value_v_ce <= '0';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '1';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '0';
ctr_load_value_rst <= '1';
ctr_store_value_ce <= '0';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when update_delta =>
if(limit_number_of_iterations = '1') then
ctr_load_value_ce <= '1';
else
ctr_load_value_ce <= '0';
end if;
if(is_delta_less_than_0 = '1' and is_rho_zero = '0') then
ctr_delta_load <= '1';
else
ctr_delta_load <= '0';
end if;
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '0';
write_enable_r <= '1';
write_enable_v <= '0';
write_enable_u <= '1';
sel_mult_r_inv <= '0';
last_u_value <= '0';
change_s_v <= '0';
change_r_u <= '0';
shift_r_u <= '1';
reg_value_s_rst <= '0';
reg_value_s_ce <= '0';
reg_value_r_rst <= '0';
reg_value_r_ce <= '0';
reg_value_v_rst <= '0';
reg_value_v_ce <= '0';
reg_value_u_rst <= '0';
reg_value_u_ce <= '0';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '1';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '0';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '0';
reg_new_value_v_ce <= '0';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '0';
reg_new_value_u0_ce <= '0';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '0';
ctr_store_value_rst <= '1';
ctr_number_of_iterations_ce <= '1';
ctr_number_of_iterations_rst <= '0';
when prepare_last_swap =>
if(is_delta_less_than_0 = '0') then
change_s_v <= '1';
change_r_u <= '1';
else
change_s_v <= '0';
change_r_u <= '0';
end if;
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '0';
write_enable_r <= '0';
write_enable_v <= '0';
write_enable_u <= '0';
sel_mult_r_inv <= '0';
last_u_value <= '0';
shift_r_u <= '0';
reg_value_s_rst <= '0';
reg_value_s_ce <= '1';
reg_value_r_rst <= '0';
reg_value_r_ce <= '1';
reg_value_v_rst <= '0';
reg_value_v_ce <= '1';
reg_value_u_rst <= '0';
reg_value_u_ce <= '1';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '1';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '0';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '0';
reg_new_value_v_ce <= '0';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '0';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '1';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '0';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when prepare_last_swap_2 =>
if(is_delta_less_than_0 = '0') then
change_s_v <= '1';
change_r_u <= '1';
else
change_s_v <= '0';
change_r_u <= '0';
end if;
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '0';
write_enable_r <= '0';
write_enable_v <= '0';
write_enable_u <= '0';
sel_mult_r_inv <= '0';
last_u_value <= '0';
shift_r_u <= '0';
reg_value_s_rst <= '0';
reg_value_s_ce <= '1';
reg_value_r_rst <= '0';
reg_value_r_ce <= '1';
reg_value_v_rst <= '0';
reg_value_v_ce <= '1';
reg_value_u_rst <= '0';
reg_value_u_ce <= '1';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '1';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '1';
reg_new_value_v_ce <= '1';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '1';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '1';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '0';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when last_swap =>
if(is_delta_less_than_0 = '0') then
change_s_v <= '1';
change_r_u <= '1';
else
change_s_v <= '0';
change_r_u <= '0';
end if;
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '1';
write_enable_r <= '1';
write_enable_v <= '1';
write_enable_u <= '1';
sel_mult_r_inv <= '0';
last_u_value <= '0';
shift_r_u <= '0';
reg_value_s_rst <= '0';
reg_value_s_ce <= '1';
reg_value_r_rst <= '0';
reg_value_r_ce <= '1';
reg_value_v_rst <= '0';
reg_value_v_ce <= '1';
reg_value_u_rst <= '0';
reg_value_u_ce <= '1';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '1';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '1';
reg_new_value_v_ce <= '1';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '1';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '1';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '1';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when finalize_swap =>
if(is_delta_less_than_0 = '0') then
change_s_v <= '1';
change_r_u <= '1';
else
change_s_v <= '0';
change_r_u <= '0';
end if;
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '1';
write_enable_r <= '1';
write_enable_v <= '1';
write_enable_u <= '1';
sel_mult_r_inv <= '0';
last_u_value <= '0';
shift_r_u <= '0';
reg_value_s_rst <= '0';
reg_value_s_ce <= '0';
reg_value_r_rst <= '0';
reg_value_r_ce <= '0';
reg_value_v_rst <= '0';
reg_value_v_ce <= '0';
reg_value_u_rst <= '0';
reg_value_u_ce <= '0';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '1';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '1';
reg_new_value_v_ce <= '1';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '1';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '0';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '1';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when final =>
signal_inv <= '0';
key_equation_found <= '1';
write_enable_s <= '0';
write_enable_r <= '0';
write_enable_v <= '0';
write_enable_u <= '0';
sel_mult_r_inv <= '0';
last_u_value <= '0';
change_s_v <= '0';
change_r_u <= '0';
shift_r_u <= '0';
reg_value_s_rst <= '0';
reg_value_s_ce <= '0';
reg_value_r_rst <= '0';
reg_value_r_ce <= '0';
reg_value_v_rst <= '0';
reg_value_v_ce <= '0';
reg_value_u_rst <= '0';
reg_value_u_ce <= '0';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '0';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '0';
reg_new_value_v_ce <= '0';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '0';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '0';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '0';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
when others =>
signal_inv <= '0';
key_equation_found <= '0';
write_enable_s <= '0';
write_enable_r <= '0';
write_enable_v <= '0';
write_enable_u <= '0';
sel_mult_r_inv <= '0';
last_u_value <= '0';
change_s_v <= '0';
change_r_u <= '0';
shift_r_u <= '0';
reg_value_s_rst <= '0';
reg_value_s_ce <= '0';
reg_value_r_rst <= '0';
reg_value_r_ce <= '0';
reg_value_v_rst <= '0';
reg_value_v_ce <= '0';
reg_value_u_rst <= '0';
reg_value_u_ce <= '0';
sel_reg_rho_rst_value <= '0';
reg_rho_rst <= '0';
reg_rho_ce <= '0';
ctr_delta_ce <= '0';
ctr_delta_load <= '0';
ctr_delta_rst <= '0';
reg_new_value_s_rst <= '0';
reg_new_value_s_ce <= '0';
reg_new_value_r_rst <= '0';
reg_new_value_r_ce <= '0';
reg_new_value_v_ce <= '0';
reg_new_value_u_rst <= '0';
reg_new_value_u_ce <= '0';
reg_new_value_u0_ce <= '0';
ctr_load_value_ce <= '0';
ctr_load_value_rst <= '0';
ctr_store_value_ce <= '0';
ctr_store_value_rst <= '0';
ctr_number_of_iterations_ce <= '0';
ctr_number_of_iterations_rst <= '0';
end case;
end process;
New_State : process (actual_state, limit_number_of_iterations, last_polynomial_coefficient, is_inv_zero, is_r0_zero, is_delta_less_than_0, is_rho_zero)
begin
case (actual_state) is
when reset =>
next_state <= load_counters;
when load_counters =>
next_state <= prepare_inital_s_r_v_u;
when prepare_inital_s_r_v_u =>
next_state <= prepare_inital_s_r_v_u_2;
when prepare_inital_s_r_v_u_2 =>
next_state <= prepare_inital_s_r_v_u_3;
when prepare_inital_s_r_v_u_3 =>
next_state <= load_inital_s_r_v_u;
when load_inital_s_r_v_u =>
if(last_polynomial_coefficient = '1') then
next_state <= last_load_inital_s_r_v_u;
else
next_state <= load_inital_s_r_v_u;
end if;
when last_load_inital_s_r_v_u =>
next_state <= load_first_values;
when load_first_values =>
next_state <= compute_rho;
when compute_rho =>
next_state <= compute_u0;
when compute_u0 =>
next_state <= prepare_compute_new_polynomials;
when prepare_compute_new_polynomials =>
next_state <= prepare_compute_new_polynomials_2;
when prepare_compute_new_polynomials_2 =>
next_state <= compute_new_polynomials;
when compute_new_polynomials =>
if(last_polynomial_coefficient = '1') then
next_state <= last_compute_new_polynomials;
else
next_state <= compute_new_polynomials;
end if;
when last_compute_new_polynomials =>
next_state <= update_delta;
when update_delta =>
if(limit_number_of_iterations = '1') then
next_state <= prepare_last_swap;
else
next_state <= load_first_values;
end if;
when prepare_last_swap =>
next_state <= prepare_last_swap_2;
when prepare_last_swap_2 =>
next_state <= last_swap;
when last_swap =>
if(last_polynomial_coefficient = '1') then
next_state <= finalize_swap;
else
next_state <= last_swap;
end if;
when finalize_swap =>
next_state <= final;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
402a5486262889474fe112dfdc7c0c15
| 0.531604 | 2.291726 | false | false | false | false |
ruygargar/LCSE_lab
|
dma/tb_dma.vhd
| 1 | 4,674 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:22:16 01/07/2014
-- Design Name:
-- Module Name: C:/Users/Ruy/Desktop/LCSE_lab/dma/tb_dma.vhd
-- Project Name: dma
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dma
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_dma IS
END tb_dma;
ARCHITECTURE behavior OF tb_dma IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dma
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
Databus : INOUT std_logic_vector(7 downto 0);
Address : OUT std_logic_vector(7 downto 0);
ChipSelect : OUT std_logic;
WriteEnable : OUT std_logic;
OutputEnable : OUT std_logic;
Send : IN std_logic;
Ready : OUT std_logic;
DMA_RQ : OUT std_logic;
DMA_ACK : IN std_logic;
TX_data : OUT std_logic_vector(7 downto 0);
Valid_D : OUT std_logic;
Ack_out : IN std_logic;
TX_RDY : IN std_logic;
RCVD_data : IN std_logic_vector(7 downto 0);
Data_read : OUT std_logic;
RX_Full : IN std_logic;
RX_empty : IN std_logic
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal Send : std_logic := '0';
signal DMA_ACK : std_logic := '0';
signal Ack_out : std_logic := '0';
signal TX_RDY : std_logic := '0';
signal RCVD_data : std_logic_vector(7 downto 0) := (others => '0');
signal RX_Full : std_logic := '1';
signal RX_empty : std_logic := '1';
--BiDirs
signal Databus : std_logic_vector(7 downto 0);
--Outputs
signal Address : std_logic_vector(7 downto 0);
signal ChipSelect : std_logic;
signal WriteEnable : std_logic;
signal OutputEnable : std_logic;
signal Ready : std_logic;
signal DMA_RQ : std_logic;
signal TX_data : std_logic_vector(7 downto 0);
signal Valid_D : std_logic;
signal Data_read : std_logic;
-- Clock period definitions
constant Clk_period : time := 25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dma PORT MAP (
Clk => Clk,
Reset => Reset,
Databus => Databus,
Address => Address,
ChipSelect => ChipSelect,
WriteEnable => WriteEnable,
OutputEnable => OutputEnable,
Send => Send,
Ready => Ready,
DMA_RQ => DMA_RQ,
DMA_ACK => DMA_ACK,
TX_data => TX_data,
Valid_D => Valid_D,
Ack_out => Ack_out,
TX_RDY => TX_RDY,
RCVD_data => RCVD_data,
Data_read => Data_read,
RX_Full => RX_Full,
RX_empty => RX_empty
);
-- Clock process definitions
Clk <= not Clk after Clk_period;
-- Stimulus
Reset <= '1' after 100 ns;
Databus <= X"00", (others => 'Z') after 326 ns, X"22" after 576 ns, X"AA" after 676 ns, (others => 'Z') after 776 ns, X"22" after 826 ns,
(others => 'Z') after 976 ns;
Address <= X"00", (others => 'Z') after 326 ns, X"88" after 576 ns, (others => 'Z') after 676 ns, X"88" after 826 ns,
(others => 'Z') after 976 ns;
ChipSelect <= '0', 'Z' after 326 ns, '1' after 576 ns, 'Z' after 676 ns, '1' after 826 ns, 'Z' after 976 ns;
WriteEnable <= '0', 'Z' after 326 ns, '1' after 576 ns, 'Z' after 676 ns, '1' after 826 ns, 'Z' after 976 ns;
OutputEnable <= '0', 'Z' after 326 ns, '0' after 576 ns, 'Z' after 676 ns, '1' after 826 ns, 'Z' after 976 ns;
Send <= '1' after 626 ns, '0' after 776 ns;
DMA_ACK <= '1' after 276 ns, '0' after 526 ns, '1' after 926 ns, '0' after 1076 ns, '1' after 1226 ns;
RCVD_data <= X"55" after 250 ns;
RX_empty <= '0' after 250 ns, '1' after 1026 ns, '0' after 1201 ns, '1' after 1376 ns;
process
begin
wait;
end process;
END;
|
gpl-3.0
|
62ad4e3c57a9c19436971228e2a67c83
| 0.569961 | 3.482861 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/ram_generator_matrix_file.vhd
| 1 | 4,734 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: QDGoppa
-- Module Name: RAM Generator Matrix
-- Project Name: QDGoppa
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavior of a RAM Bank behavioral, where it can output
-- number_of_memories at once, with different address for each memory. Only used for tests.
--
-- The circuits parameters
--
-- number_of_memories :
--
-- Number of memories in the RAM Bank
--
-- ram_address_size :
-- Address size of the RAM bank used on the circuit.
--
-- ram_word_size :
-- The size of internal word on the RAM Bank.
--
-- file_ram_word_size :
-- The size of the word used in the file to be loaded on the RAM Bank.(ARCH: FILE_LOAD)
--
-- load_file_name :
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
-- The name of the file to be used to dump the memory.
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
architecture file_load of ram_generator_matrix is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
pure function load_ram (ram_file_name : in string) return ramtype is
FILE ram_file : text is in ram_file_name;
variable line_n : line;
variable memory_ram : ramtype;
variable file_read_buffer : std_logic_vector((file_ram_word_size - 1) downto 0);
variable file_buffer_amount : integer;
variable ram_buffer_amount : integer;
begin
file_buffer_amount := file_ram_word_size;
for I in ramtype'range loop
ram_buffer_amount := 0;
if (not endfile(ram_file) or (file_buffer_amount /= file_ram_word_size)) then
while ram_buffer_amount /= ram_word_size loop
if file_buffer_amount = file_ram_word_size then
if (not endfile(ram_file)) then
readline (ram_file, line_n);
read (line_n, file_read_buffer);
else
file_read_buffer := (others => '0');
end if;
file_buffer_amount := 0;
end if;
memory_ram(I)(ram_buffer_amount) := file_read_buffer(file_buffer_amount);
ram_buffer_amount := ram_buffer_amount + 1;
file_buffer_amount := file_buffer_amount + 1;
end loop;
else
memory_ram(I) := (others => '0');
end if;
end loop;
return memory_ram;
end function;
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype := load_ram(load_file_name);
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
memory_ram <= load_ram(load_file_name);
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))) <= data_in(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
for index in 0 to (number_of_memories - 1) loop
data_out(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index)))));
end loop;
end if;
end process;
end file_load;
|
bsd-2-clause
|
27007b109e8a78c8a6b8e6071e3b82d5
| 0.504014 | 3.961506 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/multiplication/biaser/biaser.vhd
| 1 | 845 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity biaser is
generic(
EXP_BITS: natural := 6
);
port (
operation : in std_logic; --Indicates whether to add or remove the bias
exp_in: in std_logic_vector(EXP_BITS - 1 downto 0);
exp_out: out std_logic_vector(EXP_BITS - 1 downto 0)
);
end;
architecture biaser_arq of biaser is
begin
process(operation, exp_in)
variable bias_vector : std_logic_vector(EXP_BITS - 2 downto 0) := (others => '1');
variable bias : integer := to_integer(unsigned(bias_vector));
variable tmp_exp : integer := 0;
begin
tmp_exp := to_integer(unsigned(exp_in));
if operation = '0' then
exp_out <= std_logic_vector(to_signed(tmp_exp + bias, EXP_BITS));
else
exp_out <= std_logic_vector(to_signed(tmp_exp - bias, EXP_BITS));
end if;
end process;
end architecture;
|
gpl-3.0
|
d9cd0189abb83fa7dc7d3de1c0d33715
| 0.68284 | 2.893836 | false | false | false | false |
alainmarcel/Surelog
|
third_party/tests/ariane/fpga/src/apb_uart/src/uart_baudgen.vhd
| 5 | 2,234 |
--
-- UART Baudrate generator
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART baudrate generator
entity uart_baudgen is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
CLEAR : in std_logic; -- Reset generator (synchronization)
DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider
BAUDTICK : out std_logic -- 16xBaudrate tick
);
end uart_baudgen;
architecture rtl of uart_baudgen is
-- Signals
signal iCounter : unsigned(15 downto 0);
begin
-- Baudrate counter
BG_COUNT: process (CLK, RST)
begin
if (RST = '1') then
iCounter <= (others => '0');
BAUDTICK <= '0';
elsif (CLK'event and CLK = '1') then
if (CLEAR = '1') then
iCounter <= (others => '0');
elsif (CE = '1') then
iCounter <= iCounter + 1;
end if;
BAUDTICK <= '0';
if (iCounter = unsigned(DIVIDER)) then
iCounter <= (others => '0');
BAUDTICK <= '1';
end if;
end if;
end process;
end rtl;
|
apache-2.0
|
f9de90ce6cfdc0ad3d8af2d1903313c9
| 0.550582 | 4.380392 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/base_complementer/base_complementer_tb.vhd
| 1 | 1,498 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity base_complementer_tb is
end entity;
architecture base_complementer_tb_arq of base_complementer_tb is
signal number_in : std_logic_vector(15 downto 0) := (others => '0');
signal number_out : std_logic_vector(15 downto 0) := (others => '0');
component base_complementer is
generic(
TOTAL_BITS : natural := 16
);
port(
number_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
number_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
for base_complementer_0 : base_complementer use entity work.base_complementer;
begin
base_complementer_0 : base_complementer
generic map(TOTAL_BITS => 16)
port map(
number_in => number_in,
number_out => number_out
);
process
type pattern_type is record
ni : integer;
no : integer;
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
(1,-1),
(0,0),
(10,-10)
);
begin
for i in patterns'range loop
-- Set the inputs.
number_in <= std_logic_vector(to_signed(patterns(i).ni,16));
wait for 1 ns;
assert patterns(i).no = to_integer(signed(number_out)) report "BAD COMPLEMENT, GOT: " & integer'image(to_integer(signed(number_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
e6971e4a8de7cd1b3dff7165e3116411
| 0.661549 | 3.075975 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/preprocessor/preprocessor.vhd
| 1 | 2,343 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--This component add or substracts a fixed value from the coordenates to rotate them before applying cordic
entity preprocessor is
generic(TOTAL_BITS: integer := 32);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
angle_in : in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
angle_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end preprocessor;
architecture preprocessor_arq of preprocessor is
begin
process (x_in, y_in, angle_in) is
variable angle_int : integer := 0;
variable fractional_angle_part : std_logic_vector((TOTAL_BITS/2) - 1 downto 0) := (others => '0');
variable x_int : integer := 0;
variable y_int : integer := 0;
variable tmp_int: integer := 0;
begin
angle_int := to_integer(signed(angle_in(TOTAL_BITS - 1 downto TOTAL_BITS/2))); --Get only the integer part, not the factional part
fractional_angle_part := angle_in((TOTAL_BITS/2) - 1 downto 0);
x_int := to_integer(signed(x_in));
y_int := to_integer(signed(y_in));
if(angle_int > 180) then
angle_int := angle_int - 360;
elsif (angle_int < -180) then
angle_int := 360 + angle_int;
end if;
if(angle_int > 90) then
tmp_int := x_int;
x_int := -y_int;
y_int := tmp_int;
angle_int := angle_int - 90;
elsif(angle_int < -90) then
tmp_int := y_int;
y_int := -x_int;
x_int := tmp_int;
angle_int := angle_int + 90;
end if;
angle_out <= std_logic_vector(to_signed(angle_int,TOTAL_BITS/2)) & fractional_angle_part;
x_out <= std_logic_vector(to_signed(x_int,TOTAL_BITS));
y_out <= std_logic_vector(to_signed(y_int,TOTAL_BITS));
end process;
end architecture;
|
gpl-3.0
|
78eb2f477ef0320a60c5886b3c41274d
| 0.542467 | 3.507485 | false | false | false | false |
pwuertz/digitizer2fw
|
src/rtl/acquisition.vhd
| 1 | 8,762 |
-------------------------------------------------------------------------------
-- Digitizer2 acquisition logic
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sampling_pkg.all;
use work.maxfinder_pkg.all;
use work.tdc_sample_prep_pkg.all;
entity acquisition is
generic ( TDC_CNT_BITS: natural := 22 );
port (
-- acquisition domain
clk_samples: in std_logic;
samples_d_in: in din_samples_t(0 to 3);
samples_a_in: in adc_samples_t(0 to 1);
a_threshold: in a_sample_t;
a_invert: in std_logic;
a_average: in std_logic_vector(1 downto 0);
acq_mode: in std_logic_vector(1 downto 0);
acq_start_src: in std_logic_vector(2 downto 0);
acq_stop_src: in std_logic_vector(2 downto 0);
acq_reset: in std_logic;
acq_stop: in std_logic;
acq_state: out std_logic_vector(2 downto 0);
-- application domain
clk_rd: in std_logic;
rd_en: in std_logic;
rd_empty: out std_logic;
rd_data: out std_logic_vector(15 downto 0);
rd_2xcnt: out std_logic_vector(15 downto 0)
);
end acquisition;
architecture acquisition_arch of acquisition is
component tdc_sample_prep is
generic ( CNT_BITS: natural := TDC_CNT_BITS );
port (
clk: in std_logic;
samples_d_in: in din_samples_t(0 to 3);
samples_a_in: in adc_samples_t(0 to 1);
a_threshold: in a_sample_t;
a_invert: in std_logic;
a_average: in std_logic_vector(1 downto 0);
--
samples_d_out: out din_samples_t(0 to 3);
samples_a_out: out a_samples_t(0 to 1);
cnt: out unsigned(CNT_BITS-1 downto 0);
tdc_events: out tdc_events_t
);
end component;
signal tdc_d : din_samples_t ( 0 to 3 );
signal tdc_a : a_samples_t ( 0 to 1 );
signal tdc_cnt : unsigned ( TDC_CNT_BITS-1 downto 0 );
signal tdc_events : tdc_events_t;
component fifo_acquisition
port (
rst: in std_logic;
wr_clk: in std_logic;
rd_clk: in std_logic;
din : IN std_logic_vector(31 downto 0);
wr_en: in std_logic;
rd_en: in std_logic;
dout : out std_logic_vector(15 downto 0);
full: out std_logic;
empty: out std_logic;
rd_data_count: out std_logic_vector(16 downto 0)
);
end component;
signal acq_buffer_din: std_logic_vector(31 downto 0);
signal acq_buffer_dout: std_logic_vector(15 downto 0);
signal acq_buffer_rst: std_logic;
signal acq_buffer_full: std_logic;
signal acq_buffer_empty: std_logic;
signal acq_buffer_rd: std_logic;
signal acq_buffer_wr: std_logic;
signal acq_buffer_rd_cnt: std_logic_vector(16 downto 0);
signal acq_state_out: std_logic_vector(2 downto 0);
begin
tdc_sample_prep_inst: tdc_sample_prep
generic map (CNT_BITS => TDC_CNT_BITS)
port map(
clk => clk_samples,
samples_d_in => samples_d_in,
samples_a_in => samples_a_in,
a_threshold => a_threshold,
a_invert => a_invert,
a_average => a_average,
samples_d_out => tdc_d,
samples_a_out => tdc_a,
cnt => tdc_cnt,
tdc_events => tdc_events
);
fifo_acq_inst: fifo_acquisition
port map (
rst => acq_buffer_rst,
wr_clk => clk_samples,
rd_clk => clk_rd,
din => acq_buffer_din,
wr_en => acq_buffer_wr,
rd_en => acq_buffer_rd,
dout => acq_buffer_dout,
full => acq_buffer_full,
empty => acq_buffer_empty,
rd_data_count => acq_buffer_rd_cnt
);
rd_empty <= acq_buffer_empty;
rd_data <= acq_buffer_dout;
acq_buffer_rd <= rd_en;
rd_2xcnt <= acq_buffer_rd_cnt(acq_buffer_rd_cnt'high downto 1);
acquisition_process: process(clk_samples)
type event_source_map_t is array(integer range 0 to 6) of std_logic;
variable event_source_map: event_source_map_t;
type acq_state_t is (s_reset, s_wait_ready, s_waittrig, s_buffering, s_done);
variable tdc_cnt_zero: unsigned(tdc_cnt'range) := (others => '0');
variable acq_state_int: acq_state_t := s_reset;
variable tdc_cnt_ovfl: std_logic := '0';
variable start_trig: std_logic := '0';
variable stop_trig: std_logic := '0';
begin
if rising_edge(clk_samples) then
-- write state to global register, converted to unsigned/slv
acq_state_out <= std_logic_vector(to_unsigned(acq_state_t'pos(acq_state_int), 3));
-- reset acquisition fifo when in reset state
if acq_state_int = s_reset then
acq_buffer_rst <= '1';
else
acq_buffer_rst <= '0';
end if;
-- counter overflow event
if tdc_cnt = tdc_cnt_zero then
tdc_cnt_ovfl := '1';
else
tdc_cnt_ovfl := '0';
end if;
-- map of start/stop event sources
event_source_map := (
0 => tdc_cnt_ovfl,
1 => tdc_events.d1_rising.valid,
2 => tdc_events.d1_falling.valid,
3 => tdc_events.d2_rising.valid,
4 => tdc_events.d2_falling.valid,
5 => tdc_events.a_maxfound.valid,
6 => '0'
);
start_trig := '0';
stop_trig := '0';
-- state machine
case acq_state_int is
when s_reset =>
acq_state_int := s_wait_ready;
when s_wait_ready =>
if acq_buffer_full = '0' then
acq_state_int := s_waittrig;
end if;
when s_waittrig =>
start_trig := event_source_map(to_integer(unsigned(acq_start_src)));
if start_trig = '1' then
acq_state_int := s_buffering;
end if;
when s_buffering =>
stop_trig := event_source_map(to_integer(unsigned(acq_stop_src))) or acq_stop;
if acq_buffer_full = '1' or stop_trig = '1' then
acq_state_int := s_done;
end if;
when others =>
null;
end case;
-- always go to reset state when acq_reset is high
if acq_reset = '1' then
acq_state_int := s_reset;
end if;
-- select signals for fifo input
acq_buffer_wr <= '0';
acq_buffer_din <= (others => '0');
case acq_mode is
when "00" =>
-- raw sample mode (digital + analog)
acq_buffer_din <= tdc_d(0)(0) & tdc_d(1)(0) & tdc_d(2)(0) & tdc_d(3)(0) & std_logic_vector(tdc_a(0)) &
tdc_d(0)(1) & tdc_d(1)(1) & tdc_d(2)(1) & tdc_d(3)(1) & std_logic_vector(tdc_a(1));
acq_buffer_wr <= '1';
when "01" =>
-- maxfind debug mode (analog + single digital + maxfind)
acq_buffer_din <= tdc_d(0)(0) & tdc_d(1)(0) & tdc_d(2)(0) & tdc_d(3)(0) & std_logic_vector(tdc_a(0)) &
'0' & to_std_logic_vector(tdc_events.a_maxfound) & std_logic_vector(tdc_a(1));
acq_buffer_wr <= '1';
when "10" =>
-- TDC mode (counter + events)
acq_buffer_din <= tdc_cnt_ovfl & -- overflow(31)
to_std_logic_vector(tdc_events.a_maxfound) & -- valid(30) + pos(29-28)
to_std_logic_vector(tdc_events.d1_rising) & -- valid(27) + pos(26-25)
to_std_logic_vector(tdc_events.d2_rising) & -- valid(24) + pos(23-22)
std_logic_vector(tdc_cnt); -- cnt(21-0)
acq_buffer_wr <= tdc_cnt_ovfl or tdc_events.d1_rising.valid or tdc_events.d2_rising.valid or tdc_events.a_maxfound.valid;
when "11" =>
-- TDC + height mode (counter + maxvalue)
acq_buffer_din <= (others => '0');
if tdc_events.a_maxfound.valid = '1' then
-- use only the last 10 bits from maxvalue (assume non-negative value -> unsigned 10bit)
acq_buffer_din(31 downto 22) <= std_logic_vector(tdc_events.a_maxvalue(9 downto 0));
end if;
acq_buffer_din(21 downto 0) <= std_logic_vector(tdc_cnt);
acq_buffer_wr <= start_trig or tdc_cnt_ovfl or tdc_events.a_maxfound.valid;
when others =>
null;
end case;
-- override data valid if not in buffering state
if acq_state_int /= s_buffering then
acq_buffer_wr <= '0';
end if;
end if;
end process;
acq_state <= acq_state_out;
end acquisition_arch;
|
gpl-3.0
|
d4c02219c7ea9feb9786040cd6b85d00
| 0.54754 | 3.376108 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
VHDL/USB/FIFO_TO_USB.vhd
| 1 | 8,127 |
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo_mixed_widths
-- ============================================================
-- File Name: FIFO_TO_USB.vhd
-- Megafunction Name(s):
-- dcfifo_mixed_widths
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY FIFO_TO_USB IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
END FIFO_TO_USB;
ARCHITECTURE SYN OF fifo_to_usb IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (10 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (11 DOWNTO 0);
COMPONENT dcfifo_mixed_widths
GENERIC (
add_usedw_msb_bit : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
lpm_widthu_r : NATURAL;
lpm_width_r : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0);
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdreq : IN STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
wrusedw <= sub_wire1(10 DOWNTO 0);
rdusedw <= sub_wire2(11 DOWNTO 0);
dcfifo_mixed_widths_component : dcfifo_mixed_widths
GENERIC MAP (
add_usedw_msb_bit => "ON",
intended_device_family => "Cyclone IV E",
lpm_hint => "MAXIMUM_DEPTH=512",
lpm_numwords => 1024,
lpm_showahead => "OFF",
lpm_type => "dcfifo_mixed_widths",
lpm_width => 16,
lpm_widthu => 11,
lpm_widthu_r => 12,
lpm_width_r => 8,
overflow_checking => "ON",
rdsync_delaypipe => 5,
read_aclr_synch => "OFF",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 5
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
q => sub_wire0,
wrusedw => sub_wire1,
rdusedw => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "1024"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "16"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "1"
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_USEDW_MSB_BIT STRING "ON"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMUM_DEPTH=512"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "12"
-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL "rdusedw[11..0]"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL "wrusedw[10..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
-- Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_USB.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_USB.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_USB.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_USB.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_USB_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
2082993d781c78c79ddc1153a2108ef2
| 0.668635 | 3.440728 | false | false | false | false |
pwuertz/digitizer2fw
|
src/rtl/main.vhd
| 1 | 13,836 |
-------------------------------------------------------------------------------
-- Digitizer2 top level module
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.communication_pkg.all;
use work.sampling_pkg.all;
entity top_level is
port (
LED1: out std_logic;
LED2: out std_logic;
-- GCLK1 : in std_logic;
-- GPIO1_P : out std_logic;
-- GPIO1_N : out std_logic;
GND: out std_logic_vector(21 downto 0);
-- USB
USB_D: inout std_logic_vector(7 downto 0);
USB_WR: out std_logic;
USB_TXE: in std_logic;
USB_RXF: in std_logic;
USB_RD: out std_logic;
USB_OE: out std_logic;
USB_CLKOUT: in std_logic;
USB_SIWUA: out std_logic;
-- DRAM
ddr3_dq: inout std_logic_vector(15 downto 0);
ddr3_addr: out std_logic_vector(13 downto 0);
ddr3_ba: out std_logic_vector(2 downto 0);
ddr3_we_n: out std_logic;
ddr3_reset_n: out std_logic;
ddr3_ras_n: out std_logic;
ddr3_cas_n: out std_logic;
ddr3_odt: out std_logic_vector(0 downto 0);
ddr3_cke: out std_logic_vector(0 downto 0);
ddr3_ck_p: out std_logic_vector(0 downto 0);
ddr3_ck_n: out std_logic_vector(0 downto 0);
ddr3_dqs_p: inout std_logic_vector(1 downto 0);
ddr3_dqs_n: inout std_logic_vector(1 downto 0);
-- ADC
APWR_EN: out std_logic;
ADC_ENABLE: out std_logic;
ADC_SRESETB: out std_logic;
ADC_SDIO: inout std_logic;
ADC_SDENB: out std_logic;
ADC_SCLK: out std_logic;
ADC_DA_P: in std_logic_vector(12 downto 0);
ADC_DA_N: in std_logic_vector(12 downto 0);
ADC_DACLK_P: in std_logic;
ADC_DACLK_N: in std_logic;
-- DIN
DIN_P: in std_logic_vector(1 downto 0);
DIN_N: in std_logic_vector(1 downto 0)
);
end top_level;
architecture top_level_arch of top_level is
component application
port (
clk_main: in std_logic;
clk_samples: in std_logic;
LED1: out std_logic;
LED2: out std_logic;
device_temp: in std_logic_vector(11 downto 0);
-- usb communication
comm_addr: in unsigned(5 downto 0);
comm_port: in unsigned(5 downto 0);
comm_to_slave: in comm_to_slave_t;
comm_from_slave: out comm_from_slave_t;
comm_error: in std_logic;
-- ram interface
ram_calib_complete : in std_logic;
ram_rdy : in std_logic;
ram_addr : out std_logic_vector(27 downto 0);
ram_cmd : out std_logic_vector(2 downto 0);
ram_en : out std_logic;
ram_rd_data : in std_logic_vector(127 downto 0);
ram_rd_data_valid : in std_logic;
ram_wdf_rdy : in std_logic;
ram_wdf_data : out std_logic_vector(127 downto 0);
ram_wdf_wren : out std_logic;
ram_wdf_end : out std_logic;
-- analog pwr/enable/rst
APWR_EN: out std_logic;
ADC_ENABLE: out std_logic;
ADC_SRESETB: out std_logic;
-- adc program
adc_prog_start: out std_logic;
adc_prog_rd: out std_logic;
adc_prog_busy: in std_logic;
adc_prog_addr: out std_logic_vector(6 downto 0);
adc_prog_din: out std_logic_vector(15 downto 0);
adc_prog_dout: in std_logic_vector(15 downto 0);
-- analog/digital samples
sampling_rst: out std_logic;
samples_d: in din_samples_t(0 to 3);
samples_a: in adc_samples_t(0 to 1)
);
end component;
----------------------------------------------------------------------------
-- clock resourcces
component clk_core_main
port (
clk_in: in std_logic;
clk_main: out std_logic;
clk_ddr3_sys: out std_logic;
clk_ddr3_ref: out std_logic
);
end component;
component clk_core_usb
port (
clk_in: in std_logic;
clk_usb: out std_logic
);
end component;
signal clk_main: std_logic;
signal clk_main_out, clk_ddr3_sys, clk_ddr3_ref, clk_usb: std_logic;
-- dram controller
component ddr3_controller
port (
ddr3_dq : inout std_logic_vector(15 downto 0);
ddr3_dqs_p : inout std_logic_vector(1 downto 0);
ddr3_dqs_n : inout std_logic_vector(1 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(27 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(127 downto 0);
app_wdf_end : in std_logic;
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(127 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_i : in std_logic;
-- Reference Clock Ports
clk_ref_i : in std_logic;
device_temp_o : out std_logic_vector(11 downto 0);
sys_rst : in std_logic
);
end component;
signal clk_ddr3_app : std_logic;
signal ram_init_calib_complete : std_logic;
signal ram_sys_rst : std_logic := '1';
signal ram_app_rdy : std_logic;
signal ram_app_addr : std_logic_vector(27 downto 0);
signal ram_app_cmd : std_logic_vector(2 downto 0);
signal ram_app_en : std_logic;
signal ram_app_rd_data : std_logic_vector(127 downto 0);
signal ram_app_rd_data_valid : std_logic;
signal ram_app_wdf_rdy : std_logic;
signal ram_app_wdf_data : std_logic_vector(127 downto 0);
signal ram_app_wdf_wren : std_logic;
signal ram_app_wdf_end : std_logic;
signal device_temp : std_logic_vector(11 downto 0);
-- adc serial programming
component adc_program
port (
-- application interface
clk_main: in std_logic;
start: in std_logic;
rd: in std_logic;
busy: out std_logic;
addr: in std_logic_vector(6 downto 0);
din: in std_logic_vector(15 downto 0);
dout: out std_logic_vector(15 downto 0);
-- adc interface
adc_sdenb: out std_logic;
adc_sdio: inout std_logic;
adc_sclk: out std_logic
);
end component;
signal adc_prog_start: std_logic;
signal adc_prog_rd: std_logic := '0';
signal adc_prog_busy: std_logic;
signal adc_prog_addr: std_logic_vector(6 downto 0);
signal adc_prog_din: std_logic_vector(15 downto 0);
signal adc_prog_dout: std_logic_vector(15 downto 0);
-- analog/digital sampling
signal clk_samples: std_logic;
signal samples_d: din_samples_t(0 to 3);
signal samples_a: adc_samples_t(0 to 1);
signal sampling_rst: std_logic;
-- host communication
component ft2232_communication
port (
clk: in std_logic;
rst: in std_logic;
error: out std_logic;
-- application bus interface
slave_addr: out unsigned(5 downto 0);
slave_port: out unsigned(5 downto 0);
comm_to_slave: out comm_to_slave_t;
comm_from_slave: in comm_from_slave_t;
-- ftdi interface
usb_clk: in std_logic;
usb_oe_n: out std_logic;
usb_rd_n: out std_logic;
usb_wr_n: out std_logic;
usb_rxf_n: in std_logic;
usb_txe_n: in std_logic;
usb_d: inout std_logic_vector(7 downto 0)
);
end component;
signal comm_addr: unsigned(5 downto 0);
signal comm_port: unsigned(5 downto 0);
signal comm_error: std_logic;
signal comm_to_slave: comm_to_slave_t;
signal comm_from_slave: comm_from_slave_t;
begin
GND <= (others => '0');
clk_main <= clk_ddr3_app;
clk_core_main_inst: clk_core_main
port map (
clk_in => USB_CLKOUT,
clk_main => clk_main_out,
clk_ddr3_sys => clk_ddr3_sys,
clk_ddr3_ref => clk_ddr3_ref
);
clk_core_usb_inst: clk_core_usb
port map (
clk_in => USB_CLKOUT,
clk_usb => clk_usb
);
ddr3_controller_inst : ddr3_controller
port map (
-- Memory interface ports
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_cas_n => ddr3_cas_n,
ddr3_ck_n => ddr3_ck_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_cke => ddr3_cke,
ddr3_ras_n => ddr3_ras_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_we_n => ddr3_we_n,
ddr3_dq => ddr3_dq,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_dqs_p => ddr3_dqs_p,
init_calib_complete => ram_init_calib_complete,
ddr3_odt => ddr3_odt,
-- Application interface ports
app_addr => ram_app_addr,
app_cmd => ram_app_cmd,
app_en => ram_app_en,
app_wdf_data => ram_app_wdf_data,
app_wdf_end => ram_app_wdf_end,
app_wdf_wren => ram_app_wdf_wren,
app_rd_data => ram_app_rd_data,
app_rd_data_end => open,
app_rd_data_valid => ram_app_rd_data_valid,
app_rdy => ram_app_rdy,
app_wdf_rdy => ram_app_wdf_rdy,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => open,
app_ref_ack => open,
app_zq_ack => open,
ui_clk => clk_ddr3_app,
ui_clk_sync_rst => open,
-- System Clock Ports
sys_clk_i => clk_ddr3_sys,
-- Reference Clock Ports
clk_ref_i => clk_ddr3_ref,
device_temp_o => device_temp,
sys_rst => ram_sys_rst
);
adc_program_inst: adc_program
port map (
clk_main => clk_main,
start => adc_prog_start,
rd => adc_prog_rd,
busy => adc_prog_busy,
addr => adc_prog_addr,
din => adc_prog_din,
dout => adc_prog_dout,
adc_sdenb => ADC_SDENB,
adc_sdio => ADC_SDIO,
adc_sclk => ADC_SCLK
);
sampling_inst: sampling
port map (
DIN_P => DIN_P,
DIN_N => DIN_N,
ADC_DA_P => ADC_DA_P,
ADC_DA_N => ADC_DA_N,
ADC_DACLK_P => ADC_DACLK_P,
ADC_DACLK_N => ADC_DACLK_N,
app_clk => clk_samples,
samples_d => samples_d,
samples_a => samples_a,
rst => sampling_rst
);
ft2232_communication_inst: ft2232_communication
port map (
clk => clk_main,
rst => '0',
error => comm_error,
-- application register interface
slave_addr => comm_addr,
slave_port => comm_port,
comm_to_slave => comm_to_slave,
comm_from_slave => comm_from_slave,
-- ftdi interface
usb_clk => clk_usb,
usb_oe_n => USB_OE,
usb_rd_n => USB_RD,
usb_wr_n => USB_WR,
usb_rxf_n => USB_RXF,
usb_txe_n => USB_TXE,
usb_d => USB_D
);
USB_SIWUA <= '1'; -- do not use SIWUA feature for now
application_inst: application
port map (
clk_main => clk_main,
clk_samples => clk_samples,
LED1 => LED1,
LED2 => LED2,
device_temp => device_temp,
-- usb communication
comm_addr => comm_addr,
comm_port => comm_port,
comm_to_slave => comm_to_slave,
comm_from_slave => comm_from_slave,
comm_error => comm_error,
-- ram interface
ram_calib_complete => ram_init_calib_complete,
ram_rdy => ram_app_rdy,
ram_addr => ram_app_addr,
ram_cmd => ram_app_cmd,
ram_en => ram_app_en,
ram_rd_data => ram_app_rd_data,
ram_rd_data_valid => ram_app_rd_data_valid,
ram_wdf_rdy => ram_app_wdf_rdy,
ram_wdf_data => ram_app_wdf_data,
ram_wdf_wren => ram_app_wdf_wren,
ram_wdf_end => ram_app_wdf_end,
-- analog pwr/enable/rst
APWR_EN => APWR_EN,
ADC_ENABLE => ADC_ENABLE,
ADC_SRESETB => ADC_SRESETB,
-- adc program
adc_prog_start => adc_prog_start,
adc_prog_rd => adc_prog_rd,
adc_prog_busy => adc_prog_busy,
adc_prog_addr => adc_prog_addr,
adc_prog_din => adc_prog_din,
adc_prog_dout => adc_prog_dout,
-- analog/digital samples
sampling_rst => sampling_rst,
samples_d => samples_d,
samples_a => samples_a
);
end top_level_arch;
|
gpl-3.0
|
e8aa256d185a7659ae02ca6bf1a60e85
| 0.535237 | 3.287004 | false | false | false | false |
ruygargar/LCSE_lab
|
peripherics/peripherics.vhd
| 1 | 4,180 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:42:50 01/12/2014
-- Design Name:
-- Module Name: peripherics - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity peripherics is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
TX : out STD_LOGIC;
RX : in STD_LOGIC;
Databus : inout STD_LOGIC_VECTOR (7 downto 0);
Address : inout STD_LOGIC_VECTOR (7 downto 0);
ChipSelect : inout STD_LOGIC;
WriteEnable : inout STD_LOGIC;
OutputEnable : inout STD_LOGIC;
Send : in STD_LOGIC;
Ready : out STD_LOGIC;
DMA_RQ : out STD_LOGIC;
DMA_ACK : in STD_LOGIC;
Switches : out std_logic_vector(7 downto 0);
Temp_L : out std_logic_vector(6 downto 0);
Temp_H : out std_logic_vector(6 downto 0)
);
end peripherics;
architecture Behavioral of peripherics is
COMPONENT RS232top
PORT(
Reset : IN std_logic;
Clk : IN std_logic;
Data_in : IN std_logic_vector(7 downto 0);
Valid_D : IN std_logic;
RD : IN std_logic;
Data_read : IN std_logic;
Ack_in : OUT std_logic;
TX_RDY : OUT std_logic;
TD : OUT std_logic;
Data_out : OUT std_logic_vector(7 downto 0);
Full : OUT std_logic;
Empty : OUT std_logic
);
END COMPONENT;
COMPONENT dma
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
Send : IN std_logic;
DMA_ACK : IN std_logic;
Ack_out : IN std_logic;
TX_RDY : IN std_logic;
RCVD_data : IN std_logic_vector(7 downto 0);
RX_Full : IN std_logic;
RX_empty : IN std_logic;
Databus : INOUT std_logic_vector(7 downto 0);
Address : OUT std_logic_vector(7 downto 0);
ChipSelect : OUT std_logic;
WriteEnable : OUT std_logic;
OutputEnable : OUT std_logic;
Ready : OUT std_logic;
DMA_RQ : OUT std_logic;
TX_data : OUT std_logic_vector(7 downto 0);
Valid_D : OUT std_logic;
Data_read : OUT std_logic
);
END COMPONENT;
COMPONENT ram
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
WriteEnable : IN std_logic;
OutputEnable : IN std_logic;
ChipSelect : IN std_logic;
Address : IN std_logic_vector(7 downto 0);
Databus : INOUT std_logic_vector(7 downto 0);
Switches : OUT std_logic_vector(7 downto 0);
Temp_L : OUT std_logic_vector(6 downto 0);
Temp_h : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
signal data_in_i, data_out_i :std_logic_vector(7 downto 0);
signal valid_i, ack_i, txready_i, dataread_i : std_logic;
signal empty_i, full_i : std_logic;
begin
RS232: RS232top PORT MAP(
Reset => Reset,
Clk => Clk,
Data_in => data_in_i,
Valid_D => valid_i,
Ack_in => ack_i,
TX_RDY => txready_i,
TD => TX,
RD => RX,
Data_out => data_out_i,
Data_read => dataread_i,
Full => full_i,
Empty => empty_i
);
DMA0: dma PORT MAP(
Clk => Clk,
Reset => Reset,
Databus => Databus,
Address => Address,
ChipSelect => ChipSelect,
WriteEnable => WriteEnable,
OutputEnable => OutputEnable,
Send => Send,
Ready => Ready,
DMA_RQ => DMA_RQ,
DMA_ACK => DMA_ACK,
TX_data => data_in_i,
Valid_D => valid_i,
Ack_out => ack_i,
TX_RDY => txready_i,
RCVD_data => data_out_i,
Data_read => dataread_i,
RX_Full => full_i,
RX_empty => empty_i
);
RAM0: ram PORT MAP(
Clk => Clk,
Reset => Reset,
WriteEnable => WriteEnable,
OutputEnable => OutputEnable,
ChipSelect => ChipSelect,
Address => Address,
Databus => Databus,
Switches => Switches,
Temp_L => Temp_L,
Temp_H => Temp_H
);
end Behavioral;
|
gpl-3.0
|
48e0be3a49246ff5736432139b680060
| 0.599522 | 3.105498 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/solving_key_equation_5.vhd
| 1 | 21,690 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Solving_Key_Equation_5
-- Module Name: Solving_Key_Equation_5
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 2nd step in Goppa Code Decoding.
--
-- This circuit solves the polynomial key equation sigma with the polynomial syndrome.
-- To solve the key equation, this circuit employs a modified binary extended euclidean algorithm.
-- The modification is made to stop the algorithm in 2*final degree steps.
-- The syndrome is the input and expected to be of degree 2*final_degree-1, and after computations
-- polynomial C, will hold sigma with degree less or equal to final_degree.
--
-- This is pipeline circuit version that is slower than solving_key_equation_4.
-- However this version is constant time, therefore is more side channel resistant.
--
-- Parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- final_degree :
--
-- The final degree size expected for polynomial sigma to have. This parameter depends
-- of the Goppa code used.
--
-- size_final_degree :
--
-- The number of bits necessary to hold the polynomial with degree of final_degree, which
-- has final_degree + 1 coefficients. This is ceil(log2(final_degree+1)).
--
-- Dependencies:
--
-- VHDL-93
--
-- controller_solving_key_equation_5 Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_decrement_load_rst_nbits Rev 1.0
-- mult_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity solving_key_equation_5 is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 27;
-- size_final_degree : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 66;
-- size_final_degree : integer := 7
-- QD-GOPPA [2528, 2144, 32, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 32;
-- size_final_degree : integer := 5
-- QD-GOPPA [2816, 2048, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [3328, 2560, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [7296, 5632, 128, 13] --
gf_2_m : integer range 1 to 20 := 13;
final_degree : integer := 128;
size_final_degree : integer := 7
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_s : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_r : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_v : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_u : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_s : out STD_LOGIC;
write_enable_r : out STD_LOGIC;
write_enable_v : out STD_LOGIC;
write_enable_u : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_s : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_v : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_r : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_u : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_value_s : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_r : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_v : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_u : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_s : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_r : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_v : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_u : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end solving_key_equation_5;
architecture Behavioral of solving_key_equation_5 is
component controller_solving_key_equation_5
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_number_of_iterations : in STD_LOGIC;
last_polynomial_coefficient : in STD_LOGIC;
is_inv_zero : in STD_LOGIC;
is_r0_zero : in STD_LOGIC;
is_delta_less_than_0 : in STD_LOGIC;
is_rho_zero : in STD_LOGIC;
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_s : out STD_LOGIC;
write_enable_r : out STD_LOGIC;
write_enable_v : out STD_LOGIC;
write_enable_u : out STD_LOGIC;
sel_mult_r_inv : out STD_LOGIC;
last_u_value : out STD_LOGIC;
change_s_v : out STD_LOGIC;
change_r_u : out STD_LOGIC;
shift_r_u : out STD_LOGIC;
reg_value_s_rst : out STD_LOGIC;
reg_value_s_ce : out STD_LOGIC;
reg_value_r_rst : out STD_LOGIC;
reg_value_r_ce : out STD_LOGIC;
reg_value_v_rst : out STD_LOGIC;
reg_value_v_ce : out STD_LOGIC;
reg_value_u_rst : out STD_LOGIC;
reg_value_u_ce : out STD_LOGIC;
sel_reg_rho_rst_value : out STD_LOGIC;
reg_rho_rst : out STD_LOGIC;
reg_rho_ce : out STD_LOGIC;
ctr_delta_ce : out STD_LOGIC;
ctr_delta_load : out STD_LOGIC;
ctr_delta_rst : out STD_LOGIC;
reg_new_value_s_rst : out STD_LOGIC;
reg_new_value_s_ce : out STD_LOGIC;
reg_new_value_r_rst : out STD_LOGIC;
reg_new_value_r_ce : out STD_LOGIC;
reg_new_value_v_ce : out STD_LOGIC;
reg_new_value_u_rst : out STD_LOGIC;
reg_new_value_u_ce : out STD_LOGIC;
reg_new_value_u0_ce : out STD_LOGIC;
ctr_load_value_ce : out STD_LOGIC;
ctr_load_value_rst : out STD_LOGIC;
ctr_store_value_ce : out STD_LOGIC;
ctr_store_value_rst : out STD_LOGIC;
ctr_number_of_iterations_ce : out STD_LOGIC;
ctr_number_of_iterations_rst : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_decrement_load_rst_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component mult_gf_2_m
Generic (gf_2_m : integer range 1 to 20 := 11);
Port (
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal reg_value_s_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_value_s_rst : STD_LOGIC;
constant reg_value_s_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_value_s_ce : STD_LOGIC;
signal reg_value_s_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_value_r_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_value_r_rst : STD_LOGIC;
constant reg_value_r_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_value_r_ce : STD_LOGIC;
signal reg_value_r_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_value_v_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_value_v_rst : STD_LOGIC;
constant reg_value_v_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_value_v_ce : STD_LOGIC;
signal reg_value_v_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_value_u_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_value_u_rst : STD_LOGIC;
constant reg_value_u_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_value_u_ce : STD_LOGIC;
signal reg_value_u_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_reg_rho_rst_value : STD_LOGIC;
signal reg_rho_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_rho_rst : STD_LOGIC;
constant reg_rho_rst_value_0 : STD_LOGIC_VECTOR((gf_2_m - 2) downto 0) := (others => '0');
signal reg_rho_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_rho_ce : STD_LOGIC;
signal reg_rho_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_ce : STD_LOGIC;
signal reg_inv_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_delta_d : STD_LOGIC_VECTOR((size_final_degree) downto 0);
signal ctr_delta_ce : STD_LOGIC;
signal ctr_delta_load : STD_LOGIC;
signal ctr_delta_rst : STD_LOGIC;
constant ctr_delta_rst_value : STD_LOGIC_VECTOR((size_final_degree) downto 0) := std_logic_vector(to_signed(-1, size_final_degree+1));
signal ctr_delta_q : STD_LOGIC_VECTOR((size_final_degree) downto 0);
signal mult_s_rho_r_inv_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_s_rho_r_inv_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_s_rho_r_inv_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_v_rho_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_v_rho_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_v_rho_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal add_s_rho_r : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal add_v_rho_u : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_s_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_s_rst : STD_LOGIC;
constant reg_new_value_s_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(1, gf_2_m));
signal reg_new_value_s_ce : STD_LOGIC;
signal reg_new_value_s_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_r_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_r_rst : STD_LOGIC;
constant reg_new_value_r_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
signal reg_new_value_r_ce : STD_LOGIC;
signal reg_new_value_r_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_v_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_v_ce : STD_LOGIC;
signal reg_new_value_v_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_u_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_u_rst : STD_LOGIC;
constant reg_new_value_u_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(1, gf_2_m));
signal reg_new_value_u_ce : STD_LOGIC;
signal reg_new_value_u_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_u0_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_u0_ce : STD_LOGIC;
signal reg_new_value_u0_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_load_value_ce : STD_LOGIC;
signal ctr_load_value_rst : STD_LOGIC;
constant ctr_load_value_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0, size_final_degree+2));
signal ctr_load_value_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_delay_store_value_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_delay_store_value_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal shift_r_u : STD_LOGIC;
signal ctr_store_value_ce : STD_LOGIC;
signal ctr_store_value_rst : STD_LOGIC;
constant ctr_store_value_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0, size_final_degree+2));
signal ctr_store_value_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_number_of_iterations_ce : STD_LOGIC;
signal ctr_number_of_iterations_rst : STD_LOGIC;
constant ctr_number_of_iterations_rst_value : STD_LOGIC_VECTOR(size_final_degree downto 0) := std_logic_vector(to_unsigned(0, size_final_degree+1));
signal ctr_number_of_iterations_q : STD_LOGIC_VECTOR(size_final_degree downto 0);
signal sel_mult_r_inv : STD_LOGIC;
signal last_u_value : STD_LOGIC;
signal change_s_v : STD_LOGIC;
signal change_r_u : STD_LOGIC;
signal limit_number_of_iterations : STD_LOGIC;
signal last_polynomial_coefficient : STD_LOGIC;
signal is_rho_zero : STD_LOGIC;
signal is_inv_zero : STD_LOGIC;
signal is_r0_zero : STD_LOGIC;
signal is_delta_less_than_0 : STD_LOGIC;
begin
controller : controller_solving_key_equation_5
Port Map(
clk => clk,
rst => rst,
limit_number_of_iterations => limit_number_of_iterations,
last_polynomial_coefficient => last_polynomial_coefficient,
is_inv_zero => is_inv_zero,
is_r0_zero => is_r0_zero,
is_delta_less_than_0 => is_delta_less_than_0,
is_rho_zero => is_rho_zero,
signal_inv => signal_inv,
key_equation_found => key_equation_found,
write_enable_s => write_enable_s,
write_enable_r => write_enable_r,
write_enable_v => write_enable_v,
write_enable_u => write_enable_u,
sel_mult_r_inv => sel_mult_r_inv,
last_u_value => last_u_value,
change_s_v => change_s_v,
change_r_u => change_r_u,
shift_r_u => shift_r_u,
reg_value_s_rst => reg_value_s_rst,
reg_value_s_ce => reg_value_s_ce,
reg_value_r_rst => reg_value_r_rst,
reg_value_r_ce => reg_value_r_ce,
reg_value_v_rst => reg_value_v_rst,
reg_value_v_ce => reg_value_v_ce,
reg_value_u_rst => reg_value_u_rst,
reg_value_u_ce => reg_value_u_ce,
sel_reg_rho_rst_value => sel_reg_rho_rst_value,
reg_rho_rst => reg_rho_rst,
reg_rho_ce => reg_rho_ce,
ctr_delta_ce => ctr_delta_ce,
ctr_delta_load => ctr_delta_load,
ctr_delta_rst => ctr_delta_rst,
reg_new_value_s_rst => reg_new_value_s_rst,
reg_new_value_s_ce => reg_new_value_s_ce,
reg_new_value_r_rst => reg_new_value_r_rst,
reg_new_value_r_ce => reg_new_value_r_ce,
reg_new_value_v_ce => reg_new_value_v_ce,
reg_new_value_u_rst => reg_new_value_u_rst,
reg_new_value_u_ce => reg_new_value_u_ce,
reg_new_value_u0_ce => reg_new_value_u0_ce,
ctr_load_value_ce => ctr_load_value_ce,
ctr_load_value_rst => ctr_load_value_rst,
ctr_store_value_ce => ctr_store_value_ce,
ctr_store_value_rst => ctr_store_value_rst,
ctr_number_of_iterations_ce => ctr_number_of_iterations_ce,
ctr_number_of_iterations_rst => ctr_number_of_iterations_rst
);
reg_value_s : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_value_s_d,
clk => clk,
rst => reg_value_s_rst,
rst_value => reg_value_s_rst_value,
ce => reg_value_s_ce,
q => reg_value_s_q
);
reg_value_r : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_value_r_d,
clk => clk,
rst => reg_value_r_rst,
rst_value => reg_value_r_rst_value,
ce => reg_value_r_ce,
q => reg_value_r_q
);
reg_value_v : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_value_v_d,
clk => clk,
rst => reg_value_v_rst,
rst_value => reg_value_v_rst_value,
ce => reg_value_v_ce,
q => reg_value_v_q
);
reg_value_u : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_value_u_d,
clk => clk,
rst => reg_value_u_rst,
rst_value => reg_value_u_rst_value,
ce => reg_value_u_ce,
q => reg_value_u_q
);
reg_rho : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_rho_d,
clk => clk,
rst => reg_rho_rst,
rst_value => reg_rho_rst_value,
ce => reg_rho_ce,
q => reg_rho_q
);
reg_inv : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_inv_d,
clk => clk,
ce => reg_inv_ce,
q => reg_inv_q
);
ctr_delta : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+1,
decrement_value => 1
)
Port Map(
d => ctr_delta_d,
clk => clk,
ce => ctr_delta_ce,
load => ctr_delta_load,
rst => ctr_delta_rst,
rst_value => ctr_delta_rst_value,
q => ctr_delta_q
);
mult_s_rho_r_inv: mult_gf_2_m
Generic Map (
gf_2_m => gf_2_m
)
Port Map (
a => mult_s_rho_r_inv_a,
b => mult_s_rho_r_inv_b,
o => mult_s_rho_r_inv_o
);
mult_v_rho: mult_gf_2_m
Generic Map (
gf_2_m => gf_2_m
)
Port Map (
a => mult_v_rho_a,
b => mult_v_rho_b,
o => mult_v_rho_o
);
reg_new_value_s : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_s_d,
clk => clk,
rst => reg_new_value_s_rst,
rst_value => reg_new_value_s_rst_value,
ce => reg_new_value_s_ce,
q => reg_new_value_s_q
);
reg_new_value_r : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_r_d,
clk => clk,
rst => reg_new_value_r_rst,
rst_value => reg_new_value_r_rst_value,
ce => reg_new_value_r_ce,
q => reg_new_value_r_q
);
reg_new_value_v : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_v_d,
clk => clk,
ce => reg_new_value_v_ce,
q => reg_new_value_v_q
);
reg_new_value_u : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_u_d,
clk => clk,
rst => reg_new_value_u_rst,
rst_value => reg_new_value_u_rst_value,
ce => reg_new_value_u_ce,
q => reg_new_value_u_q
);
reg_new_value_u0 : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_u0_d,
clk => clk,
ce => reg_new_value_u0_ce,
q => reg_new_value_u0_q
);
ctr_number_of_iterations : counter_rst_nbits
Generic Map(
size => size_final_degree+1,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_number_of_iterations_ce,
rst => ctr_number_of_iterations_rst,
rst_value => ctr_number_of_iterations_rst_value,
q => ctr_number_of_iterations_q
);
ctr_load_value : counter_rst_nbits
Generic Map(
size => size_final_degree+2,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_load_value_ce,
rst => ctr_load_value_rst,
rst_value => ctr_load_value_rst_value,
q => ctr_load_value_q
);
ctr_store_value : counter_rst_nbits
Generic Map(
size => size_final_degree+2,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_store_value_ce,
rst => ctr_store_value_rst,
rst_value => ctr_store_value_rst_value,
q => ctr_store_value_q
);
reg_delay_store_value : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_delay_store_value_d,
clk => clk,
ce => '1',
q => reg_delay_store_value_q
);
reg_value_s_d <= value_s;
reg_value_r_d <= value_r;
reg_value_v_d <= value_v;
reg_value_u_d <= value_u;
reg_rho_d <= mult_s_rho_r_inv_o;
reg_rho_rst_value <= reg_rho_rst_value_0 & sel_reg_rho_rst_value;
reg_inv_d <= value_inv;
reg_inv_ce <= ready_inv;
ctr_delta_d <= std_logic_vector(to_signed(-1, size_final_degree+1) - signed(ctr_delta_q));
mult_s_rho_r_inv_a <= reg_inv_q when sel_mult_r_inv = '1' else
reg_rho_q;
mult_s_rho_r_inv_b <= reg_value_r_q when sel_mult_r_inv = '1' else
reg_value_s_q;
mult_v_rho_a <= reg_rho_q;
mult_v_rho_b <= reg_value_v_q;
add_s_rho_r <= mult_s_rho_r_inv_o xor reg_value_r_q;
add_v_rho_u <= mult_v_rho_o xor reg_value_u_q;
reg_new_value_s_d <= reg_value_r_q when change_s_v = '1' else
reg_value_s_q;
reg_new_value_r_d <= reg_value_s_q when change_r_u = '1' else
add_s_rho_r;
reg_new_value_v_d <= reg_value_u_q when change_s_v = '1' else
reg_value_v_q;
reg_new_value_u_d <= reg_value_v_q when change_r_u = '1' else
add_v_rho_u;
reg_new_value_u0_d <= add_v_rho_u;
new_value_inv <= reg_new_value_s_q;
new_value_s <= reg_new_value_s_q;
new_value_v <= reg_new_value_v_q;
new_value_r <= reg_new_value_r_q;
new_value_u <= reg_new_value_u0_q when last_u_value = '1' else
reg_new_value_u_q;
address_value_s <= ctr_load_value_q;
address_value_r <= ctr_load_value_q;
address_value_v <= ctr_load_value_q;
address_value_u <= ctr_load_value_q;
reg_delay_store_value_d <= ctr_store_value_q;
address_new_value_s <= ctr_store_value_q;
address_new_value_r <= reg_delay_store_value_q when shift_r_u = '1' else
ctr_store_value_q;
address_new_value_v <= ctr_store_value_q;
address_new_value_u <= reg_delay_store_value_q when shift_r_u = '1' else
ctr_store_value_q;
limit_number_of_iterations <= '1' when (ctr_number_of_iterations_q = std_logic_vector(to_unsigned(2*final_degree - 1, size_final_degree+1))) else '0';
last_polynomial_coefficient <= '1' when (ctr_store_value_q = std_logic_vector(to_unsigned(2*final_degree - 1, size_final_degree+2))) else '0';
is_inv_zero <= '1' when (reg_inv_q = std_logic_vector(to_unsigned(0, gf_2_m))) else '0';
is_rho_zero <= '1' when (reg_rho_q = std_logic_vector(to_unsigned(0, gf_2_m))) else '0';
is_r0_zero <= '1' when (reg_value_r_q = std_logic_vector(to_unsigned(0, gf_2_m))) else '0';
is_delta_less_than_0 <= '1' when (signed(ctr_delta_q) < to_signed(0, size_final_degree+1)) else '0';
end Behavioral;
|
bsd-2-clause
|
ed3b5ba2159731d1e7e8b6837c064323
| 0.64532 | 2.49856 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/components/generic_counter/generic_counter_tb.vhd
| 1 | 914 |
library ieee;
use ieee.std_logic_1164.all;
entity generic_counter_tb is
end;
architecture generic_counter_tb_func of generic_counter_tb is
signal rst_in: std_logic:='1';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal n_out: std_logic_vector(3 downto 0);
signal c_out: std_logic:='0';
component generic_counter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end component;
begin
clk_in <= not(clk_in) after 20 ns;
rst_in <= '0' after 50 ns;
enable_in <= '1' after 60 ns;
genericCounterMap: generic_counter generic map (4,19)
port map(
clk => clk_in,
rst => rst_in,
ena => enable_in,
count => n_out,
carry_o => c_out
);
end architecture;
|
gpl-3.0
|
71b1f95a50eb18119d3045f37c03caa9
| 0.618162 | 2.803681 | false | false | false | false |
laurivosandi/hdl
|
zynq/src/ov7670_controller/i2c_sender.vhd
| 1 | 5,111 |
----------------------------------------------------------------------------------
-- Engineer: <[email protected]
--
-- Description: Send the commands to the OV7670 over an I2C-like interface
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_sender is
port (
clk : in std_logic;
siod : inout std_logic;
sioc : out std_logic;
taken : out std_logic;
send : in std_logic;
id : in std_logic_vector(7 downto 0);
reg : in std_logic_vector(7 downto 0);
value : in std_logic_vector(7 downto 0)
);
end i2c_sender;
architecture behavioral of i2c_sender is
-- this value gives a 254 cycle pause before the initial frame is sent
signal divider : unsigned (7 downto 0) := "00000001";
signal busy_sr : std_logic_vector(31 downto 0) := (others => '0');
signal data_sr : std_logic_vector(31 downto 0) := (others => '1');
begin
process(busy_sr, data_sr(31))
begin
if busy_sr(11 downto 10) = "10" or
busy_sr(20 downto 19) = "10" or
busy_sr(29 downto 28) = "10" then
siod <= 'Z';
else
siod <= data_sr(31);
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
taken <= '0';
if busy_sr(31) = '0' then
SIOC <= '1';
if send = '1' then
if divider = "00000000" then
data_sr <= "100" & id & '0' & reg & '0' & value & '0' & "01";
busy_sr <= "111" & "111111111" & "111111111" & "111111111" & "11";
taken <= '1';
else
divider <= divider+1; -- this only happens on powerup
end if;
end if;
else
case busy_sr(32-1 downto 32-3) & busy_sr(2 downto 0) is
when "111"&"111" => -- start seq #1
case divider(7 downto 6) is
when "00" => SIOC <= '1';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when "111"&"110" => -- start seq #2
case divider(7 downto 6) is
when "00" => SIOC <= '1';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when "111"&"100" => -- start seq #3
case divider(7 downto 6) is
when "00" => SIOC <= '0';
when "01" => SIOC <= '0';
when "10" => SIOC <= '0';
when others => SIOC <= '0';
end case;
when "110"&"000" => -- end seq #1
case divider(7 downto 6) is
when "00" => SIOC <= '0';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when "100"&"000" => -- end seq #2
case divider(7 downto 6) is
when "00" => SIOC <= '1';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when "000"&"000" => -- Idle
case divider(7 downto 6) is
when "00" => SIOC <= '1';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when others =>
case divider(7 downto 6) is
when "00" => SIOC <= '0';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '0';
end case;
end case;
if divider = "11111111" then
busy_sr <= busy_sr(32-2 downto 0) & '0';
data_sr <= data_sr(32-2 downto 0) & '1';
divider <= (others => '0');
else
divider <= divider+1;
end if;
end if;
end if;
end process;
end behavioral;
|
mit
|
55331b60ecb4f4aad604263e93863e2f
| 0.335942 | 4.583857 | false | false | false | false |
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