repo_name
stringlengths 6
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stringlengths 6
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| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/decoBCD/decoBCD.vhd
| 2 | 1,610 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity decoBCD is
port(
ena: in std_logic; --Estara conectado al anodo del BCD para habilitarlo o no
count: in std_logic_vector(3 downto 0); --Bits del contador
a: out std_logic;
b: out std_logic;
c: out std_logic;
d: out std_logic;
e: out std_logic;
f: out std_logic;
g: out std_logic;
dp: out std_logic;
anod: out std_logic
);
end;
architecture decoBCD_arq of decoBCD is
begin
--El 7 segmentos funciona con logica invertida
process(count,ena) --Se va a activar con un cambio de valor o con un cambio de enable
begin
--Seteo todas las salidas en 0 para solo "apagar" las que necesite por cada numero
a <= '0';
b <='0';
c <= '0';
d <= '0';
e <= '0';
f <= '0';
g <= '0';
dp <= '1'; --En este caso siempre apagado
CHECK: case to_integer(unsigned(count)) is
when 0 =>
g <= '1';
when 1 =>
a <= '1';
d <= '1';
e <= '1';
f <= '1';
g <= '1';
when 2 =>
c <= '1';
f <= '1';
when 3 =>
e <= '1';
f <= '1';
when 4 =>
a <= '1';
d <= '1';
e <= '1';
when 5 =>
b <= '1';
e <= '1';
when 6 =>
b <= '1';
when 7 =>
d <= '1';
e <= '1';
f <= '1';
g <= '1';
when 8 =>
--no cambia nada
when 9 =>
d <= '1';
e <= '1';
when others =>
a <= '1';
b <= '1';
c <= '1';
d <= '1';
e <= '1';
f <= '1';
g <= '1';
end case CHECK;
anod <= not(ena);
end process;
end;
|
gpl-3.0
|
5aba84b72c98be7f2b35db00d11e50e4
| 0.459006 | 2.652389 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/tps-Gaston/tp1/generic_enabler_tb.vhd
| 2 | 672 |
library ieee;
use ieee.std_logic_1164.all;
entity generic_enabler_tb is
end;
architecture generic_enabler_tb_func of generic_enabler_tb is
signal rst_in: std_logic:='1';
signal enable_out: std_logic:='0';
signal clk_in: std_logic:='0';
component generic_enabler is
generic(PERIOD:natural := 1000000 ); --1MHz
port(
clk: in std_logic;
rst: in std_logic;
ena_out: out std_logic
);
end component;
begin
clk_in <= not(clk_in) after 1 ns;
rst_in <= '0' after 50 ns;
generic_enabler_map: generic_enabler generic map(4)
port map(
clk => clk_in,
rst => rst_in,
ena_out => enable_out
);
end architecture;
|
gpl-3.0
|
706853cda4d261b99e4035cad407bb43
| 0.635417 | 2.896552 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
VHDL_PLANB/VHDL_PLANB.vhd
| 1 | 8,719 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity VHDL_PLANB is
port
(
inclk:in std_logic:='0';
data_buffer_a:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_b:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_c:out std_logic_vector(39 downto 0):=x"0000000000";
en_row_a:out std_logic:='0';
en_row_b:out std_logic:='0';
en_row_c:out std_logic_vector(1 downto 0):="00"; --------分割为两个管脚，分配同一信号
en_col_a_1,en_col_a_2,en_col_a_3:out std_logic:='0';
en_col_b_1,en_col_b_2,en_col_b_3:out std_logic:='0';
en_col_c_1,en_col_c_2,en_col_c_3:out std_logic:='0'
);
end entity;
architecture RTL of VHDL_PLANB is
component PLL is
port
(
inclk0:in std_logic;
c0,c1,c2:out std_logic
);
end component;
component DECODER is
generic
(
constant fpr:integer:=360
);
port
(
inclk,rst:in std_logic;
control_begin:out std_logic:='0';
load_next:in std_logic;
fifo_aclr:out std_logic:='0';
fifo_en_w_1:out std_logic:='0';
fifo_en_w_2:out std_logic:='0';
fifo_en_w_3:out std_logic:='0';
fifo_data_1:out std_logic_vector(127 downto 0);
fifo_data_2:out std_logic_vector(127 downto 0);
fifo_data_3:out std_logic_vector(127 downto 0)
);
end component;
component LED is
generic
(
constant cpd:integer:=6666 ------------count per one degree（inclk下）
);
port
(
inclk:in std_logic;
rst:in std_logic;
data_buffer_a:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_b:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_c:out std_logic_vector(39 downto 0):=x"0000000000";
en_row_a:out std_logic:='0';
en_row_b:out std_logic:='0';
en_row_c:out std_logic_vector(1 downto 0):="00"; --------分割为两个管脚，分配同一信号
en_col_a_1,en_col_a_2,en_col_a_3:out std_logic:='0';
en_col_b_1,en_col_b_2,en_col_b_3:out std_logic:='0';
en_col_c_1,en_col_c_2,en_col_c_3:out std_logic:='0';
control_begin:in std_logic;
fifo_change:out std_logic;
fifo_en_r:out std_logic;
fifo_data_1:in std_logic_vector(127 downto 0);
fifo_data_2:in std_logic_vector(127 downto 0);
fifo_data_3:in std_logic_vector(127 downto 0)
);
end component;
component FIFO is
port
(
aclr:in std_logic:= '0';
data:in std_logic_vector(127 downto 0);
rdclk:in std_logic;
rdreq:in std_logic;
wrclk:in std_logic;
wrreq:in std_logic;
q:out std_logic_vector(127 downto 0)
);
end component;
signal rst:std_logic:='0';
signal clk_decoder,clk_led,clk_main:std_logic;
signal control_begin:std_logic;
signal load_next:std_logic:='0';
signal fifo_change,fifo_change_last:std_logic;
signal fifo_aclr:std_logic:='0';
signal fifo_clk_w:std_logic:='0';
signal fifo_en_w_1:std_logic:='0';
signal fifo_en_w_2:std_logic:='0';
signal fifo_en_w_3:std_logic:='0';
signal fifo_data_dec_1:std_logic_vector(127 downto 0);
signal fifo_data_dec_2:std_logic_vector(127 downto 0);
signal fifo_data_dec_3:std_logic_vector(127 downto 0);
signal fifo_en_r:std_logic:='0';
signal fifo_clk_r:std_logic:='0';
signal fifo_data_led_1:std_logic_vector(127 downto 0);
signal fifo_data_led_2:std_logic_vector(127 downto 0);
signal fifo_data_led_3:std_logic_vector(127 downto 0);
signal fifo_aclr_a:std_logic:='0';
signal fifo_en_w_1_a:std_logic:='0';
signal fifo_en_w_2_a:std_logic:='0';
signal fifo_en_w_3_a:std_logic:='0';
signal fifo_data_dec_1_a:std_logic_vector(127 downto 0);
signal fifo_data_dec_2_a:std_logic_vector(127 downto 0);
signal fifo_data_dec_3_a:std_logic_vector(127 downto 0);
signal fifo_en_r_a:std_logic:='0';
signal fifo_data_led_1_a:std_logic_vector(127 downto 0);
signal fifo_data_led_2_a:std_logic_vector(127 downto 0);
signal fifo_data_led_3_a:std_logic_vector(127 downto 0);
signal fifo_aclr_b:std_logic:='0';
signal fifo_en_w_1_b:std_logic:='0';
signal fifo_en_w_2_b:std_logic:='0';
signal fifo_en_w_3_b:std_logic:='0';
signal fifo_data_dec_1_b:std_logic_vector(127 downto 0);
signal fifo_data_dec_2_b:std_logic_vector(127 downto 0);
signal fifo_data_dec_3_b:std_logic_vector(127 downto 0);
signal fifo_en_r_b:std_logic:='0';
signal fifo_data_led_1_b:std_logic_vector(127 downto 0);
signal fifo_data_led_2_b:std_logic_vector(127 downto 0);
signal fifo_data_led_3_b:std_logic_vector(127 downto 0);
begin
CLOCK:PLL
port map
(
inclk0=>inclk,
c0=>clk_led,
c1=>clk_decoder,
c2=>clk_main
);
DECODER1:DECODER
port map
(
inclk=>clk_decoder,
rst=>rst,
control_begin=>control_begin,
load_next=>load_next,
fifo_aclr=>fifo_aclr,
fifo_en_w_1=>fifo_en_w_1,
fifo_en_w_2=>fifo_en_w_2,
fifo_en_w_3=>fifo_en_w_3,
fifo_data_1=>fifo_data_dec_1,
fifo_data_2=>fifo_data_dec_2,
fifo_data_3=>fifo_data_dec_3
);
LED1:LED
port map
(
inclk=>clk_led,
rst=>rst,
data_buffer_a=>data_buffer_a,
data_buffer_b=>data_buffer_b,
data_buffer_c=>data_buffer_c,
en_row_a=>en_row_a,
en_row_b=>en_row_b,
en_row_c=>en_row_c,
en_col_a_1=>en_col_a_1,en_col_a_2=>en_col_a_2,en_col_a_3=>en_col_a_3,
en_col_b_1=>en_col_b_1,en_col_b_2=>en_col_b_2,en_col_b_3=>en_col_b_3,
en_col_c_1=>en_col_c_1,en_col_c_2=>en_col_c_2,en_col_c_3=>en_col_c_3,
control_begin=>control_begin,
fifo_change=>fifo_change,
fifo_en_r=>fifo_en_r,
fifo_data_1=>fifo_data_led_1,
fifo_data_2=>fifo_data_led_2,
fifo_data_3=>fifo_data_led_3
);
FIFO1A:FIFO
port map
(
aclr=>fifo_aclr_a,
data=>fifo_data_dec_1_a,
rdclk=>fifo_clk_r,
rdreq=>fifo_en_r_a,
wrclk=>fifo_clk_w,
wrreq=>fifo_en_w_1_a,
q=>fifo_data_led_1_a
);
FIFO2A:FIFO
port map
(
aclr=>fifo_aclr_a,
data=>fifo_data_dec_2_a,
rdclk=>fifo_clk_r,
rdreq=>fifo_en_r_a,
wrclk=>fifo_clk_w,
wrreq=>fifo_en_w_2_a,
q=>fifo_data_led_2_a
);
FIFO3A:FIFO
port map
(
aclr=>fifo_aclr_a,
data=>fifo_data_dec_3_a,
rdclk=>fifo_clk_r,
rdreq=>fifo_en_r_a,
wrclk=>fifo_clk_w,
wrreq=>fifo_en_w_3_a,
q=>fifo_data_led_3_a
);
FIFO1B:FIFO
port map
(
aclr=>fifo_aclr_b,
data=>fifo_data_dec_1_b,
rdclk=>fifo_clk_r,
rdreq=>fifo_en_r_b,
wrclk=>fifo_clk_w,
wrreq=>fifo_en_w_1_b,
q=>fifo_data_led_1_b
);
FIFO2B:FIFO
port map
(
aclr=>fifo_aclr_b,
data=>fifo_data_dec_2_b,
rdclk=>fifo_clk_r,
rdreq=>fifo_en_r_b,
wrclk=>fifo_clk_w,
wrreq=>fifo_en_w_2_b,
q=>fifo_data_led_2_b
);
FIFO3B:FIFO
port map
(
aclr=>fifo_aclr_b,
data=>fifo_data_dec_3_b,
rdclk=>fifo_clk_r,
rdreq=>fifo_en_r_b,
wrclk=>fifo_clk_w,
wrreq=>fifo_en_w_3_b,
q=>fifo_data_led_3_b
);
fifo_data_dec_1_a<=fifo_data_dec_1;
fifo_data_dec_2_a<=fifo_data_dec_2;
fifo_data_dec_3_a<=fifo_data_dec_3;
fifo_data_dec_1_b<=fifo_data_dec_1;
fifo_data_dec_2_b<=fifo_data_dec_2;
fifo_data_dec_3_b<=fifo_data_dec_3;
fifo_clk_w<=clk_decoder;
fifo_clk_r<=clk_led;
MAIN:process(clk_main,rst)
begin
if rst='1' then
fifo_aclr_a<=fifo_aclr;
fifo_en_r_a<=fifo_en_r;
fifo_en_w_1_a<=fifo_en_w_1;
fifo_en_w_2_a<=fifo_en_w_2;
fifo_en_w_3_a<=fifo_en_w_3;
fifo_data_led_1<=fifo_data_led_1_a;
fifo_data_led_2<=fifo_data_led_2_a;
fifo_data_led_3<=fifo_data_led_3_a;
elsif rising_edge(clk_main) then
fifo_change_last<=fifo_change;
if control_begin='0' then
fifo_aclr_a<=fifo_aclr;
fifo_en_r_a<=fifo_en_r;
fifo_en_w_1_a<=fifo_en_w_1;
fifo_en_w_2_a<=fifo_en_w_2;
fifo_en_w_3_a<=fifo_en_w_3;
fifo_data_led_1<=fifo_data_led_1_a;
fifo_data_led_2<=fifo_data_led_2_a;
fifo_data_led_3<=fifo_data_led_3_a;
elsif fifo_change='1' then
fifo_en_r_b<=fifo_en_r;
fifo_data_led_1<=fifo_data_led_1_b;
fifo_data_led_2<=fifo_data_led_2_b;
fifo_data_led_3<=fifo_data_led_3_b;
fifo_aclr_b<='0';
fifo_en_w_1_b<='0';
fifo_en_w_2_b<='0';
fifo_en_w_3_b<='0';
fifo_aclr_a<=fifo_aclr;
fifo_en_w_1_a<=fifo_en_w_1;
fifo_en_w_2_a<=fifo_en_w_2;
fifo_en_w_3_a<=fifo_en_w_3;
fifo_en_r_a<='0';
elsif fifo_change='0' then
fifo_en_r_a<=fifo_en_r;
fifo_data_led_1<=fifo_data_led_1_a;
fifo_data_led_2<=fifo_data_led_2_a;
fifo_data_led_3<=fifo_data_led_3_a;
fifo_aclr_a<='0';
fifo_en_w_1_a<='0';
fifo_en_w_2_a<='0';
fifo_en_w_3_a<='0';
fifo_aclr_b<=fifo_aclr;
fifo_en_w_1_b<=fifo_en_w_1;
fifo_en_w_2_b<=fifo_en_w_2;
fifo_en_w_3_b<=fifo_en_w_3;
fifo_en_r_b<='0';
end if;
if fifo_change_last/=fifo_change then
load_next<='1';
else
load_next<='0';
end if;
end if;
end process;
end RTL;
|
gpl-2.0
|
d08fc8895b404cf6e3e986d4cdf6e115
| 0.623888 | 2.188875 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/relocate/sumbcd.vhd
| 1 | 755 |
library ieee;
use ieee.std_logic_ll64.all;
entity contBCD is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
s: out std_logic_vector(3 downto 0);
co: out std_logic
);
end;
architecture contBCD_arq of contBCD is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(clk,rst)
variable count: integer range 0 to 10;
begin
if rst = '1' then
s <= (others => '0');
co <= '0';
elsif rising_edge(clk) then
if ena := '1' then
count:=count + 1;
if count = 9 then
co <= '1';
elsif count = 10 then
count := '0';
co <= '0';
else
co <= '0';
end if;
end if;
end if;
s <= count;
end process;
end;
|
gpl-3.0
|
1e44b1b8dc5d37e628a81c5a2f0ae1ec
| 0.562914 | 2.89272 | false | false | false | false |
achan1989/In64
|
FPGA/SD_card_test.srcs/sources_1/imports/SD_card_test/test_program.vhd
| 1 | 229,147 |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Definition of a program memory for KCPSM6 including generic parameters for the
-- convenient selection of device family, program memory size and the ability to include
-- the JTAG Loader hardware for rapid software development.
--
-- This file is primarily for use during code development and it is recommended that the
-- appropriate simplified program memory definition be used in a final production design.
--
-- Generic Values Comments
-- Parameter Supported
--
-- C_FAMILY "S6" Spartan-6 device
-- "V6" Virtex-6 device
-- "7S" 7-Series device
-- (Artix-7, Kintex-7, Virtex-7 or Zynq)
--
-- C_RAM_SIZE_KWORDS 1, 2 or 4 Size of program memory in K-instructions
--
-- C_JTAG_LOADER_ENABLE 0 or 1 Set to '1' to include JTAG Loader
--
-- Notes
--
-- If your design contains MULTIPLE KCPSM6 instances then only one should have the
-- JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to
-- '1' on one instance of the program memory). Advanced users may be interested to know
-- that it is possible to connect JTAG Loader to multiple memories and then to use the
-- JTAG Loader utility to specify which memory contents are to be modified. However,
-- this scheme does require some effort to set up and the additional connectivity of the
-- multiple BRAMs can impact the placement, routing and performance of the complete
-- design. Please contact the author at Xilinx for more detailed information.
--
-- Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete
-- 12-bit address bus is connected to KCPSM6. This enables the generic to be modified
-- without requiring changes to the fundamental hardware definition. However, when the
-- program memory is 1K then only the lower 10-bits of the address are actually used and
-- the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower
-- 11-bits of the address are actually used and the valid address range is 000 to 7FF hex.
--
-- Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the
-- size of the program and the device family.
--
-- In a Spartan-6 device a BRAM is capable of holding 1K instructions. Hence a 2K program
-- will require 2 BRAMs to be used and a 4K program will require 4 BRAMs to be used. It
-- should be noted that a 4K program is not such a natural fit in a Spartan-6 device and
-- the implementation also requires a small amount of logic resulting in slightly lower
-- performance. A Spartan-6 BRAM can also be split into two 9k-bit memories suggesting
-- that a program containing up to 512 instructions could be implemented. However, there
-- is a silicon errata which makes this unsuitable and therefore it is not supported by
-- this file.
--
-- In a Virtex-6 or any 7-Series device a BRAM is capable of holding 2K instructions so
-- obviously a 2K program requires only a single BRAM. Each BRAM can also be divided into
-- 2 smaller memories supporting programs of 1K in half of a 36k-bit BRAM (generally
-- reported as being an 18k-bit BRAM). For a program of 4K instructions, 2 BRAMs are used.
--
--
-- Program defined by 'D:\Libraries\Documents\Git\In64\FPGA\SD_card_test.srcs\sources_1\imports\SD_card_test\test_program.psm'.
--
-- Generated by KCPSM6 Assembler: 12 Oct 2013 - 20:06:28.
--
-- Assembler used ROM_form template: ROM_form_JTAGLoader_14March13.vhd
--
-- Standard IEEE libraries
--
--
package jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer;
end jtag_loader_pkg;
--
package body jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer is
begin
if (size_in_k = 1) then return 10;
elsif (size_in_k = 2) then return 11;
elsif (size_in_k = 4) then return 12;
else report "Invalid BlockRAM size. Please set to 1, 2 or 4 K words." severity FAILURE;
end if;
return 0;
end function addr_width_calc;
end package body;
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.jtag_loader_pkg.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity test_program is
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end test_program;
--
architecture low_level_definition of test_program is
--
signal address_a : std_logic_vector(15 downto 0);
signal pipe_a11 : std_logic;
signal data_in_a : std_logic_vector(35 downto 0);
signal data_out_a : std_logic_vector(35 downto 0);
signal data_out_a_l : std_logic_vector(35 downto 0);
signal data_out_a_h : std_logic_vector(35 downto 0);
signal data_out_a_ll : std_logic_vector(35 downto 0);
signal data_out_a_lh : std_logic_vector(35 downto 0);
signal data_out_a_hl : std_logic_vector(35 downto 0);
signal data_out_a_hh : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b : std_logic_vector(35 downto 0);
signal data_in_b_l : std_logic_vector(35 downto 0);
signal data_in_b_ll : std_logic_vector(35 downto 0);
signal data_in_b_hl : std_logic_vector(35 downto 0);
signal data_out_b : std_logic_vector(35 downto 0);
signal data_out_b_l : std_logic_vector(35 downto 0);
signal data_out_b_ll : std_logic_vector(35 downto 0);
signal data_out_b_hl : std_logic_vector(35 downto 0);
signal data_in_b_h : std_logic_vector(35 downto 0);
signal data_in_b_lh : std_logic_vector(35 downto 0);
signal data_in_b_hh : std_logic_vector(35 downto 0);
signal data_out_b_h : std_logic_vector(35 downto 0);
signal data_out_b_lh : std_logic_vector(35 downto 0);
signal data_out_b_hh : std_logic_vector(35 downto 0);
signal enable_b : std_logic;
signal clk_b : std_logic;
signal we_b : std_logic_vector(7 downto 0);
signal we_b_l : std_logic_vector(3 downto 0);
signal we_b_h : std_logic_vector(3 downto 0);
--
signal jtag_addr : std_logic_vector(11 downto 0);
signal jtag_we : std_logic;
signal jtag_we_l : std_logic;
signal jtag_we_h : std_logic;
signal jtag_clk : std_logic;
signal jtag_din : std_logic_vector(17 downto 0);
signal jtag_dout : std_logic_vector(17 downto 0);
signal jtag_dout_1 : std_logic_vector(17 downto 0);
signal jtag_en : std_logic_vector(0 downto 0);
--
signal picoblaze_reset : std_logic_vector(0 downto 0);
signal rdl_bus : std_logic_vector(0 downto 0);
--
constant BRAM_ADDRESS_WIDTH : integer := addr_width_calc(C_RAM_SIZE_KWORDS);
--
--
component jtag_loader_6
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "V6";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_din : out STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_addr : out STD_LOGIC_VECTOR(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
jtag_clk : out std_logic;
jtag_we : out std_logic;
jtag_dout_0 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end component;
--
begin
--
--
ram_1k_generate : if (C_RAM_SIZE_KWORDS = 1) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "0000";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "0000000000000000000000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB16BWER
generic map ( DATA_WIDTH_A => 18,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 18,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"01F21D9901F21D0001E11B011A2E02411F0D02411F6902411F48022C023E0226",
INIT_01 => X"02411F0D01E80D20021412FF15FF022902411F0D01F21DFF01F21DBB01F21DAA",
INIT_02 => X"0214124002411F0D02411F3001E11B011A5B60239101021F10821150601A9501",
INIT_03 => X"1F3801E11B011A5B0211010C0214129502141200021412000214120002141200",
INIT_04 => X"010C02141287021412AA0214120102141200021412000214124802411F0D0241",
INIT_05 => X"12FFE06AD20102411F0D01E80D2001E11B011A84021412FF021412FF021412FF",
INIT_06 => X"1A5B0211020301E11B011ABE206ED2AA02411F0D01E80D2001E11B011A840214",
INIT_07 => X"0214120002141200021412000214127A02411F0D02411F3802411F3501E11B01",
INIT_08 => X"01E11B011A9D020301E11B011A8EE08DD2C0021412FF010C0214120002141200",
INIT_09 => X"02411F3401E11B011A680211021412FF021412FF02411F0D01E80D20021412FF",
INIT_0A => X"02141200021412000214120002141200021412000214127702411F0D02411F31",
INIT_0B => X"D2FF021412FF021412000214120002141200021412000214124002141269010C",
INIT_0C => X"020301E11B011ABE20D0D20020A4D20102411F0D01E80D2001E11B011A7620BD",
INIT_0D => X"12000214125102411F0D02411F3702411F3101E11B011A68021101E11B011AAB",
INIT_0E => X"1A3B0203021100EF170016EF011D021412000214120002141200021412000214",
INIT_0F => X"19021800020301E80D2001E11B011A4820FED2FE20F2D2FF021412FF01E11B01",
INIT_10 => X"1B011A76021412FF021412FF021412FF6100B900980101F20D206020021412FF",
INIT_11 => X"1A76021412FF020301E11B011ABE1000D201210CD2FF02411F0D01E80D2001E1",
INIT_12 => X"1F651F48020301E11B011ABE1000D200211DD2FF02411F0D01E80D2001E11B01",
INIT_13 => X"1F6B1F631F6F1F6C1F421F001F0D1F641F6C1F721F6F1F571F201F6F1F6C1F6C",
INIT_14 => X"1F651F721F201F6B1F631F6F1F6C1F421F001F0D1F3A1F611F741F611F641F20",
INIT_15 => X"1F641F6E1F651F531F0D1F001F201F3A1F721F6F1F721F721F651F201F641F61",
INIT_16 => X"1F671F6E1F691F641F6E1F651F531F0D1F001F441F4D1F431F201F671F6E1F69",
INIT_17 => X"1F731F6E1F6F1F701F731F651F721F201F311F521F001F441F4D1F431F411F20",
INIT_18 => X"1F611F421F001F201F3A1F651F741F791F621F201F371F521F001F201F3A1F65",
INIT_19 => X"1F721F611F431F001F0D1F651F701F791F741F201F641F721F611F631F201F64",
INIT_1A => X"1F641F721F611F431F0D1F001F0D1F4B1F4F1F201F651F701F791F741F201F64",
INIT_1B => X"1F411F461F001F0D1F641F651F731F691F6C1F611F691F741F691F6E1F691F20",
INIT_1C => X"1F741F651F671F201F741F6F1F6E1F201F641F691F641F201F3A1F4C1F411F54",
INIT_1D => X"1F0D1F2E1F701F731F651F721F201F641F651F741F631F651F701F781F651F20",
INIT_1E => X"10009C0102411F304F023F800FD01C0821E13B001A011000DF0002414BA01F00",
INIT_1F => X"22011F37A200DF0A500001FC3F0F0FD001FC4F0E4F0E4F0E4F0E0FD021E94D02",
INIT_20 => X"021102411F0D02411F5402411F4C02411F4102411F4802411F0D500002411F30",
INIT_21 => X"5001500062159101021F4200D3809300D0003080002011085000D00010822210",
INIT_22 => X"22381FFF1EFF1DFF5000022CB80050000211B00050000230D00030FE0230D000",
INIT_23 => X"B000B01050006238BF00BE009D010FF022381F001E001DC822381F001E001D19",
INIT_24 => X"00000000000000000000000000000000000000005000DF016241DE049E015000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"888888882A0D888232220888A222222220A888888888360D888288888882222A",
INITP_01 => X"0A20DD882A0A2222222220A0A0DD888362222222888888888828888882832288",
INITP_02 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA0DD888228376220888D618",
INITP_03 => X"9DA09549D940976AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INITP_04 => X"00000000000000000000000000000AC2AB54808080AAAA8A2D9080A2A2222229",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a(31 downto 0),
DOPA => data_out_a(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b(31 downto 0),
DOPB => data_out_b(35 downto 32),
DIB => data_in_b(31 downto 0),
DIPB => data_in_b(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"01F21D9901F21D0001E11B011A2E02411F0D02411F6902411F48022C023E0226",
INIT_01 => X"02411F0D01E80D20021412FF15FF022902411F0D01F21DFF01F21DBB01F21DAA",
INIT_02 => X"0214124002411F0D02411F3001E11B011A5B60239101021F10821150601A9501",
INIT_03 => X"1F3801E11B011A5B0211010C0214129502141200021412000214120002141200",
INIT_04 => X"010C02141287021412AA0214120102141200021412000214124802411F0D0241",
INIT_05 => X"12FFE06AD20102411F0D01E80D2001E11B011A84021412FF021412FF021412FF",
INIT_06 => X"1A5B0211020301E11B011ABE206ED2AA02411F0D01E80D2001E11B011A840214",
INIT_07 => X"0214120002141200021412000214127A02411F0D02411F3802411F3501E11B01",
INIT_08 => X"01E11B011A9D020301E11B011A8EE08DD2C0021412FF010C0214120002141200",
INIT_09 => X"02411F3401E11B011A680211021412FF021412FF02411F0D01E80D20021412FF",
INIT_0A => X"02141200021412000214120002141200021412000214127702411F0D02411F31",
INIT_0B => X"D2FF021412FF021412000214120002141200021412000214124002141269010C",
INIT_0C => X"020301E11B011ABE20D0D20020A4D20102411F0D01E80D2001E11B011A7620BD",
INIT_0D => X"12000214125102411F0D02411F3702411F3101E11B011A68021101E11B011AAB",
INIT_0E => X"1A3B0203021100EF170016EF011D021412000214120002141200021412000214",
INIT_0F => X"19021800020301E80D2001E11B011A4820FED2FE20F2D2FF021412FF01E11B01",
INIT_10 => X"1B011A76021412FF021412FF021412FF6100B900980101F20D206020021412FF",
INIT_11 => X"1A76021412FF020301E11B011ABE1000D201210CD2FF02411F0D01E80D2001E1",
INIT_12 => X"1F651F48020301E11B011ABE1000D200211DD2FF02411F0D01E80D2001E11B01",
INIT_13 => X"1F6B1F631F6F1F6C1F421F001F0D1F641F6C1F721F6F1F571F201F6F1F6C1F6C",
INIT_14 => X"1F651F721F201F6B1F631F6F1F6C1F421F001F0D1F3A1F611F741F611F641F20",
INIT_15 => X"1F641F6E1F651F531F0D1F001F201F3A1F721F6F1F721F721F651F201F641F61",
INIT_16 => X"1F671F6E1F691F641F6E1F651F531F0D1F001F441F4D1F431F201F671F6E1F69",
INIT_17 => X"1F731F6E1F6F1F701F731F651F721F201F311F521F001F441F4D1F431F411F20",
INIT_18 => X"1F611F421F001F201F3A1F651F741F791F621F201F371F521F001F201F3A1F65",
INIT_19 => X"1F721F611F431F001F0D1F651F701F791F741F201F641F721F611F631F201F64",
INIT_1A => X"1F641F721F611F431F0D1F001F0D1F4B1F4F1F201F651F701F791F741F201F64",
INIT_1B => X"1F411F461F001F0D1F641F651F731F691F6C1F611F691F741F691F6E1F691F20",
INIT_1C => X"1F741F651F671F201F741F6F1F6E1F201F641F691F641F201F3A1F4C1F411F54",
INIT_1D => X"1F0D1F2E1F701F731F651F721F201F641F651F741F631F651F701F781F651F20",
INIT_1E => X"10009C0102411F304F023F800FD01C0821E13B001A011000DF0002414BA01F00",
INIT_1F => X"22011F37A200DF0A500001FC3F0F0FD001FC4F0E4F0E4F0E4F0E0FD021E94D02",
INIT_20 => X"021102411F0D02411F5402411F4C02411F4102411F4802411F0D500002411F30",
INIT_21 => X"5001500062159101021F4200D3809300D0003080002011085000D00010822210",
INIT_22 => X"22381FFF1EFF1DFF5000022CB80050000211B00050000230D00030FE0230D000",
INIT_23 => X"B000B01050006238BF00BE009D010FF022381F001E001DC822381F001E001D19",
INIT_24 => X"00000000000000000000000000000000000000005000DF016241DE049E015000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"888888882A0D888232220888A222222220A888888888360D888288888882222A",
INITP_01 => X"0A20DD882A0A2222222220A0A0DD888362222222888888888828888882832288",
INITP_02 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA0DD888228376220888D618",
INITP_03 => X"9DA09549D940976AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INITP_04 => X"00000000000000000000000000000AC2AB54808080AAAA8A2D9080A2A2222229",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"01F21D9901F21D0001E11B011A2E02411F0D02411F6902411F48022C023E0226",
INIT_01 => X"02411F0D01E80D20021412FF15FF022902411F0D01F21DFF01F21DBB01F21DAA",
INIT_02 => X"0214124002411F0D02411F3001E11B011A5B60239101021F10821150601A9501",
INIT_03 => X"1F3801E11B011A5B0211010C0214129502141200021412000214120002141200",
INIT_04 => X"010C02141287021412AA0214120102141200021412000214124802411F0D0241",
INIT_05 => X"12FFE06AD20102411F0D01E80D2001E11B011A84021412FF021412FF021412FF",
INIT_06 => X"1A5B0211020301E11B011ABE206ED2AA02411F0D01E80D2001E11B011A840214",
INIT_07 => X"0214120002141200021412000214127A02411F0D02411F3802411F3501E11B01",
INIT_08 => X"01E11B011A9D020301E11B011A8EE08DD2C0021412FF010C0214120002141200",
INIT_09 => X"02411F3401E11B011A680211021412FF021412FF02411F0D01E80D20021412FF",
INIT_0A => X"02141200021412000214120002141200021412000214127702411F0D02411F31",
INIT_0B => X"D2FF021412FF021412000214120002141200021412000214124002141269010C",
INIT_0C => X"020301E11B011ABE20D0D20020A4D20102411F0D01E80D2001E11B011A7620BD",
INIT_0D => X"12000214125102411F0D02411F3702411F3101E11B011A68021101E11B011AAB",
INIT_0E => X"1A3B0203021100EF170016EF011D021412000214120002141200021412000214",
INIT_0F => X"19021800020301E80D2001E11B011A4820FED2FE20F2D2FF021412FF01E11B01",
INIT_10 => X"1B011A76021412FF021412FF021412FF6100B900980101F20D206020021412FF",
INIT_11 => X"1A76021412FF020301E11B011ABE1000D201210CD2FF02411F0D01E80D2001E1",
INIT_12 => X"1F651F48020301E11B011ABE1000D200211DD2FF02411F0D01E80D2001E11B01",
INIT_13 => X"1F6B1F631F6F1F6C1F421F001F0D1F641F6C1F721F6F1F571F201F6F1F6C1F6C",
INIT_14 => X"1F651F721F201F6B1F631F6F1F6C1F421F001F0D1F3A1F611F741F611F641F20",
INIT_15 => X"1F641F6E1F651F531F0D1F001F201F3A1F721F6F1F721F721F651F201F641F61",
INIT_16 => X"1F671F6E1F691F641F6E1F651F531F0D1F001F441F4D1F431F201F671F6E1F69",
INIT_17 => X"1F731F6E1F6F1F701F731F651F721F201F311F521F001F441F4D1F431F411F20",
INIT_18 => X"1F611F421F001F201F3A1F651F741F791F621F201F371F521F001F201F3A1F65",
INIT_19 => X"1F721F611F431F001F0D1F651F701F791F741F201F641F721F611F631F201F64",
INIT_1A => X"1F641F721F611F431F0D1F001F0D1F4B1F4F1F201F651F701F791F741F201F64",
INIT_1B => X"1F411F461F001F0D1F641F651F731F691F6C1F611F691F741F691F6E1F691F20",
INIT_1C => X"1F741F651F671F201F741F6F1F6E1F201F641F691F641F201F3A1F4C1F411F54",
INIT_1D => X"1F0D1F2E1F701F731F651F721F201F641F651F741F631F651F701F781F651F20",
INIT_1E => X"10009C0102411F304F023F800FD01C0821E13B001A011000DF0002414BA01F00",
INIT_1F => X"22011F37A200DF0A500001FC3F0F0FD001FC4F0E4F0E4F0E4F0E0FD021E94D02",
INIT_20 => X"021102411F0D02411F5402411F4C02411F4102411F4802411F0D500002411F30",
INIT_21 => X"5001500062159101021F4200D3809300D0003080002011085000D00010822210",
INIT_22 => X"22381FFF1EFF1DFF5000022CB80050000211B00050000230D00030FE0230D000",
INIT_23 => X"B000B01050006238BF00BE009D010FF022381F001E001DC822381F001E001D19",
INIT_24 => X"00000000000000000000000000000000000000005000DF016241DE049E015000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"888888882A0D888232220888A222222220A888888888360D888288888882222A",
INITP_01 => X"0A20DD882A0A2222222220A0A0DD888362222222888888888828888882832288",
INITP_02 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA0DD888228376220888D618",
INITP_03 => X"9DA09549D940976AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INITP_04 => X"00000000000000000000000000000AC2AB54808080AAAA8A2D9080A2A2222229",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate akv7;
--
end generate ram_1k_generate;
--
--
--
ram_2k_generate : if (C_RAM_SIZE_KWORDS = 2) generate
--
--
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"410DE82014FFFF29410DF2FFF2BBF2AAF299F200E1012E410D416941482C3E26",
INIT_01 => X"38E1015B110C149514001400140014001440410D4130E1015B23011F82501A01",
INIT_02 => X"FF6A01410DE820E1018414FF14FF14FF0C148714AA1401140014001448410D41",
INIT_03 => X"140014001400147A410D41384135E1015B1103E101BE6EAA410DE820E1018414",
INIT_04 => X"4134E101681114FF14FF410DE82014FFE1019D03E1018E8DC014FF0C14001400",
INIT_05 => X"FF14FF1400140014001400144014690C140014001400140014001477410D4131",
INIT_06 => X"001451410D41374131E1016811E101AB03E101BED000A401410DE820E10176BD",
INIT_07 => X"020003E820E10148FEFEF2FF14FFE1013B0311EF00EF1D140014001400140014",
INIT_08 => X"7614FF03E101BE00010CFF410DE820E1017614FF14FF14FF000001F2202014FF",
INIT_09 => X"6B636F6C42000D646C726F57206F6C6C654803E101BE00001DFF410DE820E101",
INIT_0A => X"646E65530D00203A726F7272652064616572206B636F6C42000D3A6174616420",
INIT_0B => X"736E6F7073657220315200444D434120676E69646E65530D00444D4320676E69",
INIT_0C => X"726143000D6570797420647261632064614200203A6574796220375200203A65",
INIT_0D => X"4146000D646573696C616974696E6920647261430D000D4B4F20657079742064",
INIT_0E => X"0D2E707365722064657463657078652074656720746F6E20646964203A4C4154",
INIT_0F => X"0137000A00FC0FD0FC0E0E0E0ED0E902000141300280D008E10001000041A000",
INIT_10 => X"010015011F008000008020080000821011410D4154414C41414148410D004130",
INIT_11 => X"00100038000001F0380000C83800001938FFFFFF002C00001100003000FE3000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000141040100",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"9E030A000AE6607C00010005701CCC100057187C0F808002E4001725727FFCA8",
INITP_01 => X"57FF1ECBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD89F0C4F80D8",
INITP_02 => X"0000000000000000000000000000000000000000000000100B55500013102AA9",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_l(31 downto 0),
DOPA => data_out_a_l(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_l(31 downto 0),
DOPB => data_out_b_l(35 downto 32),
DIB => data_in_b_l(31 downto 0),
DIPB => data_in_b_l(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_h: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"010F000601090A01010F000E000E000E000E000E000D0D010F010F010F010101",
INIT_01 => X"0F000D0D0100010901090109010901090109010F010F000D0DB0C8010808B0CA",
INIT_02 => X"09F069010F0006000D0D01090109010900010901090109010901090109010F01",
INIT_03 => X"0109010901090109010F010F010F000D0D0101000D0D90E9010F0006000D0D01",
INIT_04 => X"010F000D0D0101090109010F00060109000D0D01000D0DF06901090001090109",
INIT_05 => X"E9010901090109010901090109010900010901090109010901090109010F010F",
INIT_06 => X"090109010F010F010F000D0D01000D0D01000D0D90E990E9010F0006000D0D90",
INIT_07 => X"0C0C010006000D0D90E990E90109000D0D0101000B0B00010901090109010901",
INIT_08 => X"0D010901000D0D88E990E9010F0006000D0D010901090109B0DCCC0006B00109",
INIT_09 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F01000D0D88E990E9010F0006000D",
INIT_0A => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0B => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0C => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0D => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0E => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0F => X"118FD1EF28001F0700A7A7A7A70710A688CE018FA71F070E109D8D88EF01250F",
INIT_10 => X"2828B1C801A16949681800082868081101010F010F010F010F010F010F28018F",
INIT_11 => X"585828B1DFDFCE07110F0F0E110F0F0E110F0F0E28015C280158280168180168",
INIT_12 => X"0000000000000000000000000000000000000000000000000000286FB16F4F28",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"34AA7355554CCAA95555AAAAA6AA995AAAAA72A9552AD5554EAAAA52A9AAA957",
INITP_01 => X"AC82A097FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2AA59552A92",
INITP_02 => X"000000000000000000000000000000000000000000000039F0888FFB688DD556",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_h(31 downto 0),
DOPA => data_out_a_h(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_h(31 downto 0),
DOPB => data_out_b_h(35 downto 32),
DIB => data_in_b_h(31 downto 0),
DIPB => data_in_b_h(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"01F21D9901F21D0001E11B011A2E02411F0D02411F6902411F48022C023E0226",
INIT_01 => X"02411F0D01E80D20021412FF15FF022902411F0D01F21DFF01F21DBB01F21DAA",
INIT_02 => X"0214124002411F0D02411F3001E11B011A5B60239101021F10821150601A9501",
INIT_03 => X"1F3801E11B011A5B0211010C0214129502141200021412000214120002141200",
INIT_04 => X"010C02141287021412AA0214120102141200021412000214124802411F0D0241",
INIT_05 => X"12FFE06AD20102411F0D01E80D2001E11B011A84021412FF021412FF021412FF",
INIT_06 => X"1A5B0211020301E11B011ABE206ED2AA02411F0D01E80D2001E11B011A840214",
INIT_07 => X"0214120002141200021412000214127A02411F0D02411F3802411F3501E11B01",
INIT_08 => X"01E11B011A9D020301E11B011A8EE08DD2C0021412FF010C0214120002141200",
INIT_09 => X"02411F3401E11B011A680211021412FF021412FF02411F0D01E80D20021412FF",
INIT_0A => X"02141200021412000214120002141200021412000214127702411F0D02411F31",
INIT_0B => X"D2FF021412FF021412000214120002141200021412000214124002141269010C",
INIT_0C => X"020301E11B011ABE20D0D20020A4D20102411F0D01E80D2001E11B011A7620BD",
INIT_0D => X"12000214125102411F0D02411F3702411F3101E11B011A68021101E11B011AAB",
INIT_0E => X"1A3B0203021100EF170016EF011D021412000214120002141200021412000214",
INIT_0F => X"19021800020301E80D2001E11B011A4820FED2FE20F2D2FF021412FF01E11B01",
INIT_10 => X"1B011A76021412FF021412FF021412FF6100B900980101F20D206020021412FF",
INIT_11 => X"1A76021412FF020301E11B011ABE1000D201210CD2FF02411F0D01E80D2001E1",
INIT_12 => X"1F651F48020301E11B011ABE1000D200211DD2FF02411F0D01E80D2001E11B01",
INIT_13 => X"1F6B1F631F6F1F6C1F421F001F0D1F641F6C1F721F6F1F571F201F6F1F6C1F6C",
INIT_14 => X"1F651F721F201F6B1F631F6F1F6C1F421F001F0D1F3A1F611F741F611F641F20",
INIT_15 => X"1F641F6E1F651F531F0D1F001F201F3A1F721F6F1F721F721F651F201F641F61",
INIT_16 => X"1F671F6E1F691F641F6E1F651F531F0D1F001F441F4D1F431F201F671F6E1F69",
INIT_17 => X"1F731F6E1F6F1F701F731F651F721F201F311F521F001F441F4D1F431F411F20",
INIT_18 => X"1F611F421F001F201F3A1F651F741F791F621F201F371F521F001F201F3A1F65",
INIT_19 => X"1F721F611F431F001F0D1F651F701F791F741F201F641F721F611F631F201F64",
INIT_1A => X"1F641F721F611F431F0D1F001F0D1F4B1F4F1F201F651F701F791F741F201F64",
INIT_1B => X"1F411F461F001F0D1F641F651F731F691F6C1F611F691F741F691F6E1F691F20",
INIT_1C => X"1F741F651F671F201F741F6F1F6E1F201F641F691F641F201F3A1F4C1F411F54",
INIT_1D => X"1F0D1F2E1F701F731F651F721F201F641F651F741F631F651F701F781F651F20",
INIT_1E => X"10009C0102411F304F023F800FD01C0821E13B001A011000DF0002414BA01F00",
INIT_1F => X"22011F37A200DF0A500001FC3F0F0FD001FC4F0E4F0E4F0E4F0E0FD021E94D02",
INIT_20 => X"021102411F0D02411F5402411F4C02411F4102411F4802411F0D500002411F30",
INIT_21 => X"5001500062159101021F4200D3809300D0003080002011085000D00010822210",
INIT_22 => X"22381FFF1EFF1DFF5000022CB80050000211B00050000230D00030FE0230D000",
INIT_23 => X"B000B01050006238BF00BE009D010FF022381F001E001DC822381F001E001D19",
INIT_24 => X"00000000000000000000000000000000000000005000DF016241DE049E015000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"888888882A0D888232220888A222222220A888888888360D888288888882222A",
INITP_01 => X"0A20DD882A0A2222222220A0A0DD888362222222888888888828888882832288",
INITP_02 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA0DD888228376220888D618",
INITP_03 => X"9DA09549D940976AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INITP_04 => X"00000000000000000000000000000AC2AB54808080AAAA8A2D9080A2A2222229",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"01F21D9901F21D0001E11B011A2E02411F0D02411F6902411F48022C023E0226",
INIT_01 => X"02411F0D01E80D20021412FF15FF022902411F0D01F21DFF01F21DBB01F21DAA",
INIT_02 => X"0214124002411F0D02411F3001E11B011A5B60239101021F10821150601A9501",
INIT_03 => X"1F3801E11B011A5B0211010C0214129502141200021412000214120002141200",
INIT_04 => X"010C02141287021412AA0214120102141200021412000214124802411F0D0241",
INIT_05 => X"12FFE06AD20102411F0D01E80D2001E11B011A84021412FF021412FF021412FF",
INIT_06 => X"1A5B0211020301E11B011ABE206ED2AA02411F0D01E80D2001E11B011A840214",
INIT_07 => X"0214120002141200021412000214127A02411F0D02411F3802411F3501E11B01",
INIT_08 => X"01E11B011A9D020301E11B011A8EE08DD2C0021412FF010C0214120002141200",
INIT_09 => X"02411F3401E11B011A680211021412FF021412FF02411F0D01E80D20021412FF",
INIT_0A => X"02141200021412000214120002141200021412000214127702411F0D02411F31",
INIT_0B => X"D2FF021412FF021412000214120002141200021412000214124002141269010C",
INIT_0C => X"020301E11B011ABE20D0D20020A4D20102411F0D01E80D2001E11B011A7620BD",
INIT_0D => X"12000214125102411F0D02411F3702411F3101E11B011A68021101E11B011AAB",
INIT_0E => X"1A3B0203021100EF170016EF011D021412000214120002141200021412000214",
INIT_0F => X"19021800020301E80D2001E11B011A4820FED2FE20F2D2FF021412FF01E11B01",
INIT_10 => X"1B011A76021412FF021412FF021412FF6100B900980101F20D206020021412FF",
INIT_11 => X"1A76021412FF020301E11B011ABE1000D201210CD2FF02411F0D01E80D2001E1",
INIT_12 => X"1F651F48020301E11B011ABE1000D200211DD2FF02411F0D01E80D2001E11B01",
INIT_13 => X"1F6B1F631F6F1F6C1F421F001F0D1F641F6C1F721F6F1F571F201F6F1F6C1F6C",
INIT_14 => X"1F651F721F201F6B1F631F6F1F6C1F421F001F0D1F3A1F611F741F611F641F20",
INIT_15 => X"1F641F6E1F651F531F0D1F001F201F3A1F721F6F1F721F721F651F201F641F61",
INIT_16 => X"1F671F6E1F691F641F6E1F651F531F0D1F001F441F4D1F431F201F671F6E1F69",
INIT_17 => X"1F731F6E1F6F1F701F731F651F721F201F311F521F001F441F4D1F431F411F20",
INIT_18 => X"1F611F421F001F201F3A1F651F741F791F621F201F371F521F001F201F3A1F65",
INIT_19 => X"1F721F611F431F001F0D1F651F701F791F741F201F641F721F611F631F201F64",
INIT_1A => X"1F641F721F611F431F0D1F001F0D1F4B1F4F1F201F651F701F791F741F201F64",
INIT_1B => X"1F411F461F001F0D1F641F651F731F691F6C1F611F691F741F691F6E1F691F20",
INIT_1C => X"1F741F651F671F201F741F6F1F6E1F201F641F691F641F201F3A1F4C1F411F54",
INIT_1D => X"1F0D1F2E1F701F731F651F721F201F641F651F741F631F651F701F781F651F20",
INIT_1E => X"10009C0102411F304F023F800FD01C0821E13B001A011000DF0002414BA01F00",
INIT_1F => X"22011F37A200DF0A500001FC3F0F0FD001FC4F0E4F0E4F0E4F0E0FD021E94D02",
INIT_20 => X"021102411F0D02411F5402411F4C02411F4102411F4802411F0D500002411F30",
INIT_21 => X"5001500062159101021F4200D3809300D0003080002011085000D00010822210",
INIT_22 => X"22381FFF1EFF1DFF5000022CB80050000211B00050000230D00030FE0230D000",
INIT_23 => X"B000B01050006238BF00BE009D010FF022381F001E001DC822381F001E001D19",
INIT_24 => X"00000000000000000000000000000000000000005000DF016241DE049E015000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"888888882A0D888232220888A222222220A888888888360D888288888882222A",
INITP_01 => X"0A20DD882A0A2222222220A0A0DD888362222222888888888828888882832288",
INITP_02 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA0DD888228376220888D618",
INITP_03 => X"9DA09549D940976AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA",
INITP_04 => X"00000000000000000000000000000AC2AB54808080AAAA8A2D9080A2A2222229",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_2k_generate;
--
--
ram_4k_generate : if (C_RAM_SIZE_KWORDS = 4) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
data_in_a <= "000000000000000000000000000000000000";
--
s6_a11_flop: FD
port map ( D => address(11),
Q => pipe_a11,
C => clk);
--
s6_4k_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(0),
I1 => data_out_a_hl(0),
I2 => data_out_a_ll(1),
I3 => data_out_a_hl(1),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(0),
O6 => instruction(1));
--
s6_4k_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(2),
I1 => data_out_a_hl(2),
I2 => data_out_a_ll(3),
I3 => data_out_a_hl(3),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(2),
O6 => instruction(3));
--
s6_4k_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(4),
I1 => data_out_a_hl(4),
I2 => data_out_a_ll(5),
I3 => data_out_a_hl(5),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(4),
O6 => instruction(5));
--
s6_4k_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(6),
I1 => data_out_a_hl(6),
I2 => data_out_a_ll(7),
I3 => data_out_a_hl(7),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(6),
O6 => instruction(7));
--
s6_4k_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(32),
I1 => data_out_a_hl(32),
I2 => data_out_a_lh(0),
I3 => data_out_a_hh(0),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(8),
O6 => instruction(9));
--
s6_4k_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(1),
I1 => data_out_a_hh(1),
I2 => data_out_a_lh(2),
I3 => data_out_a_hh(2),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(10),
O6 => instruction(11));
--
s6_4k_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(3),
I1 => data_out_a_hh(3),
I2 => data_out_a_lh(4),
I3 => data_out_a_hh(4),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(12),
O6 => instruction(13));
--
s6_4k_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(5),
I1 => data_out_a_hh(5),
I2 => data_out_a_lh(6),
I3 => data_out_a_hh(6),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(14),
O6 => instruction(15));
--
s6_4k_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(7),
I1 => data_out_a_hh(7),
I2 => data_out_a_lh(32),
I3 => data_out_a_hh(32),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(16),
O6 => instruction(17));
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_ll <= "000" & data_out_b_ll(32) & "000000000000000000000000" & data_out_b_ll(7 downto 0);
data_in_b_lh <= "000" & data_out_b_lh(32) & "000000000000000000000000" & data_out_b_lh(7 downto 0);
data_in_b_hl <= "000" & data_out_b_hl(32) & "000000000000000000000000" & data_out_b_hl(7 downto 0);
data_in_b_hh <= "000" & data_out_b_hh(32) & "000000000000000000000000" & data_out_b_hh(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b_l(3 downto 0) <= "0000";
we_b_h(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
jtag_dout <= data_out_b_lh(32) & data_out_b_lh(7 downto 0) & data_out_b_ll(32) & data_out_b_ll(7 downto 0);
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_lh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_ll <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
data_in_b_hh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_hl <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
--
s6_4k_jtag_we_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => jtag_we,
I1 => jtag_addr(11),
I2 => '1',
I3 => '1',
I4 => '1',
I5 => '1',
O5 => jtag_we_l,
O6 => jtag_we_h);
--
we_b_l(3 downto 0) <= jtag_we_l & jtag_we_l & jtag_we_l & jtag_we_l;
we_b_h(3 downto 0) <= jtag_we_h & jtag_we_h & jtag_we_h & jtag_we_h;
--
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
--
s6_4k_jtag_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(0),
I1 => data_out_b_hl(0),
I2 => data_out_b_ll(1),
I3 => data_out_b_hl(1),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(0),
O6 => jtag_dout(1));
--
s6_4k_jtag_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(2),
I1 => data_out_b_hl(2),
I2 => data_out_b_ll(3),
I3 => data_out_b_hl(3),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(2),
O6 => jtag_dout(3));
--
s6_4k_jtag_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(4),
I1 => data_out_b_hl(4),
I2 => data_out_b_ll(5),
I3 => data_out_b_hl(5),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(4),
O6 => jtag_dout(5));
--
s6_4k_jtag_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(6),
I1 => data_out_b_hl(6),
I2 => data_out_b_ll(7),
I3 => data_out_b_hl(7),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(6),
O6 => jtag_dout(7));
--
s6_4k_jtag_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(32),
I1 => data_out_b_hl(32),
I2 => data_out_b_lh(0),
I3 => data_out_b_hh(0),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(8),
O6 => jtag_dout(9));
--
s6_4k_jtag_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(1),
I1 => data_out_b_hh(1),
I2 => data_out_b_lh(2),
I3 => data_out_b_hh(2),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(10),
O6 => jtag_dout(11));
--
s6_4k_jtag_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(3),
I1 => data_out_b_hh(3),
I2 => data_out_b_lh(4),
I3 => data_out_b_hh(4),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(12),
O6 => jtag_dout(13));
--
s6_4k_jtag_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(5),
I1 => data_out_b_hh(5),
I2 => data_out_b_lh(6),
I3 => data_out_b_hh(6),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(14),
O6 => jtag_dout(15));
--
s6_4k_jtag_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(7),
I1 => data_out_b_hh(7),
I2 => data_out_b_lh(32),
I3 => data_out_b_hh(32),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(16),
O6 => jtag_dout(17));
--
end generate loader;
--
kcpsm6_rom_ll: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"410DE82014FFFF29410DF2FFF2BBF2AAF299F200E1012E410D416941482C3E26",
INIT_01 => X"38E1015B110C149514001400140014001440410D4130E1015B23011F82501A01",
INIT_02 => X"FF6A01410DE820E1018414FF14FF14FF0C148714AA1401140014001448410D41",
INIT_03 => X"140014001400147A410D41384135E1015B1103E101BE6EAA410DE820E1018414",
INIT_04 => X"4134E101681114FF14FF410DE82014FFE1019D03E1018E8DC014FF0C14001400",
INIT_05 => X"FF14FF1400140014001400144014690C140014001400140014001477410D4131",
INIT_06 => X"001451410D41374131E1016811E101AB03E101BED000A401410DE820E10176BD",
INIT_07 => X"020003E820E10148FEFEF2FF14FFE1013B0311EF00EF1D140014001400140014",
INIT_08 => X"7614FF03E101BE00010CFF410DE820E1017614FF14FF14FF000001F2202014FF",
INIT_09 => X"6B636F6C42000D646C726F57206F6C6C654803E101BE00001DFF410DE820E101",
INIT_0A => X"646E65530D00203A726F7272652064616572206B636F6C42000D3A6174616420",
INIT_0B => X"736E6F7073657220315200444D434120676E69646E65530D00444D4320676E69",
INIT_0C => X"726143000D6570797420647261632064614200203A6574796220375200203A65",
INIT_0D => X"4146000D646573696C616974696E6920647261430D000D4B4F20657079742064",
INIT_0E => X"0D2E707365722064657463657078652074656720746F6E20646964203A4C4154",
INIT_0F => X"0137000A00FC0FD0FC0E0E0E0ED0E902000141300280D008E10001000041A000",
INIT_10 => X"010015011F008000008020080000821011410D4154414C41414148410D004130",
INIT_11 => X"00100038000001F0380000C83800001938FFFFFF002C00001100003000FE3000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000141040100",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"9E030A000AE6607C00010005701CCC100057187C0F808002E4001725727FFCA8",
INITP_01 => X"57FF1ECBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD89F0C4F80D8",
INITP_02 => X"0000000000000000000000000000000000000000000000100B55500013102AA9",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_ll(31 downto 0),
DOPA => data_out_a_ll(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_ll(31 downto 0),
DOPB => data_out_b_ll(35 downto 32),
DIB => data_in_b_ll(31 downto 0),
DIPB => data_in_b_ll(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_lh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"010F000601090A01010F000E000E000E000E000E000D0D010F010F010F010101",
INIT_01 => X"0F000D0D0100010901090109010901090109010F010F000D0DB0C8010808B0CA",
INIT_02 => X"09F069010F0006000D0D01090109010900010901090109010901090109010F01",
INIT_03 => X"0109010901090109010F010F010F000D0D0101000D0D90E9010F0006000D0D01",
INIT_04 => X"010F000D0D0101090109010F00060109000D0D01000D0DF06901090001090109",
INIT_05 => X"E9010901090109010901090109010900010901090109010901090109010F010F",
INIT_06 => X"090109010F010F010F000D0D01000D0D01000D0D90E990E9010F0006000D0D90",
INIT_07 => X"0C0C010006000D0D90E990E90109000D0D0101000B0B00010901090109010901",
INIT_08 => X"0D010901000D0D88E990E9010F0006000D0D010901090109B0DCCC0006B00109",
INIT_09 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F01000D0D88E990E9010F0006000D",
INIT_0A => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0B => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0C => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0D => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0E => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0F => X"118FD1EF28001F0700A7A7A7A70710A688CE018FA71F070E109D8D88EF01250F",
INIT_10 => X"2828B1C801A16949681800082868081101010F010F010F010F010F010F28018F",
INIT_11 => X"585828B1DFDFCE07110F0F0E110F0F0E110F0F0E28015C280158280168180168",
INIT_12 => X"0000000000000000000000000000000000000000000000000000286FB16F4F28",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"34AA7355554CCAA95555AAAAA6AA995AAAAA72A9552AD5554EAAAA52A9AAA957",
INITP_01 => X"AC82A097FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2AA59552A92",
INITP_02 => X"000000000000000000000000000000000000000000000039F0888FFB688DD556",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_lh(31 downto 0),
DOPA => data_out_a_lh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_lh(31 downto 0),
DOPB => data_out_b_lh(35 downto 32),
DIB => data_in_b_lh(31 downto 0),
DIPB => data_in_b_lh(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hl: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hl(31 downto 0),
DOPA => data_out_a_hl(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hl(31 downto 0),
DOPB => data_out_b_hl(35 downto 32),
DIB => data_in_b_hl(31 downto 0),
DIPB => data_in_b_hl(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hh(31 downto 0),
DOPA => data_out_a_hh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hh(31 downto 0),
DOPB => data_out_b_hh(35 downto 32),
DIB => data_in_b_hh(31 downto 0),
DIPB => data_in_b_hh(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"410DE82014FFFF29410DF2FFF2BBF2AAF299F200E1012E410D416941482C3E26",
INIT_01 => X"38E1015B110C149514001400140014001440410D4130E1015B23011F82501A01",
INIT_02 => X"FF6A01410DE820E1018414FF14FF14FF0C148714AA1401140014001448410D41",
INIT_03 => X"140014001400147A410D41384135E1015B1103E101BE6EAA410DE820E1018414",
INIT_04 => X"4134E101681114FF14FF410DE82014FFE1019D03E1018E8DC014FF0C14001400",
INIT_05 => X"FF14FF1400140014001400144014690C140014001400140014001477410D4131",
INIT_06 => X"001451410D41374131E1016811E101AB03E101BED000A401410DE820E10176BD",
INIT_07 => X"020003E820E10148FEFEF2FF14FFE1013B0311EF00EF1D140014001400140014",
INIT_08 => X"7614FF03E101BE00010CFF410DE820E1017614FF14FF14FF000001F2202014FF",
INIT_09 => X"6B636F6C42000D646C726F57206F6C6C654803E101BE00001DFF410DE820E101",
INIT_0A => X"646E65530D00203A726F7272652064616572206B636F6C42000D3A6174616420",
INIT_0B => X"736E6F7073657220315200444D434120676E69646E65530D00444D4320676E69",
INIT_0C => X"726143000D6570797420647261632064614200203A6574796220375200203A65",
INIT_0D => X"4146000D646573696C616974696E6920647261430D000D4B4F20657079742064",
INIT_0E => X"0D2E707365722064657463657078652074656720746F6E20646964203A4C4154",
INIT_0F => X"0137000A00FC0FD0FC0E0E0E0ED0E902000141300280D008E10001000041A000",
INIT_10 => X"010015011F008000008020080000821011410D4154414C41414148410D004130",
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INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"9E030A000AE6607C00010005701CCC100057187C0F808002E4001725727FFCA8",
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INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"010F000601090A01010F000E000E000E000E000E000D0D010F010F010F010101",
INIT_01 => X"0F000D0D0100010901090109010901090109010F010F000D0DB0C8010808B0CA",
INIT_02 => X"09F069010F0006000D0D01090109010900010901090109010901090109010F01",
INIT_03 => X"0109010901090109010F010F010F000D0D0101000D0D90E9010F0006000D0D01",
INIT_04 => X"010F000D0D0101090109010F00060109000D0D01000D0DF06901090001090109",
INIT_05 => X"E9010901090109010901090109010900010901090109010901090109010F010F",
INIT_06 => X"090109010F010F010F000D0D01000D0D01000D0D90E990E9010F0006000D0D90",
INIT_07 => X"0C0C010006000D0D90E990E90109000D0D0101000B0B00010901090109010901",
INIT_08 => X"0D010901000D0D88E990E9010F0006000D0D010901090109B0DCCC0006B00109",
INIT_09 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F01000D0D88E990E9010F0006000D",
INIT_0A => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0B => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0C => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0D => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0E => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0F => X"118FD1EF28001F0700A7A7A7A70710A688CE018FA71F070E109D8D88EF01250F",
INIT_10 => X"2828B1C801A16949681800082868081101010F010F010F010F010F010F28018F",
INIT_11 => X"585828B1DFDFCE07110F0F0E110F0F0E110F0F0E28015C280158280168180168",
INIT_12 => X"0000000000000000000000000000000000000000000000000000286FB16F4F28",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"34AA7355554CCAA95555AAAAA6AA995AAAAA72A9552AD5554EAAAA52A9AAA957",
INITP_01 => X"AC82A097FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2AA59552A92",
INITP_02 => X"000000000000000000000000000000000000000000000039F0888FFB688DD556",
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INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"410DE82014FFFF29410DF2FFF2BBF2AAF299F200E1012E410D416941482C3E26",
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INIT_04 => X"4134E101681114FF14FF410DE82014FFE1019D03E1018E8DC014FF0C14001400",
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INIT_06 => X"001451410D41374131E1016811E101AB03E101BED000A401410DE820E10176BD",
INIT_07 => X"020003E820E10148FEFEF2FF14FFE1013B0311EF00EF1D140014001400140014",
INIT_08 => X"7614FF03E101BE00010CFF410DE820E1017614FF14FF14FF000001F2202014FF",
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INIT_0B => X"736E6F7073657220315200444D434120676E69646E65530D00444D4320676E69",
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INITP_00 => X"9E030A000AE6607C00010005701CCC100057187C0F808002E4001725727FFCA8",
INITP_01 => X"57FF1ECBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD89F0C4F80D8",
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port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"010F000601090A01010F000E000E000E000E000E000D0D010F010F010F010101",
INIT_01 => X"0F000D0D0100010901090109010901090109010F010F000D0DB0C8010808B0CA",
INIT_02 => X"09F069010F0006000D0D01090109010900010901090109010901090109010F01",
INIT_03 => X"0109010901090109010F010F010F000D0D0101000D0D90E9010F0006000D0D01",
INIT_04 => X"010F000D0D0101090109010F00060109000D0D01000D0DF06901090001090109",
INIT_05 => X"E9010901090109010901090109010900010901090109010901090109010F010F",
INIT_06 => X"090109010F010F010F000D0D01000D0D01000D0D90E990E9010F0006000D0D90",
INIT_07 => X"0C0C010006000D0D90E990E90109000D0D0101000B0B00010901090109010901",
INIT_08 => X"0D010901000D0D88E990E9010F0006000D0D010901090109B0DCCC0006B00109",
INIT_09 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F01000D0D88E990E9010F0006000D",
INIT_0A => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0B => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0C => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0D => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0E => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0F => X"118FD1EF28001F0700A7A7A7A70710A688CE018FA71F070E109D8D88EF01250F",
INIT_10 => X"2828B1C801A16949681800082868081101010F010F010F010F010F010F28018F",
INIT_11 => X"585828B1DFDFCE07110F0F0E110F0F0E110F0F0E28015C280158280168180168",
INIT_12 => X"0000000000000000000000000000000000000000000000000000286FB16F4F28",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_00 => X"34AA7355554CCAA95555AAAAA6AA995AAAAA72A9552AD5554EAAAA52A9AAA957",
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port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_4k_generate;
--
--
--
--
-- JTAG Loader
--
instantiate_loader : if (C_JTAG_LOADER_ENABLE = 1) generate
--
jtag_loader_6_inst : jtag_loader_6
generic map( C_FAMILY => C_FAMILY,
C_NUM_PICOBLAZE => 1,
C_JTAG_LOADER_ENABLE => C_JTAG_LOADER_ENABLE,
C_BRAM_MAX_ADDR_WIDTH => BRAM_ADDRESS_WIDTH,
C_ADDR_WIDTH_0 => BRAM_ADDRESS_WIDTH)
port map( picoblaze_reset => rdl_bus,
jtag_en => jtag_en,
jtag_din => jtag_din,
jtag_addr => jtag_addr(BRAM_ADDRESS_WIDTH-1 downto 0),
jtag_clk => jtag_clk,
jtag_we => jtag_we,
jtag_dout_0 => jtag_dout,
jtag_dout_1 => jtag_dout, -- ports 1-7 are not used
jtag_dout_2 => jtag_dout, -- in a 1 device debug
jtag_dout_3 => jtag_dout, -- session. However, Synplify
jtag_dout_4 => jtag_dout, -- etc require all ports to
jtag_dout_5 => jtag_dout, -- be connected
jtag_dout_6 => jtag_dout,
jtag_dout_7 => jtag_dout);
--
end generate instantiate_loader;
--
end low_level_definition;
--
--
-------------------------------------------------------------------------------------------
--
-- JTAG Loader
--
-------------------------------------------------------------------------------------------
--
--
-- JTAG Loader 6 - Version 6.00
-- Kris Chaplin 4 February 2010
-- Ken Chapman 15 August 2011 - Revised coding style
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
library unisim;
use unisim.vcomponents.all;
--
entity jtag_loader_6 is
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "V6";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
jtag_din : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
jtag_addr : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0) := (others => '0');
jtag_clk : out std_logic := '0';
jtag_we : out std_logic := '0';
jtag_dout_0 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end jtag_loader_6;
--
architecture Behavioral of jtag_loader_6 is
--
signal num_picoblaze : std_logic_vector(2 downto 0);
signal picoblaze_instruction_data_width : std_logic_vector(4 downto 0);
--
signal drck : std_logic;
signal shift_clk : std_logic;
signal shift_din : std_logic;
signal shift_dout : std_logic;
signal shift : std_logic;
signal capture : std_logic;
--
signal control_reg_ce : std_logic;
signal bram_ce : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal bus_zero : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
signal jtag_en_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal jtag_en_expanded : std_logic_vector(7 downto 0) := (others => '0');
signal jtag_addr_int : std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
signal jtag_din_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal control_din : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout_int : std_logic_vector(7 downto 0):= (others => '0');
signal bram_dout_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
signal jtag_we_int : std_logic;
signal jtag_clk_int : std_logic;
signal bram_ce_valid : std_logic;
signal din_load : std_logic;
--
signal jtag_dout_0_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_1_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_2_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_3_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_4_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_5_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_6_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_7_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal picoblaze_reset_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
--
begin
bus_zero <= (others => '0');
--
jtag_loader_gen: if (C_JTAG_LOADER_ENABLE = 1) generate
--
-- Insert BSCAN primitive for target device architecture.
--
BSCAN_SPARTAN6_gen: if (C_FAMILY="S6") generate
begin
BSCAN_BLOCK_inst : BSCAN_SPARTAN6
generic map ( JTAG_CHAIN => C_JTAG_CHAIN)
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_SPARTAN6_gen;
--
BSCAN_VIRTEX6_gen: if (C_FAMILY="V6") generate
begin
BSCAN_BLOCK_inst: BSCAN_VIRTEX6
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => FALSE)
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_VIRTEX6_gen;
--
BSCAN_7SERIES_gen: if (C_FAMILY="7S") generate
begin
BSCAN_BLOCK_inst: BSCANE2
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => "FALSE")
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_7SERIES_gen;
--
--
-- Insert clock buffer to ensure reliable shift operations.
--
upload_clock: BUFG
port map( I => drck,
O => shift_clk);
--
--
-- Shift Register
--
--
control_reg_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk = '1' then
if (shift = '1') then
control_reg_ce <= shift_din;
end if;
end if;
end process control_reg_ce_shift;
--
bram_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
if(C_NUM_PICOBLAZE > 1) then
for i in 0 to C_NUM_PICOBLAZE-2 loop
bram_ce(i+1) <= bram_ce(i);
end loop;
end if;
bram_ce(0) <= control_reg_ce;
end if;
end if;
end process bram_ce_shift;
--
bram_we_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
jtag_we_int <= bram_ce(C_NUM_PICOBLAZE-1);
end if;
end if;
end process bram_we_shift;
--
bram_a_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
for i in 0 to C_BRAM_MAX_ADDR_WIDTH-2 loop
jtag_addr_int(i+1) <= jtag_addr_int(i);
end loop;
jtag_addr_int(0) <= jtag_we_int;
end if;
end if;
end process bram_a_shift;
--
bram_d_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (din_load = '1') then
jtag_din_int <= bram_dout_int;
elsif (shift = '1') then
for i in 0 to C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2 loop
jtag_din_int(i+1) <= jtag_din_int(i);
end loop;
jtag_din_int(0) <= jtag_addr_int(C_BRAM_MAX_ADDR_WIDTH-1);
end if;
end if;
end process bram_d_shift;
--
shift_dout <= jtag_din_int(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1);
--
--
din_load_select:process (bram_ce, din_load, capture, bus_zero, control_reg_ce)
begin
if ( bram_ce = bus_zero ) then
din_load <= capture and control_reg_ce;
else
din_load <= capture;
end if;
end process din_load_select;
--
--
-- Control Registers
--
num_picoblaze <= conv_std_logic_vector(C_NUM_PICOBLAZE-1,3);
picoblaze_instruction_data_width <= conv_std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1,5);
--
control_registers: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '0') and (control_reg_ce = '1') then
case (jtag_addr_int(3 downto 0)) is
when "0000" => -- 0 = version - returns (7 downto 4) illustrating number of PB
-- and (3 downto 0) picoblaze instruction data width
control_dout_int <= num_picoblaze & picoblaze_instruction_data_width;
when "0001" => -- 1 = PicoBlaze 0 reset / status
if (C_NUM_PICOBLAZE >= 1) then
control_dout_int <= picoblaze_reset_int(0) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_0-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0010" => -- 2 = PicoBlaze 1 reset / status
if (C_NUM_PICOBLAZE >= 2) then
control_dout_int <= picoblaze_reset_int(1) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_1-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0011" => -- 3 = PicoBlaze 2 reset / status
if (C_NUM_PICOBLAZE >= 3) then
control_dout_int <= picoblaze_reset_int(2) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_2-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0100" => -- 4 = PicoBlaze 3 reset / status
if (C_NUM_PICOBLAZE >= 4) then
control_dout_int <= picoblaze_reset_int(3) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_3-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0101" => -- 5 = PicoBlaze 4 reset / status
if (C_NUM_PICOBLAZE >= 5) then
control_dout_int <= picoblaze_reset_int(4) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_4-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0110" => -- 6 = PicoBlaze 5 reset / status
if (C_NUM_PICOBLAZE >= 6) then
control_dout_int <= picoblaze_reset_int(5) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_5-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0111" => -- 7 = PicoBlaze 6 reset / status
if (C_NUM_PICOBLAZE >= 7) then
control_dout_int <= picoblaze_reset_int(6) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_6-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1000" => -- 8 = PicoBlaze 7 reset / status
if (C_NUM_PICOBLAZE >= 8) then
control_dout_int <= picoblaze_reset_int(7) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_7-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1111" => control_dout_int <= conv_std_logic_vector(C_BRAM_MAX_ADDR_WIDTH -1,8);
when others => control_dout_int <= (others => '1');
end case;
else
control_dout_int <= (others => '0');
end if;
end if;
end process control_registers;
--
control_dout(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8) <= control_dout_int;
--
pb_reset: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '1') and (control_reg_ce = '1') then
picoblaze_reset_int(C_NUM_PICOBLAZE-1 downto 0) <= control_din(C_NUM_PICOBLAZE-1 downto 0);
end if;
end if;
end process pb_reset;
--
--
-- Assignments
--
control_dout (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9 downto 0) <= (others => '0') when (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8);
--
-- Qualify the blockram CS signal with bscan select output
jtag_en_int <= bram_ce when bram_ce_valid = '1' else (others => '0');
--
jtag_en_expanded(C_NUM_PICOBLAZE-1 downto 0) <= jtag_en_int;
jtag_en_expanded(7 downto C_NUM_PICOBLAZE) <= (others => '0') when (C_NUM_PICOBLAZE < 8);
--
bram_dout_int <= control_dout or jtag_dout_0_masked or jtag_dout_1_masked or jtag_dout_2_masked or jtag_dout_3_masked or jtag_dout_4_masked or jtag_dout_5_masked or jtag_dout_6_masked or jtag_dout_7_masked;
--
control_din <= jtag_din_int;
--
jtag_dout_0_masked <= jtag_dout_0 when jtag_en_expanded(0) = '1' else (others => '0');
jtag_dout_1_masked <= jtag_dout_1 when jtag_en_expanded(1) = '1' else (others => '0');
jtag_dout_2_masked <= jtag_dout_2 when jtag_en_expanded(2) = '1' else (others => '0');
jtag_dout_3_masked <= jtag_dout_3 when jtag_en_expanded(3) = '1' else (others => '0');
jtag_dout_4_masked <= jtag_dout_4 when jtag_en_expanded(4) = '1' else (others => '0');
jtag_dout_5_masked <= jtag_dout_5 when jtag_en_expanded(5) = '1' else (others => '0');
jtag_dout_6_masked <= jtag_dout_6 when jtag_en_expanded(6) = '1' else (others => '0');
jtag_dout_7_masked <= jtag_dout_7 when jtag_en_expanded(7) = '1' else (others => '0');
--
jtag_en <= jtag_en_int;
jtag_din <= jtag_din_int;
jtag_addr <= jtag_addr_int;
jtag_clk <= jtag_clk_int;
jtag_we <= jtag_we_int;
picoblaze_reset <= picoblaze_reset_int;
--
end generate jtag_loader_gen;
--
end Behavioral;
--
--
------------------------------------------------------------------------------------
--
-- END OF FILE test_program.vhd
--
------------------------------------------------------------------------------------
|
lgpl-3.0
|
da5fb710b0e0e0a5622f61beeeb5a134
| 0.626397 | 5.13794 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/counter_increment_decrement_load_rst_nbits.vhd
| 1 | 2,508 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_increment_decrement_load_rst_n_bits
-- Module Name: Counter_increment_decrement_load_rst_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Counter of size bits with reset signal, that can increment or decrements
-- when ce equals to 1.
-- The reset is synchronous and the value loaded during reset is defined by reset_value.
-- The counter has a synchronous load signal, which will register the value on input d,
-- when load is 1 and reset is 0.
--
-- The circuits parameters
--
-- size :
--
-- The size of the counter in bits.
--
-- increment_value :
--
-- The amount will be incremented each cycle, when increment_decrement = 0.
--
-- decrement_value :
--
-- The amount will be decremented each cycle, when increment_decrement = 1.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_increment_decrement_load_rst_nbits is
Generic(
size : integer;
increment_value : integer;
decrement_value : integer
);
Port(
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
increment_decrement : STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end counter_increment_decrement_load_rst_nbits;
architecture Behavioral of counter_increment_decrement_load_rst_nbits is
signal internal_value : UNSIGNED((size - 1) downto 0);
begin
process(clk, ce, load, increment_decrement, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= unsigned(rst_value);
elsif(ce = '1') then
if(load = '1') then
internal_value <= unsigned(d);
elsif(increment_decrement = '1') then
internal_value <= internal_value - to_unsigned(decrement_value, internal_value'Length);
else
internal_value <= internal_value + to_unsigned(increment_value, internal_value'Length);
end if;
else
null;
end if;
end if;
end process;
q <= std_logic_vector(internal_value);
end Behavioral;
|
bsd-2-clause
|
058c0348858b8811bc7cb45d03897916
| 0.64673 | 3.483333 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/class_adder/class_adder.vhd
| 1 | 689 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity class_adder is
generic(N: integer:= 4);
port(
number1_in: in std_logic_vector(N-1 downto 0);
number2_in: in std_logic_vector(N-1 downto 0);
cin: in std_logic;
result: out std_logic_vector(N-1 downto 0);
cout: out std_logic
);
end;
architecture class_adder_arq of class_adder is
signal aux: unsigned (N+1 downto 0) := to_unsigned(0, N+2);
begin
aux <= ('0' & unsigned(number1_in) & cin) + ('0' & unsigned(number2_in) & '1');
result <= std_logic_vector( aux (N downto 1) );
cout <= aux (N+1);
end;
|
gpl-3.0
|
cd28f0788425c32bd1e3c92d1547456e
| 0.567489 | 3.089686 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
VHDL/USB/COUNTER_NORMAL.vhd
| 1 | 4,560 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: COUNTER_NORMAL.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY COUNTER_NORMAL IS
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END COUNTER_NORMAL;
ARCHITECTURE SYN OF counter_normal IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(2 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 3
)
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "3"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL "q[2..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 3 0 @q 0 0 3 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER_NORMAL.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER_NORMAL.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER_NORMAL.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER_NORMAL.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL COUNTER_NORMAL_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
gpl-2.0
|
6e2dca990f007aeefc1ec51083ab9bf3
| 0.650658 | 3.656776 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/number_splitter/number_splitter.vhd
| 1 | 1,023 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity number_splitter is
generic(
TOTAL_BITS:natural := 23;
EXP_BITS:natural := 6
);
port (
number_in: in std_logic_vector(TOTAL_BITS-1 downto 0);
sign_out: out std_logic;
exp_out: out std_logic_vector(EXP_BITS-1 downto 0);
mant_out: out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0)
);
end;
architecture number_splitter_arq of number_splitter is
begin
process(number_in)
begin
sign_out <= number_in(TOTAL_BITS-1);
exp_out <= number_in(TOTAL_BITS-2 downto TOTAL_BITS-1-EXP_BITS);
mant_out <= number_in(TOTAL_BITS-EXP_BITS-2 downto 0);
--report "WHOLE: " & integer'image(to_integer(unsigned(number_in)));
--report "SIGN: " & std_logic'image(number_in(TOTAL_BITS-1));
--report "EXP: " & integer'image(to_integer(unsigned(number_in(TOTAL_BITS-2 downto TOTAL_BITS-1-EXP_BITS))));
--report "MAN: " & integer'image(to_integer(unsigned(number_in(TOTAL_BITS-EXP_BITS-2 downto 0))));
end process;
end architecture;
|
gpl-3.0
|
0e09f41dcadac54d2d67cacab968425b
| 0.69697 | 2.772358 | false | false | false | false |
achan1989/In64
|
FPGA/SD_card_test.srcs/sources_1/ip/mig_v3_92_0/ATLYS_DDR/example_design/rtl/example_top.vhd
| 1 | 42,962 |
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity example_top is
generic
(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3000;
-- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
C3_HW_TESTING : string := "FALSE";
-- Determines the address space accessed by the traffic generator,
-- # = FALSE, Smaller address space,
-- # = TRUE, Large address space.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 13;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3
-- External memory bank address width.
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end example_top;
architecture arc of example_top is
component memc3_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0);
p2_cmd_bl : in std_logic_vector(5 downto 0);
p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
component memc3_tb_top is
generic (
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_NUM_DQ_PINS : integer;
C_MEM_BURST_LEN : integer;
C_MEM_NUM_COL_BITS : integer;
C_SMALL_DEVICE : string;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0);
C_p0_DATA_MODE : std_logic_vector(3 downto 0);
C_p0_END_ADDRESS : std_logic_vector(31 downto 0);
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0);
C_p2_DATA_MODE : std_logic_vector(3 downto 0);
C_p2_END_ADDRESS : std_logic_vector(31 downto 0);
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0)
);
port (
error : out std_logic;
calib_done : in std_logic;
clk0 : in std_logic;
rst0 : in std_logic;
cmp_error : out std_logic;
cmp_data_valid : out std_logic;
vio_modify_enable : in std_logic;
error_status : out std_logic_vector(127 downto 0);
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_data : out std_logic_vector(31 downto 0);
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0)
);
end component;
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_CLKOUT0_DIVIDE : integer := 1;
constant C3_CLKOUT1_DIVIDE : integer := 1;
constant C3_CLKOUT2_DIVIDE : integer := 16;
constant C3_CLKOUT3_DIVIDE : integer := 8;
constant C3_CLKFBOUT_MULT : integer := 2;
constant C3_DIVCLK_DIVIDE : integer := 1;
constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"20";
constant C3_MEM_TRAS : integer := 42500;
constant C3_MEM_TRCD : integer := 12500;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 127500;
constant C3_MEM_TRP : integer := 12500;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 7500;
constant C3_MEM_TYPE : string := "DDR2";
constant C3_MEM_DENSITY : string := "1Gb";
constant C3_MEM_BURST_LEN : integer := 4;
constant C3_MEM_CAS_LATENCY : integer := 5;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV2";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 0;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
constant C3_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p2_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c3_p0_cmd_en : std_logic;
signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p0_cmd_empty : std_logic;
signal c3_p0_cmd_full : std_logic;
signal c3_p0_wr_en : std_logic;
signal c3_p0_wr_mask : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
signal c3_p0_wr_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_wr_full : std_logic;
signal c3_p0_wr_empty : std_logic;
signal c3_p0_wr_count : std_logic_vector(6 downto 0);
signal c3_p0_wr_underrun : std_logic;
signal c3_p0_wr_error : std_logic;
signal c3_p0_rd_en : std_logic;
signal c3_p0_rd_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_rd_full : std_logic;
signal c3_p0_rd_empty : std_logic;
signal c3_p0_rd_count : std_logic_vector(6 downto 0);
signal c3_p0_rd_overflow : std_logic;
signal c3_p0_rd_error : std_logic;
signal c3_p2_cmd_en : std_logic;
signal c3_p2_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p2_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p2_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p2_cmd_empty : std_logic;
signal c3_p2_cmd_full : std_logic;
signal c3_p2_rd_en : std_logic;
signal c3_p2_rd_data : std_logic_vector(31 downto 0);
signal c3_p2_rd_full : std_logic;
signal c3_p2_rd_empty : std_logic;
signal c3_p2_rd_count : std_logic_vector(6 downto 0);
signal c3_p2_rd_overflow : std_logic;
signal c3_p2_rd_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
error <= c3_error;
calib_done <= c3_calib_done;
c3_sys_clk_p <= '0';
c3_sys_clk_n <= '0';
c3_selfrefresh_enter <= '0';
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C3_INCLK_PERIOD
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_i => c3_sys_rst_i,
clk0 => c3_clk0,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C3_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p0_cmd_clk => c3_clk0,
p0_cmd_en => c3_p0_cmd_en,
p0_cmd_instr => c3_p0_cmd_instr,
p0_cmd_bl => c3_p0_cmd_bl,
p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
p0_cmd_empty => c3_p0_cmd_empty,
p0_cmd_full => c3_p0_cmd_full,
p0_wr_clk => c3_clk0,
p0_wr_en => c3_p0_wr_en,
p0_wr_mask => c3_p0_wr_mask,
p0_wr_data => c3_p0_wr_data,
p0_wr_full => c3_p0_wr_full,
p0_wr_empty => c3_p0_wr_empty,
p0_wr_count => c3_p0_wr_count,
p0_wr_underrun => c3_p0_wr_underrun,
p0_wr_error => c3_p0_wr_error,
p0_rd_clk => c3_clk0,
p0_rd_en => c3_p0_rd_en,
p0_rd_data => c3_p0_rd_data,
p0_rd_full => c3_p0_rd_full,
p0_rd_empty => c3_p0_rd_empty,
p0_rd_count => c3_p0_rd_count,
p0_rd_overflow => c3_p0_rd_overflow,
p0_rd_error => c3_p0_rd_error,
p2_cmd_clk => c3_clk0,
p2_cmd_en => c3_p2_cmd_en,
p2_cmd_instr => c3_p2_cmd_instr,
p2_cmd_bl => c3_p2_cmd_bl,
p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
p2_cmd_empty => c3_p2_cmd_empty,
p2_cmd_full => c3_p2_cmd_full,
p2_rd_clk => c3_clk0,
p2_rd_en => c3_p2_rd_en,
p2_rd_data => c3_p2_rd_data,
p2_rd_full => c3_p2_rd_full,
p2_rd_empty => c3_p2_rd_empty,
p2_rd_count => c3_p2_rd_count,
p2_rd_overflow => c3_p2_rd_overflow,
p2_rd_error => c3_p2_rd_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
memc3_tb_top_inst : memc3_tb_top
generic map
(
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_SMALL_DEVICE => C3_SMALL_DEVICE,
C_p0_BEGIN_ADDRESS => C3_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C3_p0_DATA_MODE,
C_p0_END_ADDRESS => C3_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C3_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C3_p0_PRBS_SADDR_MASK_POS,
C_p2_BEGIN_ADDRESS => C3_p2_BEGIN_ADDRESS,
C_p2_DATA_MODE => C3_p2_DATA_MODE,
C_p2_END_ADDRESS => C3_p2_END_ADDRESS,
C_p2_PRBS_EADDR_MASK_POS => C3_p2_PRBS_EADDR_MASK_POS,
C_p2_PRBS_SADDR_MASK_POS => C3_p2_PRBS_SADDR_MASK_POS
)
port map
(
error => c3_error,
calib_done => c3_calib_done,
clk0 => c3_clk0,
rst0 => c3_rst0,
cmp_error => c3_cmp_error,
cmp_data_valid => c3_cmp_data_valid,
vio_modify_enable => c3_vio_modify_enable,
error_status => c3_error_status,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
cmp_data => c3_cmp_data,
p0_mcb_cmd_en_o => c3_p0_cmd_en,
p0_mcb_cmd_instr_o => c3_p0_cmd_instr,
p0_mcb_cmd_bl_o => c3_p0_cmd_bl,
p0_mcb_cmd_addr_o => c3_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c3_p0_cmd_full,
p0_mcb_wr_en_o => c3_p0_wr_en,
p0_mcb_wr_mask_o => c3_p0_wr_mask,
p0_mcb_wr_data_o => c3_p0_wr_data,
p0_mcb_wr_full_i => c3_p0_wr_full,
p0_mcb_wr_fifo_counts => c3_p0_wr_count,
p0_mcb_rd_en_o => c3_p0_rd_en,
p0_mcb_rd_data_i => c3_p0_rd_data,
p0_mcb_rd_empty_i => c3_p0_rd_empty,
p0_mcb_rd_fifo_counts => c3_p0_rd_count,
p2_mcb_cmd_en_o => c3_p2_cmd_en,
p2_mcb_cmd_instr_o => c3_p2_cmd_instr,
p2_mcb_cmd_bl_o => c3_p2_cmd_bl,
p2_mcb_cmd_addr_o => c3_p2_cmd_byte_addr,
p2_mcb_cmd_full_i => c3_p2_cmd_full,
p2_mcb_rd_en_o => c3_p2_rd_en,
p2_mcb_rd_data_i => c3_p2_rd_data,
p2_mcb_rd_empty_i => c3_p2_rd_empty,
p2_mcb_rd_fifo_counts => c3_p2_rd_count
);
end arc;
|
lgpl-3.0
|
229428761a34266a7b402b56652504e6
| 0.45638 | 3.413204 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/sign_based_complementer/sign_based_complementer.vhd
| 1 | 1,379 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--STEP 2
--This component takes the signs of the 2 numbers to operate with and returns the base complement of the mantissa received
--if the signs are different.
entity sign_based_complementer is
generic(
BITS : natural := 16
);
port(
sign_1_in : in std_logic;
sign_2_in : in std_logic;
man_in : in std_logic_vector(BITS - 1 downto 0);
man_out : out std_logic_vector(BITS - 1 downto 0)
);
end sign_based_complementer;
architecture sign_based_complementer_arq of sign_based_complementer is
signal complemented_mantissa : std_logic_vector(BITS - 1 downto 0) := (others => '0');
component base_complementer is
generic(
TOTAL_BITS : natural := 16
);
port(
number_in: in std_logic_vector(TOTAL_BITS - 1 downto 0);
number_out: out std_logic_vector(TOTAL_BITS - 1 downto 0)
);
end component;
for base_complementer_0 : base_complementer use entity work.base_complementer;
begin
base_complementer_0 : base_complementer
generic map(TOTAL_BITS => BITS)
port map(
number_in => man_in,
number_out => complemented_mantissa
);
process(sign_1_in, sign_2_in, man_in, complemented_mantissa) is
begin
if (sign_1_in /= sign_2_in) then
man_out <= complemented_mantissa;
else
man_out <= man_in;
end if;
end process;
end;
|
gpl-3.0
|
d2adfea805ab24e5dd7dcb8477d78152
| 0.680203 | 3.11991 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-LuGus/TP2-Voltimetro/display.vhd
| 1 | 7,782 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utility.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity display is
port (
mclk: in std_logic;
mrst: in std_logic;
mena: in std_logic;
v_in_plus: in std_logic;
v_in_minus: in std_logic;
v_out: out std_logic;
hs: out std_logic;
vs: out std_logic;
red_o: out std_logic_vector(2 downto 0);
grn_o: out std_logic_vector(2 downto 0);
blu_o: out std_logic_vector(1 downto 0)
-- red_o: out std_logic;
-- grn_o: out std_logic;
-- blu_o: out std_logic
);
attribute loc: string;
-- Mapeo de pines para el kit Nexys 2 (spartan 3E)
attribute loc of mclk: signal is "B8";
attribute loc of hs: signal is "T4";
attribute loc of vs: signal is "U3";
attribute loc of red_o: signal is "R8 T8 R9";
attribute loc of grn_o: signal is "P6 P8 N8";
attribute loc of blu_o: signal is "U4 U5";
attribute loc of mrst: signal is "H13";
attribute loc of mena: signal is "E18";
attribute loc of v_in_plus: signal is "G15";
attribute loc of v_in_minus: signal is "G16";
attribute loc of v_out: signal is "H16";
--attribute loc of mclk: signal is "C9";
--attribute loc of mrst: signal is "H13";
--attribute loc of mena: signal is "D18";
--attribute loc of hs: signal is "F15";
--attribute loc of vs: signal is "F14";
--attribute loc of red_o: signal is "H14";
--attribute loc of grn_o: signal is "H15";
--attribute loc of blu_o: signal is "G15";
end;
architecture display_arq of display is
component vga_ctrl is
port (
mclk: in std_logic;
red_i: in std_logic;
grn_i: in std_logic;
blu_i: in std_logic;
hs: out std_logic;
vs: out std_logic;
red_o: out std_logic_vector(2 downto 0);
grn_o: out std_logic_vector(2 downto 0);
blu_o: out std_logic_vector(1 downto 0);
-- red_o: out std_logic;
-- grn_o: out std_logic;
-- blu_o: out std_logic;
pixel_row: out std_logic_vector(9 downto 0);
pixel_col: out std_logic_vector(9 downto 0)
);
end component;
component ones_generator is
generic (
PERIOD: natural := 30000;
COUNT: natural := 15500
);
port(
clk: in std_logic;
count_o: out std_logic
);
end component;
component bcd_1_counter is
generic (
COUNTERS:natural := 5;
OUTPUT:natural := 3
);
port (
clk_in: in std_logic;
rst_in: in std_logic;
ena_in: in std_logic;
counter_out: out bcd_vector (OUTPUT-1 downto 0)
);
end component;
component char_ROM is
generic(
N: integer:= 6;
M: integer:= 3;
W: integer:= 8
);
port(
char_address: in std_logic_vector(5 downto 0);
font_row, font_col: in std_logic_vector(M-1 downto 0);
rom_out: out std_logic
);
end component;
component bcd_multiplexer is
port(
bcd0_input : in std_logic_vector(3 downto 0);
bcd1_input : in std_logic_vector(3 downto 0);
bcd2_input : in std_logic_vector(3 downto 0);
bcd3_input : in std_logic_vector(3 downto 0);
bcd4_input : in std_logic_vector(3 downto 0);
bcd5_input : in std_logic_vector(3 downto 0);
mux_selector : in std_logic_vector (2 downto 0);
mux_output : out std_logic_vector (5 downto 0)
);
end component;
component rom_manager is
generic (
SCREEN_H:natural := 1080;
SCREEN_W:natural := 1920;
BITS:natural := 11
);
port (
pixel_x_v: in std_logic_vector(BITS-1 downto 0);
pixel_y_v: in std_logic_vector(BITS-1 downto 0);
to_mux_v: out std_logic_vector(2 downto 0);
char_x_v: out std_logic_vector(2 downto 0);
char_y_v: out std_logic_vector(2 downto 0)
);
end component;
component FFD_Array is
generic (
SIZE: natural := 12
);
port(
enable: in std_logic;
reset: in std_logic;
clk: in std_logic;
Q: out std_logic_vector(SIZE-1 downto 0);
D: in std_logic_vector(SIZE-1 downto 0)
);
end component;
component voltage_registry_enabler is
port (
clk_in: in std_logic;
rst_in: in std_logic;
ena_in: in std_logic;
out_1: out std_logic;
out_2: out std_logic
);
end component;
signal pixel_row: std_logic_vector(9 downto 0);
signal pixel_col: std_logic_vector(9 downto 0);
signal color: std_logic;
signal mux_to_rom: std_logic_vector(5 downto 0);
signal manager_to_rom_row: std_logic_vector(2 downto 0);
signal manager_to_rom_col: std_logic_vector(2 downto 0);
signal manager_to_mux: std_logic_vector(2 downto 0);
signal reg_to_mux1: std_logic_vector(3 downto 0);
signal reg_to_mux2: std_logic_vector(3 downto 0);
signal reg_to_mux3: std_logic_vector(3 downto 0);
signal ones_generator_to_counter: std_logic;
signal enabler_to_reg: std_logic;
signal enabler_to_counter: std_logic;
signal reg_in0: std_logic_vector(3 downto 0);
signal reg_in1: std_logic_vector(3 downto 0);
signal reg_in2: std_logic_vector(3 downto 0);
signal reg_in: std_logic_vector(11 downto 0);
signal v_out_aux: std_logic;
signal to_ff:std_logic;
begin
reg_in <= reg_in0®_in1®_in2;
vga_controller_map: vga_ctrl
port map(
mclk => mclk,
red_i => color,
grn_i => color,
blu_i => '1',
hs => hs,
vs => vs,
red_o => red_o,
grn_o => grn_o,
blu_o => blu_o,
pixel_row => pixel_row,
pixel_col => pixel_col
);
char_ROM_map: char_ROM
port map(
char_address => mux_to_rom,
font_row => manager_to_rom_row,
font_col => manager_to_rom_col,
rom_out => color
);
rom_manager_map: rom_manager
generic map(384,680,10)
port map(
pixel_x_v => pixel_col,
pixel_y_v => pixel_row,
to_mux_v => manager_to_mux,
char_x_v => manager_to_rom_col,
char_y_v => manager_to_rom_row
);
FFD_Array_map: FFD_Array
generic map(12)
port map(
enable => enabler_to_reg,
reset => mrst,
clk => mclk,
Q(3 downto 0) => reg_to_mux1,
Q(7 downto 4) => reg_to_mux2,
Q(11 downto 8) => reg_to_mux3,
D => reg_in
);
bcd_multiplexer_map: bcd_multiplexer
port map(
bcd0_input => reg_to_mux1,
bcd1_input => "1010", --comma in rom
bcd2_input => reg_to_mux2,
bcd3_input => reg_to_mux3,
bcd4_input => "1100",--V in rom
bcd5_input => "1011", --space in rom
mux_selector => manager_to_mux,
mux_output => mux_to_rom
);
ones_generator_map: ones_generator
generic map(33000,23100)
port map(
clk => mclk,
count_o => ones_generator_to_counter
);
v_out <= v_out_aux;
bcd_1_counter_map: bcd_1_counter
port map(
clk_in => mclk,
rst_in => enabler_to_counter,
ena_in => v_out_aux,
counter_out(0) => reg_in0,
counter_out(1) => reg_in1,
counter_out(2) => reg_in2
);
voltage_registry_enabler_map: voltage_registry_enabler
port map(
clk_in => mclk,
rst_in => mrst,
ena_in => '1',
out_1 => enabler_to_reg,
out_2 => enabler_to_counter
);
IBUFDS_inst : IBUFDS
-- generic map (
-- CAPACITANCE => "DONT_CARE", -- "LOW", "NORMAL", "DONT_CARE" (Spartan-3 only)
-- DIFF_TERM => FALSE, -- Differential Termination
-- IOSTANDARD => "DEFAULT")
port map (
O => to_ff, -- Buffer output
I => v_in_plus, -- Diff_p buffer input (connect directly to top-level port)
IB => v_in_minus -- Diff_n buffer input (connect directly to top-level port)
);
FFD_Array_map2: FFD_Array
generic map(1)
port map(
enable => '1',
reset => mrst,
clk => mclk,
Q(0) => v_out_aux,
D(0) => to_ff
);
end;
|
gpl-3.0
|
61acd6a105d36f5632e50b0127fd6673
| 0.595477 | 2.805335 | false | false | false | false |
pwuertz/digitizer2fw
|
src/rtl/sampling_pkg.vhd
| 1 | 1,876 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sampling_pkg is
constant ADC_SAMPLE_BITS: integer := 12;
subtype a_sample_t is signed(ADC_SAMPLE_BITS-1 downto 0);
type adc_sample_t is
record
data: a_sample_t;
ovfl: std_logic;
end record;
function to_std_logic_vector(x: adc_sample_t) return std_logic_vector;
function to_adc_sample_t(x: std_logic_vector) return adc_sample_t;
type a_samples_t is array (natural range <>) of a_sample_t;
type adc_samples_t is array (natural range <>) of adc_sample_t;
type din_samples_t is array (natural range <>) of std_logic_vector(1 downto 0);
component sampling
port (
-- data in from pins
DIN_P: in std_logic_vector(1 downto 0);
DIN_N: in std_logic_vector(1 downto 0);
ADC_DA_P: in std_logic_vector(12 downto 0);
ADC_DA_N: in std_logic_vector(12 downto 0);
ADC_DACLK_P: in std_logic;
ADC_DACLK_N: in std_logic;
-- data in to device
app_clk: out std_logic;
samples_d: out din_samples_t(0 to 3);
samples_a: out adc_samples_t(0 to 1);
-- control
rst: in std_logic
);
end component;
end sampling_pkg;
package body sampling_pkg is
function to_std_logic_vector(x: adc_sample_t) return std_logic_vector is
variable result: std_logic_vector(ADC_SAMPLE_BITS downto 0);
begin
result(ADC_SAMPLE_BITS) := x.ovfl;
result(ADC_SAMPLE_BITS-1 downto 0) := std_logic_vector(x.data);
return result;
end to_std_logic_vector;
function to_adc_sample_t(x: std_logic_vector) return adc_sample_t is
variable result: adc_sample_t;
begin
result.ovfl := x(x'low + ADC_SAMPLE_BITS);
result.data := signed(x(x'low + ADC_SAMPLE_BITS-1 downto x'low));
return result;
end to_adc_sample_t;
end sampling_pkg;
|
gpl-3.0
|
53435d61afb36227f7c9a8c69035a751
| 0.642324 | 3.174281 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
VHDL_PLANB/FIFO.vhd
| 1 | 6,837 |
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
-- ============================================================
-- File Name: FIFO.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY FIFO IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
);
END FIFO;
ARCHITECTURE SYN OF fifo IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0);
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (127 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(127 DOWNTO 0);
dcfifo_component : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone IV E",
lpm_numwords => 128,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 128,
lpm_widthu => 7,
overflow_checking => "ON",
rdsync_delaypipe => 4,
read_aclr_synch => "OFF",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "ON",
wrsync_delaypipe => 4
)
PORT MAP (
aclr => aclr,
data => data,
rdclk => rdclk,
rdreq => rdreq,
wrclk => wrclk,
wrreq => wrreq,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "128"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "128"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "128"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL "data[127..0]"
-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL "q[127..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
e30f3f363d6aa5503065c12ae04f6c98
| 0.665497 | 3.592748 | false | false | false | false |
laurivosandi/hdl
|
arithmetic/src/alu.vhd
| 1 | 2,449 |
library ieee;
use ieee.std_logic_1164.all;
entity alu is
generic (
WIDTH: integer := 8
);
port (
a : in std_logic_vector (WIDTH-1 downto 0);
b : in std_logic_vector (WIDTH-1 downto 0);
cin : in std_logic;
ctrl : in std_logic_vector ( 1 downto 0);
cout : out std_logic;
q : out std_logic_vector (WIDTH-1 downto 0)
);
end alu;
architecture behavioral of alu is
component carry_ripple_adder
generic (
WIDTH : integer
);
port (
a : in std_logic_vector (WIDTH-1 downto 0);
b : in std_logic_vector (WIDTH-1 downto 0);
ci : in std_logic;
s : out std_logic_vector (WIDTH-1 downto 0);
co : out std_logic
);
end component;
signal operand1 : std_logic_vector (WIDTH-1 downto 0);
signal operand2 : std_logic_vector (WIDTH-1 downto 0);
signal operand2_complement : std_logic_vector (WIDTH-1 downto 0);
signal sum : std_logic_vector (WIDTH-1 downto 0);
signal sum_carry : std_logic;
signal difference : std_logic_vector (WIDTH-1 downto 0);
signal difference_carry : std_logic;
begin
-- Connect inputs
operand1 <= a;
operand2 <= b;
-- Addition
adder1: carry_ripple_adder
generic map(
WIDTH
)
port map(
a => operand1,
b => operand2,
ci => '0',
s => sum,
co => sum_carry
);
-- Subtraction
operand2_complement <= not operand2;
adder2: carry_ripple_adder
generic map(
WIDTH
)
port map(
a => operand1,
b => operand2_complement,
ci => '1',
s => difference,
co => difference_carry
);
-- Control logic and inlined NOR and NAND operations
q <= sum when ctrl ="00" else
difference when ctrl ="01" else
operand1 nor operand2 when ctrl ="10" else
operand1 nand operand2 when ctrl ="11" else
(others => '0');
-- Carry bit
cout <= sum_carry when ctrl = "00" else
difference_carry when ctrl = "01" else
'0';
end;
|
mit
|
d2904367a83caa8b3f6715761bcedb59
| 0.481829 | 4.200686 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
VHDL/BLUETOOTH/BLUETOOTH_CONTROL.vhd
| 1 | 2,807 |
--FPGA application for this system.
--copyright(c) 2014 dtysky
--This program is free software; you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation; either version 2 of the License, or
--(at your option) any later version.
--This program is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License along
--with this program; if not, write to the Free Software Foundation, Inc.,
--51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity BLUETOOTH_CONTROL is
port
(
clk_self,pll_lock:in std_logic;
bluetooth_rqu:in std_logic:='0';
bluetooth_ack:out std_logic:='0';
bluetooth_reset:out std_logic:='0';
bluetooth_data:inout std_logic_vector(3 downto 0):=x"0";
in_rqu:out std_logic:='0';
in_end:in std_logic:='0';
data_in:out std_logic_vector(7 downto 0)
--error:std_logic
);
end entity;
architecture bluetooth of BLUETOOTH_CONTROL is
type states is (free,recieve,ack,sync,reset);
signal state:states:=free;
signal data_buffer:std_logic_vector(7 downto 0):=x"00";
begin
MAIN:process(clk_self,pll_lock)
variable con_recieve:integer range 0 to 3:=0;
begin
if clk_self'event and clk_self='1' and pll_lock='1' then
------------IDLE------------
if state=free then
bluetooth_ack<='0';
bluetooth_reset<='0';
if bluetooth_rqu='1' then
state<=recieve;
else
state<=state;
end if;
----------RECIEVE-----------
elsif state=recieve then
if con_recieve=0 then
data_buffer(7 downto 4)<=bluetooth_data;
con_recieve:=1;
state<=ack;
else
data_buffer(7 downto 4)<=bluetooth_data;
con_recieve:=0;
state<=ack;
end if;
------------ACK------------
elsif state=ack then
bluetooth_ack<='1';
if con_recieve=1 then
in_rqu<='1';
data_in<=data_buffer;
state<=sync;
elsif bluetooth_rqu='0' then
state<=free;
else
state<=state;
end if;
-----------SYNC------------
elsif state=sync then
if in_end='1' then
in_rqu<='0';
state<=free;
else
state<=state;
end if;
----------RESET-----------
elsif state=reset then
con_recieve:=0;
bluetooth_reset<='1';
in_rqu<='0';
state<=free;
else
state<=reset;
end if;
end if;
end process;
end bluetooth;
|
gpl-2.0
|
acbc974eb26ed237e742b7b8f42044af
| 0.625935 | 3.31405 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/TP1-Contador/generic_counter_tb.vhd
| 1 | 913 |
library ieee;
use ieee.std_logic_1164.all;
entity generic_counter_tb is
end;
architecture generic_counter_tb_func of generic_counter_tb is
signal rst_in: std_logic:='1';
signal ena_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal n_out: std_logic_vector(3 downto 0);
signal c_out: std_logic:='0';
component generic_counter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15
);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
counter_out: out std_logic_vector(BITS-1 downto 0);
carry_out: out std_logic
);
end component;
begin
clk_in <= not(clk_in) after 1 ns;
rst_in <= '0' after 10 ns;
ena_in <= '1' after 20 ns;
generic_counter_map: generic_counter
generic map (4,15)
port map(
clk => clk_in,
rst => rst_in,
ena => ena_in,
counter_out => n_out,
carry_out => c_out
);
end architecture;
|
gpl-3.0
|
26a094e6d6f5a1e6fa5d9d1181e4f104
| 0.62322 | 2.709199 | false | false | false | false |
hitomi2500/wasca
|
fpga_firmware/wasca/wasca_inst.vhd
| 1 | 9,252 |
component wasca is
port (
abus_avalon_sdram_bridge_0_abus_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
abus_avalon_sdram_bridge_0_abus_read : in std_logic := 'X'; -- read
abus_avalon_sdram_bridge_0_abus_data : inout std_logic_vector(15 downto 0) := (others => 'X'); -- data
abus_avalon_sdram_bridge_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
abus_avalon_sdram_bridge_0_abus_direction : out std_logic; -- direction
abus_avalon_sdram_bridge_0_abus_interrupt_disable_out : out std_logic; -- interrupt_disable_out
abus_avalon_sdram_bridge_0_abus_interrupt : out std_logic; -- interrupt
abus_avalon_sdram_bridge_0_abus_writebyteenable_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- writebyteenable_n
abus_avalon_sdram_bridge_0_abus_reset : in std_logic := 'X'; -- reset
abus_avalon_sdram_bridge_0_sdram_addr : out std_logic_vector(12 downto 0); -- addr
abus_avalon_sdram_bridge_0_sdram_ba : out std_logic_vector(1 downto 0); -- ba
abus_avalon_sdram_bridge_0_sdram_cas_n : out std_logic; -- cas_n
abus_avalon_sdram_bridge_0_sdram_cke : out std_logic; -- cke
abus_avalon_sdram_bridge_0_sdram_cs_n : out std_logic; -- cs_n
abus_avalon_sdram_bridge_0_sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
abus_avalon_sdram_bridge_0_sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
abus_avalon_sdram_bridge_0_sdram_ras_n : out std_logic; -- ras_n
abus_avalon_sdram_bridge_0_sdram_we_n : out std_logic; -- we_n
abus_avalon_sdram_bridge_0_sdram_clk : out std_logic; -- clk
buffered_spi_mosi : out std_logic; -- mosi
buffered_spi_clk : out std_logic; -- clk
buffered_spi_miso : in std_logic := 'X'; -- miso
buffered_spi_cs : out std_logic; -- cs
buffered_spi_sync : in std_logic := 'X'; -- sync
clk_clk : in std_logic := 'X'; -- clk
clock_116_mhz_clk : out std_logic; -- clk
heartbeat_heartbeat_out : out std_logic; -- heartbeat_out
reset_reset_n : in std_logic := 'X'; -- reset_n
reset_controller_0_reset_in1_reset : in std_logic := 'X'; -- reset
uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_0_external_connection_txd : out std_logic -- txd
);
end component wasca;
u0 : component wasca
port map (
abus_avalon_sdram_bridge_0_abus_address => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_address, -- abus_avalon_sdram_bridge_0_abus.address
abus_avalon_sdram_bridge_0_abus_read => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_read, -- .read
abus_avalon_sdram_bridge_0_abus_data => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_data, -- .data
abus_avalon_sdram_bridge_0_abus_chipselect => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_chipselect, -- .chipselect
abus_avalon_sdram_bridge_0_abus_direction => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_direction, -- .direction
abus_avalon_sdram_bridge_0_abus_interrupt_disable_out => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_interrupt_disable_out, -- .interrupt_disable_out
abus_avalon_sdram_bridge_0_abus_interrupt => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_interrupt, -- .interrupt
abus_avalon_sdram_bridge_0_abus_writebyteenable_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_writebyteenable_n, -- .writebyteenable_n
abus_avalon_sdram_bridge_0_abus_reset => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_reset, -- .reset
abus_avalon_sdram_bridge_0_sdram_addr => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_addr, -- abus_avalon_sdram_bridge_0_sdram.addr
abus_avalon_sdram_bridge_0_sdram_ba => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_ba, -- .ba
abus_avalon_sdram_bridge_0_sdram_cas_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cas_n, -- .cas_n
abus_avalon_sdram_bridge_0_sdram_cke => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cke, -- .cke
abus_avalon_sdram_bridge_0_sdram_cs_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cs_n, -- .cs_n
abus_avalon_sdram_bridge_0_sdram_dq => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_dq, -- .dq
abus_avalon_sdram_bridge_0_sdram_dqm => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_dqm, -- .dqm
abus_avalon_sdram_bridge_0_sdram_ras_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_ras_n, -- .ras_n
abus_avalon_sdram_bridge_0_sdram_we_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_we_n, -- .we_n
abus_avalon_sdram_bridge_0_sdram_clk => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_clk, -- .clk
buffered_spi_mosi => CONNECTED_TO_buffered_spi_mosi, -- buffered_spi.mosi
buffered_spi_clk => CONNECTED_TO_buffered_spi_clk, -- .clk
buffered_spi_miso => CONNECTED_TO_buffered_spi_miso, -- .miso
buffered_spi_cs => CONNECTED_TO_buffered_spi_cs, -- .cs
buffered_spi_sync => CONNECTED_TO_buffered_spi_sync, -- .sync
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clock_116_mhz_clk => CONNECTED_TO_clock_116_mhz_clk, -- clock_116_mhz.clk
heartbeat_heartbeat_out => CONNECTED_TO_heartbeat_heartbeat_out, -- heartbeat.heartbeat_out
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
reset_controller_0_reset_in1_reset => CONNECTED_TO_reset_controller_0_reset_in1_reset, -- reset_controller_0_reset_in1.reset
uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd
uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd -- .txd
);
|
gpl-2.0
|
6d8a0527d40ac6deed832ac8133e072d
| 0.414397 | 4.471725 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/controller_polynomial_computing.vhd
| 1 | 15,435 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Polynomial_Computing
-- Module Name: Controller_Polynomial_Computing
-- Project Name: McEliece Goppa decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 3rd step in Goppa Decoding.
--
-- This circuit is the state machine for polynomial_syndrome_computing_n.
-- This state machine is only active during polynomial sigma evaluation and roots search.
-- During syndrome computation this circuit is ignored and controlled by
-- controller_syndrome_computing.
--
-- For optimizations in polynomial_syndrome_computing_n_v2 both states machines were joined
-- joined into a single one that can run both algorithms.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity controller_polynomial_computing is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_load_x_values : in STD_LOGIC;
last_store_x_values : in STD_LOGIC;
limit_polynomial_degree : in STD_LOGIC;
pipeline_ready : in STD_LOGIC;
evaluation_data_in : out STD_LOGIC;
reg_write_enable_rst : out STD_LOGIC;
ctr_load_x_address_ce : out STD_LOGIC;
ctr_load_x_address_rst : out STD_LOGIC;
ctr_store_x_address_ce : out STD_LOGIC;
ctr_store_x_address_rst : out STD_LOGIC;
reg_first_values_ce : out STD_LOGIC;
reg_first_values_rst : out STD_LOGIC;
ctr_address_polynomial_ce : out STD_LOGIC;
ctr_address_polynomial_rst : out STD_LOGIC;
reg_x_rst_rst : out STD_LOGIC;
shift_polynomial_ce_ce : out STD_LOGIC;
shift_polynomial_ce_rst : out STD_LOGIC;
last_coefficients : out STD_LOGIC;
evaluation_finalized : out STD_LOGIC
);
end controller_polynomial_computing;
architecture Behavioral of controller_polynomial_computing is
type State is (reset, load_counter, load_first_polynomial_coefficient, reset_first_polynomial_coefficient, prepare_load_polynomial_coefficient, load_polynomial_coefficient, reset_polynomial_coefficient, load_x, load_x_write_x, last_load_x_write_x, write_x, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, last_load_x_values, last_store_x_values, limit_polynomial_degree, pipeline_ready)
begin
case (actual_state) is
when reset =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '1';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '1';
reg_x_rst_rst <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '1';
last_coefficients <= '0';
evaluation_finalized <= '0';
when load_counter =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '1';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
when load_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
elsif(limit_polynomial_degree = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '1';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
end if;
when reset_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '1';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '1';
evaluation_finalized <= '0';
end if;
when prepare_load_polynomial_coefficient =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '1';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '1';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
when load_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
elsif(limit_polynomial_degree = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '1';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
end if;
when reset_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '1';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '1';
evaluation_finalized <= '0';
end if;
when load_x =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
when load_x_write_x =>
if(last_load_x_values = '1' and limit_polynomial_degree = '0') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
end if;
when last_load_x_write_x =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
when write_x =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
when final =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '1';
when others =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
end case;
end process;
NewState: process (actual_state, last_load_x_values, last_store_x_values, limit_polynomial_degree, pipeline_ready)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= load_first_polynomial_coefficient;
when load_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= load_x;
elsif(limit_polynomial_degree = '1') then
next_state <= reset_first_polynomial_coefficient;
else
next_state <= load_first_polynomial_coefficient;
end if;
when reset_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= load_x;
else
next_state <= reset_first_polynomial_coefficient;
end if;
when prepare_load_polynomial_coefficient =>
next_state <= load_polynomial_coefficient;
when load_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= load_x;
elsif(limit_polynomial_degree = '1') then
next_state <= reset_polynomial_coefficient;
else
next_state <= load_polynomial_coefficient;
end if;
when reset_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= load_x;
else
next_state <= reset_polynomial_coefficient;
end if;
when load_x =>
next_state <= load_x_write_x;
when load_x_write_x =>
if(last_load_x_values = '1') then
if(limit_polynomial_degree = '1') then
next_state <= last_load_x_write_x;
else
next_state <= prepare_load_polynomial_coefficient;
end if;
else
next_state <= load_x_write_x;
end if;
when last_load_x_write_x =>
next_state <= write_x;
when write_x =>
if(last_store_x_values = '1') then
next_state <= final;
else
next_state <= write_x;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
af75be399b2080feff7b96dfff0e0759
| 0.600842 | 2.792654 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/polynomial_syndrome_computing_n_v2.vhd
| 1 | 29,936 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Polynomial_Syndrome_Computing_N_v2
-- Module Name: Polynomial_Syndrome_Computing_N_v2
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st and 3rd step in Goppa Decoding.
--
-- This circuit can find the roots of polynomial sigma and compute the syndrome from
-- the received ciphertext. The algorithm run by the circuit is chosen from one of the inputs.
-- Both circuits were joined into the same, because several computing parts are reused in
-- the computations, therefore this circuit needs less area than two apart.
--
-- For the computation this circuit applies the Horner scheme during finding roots, where at each stage
-- an accumulator is multiplied by respective x and then added accumulated with coefficient.
-- In Horner scheme algorithm, it begin from the most significative coefficient until reaches
-- lesser significative coefficient.
--
-- In syndrome generation it is applied alternant syndrome generation, where at each pipeline
-- stage is computed one syndrome iteration. A syndrome iteration is the multiplication of
-- one powering element by one support element.
--
-- The circuits parameters
--
-- number_of_pipelines :
--
-- Number of pipelines used in the circuit to test the support elements and
-- correct the message. Each pipeline needs at least 2 memory ram to store
-- intermediate results.
--
-- pipeline_size :
--
-- The number of stages the pipeline has. More stages means more values of value_sigma
-- are tested at once.
--
-- size_pipeline_size :
--
-- The number of bits necessary to store the pipeline_size.
-- This number is ceil(log2(pipeline_size))
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- polynomial_degree :
--
-- The polynomial degree to be evaluated. Therefore the polynomial has
-- polynomial_degree+1 coefficients. This parameters depends of the Goppa code used.
--
-- size_polynomial_degree :
--
-- The number of bits necessary to store polynomial_degree.
-- This number is ceil(log2(polynomial_degree+1))
--
-- number_of_values_x :
--
-- The size of the memory that holds all support elements. This parameter
-- depends of the Goppa code used.
--
-- size_number_of_values_x :
-- The number of bits necessary to store all support elements.
-- this number is ceil(log2(number_of_values_x)).
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- pipeline_polynomial_calc_v4 Rev 1.0
-- controller_polynomial_computing Rev 1.0
-- controller_syndrome_computing Rev 1.0
-- pow2_gf_2_m Rev 1.0
-- shift_register_rst_nbits Rev 1.0
-- shift_register_nbits Rev 1.0
-- register_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_increment_decrement_load_rst_nbits Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity polynomial_syndrome_computing_n_v2 is
Generic (
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 28;
-- size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 11;
-- number_of_errors : integer := 27;
-- size_number_of_errors : integer := 5;
-- number_of_support_elements: integer := 2048;
-- size_number_of_support_elements : integer := 11
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 51;
-- size_pipeline_size : integer := 6;
-- gf_2_m : integer range 1 to 20 := 11;
-- number_of_errors : integer := 50;
-- size_number_of_errors : integer := 6;
-- number_of_support_elements: integer := 2048;
-- size_number_of_support_elements : integer := 11
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 67;
-- size_pipeline_size : integer := 6;
-- gf_2_m : integer range 1 to 20 := 12;
-- number_of_errors : integer := 66;
-- size_number_of_errors : integer := 7;
-- number_of_support_elements : integer := 3307;
-- size_number_of_support_elements : integer := 12;
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 33;
-- size_pipeline_size : integer := 6;
-- gf_2_m : integer range 1 to 20 := 12;
-- number_of_errors : integer := 32;
-- size_number_of_errors : integer := 6;
-- number_of_support_elements: integer := 2528;
-- size_number_of_support_elements : integer := 12
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7;
-- number_of_support_elements: integer := 2816;
-- size_number_of_support_elements : integer := 12
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7;
-- number_of_support_elements: integer := 3328;
-- size_number_of_support_elements : integer := 12
-- QD-GOPPA [7296, 5632, 128, 13] --
number_of_pipelines : integer := 1;
pipeline_size : integer := 2;
size_pipeline_size : integer := 2;
gf_2_m : integer range 1 to 20 := 13;
number_of_errors : integer := 128;
size_number_of_errors : integer := 8;
number_of_support_elements: integer := 7296;
size_number_of_support_elements : integer := 13
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_message : in STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_h : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
computation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
address_value_error : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_value_error : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_error : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0)
);
end polynomial_syndrome_computing_n_v2;
architecture RTL of polynomial_syndrome_computing_n_v2 is
component pipeline_polynomial_calc_v4
Generic (
gf_2_m : integer range 1 to 20;
size : integer
);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((((gf_2_m)*size) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
reg_x_rst : in STD_LOGIC_VECTOR((size - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((((gf_2_m)*size) - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component pow2_gf_2_m
Generic(
gf_2_m : integer range 1 to 20
);
Port(
a : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0)
);
end component;
component shift_register_rst_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component shift_register_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component register_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_decrement_rst_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_increment_decrement_load_rst_nbits
Generic (
size : integer;
increment_value : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
increment_decrement : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component controller_polynomial_syndrome_computing
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
mode_polynomial_syndrome : in STD_LOGIC;
last_load_x_values : in STD_LOGIC;
last_store_x_values : in STD_LOGIC;
limit_polynomial_degree : in STD_LOGIC;
last_syndrome_value : in STD_LOGIC;
final_syndrome_evaluation : in STD_LOGIC;
pipeline_ready : in STD_LOGIC;
evaluation_data_in : out STD_LOGIC;
reg_write_enable_rst : out STD_LOGIC;
ctr_load_x_address_ce : out STD_LOGIC;
ctr_load_x_address_rst : out STD_LOGIC;
ctr_store_x_address_ce : out STD_LOGIC;
ctr_store_x_address_rst : out STD_LOGIC;
reg_first_values_ce : out STD_LOGIC;
reg_first_values_rst : out STD_LOGIC;
ctr_address_polynomial_syndrome_ce : out STD_LOGIC;
ctr_address_polynomial_syndrome_load : out STD_LOGIC;
ctr_address_polynomial_syndrome_increment_decrement : out STD_LOGIC;
ctr_address_polynomial_syndrome_rst : out STD_LOGIC;
reg_x_rst_rst : out STD_LOGIC;
reg_store_temporary_syndrome_ce : out STD_LOGIC;
reg_final_syndrome_evaluation_ce : out STD_LOGIC;
reg_final_syndrome_evaluation_rst : out STD_LOGIC;
shift_polynomial_ce_ce : out STD_LOGIC;
shift_polynomial_ce_rst : out STD_LOGIC;
shift_syndrome_mode_data_in : out STD_LOGIC;
shift_syndrome_mode_rst : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
finalize_syndrome : out STD_LOGIC;
last_coefficients : out STD_LOGIC;
computation_finalized : out STD_LOGIC
);
end component;
signal pipeline_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal pipeline_value_polynomial : STD_LOGIC_VECTOR(((gf_2_m)*(pipeline_size)*(number_of_pipelines) - 1) downto 0);
signal square_value_h : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal new_value_intermediate_syndrome : STD_LOGIC_VECTOR(((gf_2_m)*(pipeline_size)*(number_of_pipelines) - 1) downto 0);
constant coefficient_zero : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
constant first_acc : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
constant first_x_pow : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(1, gf_2_m));
signal reg_polynomial_coefficients_d : STD_LOGIC_VECTOR((((gf_2_m)*pipeline_size) - 1) downto 0);
signal reg_polynomial_coefficients_ce : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal reg_polynomial_coefficients_q : STD_LOGIC_VECTOR((((gf_2_m)*pipeline_size) - 1) downto 0);
signal reg_x_rst_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_x_rst_ce : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal reg_x_rst_rst : STD_LOGIC;
signal reg_x_rst_q : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal reg_x_rst : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal shift_polynomial_ce_data_in : STD_LOGIC;
signal shift_polynomial_ce_ce : STD_LOGIC;
signal shift_polynomial_ce_rst : STD_LOGIC;
constant shift_polynomial_ce_rst_value : STD_LOGIC_VECTOR(pipeline_size downto 0) := std_logic_vector(to_unsigned(1, pipeline_size+1));
signal shift_polynomial_ce_q : STD_LOGIC_VECTOR(pipeline_size downto 0);
signal finalize_syndrome : STD_LOGIC;
signal shift_syndrome_mode_data_in : STD_LOGIC;
signal shift_syndrome_mode_rst : STD_LOGIC;
constant shift_syndrome_mode_rst_value : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0) := std_logic_vector(to_unsigned(1, pipeline_size));
signal shift_syndrome_mode_q : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal ctr_load_x_address_ce : STD_LOGIC;
signal ctr_load_x_address_rst : STD_LOGIC;
constant ctr_load_x_address_rst_value : STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0) := std_logic_vector(to_unsigned(0, size_number_of_support_elements));
signal ctr_load_x_address_q : STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
signal ctr_store_x_address_ce : STD_LOGIC;
signal ctr_store_x_address_rst : STD_LOGIC;
constant ctr_store_x_address_rst_value : STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0) := std_logic_vector(to_unsigned(0, size_number_of_support_elements));
signal ctr_store_x_address_q : STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
signal ctr_address_polynomial_syndrome_d : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0);
signal ctr_address_polynomial_syndrome_ce : STD_LOGIC;
signal ctr_address_polynomial_syndrome_load : STD_LOGIC;
signal ctr_address_polynomial_syndrome_increment_decrement : STD_LOGIC;
signal ctr_address_polynomial_syndrome_rst : STD_LOGIC;
signal ctr_address_polynomial_syndrome_rst_value : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0) := std_logic_vector(to_unsigned(number_of_errors*2, size_number_of_errors+1));
signal ctr_address_polynomial_syndrome_q : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0);
signal reg_store_temporary_syndrome_d : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0);
signal reg_store_temporary_syndrome_ce : STD_LOGIC;
signal reg_store_temporary_syndrome_q : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0);
signal reg_first_values_ce : STD_LOGIC;
signal reg_first_values_rst : STD_LOGIC;
constant reg_first_values_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "1";
signal reg_first_values_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_final_syndrome_evaluation_ce : STD_LOGIC;
signal reg_final_syndrome_evaluation_rst : STD_LOGIC;
constant reg_final_syndrome_evaluation_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_final_syndrome_evaluation_q : STD_LOGIC_VECTOR(0 downto 0);
signal evaluation_data_in : STD_LOGIC;
signal evaluation_data_out : STD_LOGIC;
signal reg_write_enable_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_write_enable_rst : STD_LOGIC;
constant reg_write_enable_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_write_enable_q : STD_LOGIC_VECTOR(0 downto 0);
signal pipeline_ready : STD_LOGIC;
signal limit_polynomial_degree : STD_LOGIC;
signal last_syndrome_value : STD_LOGIC;
signal final_syndrome_evaluation : STD_LOGIC;
signal last_coefficients : STD_LOGIC;
signal last_load_x_values : STD_LOGIC;
signal last_store_x_values : STD_LOGIC;
signal value_evaluated : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal last_evaluations : STD_LOGIC;
signal is_error_position : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
constant error_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal message_data_in : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal message_data_q : STD_LOGIC_VECTOR((((number_of_pipelines)*(pipeline_size+1)) - 1) downto 0);
signal message_data_out : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal poly_reg_polynomial_coefficients_d : STD_LOGIC_VECTOR(((gf_2_m)*(pipeline_size) - 1) downto 0);
constant ctr_address_polynomial_rst_value : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0) := std_logic_vector(to_unsigned(number_of_errors, size_number_of_errors+1));
signal synd_reg_polynomial_coefficients_d : STD_LOGIC_VECTOR(((gf_2_m)*(pipeline_size) - 1) downto 0);
constant ctr_address_syndrome_rst_value : STD_LOGIC_VECTOR ((size_number_of_errors) downto 0) := std_logic_vector(to_unsigned(number_of_errors*2, size_number_of_errors+1));
begin
pipelines : for I in 0 to (number_of_pipelines - 1) generate
square_I : entity work.pow2_gf_2_m(Software_POLYNOMIAL)
Generic Map(gf_2_m => gf_2_m)
Port Map(
a => value_h(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
o => square_value_h(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)))
);
pipeline_I : pipeline_polynomial_calc_v4
Generic Map (
gf_2_m => gf_2_m,
size => pipeline_size
)
Port Map(
value_x => value_x(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
value_polynomial => pipeline_value_polynomial((((gf_2_m)*pipeline_size*(I + 1)) - 1) downto (((gf_2_m)*pipeline_size*(I)))),
value_acc => pipeline_value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
reg_x_rst => reg_x_rst,
mode_polynomial_syndrome => mode_polynomial_syndrome,
clk => clk,
new_value_acc => value_evaluated(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
new_value_syndrome => new_value_intermediate_syndrome((((gf_2_m)*pipeline_size*(I + 1)) - 1) downto (((gf_2_m)*pipeline_size*(I))))
);
pipeline_value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) when (reg_first_values_q(0) = '0') else
square_value_h(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) when (mode_polynomial_syndrome = '1' and value_message(I) = '1') else
first_acc;
shift_message : shift_register_nbits
Generic Map(size => pipeline_size + 1)
Port Map(
data_in => message_data_in(I),
clk => clk,
ce => '1',
q => message_data_q(((pipeline_size + 1)*(I + 1) - 1) downto ((pipeline_size + 1)*(I))),
data_out => message_data_out(I)
);
is_error_position(I) <= '1' when value_evaluated(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) = error_value else '0';
message_data_in(I) <= value_message(I);
new_value_message(I) <= (not message_data_out(I)) when is_error_position(I) = '1' else message_data_out(I);
value_error(I) <= is_error_position(I);
first_case : if I = 0 generate
pipeline_value_polynomial((((gf_2_m)*pipeline_size*(I+1)) - 1) downto (((gf_2_m)*pipeline_size*I))) <= reg_polynomial_coefficients_q;
end generate first_case;
other_cases : if I > 0 generate
pipeline_value_polynomial((((gf_2_m)*pipeline_size*(I+1)) - 1) downto (((gf_2_m)*pipeline_size*I))) <= new_value_intermediate_syndrome((((gf_2_m)*pipeline_size*(I)) - 1) downto (((gf_2_m)*pipeline_size*(I - 1)))) when mode_polynomial_syndrome = '1' else
reg_polynomial_coefficients_q;
end generate other_cases;
end generate;
polynomial : for I in 0 to (pipeline_size - 1) generate
reg_polynomial_coefficients_I : register_nbits
Generic Map (size => gf_2_m)
Port Map(
d => reg_polynomial_coefficients_d(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
clk => clk,
ce => reg_polynomial_coefficients_ce(I),
q => reg_polynomial_coefficients_q(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)))
);
reg_x_rst_I : register_rst_nbits
Generic Map (size => 1)
Port Map(
d => reg_x_rst_d,
clk => clk,
ce => reg_x_rst_ce(I),
rst => reg_x_rst_rst,
rst_value => "0",
q => reg_x_rst_q(I downto I)
);
reg_x_rst(I) <= (reg_x_rst_q(I) or (limit_polynomial_degree and shift_polynomial_ce_q(I)));
poly_reg_polynomial_coefficients_d(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= coefficient_zero when (last_coefficients = '1') else
value_polynomial;
first_case : if I = 0 generate
synd_reg_polynomial_coefficients_d(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= coefficient_zero when (shift_polynomial_ce_q(I) = '1') else
new_value_intermediate_syndrome(((number_of_pipelines-1)*(pipeline_size)*(gf_2_m)+(gf_2_m)*(I + 1) - 1) downto ((number_of_pipelines-1)*(pipeline_size)*(gf_2_m)+(gf_2_m)*(I)));
end generate first_case;
other_cases : if I > 0 generate
synd_reg_polynomial_coefficients_d(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= coefficient_zero when (shift_polynomial_ce_q(I) = '1') else
reg_polynomial_coefficients_q(((gf_2_m)*(I) - 1) downto ((gf_2_m)*(I - 1))) when (shift_syndrome_mode_q(I) = '0') else
new_value_intermediate_syndrome(((number_of_pipelines-1)*(pipeline_size)*(gf_2_m)+(gf_2_m)*(I + 1) - 1) downto ((number_of_pipelines-1)*(pipeline_size)*(gf_2_m)+(gf_2_m)*(I)));
end generate other_cases;
reg_polynomial_coefficients_ce(I) <= ((shift_syndrome_mode_q(I)) or finalize_syndrome) when mode_polynomial_syndrome = '1' else
shift_polynomial_ce_q(I);
end generate;
controller : controller_polynomial_syndrome_computing
Port Map(
clk => clk,
rst => rst,
mode_polynomial_syndrome => mode_polynomial_syndrome,
last_load_x_values => last_load_x_values,
last_store_x_values => last_store_x_values,
limit_polynomial_degree => limit_polynomial_degree,
last_syndrome_value => last_syndrome_value,
final_syndrome_evaluation => final_syndrome_evaluation,
pipeline_ready => pipeline_ready,
evaluation_data_in => evaluation_data_in,
reg_write_enable_rst => reg_write_enable_rst,
ctr_load_x_address_ce => ctr_load_x_address_ce,
ctr_load_x_address_rst => ctr_load_x_address_rst,
ctr_store_x_address_ce => ctr_store_x_address_ce,
ctr_store_x_address_rst => ctr_store_x_address_rst,
reg_first_values_ce => reg_first_values_ce,
reg_first_values_rst => reg_first_values_rst,
ctr_address_polynomial_syndrome_ce => ctr_address_polynomial_syndrome_ce,
ctr_address_polynomial_syndrome_load => ctr_address_polynomial_syndrome_load,
ctr_address_polynomial_syndrome_increment_decrement => ctr_address_polynomial_syndrome_increment_decrement,
ctr_address_polynomial_syndrome_rst => ctr_address_polynomial_syndrome_rst,
reg_x_rst_rst => reg_x_rst_rst,
reg_store_temporary_syndrome_ce => reg_store_temporary_syndrome_ce,
reg_final_syndrome_evaluation_ce => reg_final_syndrome_evaluation_ce,
reg_final_syndrome_evaluation_rst => reg_final_syndrome_evaluation_rst,
shift_polynomial_ce_ce => shift_polynomial_ce_ce,
shift_polynomial_ce_rst => shift_polynomial_ce_rst,
shift_syndrome_mode_data_in => shift_syndrome_mode_data_in,
shift_syndrome_mode_rst => shift_syndrome_mode_rst,
write_enable_new_value_syndrome => write_enable_new_value_syndrome,
finalize_syndrome => finalize_syndrome,
last_coefficients => last_coefficients,
computation_finalized => computation_finalized
);
shift_polynomial_ce : shift_register_rst_nbits
Generic Map(
size => pipeline_size + 1
)
Port Map(
data_in => shift_polynomial_ce_data_in,
clk => clk,
ce => shift_polynomial_ce_ce,
rst => shift_polynomial_ce_rst,
rst_value => shift_polynomial_ce_rst_value,
q => shift_polynomial_ce_q,
data_out => shift_polynomial_ce_data_in
);
shift_syndrome_mode : shift_register_rst_nbits
Generic Map(
size => pipeline_size
)
Port Map(
data_in => shift_syndrome_mode_data_in,
clk => clk,
ce => '1',
rst => shift_syndrome_mode_rst,
rst_value => shift_syndrome_mode_rst_value,
q => shift_syndrome_mode_q,
data_out => open
);
evaluation : shift_register_nbits
Generic Map(
size => pipeline_size
)
Port Map(
data_in => evaluation_data_in,
clk => clk,
ce => '1',
q => open,
data_out => evaluation_data_out
);
reg_write_enable : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_write_enable_d,
clk => clk,
ce => '1',
rst => reg_write_enable_rst,
rst_value => reg_write_enable_rst_value,
q => reg_write_enable_q
);
ctr_address_polynomial_syndrome : counter_increment_decrement_load_rst_nbits
Generic Map(
size => size_number_of_errors+1,
increment_value => 1,
decrement_value => 1
)
Port Map(
d => ctr_address_polynomial_syndrome_d,
clk => clk,
ce => ctr_address_polynomial_syndrome_ce,
load => ctr_address_polynomial_syndrome_load,
increment_decrement => ctr_address_polynomial_syndrome_increment_decrement,
rst => ctr_address_polynomial_syndrome_rst,
rst_value => ctr_address_polynomial_syndrome_rst_value,
q => ctr_address_polynomial_syndrome_q
);
reg_store_temporary_syndrome : register_nbits
Generic Map(
size => size_number_of_errors+1
)
Port Map(
d => reg_store_temporary_syndrome_d,
clk => clk,
ce => reg_store_temporary_syndrome_ce,
q => reg_store_temporary_syndrome_q
);
ctr_load_x_address : counter_rst_nbits
Generic Map(
size => size_number_of_support_elements,
increment_value => number_of_pipelines
)
Port Map(
clk => clk,
ce => ctr_load_x_address_ce,
rst => ctr_load_x_address_rst,
rst_value => ctr_load_x_address_rst_value,
q => ctr_load_x_address_q
);
ctr_store_x_address : counter_rst_nbits
Generic Map(
size => size_number_of_support_elements,
increment_value => number_of_pipelines
)
Port Map(
clk => clk,
ce => ctr_store_x_address_ce,
rst => ctr_store_x_address_rst,
rst_value => ctr_store_x_address_rst_value,
q => ctr_store_x_address_q
);
reg_first_values : register_rst_nbits
Generic Map(size => 1)
Port Map(
d => "0",
clk => clk,
ce => reg_first_values_ce,
rst => reg_first_values_rst,
rst_value => reg_first_values_rst_value,
q => reg_first_values_q
);
reg_final_syndrome_evaluation : register_rst_nbits
Generic Map(size => 1)
Port Map(
d => "1",
clk => clk,
ce => reg_final_syndrome_evaluation_ce,
rst => reg_final_syndrome_evaluation_rst,
rst_value => reg_final_syndrome_evaluation_rst_value,
q => reg_final_syndrome_evaluation_q
);
new_value_acc <= value_evaluated;
reg_x_rst_d(0) <= limit_polynomial_degree;
reg_x_rst_ce <= shift_polynomial_ce_q((pipeline_size - 1) downto 0);
reg_polynomial_coefficients_d <= synd_reg_polynomial_coefficients_d when mode_polynomial_syndrome = '1' else
poly_reg_polynomial_coefficients_d;
ctr_address_polynomial_syndrome_rst_value <= ctr_address_syndrome_rst_value when mode_polynomial_syndrome = '1' else
ctr_address_polynomial_rst_value;
address_value_polynomial <= ctr_address_polynomial_syndrome_q((size_number_of_errors - 1) downto 0);
address_value_x <= ctr_load_x_address_q;
address_value_acc <= ctr_load_x_address_q;
address_value_message <= ctr_load_x_address_q;
address_new_value_acc <= ctr_store_x_address_q;
address_new_value_message <= ctr_store_x_address_q;
address_value_error <= ctr_store_x_address_q;
address_new_value_syndrome <= ctr_address_polynomial_syndrome_q;
reg_store_temporary_syndrome_d <= ctr_address_polynomial_syndrome_q;
ctr_address_polynomial_syndrome_d <= reg_store_temporary_syndrome_q;
pipeline_ready <= shift_polynomial_ce_q(pipeline_size-1);
limit_polynomial_degree <= '1' when (signed(ctr_address_polynomial_syndrome_q) = to_signed(-1, ctr_address_polynomial_syndrome_q'length)) else '0';
last_syndrome_value <= '1' when (ctr_address_polynomial_syndrome_q = std_logic_vector(to_signed(0, ctr_address_polynomial_syndrome_q'Length))) else '0';
last_evaluations <= limit_polynomial_degree and shift_polynomial_ce_q(pipeline_size);
final_syndrome_evaluation <= reg_final_syndrome_evaluation_q(0);
reg_write_enable_d(0) <= evaluation_data_out;
new_value_syndrome <= reg_polynomial_coefficients_q(((gf_2_m)*(pipeline_size) - 1) downto ((gf_2_m)*(pipeline_size - 1)));
write_enable_new_value_acc <= reg_write_enable_q(0);
write_enable_new_value_message <= '0' when mode_polynomial_syndrome = '1' else
reg_write_enable_q(0) and last_evaluations;
write_enable_value_error <= '0' when mode_polynomial_syndrome = '1' else
reg_write_enable_q(0) and last_evaluations;
last_load_x_values <= '1' when ctr_load_x_address_q = std_logic_vector(to_unsigned(((number_of_support_elements - 1)/number_of_pipelines)*number_of_pipelines, ctr_load_x_address_q'Length)) else '0';
last_store_x_values <= '1' when ctr_store_x_address_q = std_logic_vector(to_unsigned(((number_of_support_elements - 1)/number_of_pipelines)*number_of_pipelines, ctr_load_x_address_q'Length)) else '0';
end RTL;
|
bsd-2-clause
|
92afb10d4b3a4127e6c6b77473a8b93b
| 0.680318 | 2.942113 | false | false | false | false |
rajvinjamuri/ECE385_VHDL
|
keyboard_processor.vhd
| 1 | 3,052 |
---------------------------------------------------------------------------
-- keyboard_processor.vhd --
-- Sai Koppula --
-- 3-13 --
-- --
-- Purpose/Description --
-- Takes in ps2data and outputs the right make codes --
-- --
-- --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
-- --
-- --
--Updates --
-- --
-- >changed A/B_out to just A/B --
-- >condensed signals for clearer reading --
-- >changed re buses from 7 downto 0 to 10 downto 0 --
-- >changed name of data bits in for uniformity --
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity keyboard_processor is
Port ( Clk : in std_logic; --takes in modified clock
Status : in std_logic_vector(1 downto 0);
ps2data : in std_logic; --from keyboard
Reset : in std_logic;
SR_Out : out std_logic_vector(10 downto 0); --one code
PR_Out : out std_logic_vector(10 downto 0) --prev code
);
end keyboard_processor;
architecture Behavioral of keyboard_processor is
component reg_unit is
Port ( Clk : in std_logic;
ClrSR, ClrPR : in std_logic;
D_In : in std_logic_vector(10 downto 0);
SR_In : in std_logic;
Ld_SR : in std_logic;
Ld_PR : in std_logic;
Shift_En : in std_logic;
SR_out : out std_logic;
PR_out : out std_logic;
SR : out std_logic_vector(10 downto 0);
PR : out std_logic_vector(10 downto 0));
end component reg_unit;
signal ClrSR, ClrPR : std_logic;
signal SR_In, Ld_SR, Ld_PR, Shift_En : std_logic;
signal D_In : std_logic_vector(10 downto 0);
signal nreset, data: std_logic;
begin
nreset <= Reset;
data <= ps2data;
Registers : reg_unit
port map( Clk => Clk,
ClrSR => ClrSR,
ClrPR => ClrPR,
D_In => D_In,
SR_In => SR_In,
Ld_SR => Ld_SR,
Ld_PR => Ld_PR,
Shift_En => Shift_En,
SR => SR_Out,
PR => PR_Out);
pass_Data: process(Status, data) --shift data from prev code into another register
begin
if (Status = "10")
then Shift_En <= '1';
else Shift_En <= '0';
end if;
ClrSR <= nreset;
ClrPr <= nreset;
SR_In <= data;
Ld_SR <= '0';
Ld_PR <= '0';
end process;
end Behavioral;
|
mit
|
70ce33d79cdf2b7ff4e4ee7b108e6e7b
| 0.42464 | 4.042384 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/angle_step_applier/angle_step_applier_tb.vhd
| 1 | 3,287 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity angle_step_applier_tb is
end entity;
architecture angle_step_applier_tb_arq of angle_step_applier_tb is
signal x_in: std_logic_vector(31 downto 0) := (others => '0');
signal y_in: std_logic_vector(31 downto 0) := (others => '0');
signal z_in: std_logic_vector(31 downto 0) := (others => '0');
signal step_index : integer := 0;
signal x_out : std_logic_vector(31 downto 0) := (others => '0');
signal y_out : std_logic_vector(31 downto 0) := (others => '0');
signal z_out : std_logic_vector(31 downto 0) := (others => '0');
component angle_step_applier is
generic(TOTAL_BITS: integer := 32);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
z_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
step_index : in integer := 0;
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
z_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
for angle_step_applier_0 : angle_step_applier use entity work.angle_step_applier;
begin
angle_step_applier_0 : angle_step_applier
port map(
x_in => x_in,
y_in => y_in,
z_in => z_in,
step_index => step_index,
x_out => x_out,
y_out => y_out,
z_out => z_out
);
process
type pattern_type is record
si : integer;
xi : std_logic_vector(31 downto 0);
yi : std_logic_vector(31 downto 0);
zi : std_logic_vector(31 downto 0);
xo : std_logic_vector(31 downto 0);
yo : std_logic_vector(31 downto 0);
zo : std_logic_vector(31 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
(0,
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000001011010000000000000000"),
(0,
"00000000000000010000000000000000",
"00000000000000000000000000000000",
"00000000001011010000000000000000",
"00000000000000010000000000000000",
"00000000000000010000000000000000",
"00000000000000000000000000000000"),
(0,
"00000000000000010000000000000000",
"00000000000000010000000000000000",
"00000000001011010000000000000000",
"00000000000000000000000000000000",
"00000000000000100000000000000000",
"00000000000000000000000000000000")
);
begin
for i in patterns'range loop
-- Set the inputs.
x_in <= patterns(i).xi;
y_in <= patterns(i).yi;
z_in <= patterns(i).zi;
step_index <= patterns(i).si;
wait for 1 ns;
assert patterns(i).xo = x_out report "BAD X, GOT: " & integer'image(to_integer(signed(x_out)));
assert patterns(i).yo = y_out report "BAD Y, GOT: " & integer'image(to_integer(signed(y_out)));
assert patterns(i).zo = z_out report "BAD Z, GOT: " & integer'image(to_integer(signed(z_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
f837225c3f3f954c2e6194c6cf539485
| 0.662915 | 3.248024 | false | false | false | false |
hitomi2500/wasca
|
obsolete/fpga_firmware_V2/ip_repo/ABus2AXI4Lite/hdl/ABus2AXI4Lite_Master_AXI.vhd
| 2 | 32,981 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ABus2AXI4Lite_Master_AXI is
generic (
C_MASTER_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"40000000";
C_MASTER_AXI_ADDR_WIDTH : integer := 32;
C_MASTER_AXI_DATA_WIDTH : integer := 32
);
port (
-- Users to add ports here
abus_address : in std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
abus_data_in : in std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_data_out : out std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_data_direction : out std_logic := '0'; -- .direction
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_wait : out std_logic := '1'; -- .waitrequest
abus_wait_direction : out std_logic := '0'; -- .direction
abus_irq : out std_logic := '0'; -- .interrupt
abus_irq_direction : out std_logic := '0'; -- .direction
abus_reset : in std_logic := '0'; -- .saturn_reset
-- User ports ends
-- Do not modify the ports beyond this line
-- AXI clock signal
MASTER_AXI_ACLK : in std_logic;
-- AXI active low reset signal
MASTER_AXI_ARESETN : in std_logic;
-- Master Interface Write Address Channel ports. Write address (issued by master)
MASTER_AXI_AWADDR : out std_logic_vector(C_MASTER_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type.
-- This signal indicates the privilege and security level of the transaction,
-- and whether the transaction is a data access or an instruction access.
MASTER_AXI_AWPROT : out std_logic_vector(2 downto 0);
-- Write address valid.
-- This signal indicates that the master signaling valid write address and control information.
MASTER_AXI_AWVALID : out std_logic;
-- Write address ready.
-- This signal indicates that the slave is ready to accept an address and associated control signals.
MASTER_AXI_AWREADY : in std_logic;
-- Master Interface Write Data Channel ports. Write data (issued by master)
MASTER_AXI_WDATA : out std_logic_vector(C_MASTER_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes.
-- This signal indicates which byte lanes hold valid data.
-- There is one write strobe bit for each eight bits of the write data bus.
MASTER_AXI_WSTRB : out std_logic_vector(C_MASTER_AXI_DATA_WIDTH/8-1 downto 0);
-- Write valid. This signal indicates that valid write data and strobes are available.
MASTER_AXI_WVALID : out std_logic;
-- Write ready. This signal indicates that the slave can accept the write data.
MASTER_AXI_WREADY : in std_logic;
-- Master Interface Write Response Channel ports.
-- This signal indicates the status of the write transaction.
MASTER_AXI_BRESP : in std_logic_vector(1 downto 0);
-- Write response valid.
-- This signal indicates that the channel is signaling a valid write response
MASTER_AXI_BVALID : in std_logic;
-- Response ready. This signal indicates that the master can accept a write response.
MASTER_AXI_BREADY : out std_logic;
-- Master Interface Read Address Channel ports. Read address (issued by master)
MASTER_AXI_ARADDR : out std_logic_vector(C_MASTER_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type.
-- This signal indicates the privilege and security level of the transaction,
-- and whether the transaction is a data access or an instruction access.
MASTER_AXI_ARPROT : out std_logic_vector(2 downto 0);
-- Read address valid.
-- This signal indicates that the channel is signaling valid read address and control information.
MASTER_AXI_ARVALID : out std_logic;
-- Read address ready.
-- This signal indicates that the slave is ready to accept an address and associated control signals.
MASTER_AXI_ARREADY : in std_logic;
-- Master Interface Read Data Channel ports. Read data (issued by slave)
MASTER_AXI_RDATA : in std_logic_vector(C_MASTER_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the read transfer.
MASTER_AXI_RRESP : in std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is signaling the required read data.
MASTER_AXI_RVALID : in std_logic;
-- Read ready. This signal indicates that the master can accept the read data and response information.
MASTER_AXI_RREADY : out std_logic
);
end ABus2AXI4Lite_Master_AXI;
architecture implementation of ABus2AXI4Lite_Master_AXI is
-- function called clogb2 that returns an integer which has the
-- value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
-- AXI4LITE signals
--write address valid
signal axi_awvalid : std_logic:='0';
--write data valid
signal axi_wvalid : std_logic:='0';
--read address valid
signal axi_arvalid : std_logic:='0';
--read data acceptance
signal axi_rready : std_logic:='0';
--write response acceptance
signal axi_bready : std_logic:='0';
--write address
signal axi_awaddr : std_logic_vector(C_MASTER_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
--write data
signal axi_wdata : std_logic_vector(C_MASTER_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
--read addresss
signal axi_araddr : std_logic_vector(C_MASTER_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
--write strobe
signal axi_wstrb : std_logic_vector(C_MASTER_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0');
signal write_resp_error : std_logic_vector(2 downto 0) := (others => '0');
--abus input signals latches are non required,latching is done on upper level
--signal abus_data_in_p1 : std_logic_vector(15 downto 0) := (others => '0');
--signal abus_data_in_p2 : std_logic_vector(15 downto 0) := (others => '0');
signal abus_chipselect_p1 : std_logic_vector(2 downto 0) := (others => '0');
--signal abus_chipselect_p2 : std_logic_vector(2 downto 0) := (others => '0');
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0');
signal abus_chipselect_end_pulse : std_logic_vector(2 downto 0) := (others => '0');
signal abus_read_p1 : std_logic := '0';
--signal abus_read_p2 : std_logic := '0';
signal abus_read_pulse : std_logic := '0';
signal abus_read_end_pulse : std_logic := '0';
signal abus_write_p1 : std_logic_vector(1 downto 0) := (others => '0');
--signal abus_write_p2 : std_logic_vector(1 downto 0) := (others => '0');
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0');
signal abus_write_end_pulse : std_logic_vector(1 downto 0) := (others => '0');
signal abus_reset_p1 : std_logic := '0';
--signal abus_reset_p2 : std_logic := '0';
signal abus_reset_pulse : std_logic := '0';
signal abus_start_pulse : std_logic := '0';
signal abus_burst_pulse : std_logic := '0';
signal abus_burst_end_pulse : std_logic := '0';
signal abus_transaction_active : std_logic := '0';
signal abus_transaction_write : std_logic := '0';
signal abus_transaction_read : std_logic := '0';
TYPE write_address_state_type IS (AW_IDLE,AW_WRITE);
SIGNAL write_address_state : write_address_state_type := AW_IDLE;
TYPE write_data_state_type IS (W_IDLE,W_WRITE);
SIGNAL write_data_state : write_data_state_type := W_IDLE;
TYPE read_address_state_type IS (AR_IDLE,AR_WRITE);
SIGNAL read_address_state : read_address_state_type := AR_IDLE;
TYPE read_data_state_type IS (R_IDLE,R_WRITE);
SIGNAL read_data_state : read_data_state_type := R_IDLE;
signal abus_write_a1 : std_logic := '0';
signal abus_read_a1 : std_logic := '0';
signal abus_read_cache_address : std_logic_vector(23 downto 0) := (others => '0');
signal abus_read_cache_data : std_logic_vector(31 downto 0) := (others => '0');
signal mode_32M_ROM : std_logic := '0';
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
TYPE wasca_mem_region_type IS (REGION_ID,REGION_ROM,REGION_RAM,REGION_BOOTCODE,REGION_REGISTERS,REGION_FILESYSTEM);
SIGNAL wasca_region : wasca_mem_region_type := REGION_BOOTCODE;
signal abus_data_out_regs : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_out_axi : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_out_filesystem : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_out_bootrom : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_out_we_regs : std_logic := '0';
signal abus_data_out_we_axi : std_logic := '0';
signal abus_data_out_we_filesystem : std_logic := '0';
signal abus_data_out_we_bootrom : std_logic := '0';
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
begin
--some magic - deciding mode from MODE rerister input
-- process(MASTER_AXI_ACLK)
-- begin
-- if (rising_edge (MASTER_AXI_ACLK)) then
-- REG_MODE
-- end if;
-- end process;
--Adding the offset address to the base addr of the slave
MASTER_AXI_AWADDR <= std_logic_vector (unsigned(C_MASTER_TARGET_SLAVE_BASE_ADDR) + unsigned(axi_awaddr));
--AXI 4 write data
MASTER_AXI_WDATA <= axi_wdata;
MASTER_AXI_AWPROT <= "000";
MASTER_AXI_AWVALID <= axi_awvalid;
--Write Data(W)
MASTER_AXI_WVALID <= axi_wvalid;
--Set all byte strobes in this example
MASTER_AXI_WSTRB <= axi_wstrb;
--Write Response (B)
MASTER_AXI_BREADY <= axi_bready;
--Read Address (AR)
MASTER_AXI_ARADDR <= std_logic_vector(unsigned(C_MASTER_TARGET_SLAVE_BASE_ADDR) + unsigned(axi_araddr));
MASTER_AXI_ARVALID <= axi_arvalid;
MASTER_AXI_ARPROT <= "001";
--Read and Read Response (R)
MASTER_AXI_RREADY <= axi_rready;
--latch abus input signals, pulses are generated on the falling edge
--abus_data_in_p1 <= abus_data_in when rising_edge(MASTER_AXI_ACLK);
--abus_data_in_p2 <= abus_data_in_p1 when rising_edge(MASTER_AXI_ACLK);
abus_chipselect_p1 <= abus_chipselect when rising_edge(MASTER_AXI_ACLK);
--abus_chipselect_p2 <= abus_chipselect_p1 when rising_edge(MASTER_AXI_ACLK);
abus_chipselect_pulse <= abus_chipselect_p1 and not abus_chipselect;
abus_chipselect_end_pulse <= abus_chipselect and not abus_chipselect_p1;
abus_read_p1 <= abus_read when rising_edge(MASTER_AXI_ACLK);
--abus_read_p2 <= abus_read_p1 when rising_edge(MASTER_AXI_ACLK);
abus_read_pulse <= abus_read_p1 and not abus_read;
abus_read_end_pulse <= abus_read and not abus_read_p1;
abus_write_p1 <= abus_write when rising_edge(MASTER_AXI_ACLK);
--abus_write_p2 <= abus_write_p1 when rising_edge(MASTER_AXI_ACLK);
abus_write_pulse <= abus_write_p1 and not abus_write;
abus_write_end_pulse <= abus_write and not abus_write_p1;
abus_reset_p1 <= abus_reset when rising_edge(MASTER_AXI_ACLK);
--abus_reset_p2 <= abus_reset_p1 when rising_edge(MASTER_AXI_ACLK);
abus_reset_pulse <= abus_reset_p1 and not abus_reset;
--transaction state and control signals
abus_start_pulse <= (not abus_transaction_active) and (abus_read_pulse or abus_write_pulse(0) or abus_write_pulse(1) or abus_chipselect_pulse(0)
or abus_chipselect_pulse(1));-- or abus_chipselect_pulse(2) --we don't serve ABus CS2 transactions yet
abus_burst_pulse <= (abus_transaction_active) and (abus_read_pulse or abus_write_pulse(0) or abus_write_pulse(1) or abus_chipselect_pulse(0)
or abus_chipselect_pulse(1)) -- or abus_chipselect_pulse(2) --we don't serve ABus CS2 transactions yet
and (abus_transaction_read or abus_transaction_write);
abus_burst_end_pulse <= ( ((abus_read_end_pulse or abus_write_end_pulse(0) or abus_write_end_pulse(1)) and not
(abus_chipselect_p1(0) and abus_chipselect_p1(1) and abus_chipselect_p1(2)) )
or ((abus_chipselect_end_pulse(0) or abus_chipselect_end_pulse(1)) and not(abus_read and abus_write(0) and abus_write(1))) );
-- or abus_chipselect_end_pulse(2) --we don't serve ABus CS2 transactions yet
--detect if current address is applied to registers (not memory)
process(MASTER_AXI_ACLK)
begin
if (rising_edge (MASTER_AXI_ACLK)) then
if abus_chipselect_p1(0) = '0' then
--cs0 region
if mode_32M_ROM = '1' then
--32M ROM mode, map cs0 completely into ROM space
wasca_region <= REGION_ROM;
else
--other modes
if abus_address(25 downto 12) = "11"&X"FFE" then
wasca_region <= REGION_FILESYSTEM;
elsif abus_address(25 downto 12) = "11"&X"FFF" then
wasca_region <= REGION_REGISTERS;
elsif abus_address(25 downto 16) = "11"&X"FF" then
wasca_region <= REGION_ROM; --this area is reserved, mapping as ROM for now
elsif wasca_mode = MODE_RAM_1M or wasca_mode = MODE_RAM_4M then
wasca_region <= REGION_RAM; --mapping whole cs0 onto RAM, although only up to 4MB (32MBit) will be used
elsif wasca_mode = MODE_INIT then
wasca_region <= REGION_BOOTCODE; --map all the cs0 range to BRAM with bootcode
else
wasca_region <= REGION_ROM; --everything else is mapped as ROM
end if;
end if;
elsif abus_chipselect_p1(1) = '0' then
--cs1 region
if abus_address(25 downto 2) = X"FFFF" then
--id register
wasca_region <= REGION_ID;
elsif mode_32M_ROM = '1' then
--32M ROM mode, wasca's control is mapped here
if abus_address(25 downto 12) = "11"&X"FFE" then
wasca_region <= REGION_FILESYSTEM;
elsif abus_address(25 downto 12) = "11"&X"FFF" then
wasca_region <= REGION_REGISTERS;
elsif abus_address(25 downto 16) = "11"&X"FF" then
wasca_region <= REGION_ROM; --this area is reserved, mapping as ROM for now
end if;
else
wasca_region <= REGION_RAM; --should be used only by power meme emulation
end if;
end if;
end if;
end process;
process(MASTER_AXI_ACLK)
begin
if (rising_edge (MASTER_AXI_ACLK)) then
if abus_start_pulse = '1' then
abus_transaction_active <= '1';
elsif abus_read_p1 = '1' and abus_write_p1 = "11" and abus_chipselect_p1 = "111" then
abus_transaction_active <= '0';
end if;
end if;
end process;
process(MASTER_AXI_ACLK)
begin
if (rising_edge (MASTER_AXI_ACLK)) then
if abus_read_pulse = '1' then
abus_transaction_read <= '1';
elsif abus_read_p1 = '1' and abus_chipselect_p1 = "111" then
abus_transaction_read <= '0';
end if;
end if;
end process;
process(MASTER_AXI_ACLK)
begin
if (rising_edge (MASTER_AXI_ACLK)) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
abus_transaction_write <= '1';
elsif abus_write_p1 = "11" and abus_chipselect_p1 = "111" then
abus_transaction_write <= '0';
end if;
end if;
end process;
----------------------
--Write Address Channel
----------------------
--every write access is treated as independent, even within burst
--for each access we provide new address to axi
--since axi is 32 bit, and abus is 16 bit, address a1 is latched to provide axi strobe signal
process(MASTER_AXI_ACLK)
begin
if (rising_edge (MASTER_AXI_ACLK)) then
if (MASTER_AXI_ARESETN = '0' ) then
axi_awvalid <= '0';
write_address_state <= AW_IDLE;
else
case write_address_state is
when AW_IDLE =>
if (abus_write_pulse(0)='1' or abus_write_pulse(1)='1')
or (abus_burst_pulse = '1' and abus_transaction_write = '1') then
--axi transactions whould be only issued on RAM and ROM regions
if wasca_region = REGION_RAM or wasca_region = REGION_ROM then
write_address_state <= AW_WRITE;
axi_awvalid <= '1';
axi_awaddr <= std_logic_vector(resize(unsigned(abus_address(25 downto 2)&"00"),C_MASTER_AXI_ADDR_WIDTH));
abus_write_a1 <= abus_address(1);
end if;
end if;
when AW_WRITE =>
if MASTER_AXI_AWREADY = '1' then
write_address_state <= AW_IDLE;
axi_awvalid <= '0';
end if;
end case;
end if;
end if;
end process;
----------------------
--Write Data Channel
----------------------
--Writes are done independently for every strobe within burst
--Abus is 16-bit bus with per-byte write latches
--So we either write 16 of 8 bits onto 32-bit AXI
--When axi_wvalid arrives, address should be already stable
--so we can safely assume that abus_registers signal is already multiplexed
process(MASTER_AXI_ACLK)
begin
if (rising_edge (MASTER_AXI_ACLK)) then
if (MASTER_AXI_ARESETN = '0' ) then
axi_wvalid <= '0';
write_data_state <= W_IDLE;
else
case write_data_state is
when W_IDLE =>
if axi_awvalid = '1' then --t's a memory access, not registers
write_data_state <= W_WRITE;
axi_wvalid <= '1';
axi_wdata <= abus_data_in&abus_data_in;
if abus_write_a1='1' then
axi_wstrb <= "00"¬(abus_write_p1(1))¬(abus_write_p1(0));
else
axi_wstrb <= not(abus_write_p1(1))¬(abus_write_p1(0))&"00";
end if;
end if;
when W_WRITE =>
if (MASTER_AXI_WREADY = '1' and axi_wvalid = '1') then
--Data accepted by interconnect/slave (issue of MASTER_AXI_WREADY by slave)
write_data_state <= W_IDLE;
axi_wvalid <= '0';
axi_wstrb <= "0000";
end if;
end case;
end if;
end if;
end process;
------------------------------
--Write Response (B) Channel
------------------------------
--To prevent issuing another write while previous one is not ready, we reset ABUS wait signal only when bresp arrives
process(MASTER_AXI_ACLK)
begin
if (rising_edge (MASTER_AXI_ACLK)) then
if (MASTER_AXI_ARESETN = '0') then
axi_bready <= '0';
else
if (MASTER_AXI_BVALID = '1' and axi_bready = '0') then
-- accept/acknowledge bresp with axi_bready by the master
-- when MASTER_AXI_BVALID is asserted by slave
axi_bready <= '1';
elsif (axi_bready = '1') then
-- deassert after one clock cycle
axi_bready <= '0';
write_resp_error <= (axi_bready & MASTER_AXI_BVALID & MASTER_AXI_BRESP(1));
end if;
end if;
end if;
end process;
------------------------------
--Read Address Channel
------------------------------
--read is a bit tricky
--to prevent axi over-read we can cache every 32-bit location (further caching is up to axi infrastructure)
--so basically we remember last accessed 32-bit address, and if if is the same as was before, we do not issue
--another read
process(MASTER_AXI_ACLK)
begin
if (rising_edge (MASTER_AXI_ACLK)) then
if (MASTER_AXI_ARESETN = '0' ) then
axi_arvalid <= '0';
read_address_state <= AR_IDLE;
abus_read_cache_address <= X"FAFAFA";
else
case read_address_state is
when AR_IDLE =>
if abus_read_pulse='1'
or (abus_burst_pulse = '1' and abus_transaction_read = '1') then
--axi transactions whould be only issued on RAM and ROM regions
if wasca_region = REGION_RAM or wasca_region = REGION_ROM then
if ( abus_address(25 downto 2) = abus_read_cache_address) then
null; --do nothing on cached access
else
read_address_state <= AR_WRITE;
axi_arvalid <= '1';
axi_araddr <= std_logic_vector(resize(unsigned(abus_address(25 downto 2)&"00"),C_MASTER_AXI_ADDR_WIDTH));
abus_read_a1 <= abus_address(1);
abus_read_cache_address <= abus_address(25 downto 2);
end if;
end if;
end if;
when AR_WRITE =>
if MASTER_AXI_ARREADY = '1' then
read_address_state <= AR_IDLE;
axi_arvalid <= '0';
end if;
end case;
end if;
end if;
end process;
----------------------------------
--Read Data (and Response) Channel
----------------------------------
--The Read Data channel returns the results of the read request
--The master will accept the read data by asserting axi_rready
--when there is a valid read data available.
--While not necessary per spec, it is advisable to reset READY signals in
--case of differing reset latencies between master/slave.
process(MASTER_AXI_ACLK)
begin
if (rising_edge (MASTER_AXI_ACLK)) then
if MASTER_AXI_ARESETN = '0' then
axi_rready <= '1';
else
if (MASTER_AXI_RVALID = '1' and axi_rready = '0') then
-- accept/acknowledge rdata/rresp with axi_rready by the master
-- when MASTER_AXI_RVALID is asserted by slave
axi_rready <= '1';
elsif (axi_rready = '1') then
abus_read_cache_data <= MASTER_AXI_RDATA;
-- deassert after one clock cycle
axi_rready <= '0';
end if;
end if;
end if;
end process;
----------------------------------
--Registers write
----------------------------------
process(MASTER_AXI_ACLK)
begin
if (rising_edge (MASTER_AXI_ACLK)) then
if (abus_write_pulse(0)='1' or abus_write_pulse(1)='1')
or (abus_burst_pulse = '1' and abus_transaction_write = '1') then
if wasca_region = REGION_REGISTERS then
case abus_address(11 downto 0) is
when X"FF4" =>
REG_MODE <= abus_data_in;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
----------------------------------
--Registers read
----------------------------------
process(MASTER_AXI_ACLK)
begin
if (rising_edge (MASTER_AXI_ACLK)) then
if abus_read_pulse='1' or (abus_burst_pulse = '1' and abus_transaction_write = '1') then
if wasca_region = REGION_REGISTERS then
case abus_address(11 downto 0) is
when X"FF0" =>
abus_data_out_regs <= REG_PCNTR;
when X"FF2" =>
abus_data_out_regs <= REG_STATUS;
when X"FF4" =>
abus_data_out_regs <= REG_MODE;
when X"FF6" =>
abus_data_out_regs <= REG_HWVER;
when X"FF8" =>
abus_data_out_regs <= REG_SWVER;
when X"FFA" =>
abus_data_out_regs <= X"646f";
when X"FFC" =>
abus_data_out_regs <= X"6F64";
when X"FFE" =>
abus_data_out_regs <= X"6C5C";
when others =>
abus_data_out_regs <= X"DEAF";
end case;
end if;
end if;
end if;
end process;
--output cached data to abus according to abus address
abus_data_out_axi <= abus_read_cache_data(15 downto 0) when abus_address(1) = '1' else
abus_read_cache_data(31 downto 16);
----------------------------------
--Abus data output enable
----------------------------------
process(MASTER_AXI_ACLK)
begin
if (rising_edge (MASTER_AXI_ACLK)) then
if MASTER_AXI_ARESETN = '0' then
abus_data_direction <= '0';
else
if abus_read_pulse='1'
or (abus_burst_pulse = '1' and abus_transaction_read = '1') then
abus_data_direction <= '1';
elsif abus_burst_end_pulse = '1' then
abus_data_direction <= '0';
end if;
end if;
end if;
end process;
----------------------------------
--Address demux for registers and other splecial locations
----------------------------------
----------------------------------
--Boot ROM
----------------------------------
end implementation;
|
gpl-2.0
|
e00b24896251fde77583eb6a9f74f15b
| 0.461599 | 4.489654 | false | false | false | false |
laurivosandi/hdl
|
arithmetic/src/booth4.vhd
| 1 | 1,659 |
library ieee;
use ieee.std_logic_1164.all;
-- Consider multiplication of a and b:
-- d is radix-4 booth encoded bits of digit of the multiplier b
-- a is the bit vector of multiplicand
-- n is the 2's complement of a
-- m is the multiplication of d and a
entity booth4 is
Port ( a : in std_logic_vector (15 downto 0);
d : in std_logic_vector (2 downto 0);
m : out std_logic_vector (16 downto 0));
end booth4;
architecture behavioral of booth4 is
component cla is
generic (N : integer := 16);
port (
a : in std_logic_vector (N-1 downto 0);
b : in std_logic_vector (N-1 downto 0);
ci : in std_logic;
s : out std_logic_vector (N-1 downto 0);
co : out std_logic
);
end component;
-- Signals for two's complement
signal ai : std_logic_vector(15 DOWNTO 0);
signal an : std_logic_vector(15 DOWNTO 0);
begin
-- Two's complement of a,
-- assuming that of course compiler takes care of
-- getting rid of duplicate two's complement circuits
ai <= not a;
cla_stage: cla generic map (N=>16) port map(
a => ai, b => "0000000000000001", ci => '0', s => an
);
-- Dummy lookup table
with d select
m <=a(15) & a when "001", -- Sign expanded addition
a(15) & a when "010", -- Same as previous
a & "0" when "011", -- Add double
an & "0" when "100", -- Subtract double
an(15) & an when "101", -- Sign expanded subtraction
an(15) & an when "110",
"00000000000000000" when others;
end behavioral;
|
mit
|
7621f030673f207c1220fdd5bf4c942b
| 0.568415 | 3.711409 | false | false | false | false |
rodrigoazs/-7-5-Reed-Solomon
|
code/write_error.vhd
| 1 | 1,224 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity write_error is
port (clock: in std_logic;
message: in std_logic_vector(14 downto 0)
);
end write_error;
architecture behavioral of write_error is
signal counter_write: std_logic_vector(2 downto 0)
:= "000";
begin
process(clock)
file file_pointer : text;
variable line_content : string(1 to 15);
variable line_num : line;
variable i,j : integer := 0;
variable char : character:='0';
begin
if (clock'event and clock='1') then
counter_write <= counter_write + 1;
if(i = 0 and counter_write = "111") then
file_open(file_pointer,"write_error.txt",write_mode);
end if;
if (counter_write = "111") then
for j in 0 to 14 loop
if(message(j) = '0') then
line_content(15-j) := '0';
else
line_content(15-j) := '1';
end if;
end loop;
write(line_num,line_content);
writeline (file_pointer,line_num);
i := 1;
counter_write <= "001";
end if;
end if;
end process;
end behavioral;
|
mit
|
75e00dbb81cad87c79d20d97c683af0d
| 0.671569 | 3.098734 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/components/char_rom.vhd
| 1 | 4,241 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Char_ROM is
generic(
N: integer:= 6;
M: integer:= 3;
W: integer:= 8
);
port(
char_address: in std_logic_vector(5 downto 0);
font_row, font_col: in std_logic_vector(M-1 downto 0);
rom_out: out std_logic
);
end;
architecture p of Char_ROM is
subtype tipoLinea is std_logic_vector(0 to W-1);
type char is array(0 to W-1) of tipoLinea;
constant A: char:= (
"00011000",
"00111100",
"01100110",
"01100110",
"01111110",
"01100110",
"01100110",
"00000000"
);
constant B: char:= (
"01111100",
"01100110",
"01100110",
"01111100",
"01100110",
"01100110",
"01111100",
"00000000"
);
constant C: char:= (
"00111110",
"01100011",
"01100000",
"01100000",
"01100000",
"01100011",
"00111110",
"00000000"
);
constant D: char:= (
"01111100",
"01100110",
"01100011",
"01100011",
"01100011",
"01100110",
"01111100",
"00000000"
);
constant E: char:= (
"01111110",
"01100000",
"01100000",
"01111000",
"01100000",
"01100000",
"01111110",
"00000000"
);
constant F: char:= (
"01111110",
"01100000",
"01100000",
"01111000",
"01100000",
"01100000",
"01100000",
"00000000"
);
constant G: char:= (
"00111100",
"01100010",
"01100000",
"01101110",
"01100110",
"01100110",
"00111100",
"00000000"
);
constant H: char:= (
"01100110",
"01100110",
"01100110",
"01111110",
"01100110",
"01100110",
"01100110",
"00000000"
);
constant N_Char: char:= (
"01100110",
"01100110",
"01110110",
"01110110",
"01101110",
"01101110",
"01100110",
"00000000"
);
constant O: char:= (
"00111100",
"01100110",
"01100110",
"01100110",
"01100110",
"01100110",
"00111100",
"00000000"
);
constant Err: char:= (
"00000000",
"01111110",
"01111110",
"01100110",
"01100110",
"01111110",
"01111110",
"00000000"
);
type memo is array(0 to 255) of tipoLinea;
signal RAM: memo:= (
0 => A(0), 1 => A(1), 2 => A(2), 3 => A(3), 4 => A(4), 5 => A(5), 6 => A(6), 7 => A(7),
8 => B(0), 9 => B(1), 10 => B(2), 11 => B(3), 12 => B(4), 13 => B(5), 14 => B(6), 15 => B(7),
16 => C(0), 17 => C(1), 18 => C(2), 19 => C(3), 20 => C(4), 21 => C(5), 22 => C(6), 23 => C(7),
24 => D(0), 25 => D(1), 26 => D(2), 27 => D(3), 28 => D(4), 29 => D(5), 30 => D(6), 31 => D(7),
32 => E(0), 33 => E(1), 34 => E(2), 35 => E(3), 36 => E(4), 37 => E(5), 38 => E(6), 39 => E(7),
40 => F(0), 41 => F(1), 42 => F(2), 43 => F(3), 44 => F(4), 45 => F(5), 46 => F(6), 47 => F(7),
48 => G(0), 49 => G(1), 50 => G(2), 51 => G(3), 52 => G(4), 53 => G(5), 54 => G(6), 55 => G(7),
56 => H(0), 57 => H(1), 58 => H(2), 59 => H(3), 60 => H(4), 61 => H(5), 62 => H(6), 63 => H(7),
64 => N_Char(0), 65 => N_Char(1), 66 => N_Char(2), 67 => N_Char(3), 68 => N_Char(4), 69 => N_Char(5), 70 => N_Char(6), 71 => N_Char(7),
72 => O(0), 73 => O(1), 74 => O(2), 75 => O(3), 76 => O(4), 77 => O(5), 78 => O(6), 79 => O(7),
80 => Err(0), 81 => Err(1), 82 => Err(2), 83 => Err(3), 84 => Err(4), 85 => Err(5), 86 => Err(6), 87 => Err(7),
88 to 255 => "00000000"
);
signal char_addr_aux: std_logic_vector(8 downto 0);
begin
char_addr_aux <= char_address & font_row;
rom_out <= RAM(conv_integer(char_addr_aux))(conv_integer(font_col));
end;
|
gpl-3.0
|
4e9ac7303cc40c2b5abaddcbbc32994f
| 0.412403 | 2.992943 | false | false | false | false |
rodrigoazs/-7-5-Reed-Solomon
|
code/full_adder.vhd
| 1 | 1,029 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity fa is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum1 : out std_logic;
sum0 : out std_logic);
end fa;
architecture Behavioral of fa is
signal s1 : std_logic;
signal s2 : std_logic;
signal s3 : std_logic;
signal s4 : std_logic;
signal s5 : std_logic;
signal s6 : std_logic;
signal s7 : std_logic;
signal s8 : std_logic;
begin
s1 <= (not a) and b and c;
s2 <= a and (not b) and c;
s3 <= a and b and (not c);
s4 <= a and b and c;
sum1 <= s1 or s2 or s3 or s4;
s5 <= (not a) and b and (not c);
s6 <= a and (not b) and (not c);
s7 <= (not a) and (not b) and c;
s8 <= a and b and c;
sum0 <= s5 or s6 or s7 or s8;
end Behavioral;
|
mit
|
2c0299e3f797302cc730b93c1e898ccf
| 0.601555 | 2.842541 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/TP1-Contador/anode_selector_tb.vhd
| 1 | 911 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity anode_selector_tb is
end;
architecture anode_selector_func of anode_selector_tb is
signal signal_in_a : std_logic:='0';
signal signal_in_b : std_logic:='0';
signal signal_in : std_logic_vector (1 downto 0);
signal signal_out : std_logic_vector (3 downto 0);
component anode_selector is
port(
selector_in : in std_logic_vector (1 downto 0);
selector_out : out std_logic_vector (3 downto 0)
);
end component;
begin
signal_in_a <= not signal_in_a after 10 ns;
signal_in_b <= not signal_in_b after 20 ns;
signal_in(0) <= signal_in_a;
signal_in(1) <= signal_in_b;
anode_selectorMap: anode_selector
port map(
selector_in => signal_in,
selector_out => signal_out
);
end anode_selector_func;
|
gpl-3.0
|
d3e893485965000098b9314856a4420a
| 0.607025 | 3.152249 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/controller_syndrome_calculator_2_pipe_v3_master.vhd
| 1 | 28,556 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Syndrome_Calculator_2_pipe_v3_master
-- Module Name: Controller_Syndrome_Calculator_2_pipe_v3_master
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st step in Goppa Code Decoding.
--
-- This circuit is the state machine that controls the syndrome_calculator_n_pipe_v3
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_syndrome_calculator_2_pipe_v3_master is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
almost_units_ready : in STD_LOGIC;
empty_units : in STD_LOGIC;
limit_ctr_codeword_q : in STD_LOGIC;
limit_ctr_syndrome_q : in STD_LOGIC;
reg_first_syndrome_q : in STD_LOGIC_VECTOR(0 downto 0);
reg_codeword_q : in STD_LOGIC_VECTOR(0 downto 0);
start_calculation : in STD_LOGIC;
slaves_finished : in STD_LOGIC;
ready_calculation : out STD_LOGIC;
finished_calculation : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
control_units_ce : out STD_LOGIC;
control_units_rst : out STD_LOGIC;
int_reg_L_ce : out STD_LOGIC;
square_h : out STD_LOGIC;
int_reg_h_ce : out STD_LOGIC;
int_reg_h_rst : out STD_LOGIC;
int_sel_reg_h : out STD_LOGIC;
reg_load_L_ce : out STD_LOGIC;
reg_load_h_ce : out STD_LOGIC;
reg_load_h_rst : out STD_LOGIC;
reg_load_syndrome_ce : out STD_LOGIC;
reg_load_syndrome_rst : out STD_LOGIC;
reg_new_value_syndrome_ce : out STD_LOGIC;
reg_new_value_master_syndrome_ce : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_first_syndrome_ce : out STD_LOGIC;
reg_first_syndrome_rst : out STD_LOGIC;
ctr_load_address_syndrome_ce : out STD_LOGIC;
ctr_load_address_syndrome_rst : out STD_LOGIC;
ctr_store_address_syndrome_ce : out STD_LOGIC;
ctr_store_address_syndrome_rst : out STD_LOGIC;
ctr_load_address_codeword_ce : out STD_LOGIC;
ctr_load_address_codeword_rst : out STD_LOGIC;
reg_load_limit_codeword_rst : out STD_LOGIC;
reg_load_limit_codeword_ce : out STD_LOGIC;
reg_calc_limit_codeword_rst : out STD_LOGIC;
reg_calc_limit_codeword_ce : out STD_LOGIC
);
end controller_syndrome_calculator_2_pipe_v3_master;
architecture Behavioral of controller_syndrome_calculator_2_pipe_v3_master is
type State is (reset, load_counters, prepare_values, load_values, jump_codeword, clear_remaining_units, wait_for_other_units, prepare_synd, prepare_synd_2, prepare_synd_3, prepare_synd_4, load_store_synd, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, limit_ctr_codeword_q, limit_ctr_syndrome_q, reg_first_syndrome_q, reg_codeword_q, almost_units_ready, empty_units, start_calculation, slaves_finished)
begin
case (actual_state) is
when reset =>
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '1';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
reg_load_limit_codeword_rst <= '1';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '1';
reg_calc_limit_codeword_ce <= '0';
when load_counters =>
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
reg_load_limit_codeword_rst <= '1';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '1';
reg_calc_limit_codeword_ce <= '0';
when prepare_values =>
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
when load_values =>
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '0';
reg_codeword_ce <= '1';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
when jump_codeword =>
if(reg_codeword_q(0) = '1') then
if(almost_units_ready = '1' ) then
ready_calculation <= '1';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '1';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '0';
reg_codeword_ce <= '1';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
elsif(limit_ctr_codeword_q = '1') then
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '1';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '0';
reg_codeword_ce <= '1';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
else
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '1';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '0';
reg_codeword_ce <= '1';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
end if;
elsif(limit_ctr_codeword_q = '1') then
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '0';
reg_codeword_ce <= '1';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
else
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '0';
reg_codeword_ce <= '1';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
end if;
when clear_remaining_units =>
if(almost_units_ready = '1') then
ready_calculation <= '1';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '1';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
else
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '1';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
end if;
when wait_for_other_units =>
ready_calculation <= '1';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
when prepare_synd =>
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '1';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '1';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
when prepare_synd_2 =>
if(reg_first_syndrome_q(0) = '1') then
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
else
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '1';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
end if;
when prepare_synd_3 =>
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '1';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
when prepare_synd_4 =>
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '1';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_new_value_master_syndrome_ce <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
when load_store_synd =>
if(limit_ctr_syndrome_q = '1') then
if(limit_ctr_codeword_q = '1') then
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '1';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '1';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_new_value_master_syndrome_ce <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '1';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
else
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '1';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '1';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_new_value_master_syndrome_ce <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '1';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
end if;
else
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '1';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '1';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_new_value_master_syndrome_ce <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
ctr_store_address_syndrome_ce <= '1';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
end if;
when final =>
ready_calculation <= '1';
finished_calculation <= '1';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
reg_load_limit_codeword_rst <= '1';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '1';
reg_calc_limit_codeword_ce <= '0';
when others =>
ready_calculation <= '0';
finished_calculation <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '1';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_new_value_master_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
ctr_store_address_syndrome_ce <= '0';
ctr_store_address_syndrome_rst <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
reg_load_limit_codeword_rst <= '1';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '1';
reg_calc_limit_codeword_ce <= '0';
end case;
end process;
NewState: process (actual_state, limit_ctr_codeword_q, limit_ctr_syndrome_q, reg_first_syndrome_q, reg_codeword_q, almost_units_ready, empty_units, start_calculation, slaves_finished)
begin
case (actual_state) is
when reset =>
next_state <= load_counters;
when load_counters =>
next_state <= prepare_values;
when prepare_values =>
next_state <= load_values;
when load_values =>
next_state <= jump_codeword;
when jump_codeword =>
if(reg_codeword_q(0) = '1') then
if(almost_units_ready = '1') then
if(start_calculation = '1') then
next_state <= prepare_synd;
else
next_state <= wait_for_other_units;
end if;
elsif(limit_ctr_codeword_q = '1') then
next_state <= clear_remaining_units;
else
next_state <= jump_codeword;
end if;
elsif(limit_ctr_codeword_q = '1') then
if(empty_units = '1' and slaves_finished = '1') then
next_state <= final;
else
next_state <= clear_remaining_units;
end if;
else
next_state <= jump_codeword;
end if;
when clear_remaining_units =>
if(almost_units_ready = '1') then
if(start_calculation = '1') then
next_state <= prepare_synd;
else
next_state <= wait_for_other_units;
end if;
else
next_state <= clear_remaining_units;
end if;
when wait_for_other_units =>
if(start_calculation = '1') then
next_state <= prepare_synd;
else
next_state <= wait_for_other_units;
end if;
when prepare_synd =>
next_state <= prepare_synd_2;
when prepare_synd_2 =>
next_state <= prepare_synd_3;
when prepare_synd_3 =>
next_state <= prepare_synd_4;
when prepare_synd_4 =>
next_state <= load_store_synd;
when load_store_synd =>
if(limit_ctr_syndrome_q = '1') then
if(limit_ctr_codeword_q = '1') then
if(slaves_finished = '1') then
next_state <= final;
else
next_state <= clear_remaining_units;
end if;
else
next_state <= jump_codeword;
end if;
else
next_state <= load_store_synd;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
e53d93c8c65b54a397482c07e724ca38
| 0.576902 | 2.628982 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/finite_field/pow2_gf_2_m_Software.vhd
| 1 | 7,715 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Pow2_GF_2_M
-- Module Name: Pow2_GF_2_M
-- Project Name: GF_2_M Arithmetic
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit computes the power of 2 of a GF(2^m) element.
-- The strategy for this computation is pure combinatorial.
-- This version is for primitive polynomials present on the software implementation
-- of binary Goppa codes.
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit.
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
architecture Software_POLYNOMIAL of pow2_gf_2_m is
begin
GF_2_1 : if gf_2_m = 1 generate
o <= a;
end generate;
GF_2_2 : if gf_2_m = 2 generate -- x^2 + x^1 + 1
o(0) <= a(1) xor a(0);
o(1) <= a(1);
end generate;
GF_2_3 : if gf_2_m = 3 generate -- x^3 + x^1 + 1
o(0) <= a(0);
o(1) <= a(2);
o(2) <= a(1) xor a(2);
end generate;
GF_2_4 : if gf_2_m = 4 generate -- x^4 + x^1 + 1
o(0) <= a(0) xor a(2);
o(1) <= a(2);
o(2) <= a(1) xor a(3);
o(3) <= a(3);
end generate;
GF_2_5 : if gf_2_m = 5 generate -- x^5 + x^2 + 1
o(0) <= a(0) xor a(4);
o(1) <= a(3);
o(2) <= a(1) xor a(4);
o(3) <= a(4) xor a(3);
o(4) <= a(2);
end generate;
GF_2_6 : if gf_2_m = 6 generate -- x^6 + x^1 + 1
o(0) <= a(0) xor a(3);
o(1) <= a(3);
o(2) <= a(1) xor a(4);
o(3) <= a(4);
o(4) <= a(2) xor a(5);
o(5) <= a(5);
end generate;
GF_2_7 : if gf_2_m = 7 generate -- x^7 + x^1 + 1
o(0) <= a(0);
o(1) <= a(4);
o(2) <= a(1) xor a(4);
o(3) <= a(5);
o(4) <= a(2) xor a(5);
o(5) <= a(6);
o(6) <= a(3) xor a(6);
end generate;
GF_2_8 : if gf_2_m = 8 generate -- x^8 + x^4 + x^3 + x^2 + 1
o(0) <= a(0) xor a(4) xor a(6) xor a(7);
o(1) <= a(7);
o(2) <= a(1) xor a(4) xor a(5) xor a(6);
o(3) <= a(4) xor a(6);
o(4) <= a(2) xor a(4) xor a(5) xor a(7);
o(5) <= a(5);
o(6) <= a(3) xor a(5) xor a(6);
o(7) <= a(6);
end generate;
GF_2_9 : if gf_2_m = 9 generate -- x^9 + x^4 + 1
o(0) <= a(0) xor a(7);
o(1) <= a(5);
o(2) <= a(1) xor a(8);
o(3) <= a(6);
o(4) <= a(2) xor a(7);
o(5) <= a(5) xor a(7);
o(6) <= a(3) xor a(8);
o(7) <= a(6) xor a(8);
o(8) <= a(4);
end generate;
GF_2_10 : if gf_2_m = 10 generate -- x^10 + x^3 + 1
o(0) <= a(0) xor a(5);
o(1) <= a(9);
o(2) <= a(1) xor a(6);
o(3) <= a(5);
o(4) <= a(2) xor a(7) xor a(9);
o(5) <= a(6);
o(6) <= a(3) xor a(8);
o(7) <= a(7);
o(8) <= a(4) xor a(9);
o(9) <= a(8);
end generate;
GF_2_11 : if gf_2_m = 11 generate -- x^11 + x^2 + 1
o(0) <= a(0) xor a(10);
o(1) <= a(6);
o(2) <= a(1) xor a(10);
o(3) <= a(7) xor a(6);
o(4) <= a(2);
o(5) <= a(8) xor a(7);
o(6) <= a(3);
o(7) <= a(9) xor a(8);
o(8) <= a(4);
o(9) <= a(10) xor a(9);
o(10) <= a(5);
end generate;
GF_2_12 : if gf_2_m = 12 generate -- x^12 + x^6 + x^4 + x^1 + 1
o(0) <= a(0) xor a(6) xor a(9) xor a(10);
o(1) <= a(6) xor a(9) xor a(10);
o(2) <= a(1) xor a(7) xor a(10) xor a(11);
o(3) <= a(7) xor a(10) xor a(11);
o(4) <= a(2) xor a(6) xor a(8) xor a(9) xor a(10) xor a(11);
o(5) <= a(8) xor a(11);
o(6) <= a(3) xor a(6) xor a(7) xor a(11);
o(7) <= a(9);
o(8) <= a(4) xor a(7) xor a(8);
o(9) <= a(10);
o(10) <= a(5) xor a(8) xor a(9);
o(11) <= a(11);
end generate;
GF_2_13 : if gf_2_m = 13 generate -- x^13 + x^4 + x^3 + x^1 + 1
o(0) <= a(0) xor a(11);
o(1) <= a(7) xor a(11) xor a(12);
o(2) <= a(1) xor a(7);
o(3) <= a(8) xor a(11) xor a(12);
o(4) <= a(2) xor a(7) xor a(8) xor a(11) xor a(12);
o(5) <= a(7) xor a(9);
o(6) <= a(3) xor a(8) xor a(9) xor a(12);
o(7) <= a(8) xor a(10);
o(8) <= a(4) xor a(9) xor a(10);
o(9) <= a(11) xor a(9);
o(10) <= a(5) xor a(10) xor a(11);
o(11) <= a(10) xor a(12);
o(12) <= a(6) xor a(11) xor a(12);
end generate;
GF_2_14 : if gf_2_m = 14 generate -- x^14 + x^5 + x^3 + x^1 + 1
o(0) <= a(0) xor a(7);
o(1) <= a(7) xor a(12) xor a(13);
o(2) <= a(1) xor a(8) xor a(12) xor a(13);
o(3) <= a(7) xor a(8) xor a(13);
o(4) <= a(2) xor a(9) xor a(12);
o(5) <= a(7) xor a(8) xor a(9);
o(6) <= a(3) xor a(10) xor a(12);
o(7) <= a(8) xor a(9) xor a(10);
o(8) <= a(4) xor a(11) xor a(13);
o(9) <= a(9) xor a(10) xor a(11);
o(10) <= a(5) xor a(12);
o(11) <= a(10) xor a(11) xor a(12);
o(12) <= a(6) xor a(13);
o(13) <= a(11) xor a(12) xor a(13);
end generate;
GF_2_15 : if gf_2_m = 15 generate -- x^15 + x^1 + 1
o(0) <= a(0);
o(1) <= a(8);
o(2) <= a(1) xor a(8);
o(3) <= a(9);
o(4) <= a(2) xor a(9);
o(5) <= a(10);
o(6) <= a(3) xor a(10);
o(7) <= a(11);
o(8) <= a(4) xor a(11);
o(9) <= a(12);
o(10) <= a(5) xor a(12);
o(11) <= a(13);
o(12) <= a(6) xor a(13);
o(13) <= a(14);
o(14) <= a(7) xor a(14);
end generate;
GF_2_16 : if gf_2_m = 16 generate -- x^16 + x^5 + x^3 + x^2 + 1
o(0) <= a(0) xor a(8) xor a(15);
o(1) <= a(14) xor a(15);
o(2) <= a(1) xor a(8) xor a(9) xor a(15);
o(3) <= a(8) xor a(14) xor a(15);
o(4) <= a(2) xor a(9) xor a(10) xor a(14) xor a(15);
o(5) <= a(8) xor a(9);
o(6) <= a(3) xor a(10) xor a(11) xor a(14);
o(7) <= a(9) xor a(10);
o(8) <= a(4) xor a(11) xor a(12) xor a(15);
o(9) <= a(10) xor a(11);
o(10) <= a(5) xor a(12) xor a(13);
o(11) <= a(11) xor a(12);
o(12) <= a(6) xor a(13) xor a(14);
o(13) <= a(12) xor a(13);
o(14) <= a(7) xor a(14) xor a(15);
o(15) <= a(13) xor a(14);
end generate;
GF_2_17 : if gf_2_m = 17 generate -- x^17 + x^3 + 1
o(0) <= a(0);
o(1) <= a(9) xor a(16);
o(2) <= a(1);
o(3) <= a(10);
o(4) <= a(2) xor a(9) xor a(16);
o(5) <= a(11);
o(6) <= a(3) xor a(10);
o(7) <= a(12);
o(8) <= a(4) xor a(11);
o(9) <= a(13);
o(10) <= a(5) xor a(12);
o(11) <= a(14);
o(12) <= a(6) xor a(13);
o(13) <= a(15);
o(14) <= a(7) xor a(14);
o(15) <= a(16);
o(16) <= a(8) xor a(15);
end generate;
GF_2_18 : if gf_2_m = 18 generate -- x^18 + x^7 + 1
o(0) <= a(0) xor a(9);
o(1) <= a(15);
o(2) <= a(1) xor a(10);
o(3) <= a(16);
o(4) <= a(2) xor a(11);
o(5) <= a(17);
o(6) <= a(3) xor a(12);
o(7) <= a(9);
o(8) <= a(4) xor a(13) xor a(15);
o(9) <= a(10);
o(10) <= a(5) xor a(14) xor a(16);
o(11) <= a(11);
o(12) <= a(6) xor a(15) xor a(17);
o(13) <= a(12);
o(14) <= a(7) xor a(16);
o(15) <= a(13);
o(16) <= a(8) xor a(17);
o(17) <= a(14);
end generate;
GF_2_19 : if gf_2_m = 19 generate -- x^19 + x^5 + x^2 + x^1 + 1
o(0) <= a(0) xor a(18);
o(1) <= a(10) xor a(17) xor a(18);
o(2) <= a(1) xor a(10) xor a(17) xor a(18);
o(3) <= a(10) xor a(11) xor a(17) xor a(18);
o(4) <= a(2) xor a(11) xor a(18);
o(5) <= a(11) xor a(12);
o(6) <= a(3) xor a(10) xor a(12) xor a(17);
o(7) <= a(12) xor a(13);
o(8) <= a(4) xor a(11) xor a(13) xor a(18);
o(9) <= a(13) xor a(14);
o(10) <= a(5) xor a(12) xor a(14);
o(11) <= a(14) xor a(15);
o(12) <= a(6) xor a(13) xor a(15);
o(13) <= a(15) xor a(16);
o(14) <= a(7) xor a(14) xor a(16);
o(15) <= a(16) xor a(17);
o(16) <= a(8) xor a(15) xor a(17);
o(17) <= a(17) xor a(18);
o(18) <= a(9) xor a(16) xor a(18);
end generate;
GF_2_20 : if gf_2_m = 20 generate -- x^20 + x^3 + 1
o(0) <= a(0) xor a(10);
o(1) <= a(19);
o(2) <= a(1) xor a(11);
o(3) <= a(10);
o(4) <= a(2) xor a(12) xor a(19);
o(5) <= a(11);
o(6) <= a(3) xor a(13);
o(7) <= a(12);
o(8) <= a(4) xor a(14);
o(9) <= a(13);
o(10) <= a(5) xor a(15);
o(11) <= a(14);
o(12) <= a(6) xor a(16);
o(13) <= a(15);
o(14) <= a(7) xor a(17);
o(15) <= a(16);
o(16) <= a(8) xor a(18);
o(17) <= a(17);
o(18) <= a(9) xor a(19);
o(19) <= a(18);
end generate;
end Software_POLYNOMIAL;
|
bsd-2-clause
|
16fbe84c7917bb2af05fd7b633cf799f
| 0.453532 | 1.794186 | false | false | false | false |
ruygargar/LCSE_lab
|
uc/uc.vhd
| 1 | 11,158 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06:17:01 01/26/2014
-- Design Name:
-- Module Name: uc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.PIC_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uc is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
ROM_Data : in STD_LOGIC_VECTOR (11 downto 0);
ROM_Address : out STD_LOGIC_VECTOR (11 downto 0);
Databus : out STD_LOGIC_VECTOR (7 downto 0);
RAM_Address : out STD_LOGIC_VECTOR (7 downto 0);
RAM_CS : out STD_LOGIC;
RAM_WE : out STD_LOGIC;
RAM_OE : out STD_LOGIC;
ALU_Operation : out alu_op;
ALU_Index : in STD_LOGIC_VECTOR (7 downto 0);
Flag_Z : in STD_LOGIC;
Flag_C : in STD_LOGIC;
Flag_N : in STD_LOGIC;
Flag_E : in STD_LOGIC;
DMA_RQ : in STD_LOGIC;
DMA_ACK : out STD_LOGIC;
Send : out STD_LOGIC;
DMA_Ready : in STD_LOGIC);
end uc;
architecture pipelined of uc is
-- Fetch signals.
signal I_data_i, I_add_i : std_logic_vector(11 downto 0);
signal PC_reg, PC_in : std_logic_vector(11 downto 0);
signal IR_reg : std_logic_vector(11 downto 0);
signal LT_latch : std_logic_vector(11 downto 0);
signal LN : std_logic; -- Literal Needed.
signal PC1, jump_address, no_jump_address : std_logic_vector(11 downto 0);
signal jumping : std_logic;
-- Decode signals.
signal Jump_reg, Jump_in : std_logic;
signal JumpC_reg, JumpC_in : std_logic;
signal A_op_reg, A_op_in : alu_op;
signal D_ctl_reg, D_ctl_in : std_logic_vector(2 downto 0); -- CS&WE&OE
signal D_valid_reg, D_valid_in : std_logic;
signal IDN : std_logic; -- Index Needed.
signal D_data_reg, D_data_in : std_logic_vector(7 downto 0);
signal D_add_aux, D_add_aux_id : std_logic_vector(7 downto 0);
signal D_add_reg, D_add_in : std_logic_vector(7 downto 0);
signal jump_add_reg : std_logic_vector(11 downto 0);
signal start_send_reg, start_send_in : std_logic;
-- Execute signals.
signal NVD_reg : std_logic; -- Not Valid Data.
signal BR : std_logic; -- Buses Released.
signal RAM_Address_i : std_logic_vector(7 downto 0);
signal RAM_CS_i : std_logic;
signal RAM_WE_i : std_logic;
signal RAM_OE_i : std_logic;
-- FSM Send/DMA_RQ Controller.
type FSM_state is (idle, SND_free, SND_wait, SND_catch,
DMA_wait_non_jumpc, DMA_free, DMA_wait, DMA_catch);
signal FSM_now, FSM_next : FSM_state;
signal FF_enable : std_logic;
begin
-- Fetch Stage Logic:
I_data_i <= ROM_Data;
ROM_Address <= I_add_i;
-- -- Program Counter and Instruction Register.
process(Clk, Reset, PC_in, I_data_i)
begin
if Reset = '0' then
PC_reg <= X"000";
IR_reg <= X"000";
elsif Clk'event and Clk = '1' then
if FF_enable = '1' then
PC_reg <= PC_in;
IR_reg <= I_data_i;
end if;
end if;
end process;
-- -- Latch used to store the literal in 2-word instructions.
process(Clk, LN, I_data_i, LT_latch)
begin
if Clk = '1' and LN = '1' then
LT_latch <= I_data_i;
else
LT_latch <= LT_latch;
end if;
end process;
-- -- Next PC and ROM Address combinational logic.
PC1 <= PC_reg + X"001";
jump_address <= jump_add_reg;
no_jump_address <= PC1 when (Clk = '0' and LN = '1')
else PC_reg;
I_add_i <= jump_address when jumping = '1'
else no_jump_address;
PC_in <= I_add_i + X"001";
-- Decode Stage Logic:
-- -- Internal Pipeline's Registers.
process(Clk, Reset)
begin
if Reset = '0' then
A_op_reg <= nop;
Jump_reg <= '0';
JumpC_reg <= '0';
D_ctl_reg <= "000";
D_valid_reg <= '0';
D_data_reg <= X"00";
D_add_reg <= X"00";
jump_add_reg <= X"000";
start_send_reg <= '0';
elsif Clk'event and Clk = '1' then
if FF_enable = '1' then
A_op_reg <= A_op_in;
Jump_reg <= Jump_in;
JumpC_reg <= JumpC_in;
D_ctl_reg <= D_ctl_in;
D_valid_reg <= D_valid_in;
D_data_reg <= D_data_in;
D_add_reg <= D_add_in;
jump_add_reg <= LT_latch;
start_send_reg <= start_send_in;
end if;
end if;
end process;
-- -- Combinational Microinstruction Decoder.
process(IR_reg)
begin
A_op_in <= nop;
Jump_in <= '0';
JumpC_in <= '0';
D_ctl_in <= "000";
D_valid_in <= '1';
LN <= '0';
IDN <= '0';
start_send_in <= '0';
case IR_reg(7 downto 6) is
when TYPE_1 =>
case IR_reg(5 downto 0) is
when ALU_ADD => A_op_in <= op_add;
when ALU_SUB => A_op_in <= op_sub;
when ALU_SHIFTL => A_op_in <= op_shiftl;
when ALU_SHIFTR => A_op_in <= op_shiftr;
when ALU_AND => A_op_in <= op_and;
when ALU_OR => A_op_in <= op_or;
when ALU_XOR => A_op_in <= op_xor;
when ALU_CMPE => A_op_in <= op_cmpe;
when ALU_CMPG => A_op_in <= op_cmpg;
when ALU_CMPL => A_op_in <= op_cmpl;
when ALU_ASCII2BIN => A_op_in <= op_ascii2bin;
when ALU_BIN2ASCII => A_op_in <= op_bin2ascii;
when others =>
end case;
when TYPE_2 =>
LN <= '1';
case IR_reg(5 downto 0) is
when JMP_UNCOND => Jump_in <= '1';
when JMP_COND => JumpC_in <= '1';
when others =>
end case;
when TYPE_3 =>
case IR_reg(5 downto 0) is
-- LD entre registros.
when LD&SRC_ACC&DST_A => A_op_in <= op_mvacc2a;
when LD&SRC_ACC&DST_B => A_op_in <= op_mvacc2b;
when LD&SRC_ACC&DST_INDX => A_op_in <= op_mvacc2id;
-- LD en registros desde dato literal.
when LD&SRC_CONSTANT&DST_A => A_op_in <= op_lda;
LN <= '1';
when LD&SRC_CONSTANT&DST_B => A_op_in <= op_ldb;
LN <= '1';
when LD&SRC_CONSTANT&DST_ACC => A_op_in <= op_ldacc;
LN <= '1';
when LD&SRC_CONSTANT&DST_INDX => A_op_in <= op_ldid;
LN <= '1';
-- LD en registros desde dirección de memoria literal.
when LD&SRC_MEM&DST_A => A_op_in <= op_lda;
LN <= '1';
D_valid_in <= '0';
D_ctl_in <= "101";
when LD&SRC_MEM&DST_B => A_op_in <= op_ldb;
LN <= '1';
D_valid_in <= '0';
D_ctl_in <= "101";
when LD&SRC_MEM&DST_ACC => A_op_in <= op_ldacc;
LN <= '1';
D_valid_in <= '0';
D_ctl_in <= "101";
when LD&SRC_MEM&DST_INDX => A_op_in <= op_ldid;
LN <= '1';
D_valid_in <= '0';
D_ctl_in <= "101";
-- LD en registros desde dirección de memoria indexada.
when LD&SRC_INDXD_MEM&DST_A => A_op_in <= op_lda;
LN <= '1';
IDN <= '1';
D_valid_in <= '0';
D_ctl_in <= "101";
when LD&SRC_INDXD_MEM&DST_B => A_op_in <= op_ldb;
LN <= '1';
IDN <= '1';
D_valid_in <= '0';
D_ctl_in <= "101";
when LD&SRC_INDXD_MEM&DST_ACC => A_op_in <= op_ldacc;
LN <= '1';
IDN <= '1';
D_valid_in <= '0';
D_ctl_in <= "101";
when LD&SRC_INDXD_MEM&DST_INDX => A_op_in <= op_ldid;
LN <= '1';
IDN <= '1';
D_valid_in <= '0';
D_ctl_in <= "101";
-- WR desde registro ACC en memoria literal.
when WR&SRC_ACC&DST_MEM => A_op_in <= op_oeacc;
LN <= '1';
D_valid_in <= '0';
D_ctl_in <= "110";
-- WR desde registro ACC en memoria indexada.
when WR&SRC_ACC&DST_INDXD_MEM => A_op_in <= op_oeacc;
LN <= '1';
IDN <= '1';
D_valid_in <= '0';
D_ctl_in <= "110";
when others =>
end case;
when TYPE_4 =>
start_send_in <= '1';
when others =>
end case;
end process;
D_data_in <= LT_latch(7 downto 0);
D_add_aux <= LT_latch(7 downto 0);
D_add_aux_id <= LT_latch(7 downto 0) + ALU_Index;
D_add_in <= D_add_aux_id when IDN = '1'
else D_add_aux;
-- Execute Stage Logic:
jumping <= Jump_reg or (JumpC_reg and Flag_Z);
process(Clk, Reset)
begin
if Reset = '0' then
NVD_reg <= '0';
elsif Clk'event and Clk = '1' then
if FF_enable = '1' then
NVD_reg <= jumping;
end if;
end if;
end process;
ALU_Operation <= A_op_reg when NVD_reg = '0'
else nop;
Databus <= D_data_reg(7 downto 0) when (D_valid_reg = '1' and BR = '0')
else (others => 'Z');
RAM_Address_i <= D_add_reg;
RAM_Address <= RAM_Address_i when BR = '0'
else (others => 'Z');
RAM_CS_i <= D_ctl_reg(2) when NVD_reg = '0'
else '0';
RAM_CS <= RAM_CS_i when BR = '0'
else 'Z';
RAM_WE_i <= D_ctl_reg(1) when NVD_reg = '0'
else '0';
RAM_WE <= RAM_WE_i when BR = '0'
else 'Z';
RAM_OE_i <= D_ctl_reg(0) when NVD_reg = '0'
else '0';
RAM_OE <= RAM_OE_i when BR = '0'
else 'Z';
-- FSM Send/DMA Ack Controller:
process(Clk, Reset)
begin
if Reset <= '0' then
FSM_now <= idle;
elsif Clk'event and Clk = '1' then
FSM_now <= FSM_next;
end if;
end process;
process(FSM_now, start_send_reg, DMA_Ready, DMA_RQ)
begin
BR <= '0';
FF_enable <= '1';
Send <= '0';
DMA_ACK <= '0';
case FSM_now is
when idle =>
if start_send_reg = '1' then
FSM_next <= SND_free;
elsif DMA_RQ = '1' then
FSM_next <= DMA_wait_non_jumpc;
else
FSM_next <= idle;
end if;
when SND_free =>
FF_enable <= '0';
Send <= '1';
if DMA_Ready <= '0' then
FSM_next <= SND_wait;
else
FSM_next <= SND_free;
end if;
when SND_wait =>
BR <= '1';
FF_enable <= '0';
Send <= '1';
if DMA_Ready <= '1' then
FSM_next <= SND_catch;
else
FSM_next <= SND_wait;
end if;
when SND_catch =>
BR <= '1';
FF_enable <= '0';
Send <= '0';
FSM_next <= idle;
when DMA_wait_non_jumpc =>
if JumpC_in = '1' then
FSM_next <= DMA_wait_non_jumpc;
else
FSM_next <= DMA_free;
end if;
when DMA_free =>
DMA_ACK <= '1';
FSM_next <= DMA_wait;
when DMA_wait =>
BR <= '1';
FF_enable <= '0';
DMA_ACK <= '1';
if DMA_RQ <= '0' then
FSM_next <= DMA_catch;
else
FSM_next <= DMA_wait;
end if;
when DMA_catch =>
BR <= '1';
FF_enable <= '0';
DMA_ACK <= '0';
FSM_next <= idle;
end case;
end process;
end pipelined;
|
gpl-3.0
|
1535479fb2a5513473c24a558fb14a9d
| 0.514519 | 2.748276 | false | false | false | false |
jgibbard/fir_filter
|
mac_module_tb.vhd
| 1 | 7,482 |
---------------------------------------------------------------------------
-- Project : FIR Filter
-- Author : James Gibbard ([email protected])
-- Date : 2017-03-25
-- File : mac_module_tb.vhd
-- Module :
---------------------------------------------------------------------------
-- Description : Basic test bench for testing a multiply accumulate unit
-- Assumes both the multiply and sum opetations are registered.
-- Run simulator for 2.6uS to complete all tests
---------------------------------------------------------------------------
-- Change Log
-- Version 0.0.1 : Initial version
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use STD.textio.all;
use ieee.std_logic_textio.all;
entity mac_module_tb is
end mac_module_tb;
architecture testbench of mac_module_tb is
constant multiplier_input_a_size : integer := 16;
constant multiplier_input_b_size : integer := 16;
constant accumulator_size : integer := 48;
signal clk : std_logic;
signal rst : std_logic;
signal en : std_logic;
signal a : signed(multiplier_input_a_size - 1 downto 0);
signal b : signed(multiplier_input_b_size- 1 downto 0);
signal accum : signed(accumulator_size - 1 downto 0);
constant clk_period : time := 20 ns;
begin
--Instantiate the UUT
uut : entity work.mac_module
generic map (
a_in_size =>multiplier_input_a_size,
b_in_size => multiplier_input_b_size,
accumulator_size => accumulator_size
)
port map (
clk => clk,
rst => rst,
en_in => en,
a_in => a,
b_in => b,
accum_out => accum
);
--Make a clock signal with a 50% duty cycle
clk_gen : process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process clk_gen;
--Tests very basic operation of UUT
--Basic checks on rst and enable signals
--Checks operation of MAC unit with small and large inputs
test_vectors : process
begin
--Start in Reset
rst <= '1';
en <= '0';
a <= X"0000";
b <= X"0000";
report "Take UUT out of reset";
--Take module out of reset
wait until clk = '1';
wait until clk = '1';
rst <= '0';
report "Test 1: Single multiply operation (1*2)";
--Test Single multiply accumulate operation
wait until clk = '1';
en <= '1';
a <= X"0001";
b <= X"0002";
--Wait 3 clock cycles (2 cycle latency, read on third clock edge)
for temp in 1 to 3 loop
wait until clk = '1';
end loop;
--Check that the multiply occured ok and the value was added to the accumulator
assert accum = 2 report "Accumulator output different to expected value! Expected: 2. Actual: " & integer'image(to_integer(accum)) severity FAILURE;
report "Test 2: Check accumulator (1*2) + (1*2)";
--Wait another cycle to check that the value in the accumulator doubles
wait until clk = '1';
assert accum = 4 report "Accumulator output different to expected value! Expected: 4. Actual: " & integer'image(to_integer(accum)) severity FAILURE;
report "Test 3: Test module reset";
--Test reset condition
rst <= '1';
--Set inputs to non-zero value
a <= X"0001";
b <= X"0001";
--Wait 2 clock cycles (rst takes one clock cycle, read value on 2nd clock edge)
for temp in 1 to 2 loop
wait until clk = '1';
end loop;
assert accum = 0 report "Accumulator was not reset when reset signal applied!" severity FAILURE;
report "Test 4: Test module enable signal";
--Test enable signal
wait until clk = '1';
--Accumulator = 0+(1*2)=2
rst <= '0';
en <= '1';
a <= X"0001";
b <= X"0002";
wait until clk = '1';
--Accumulator = 2+(3*4)=14
a <= X"0003";
b <= X"0004";
wait until clk = '1';
--Accumulator = Accumulator
--This input should not be added to the accumulator as en == '0'
a <= X"0005";
b <= X"0006";
en <= '0';
wait until clk = '1';
--Accumulator = 14 + (0*0)
a <= X"0000";
b <= X"0000";
en <= '1';
--Wait 2 clock cycles. 3*4=12 should stored in the multi_res register,
--So after 1 clock cycle the accumulator output should be updated (12 + 2)
--The value is read on the cycle afterwards meaning a wait of 2 cycles.
for temp in 1 to 2 loop
wait until clk = '1';
end loop;
assert accum = 14 report "Enable signal did not operate as intended" severity FAILURE;
report "Test 5: Test for multiplier overflow (32767 * 32767)";
--Reset accumulator
rst <= '1';
wait until clk = '1';
rst <= '0';
--Check for multiplier overflow
a <= to_signed(32767, 16);
b <= to_signed(32767, 16);
for temp in 1 to 3 loop
wait until clk = '1';
end loop;
assert accum = 1073676289 report "Multiplier value incorrect: 32767 * -32767 = 1073676289. Actual: " & integer'image(to_integer(accum)) severity FAILURE;
--Reset accumulator
rst <= '1';
wait until clk = '1';
rst <= '0';
report "Test 6: Test for multiplier overflow (-32768 * -32768)";
--Check for multiplier overflow
a <= to_signed(-32768, 16);
b <= to_signed(-32768, 16);
for temp in 1 to 3 loop
wait until clk = '1';
end loop;
assert accum = 1073741824 report "Multiplier value incorrect: -32768 * -32767 = 1073741824. Actual: " & integer'image(to_integer(accum)) severity FAILURE;
--Reset accumulator
rst <= '1';
wait until clk = '1';
rst <= '0';
report "Test 7: Test for multiplier overflow (-32768 * 32767)";
--Check negative multiply result
a <= to_signed(-32768, 16);
b <= to_signed(32767, 16);
for temp in 1 to 3 loop
wait until clk = '1';
end loop;
assert accum = -1073709056 report "Negative multiply failed: -32768 * 32767 = -1073709056. Actual: " & integer'image(to_integer(accum)) severity FAILURE;
--Reset accumulator
rst <= '1';
wait until clk = '1';
rst <= '0';
report "Test 8: Test accumulator over 100 MAC operations";
--Test accumulator
a <= X"000A";
b <= X"0001";
for temp in 1 to 102 loop
wait until clk = '1';
end loop;
assert accum = 1000 report "Accumulator failed. Expected: 1000, Actual: " & integer'image(to_integer(accum)) severity FAILURE;
report "Simulation done. All tests completed successfully!";
wait;
end process test_vectors;
end testbench;
|
unlicense
|
769c4fe4017b3aa28e48eb85e3c4e3c5
| 0.515638 | 4.372881 | false | true | false | false |
laurivosandi/hdl
|
zynq/src/frequency_divider.vhd
| 1 | 817 |
library ieee;
use ieee.std_logic_1164.all;
entity frequency_divider is
generic (
RATIO : integer := 50000000);
port (
clk_in : in std_logic;
reset : in std_logic;
clk_out : out std_logic);
end;
architecture behavioral of frequency_divider is
signal temporal: std_logic;
signal counter : integer range 0 to RATIO := 0;
begin
frequency_divider_process: process (reset, clk_in) begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if (counter = RATIO) then
temporal <= not(temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end;
|
mit
|
873d618062e4b41bb6e63a4cee42686f
| 0.538556 | 4.085 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/bcd_controller/bcd_controller_tb.vhd
| 1 | 1,011 |
library ieee;
use ieee.std_logic_1164.all;
entity bcd_controller_tb is
end;
architecture bcd_controller_tb_func of bcd_controller_tb is
signal clk_in: std_logic:='0';
signal anod_out: std_logic_vector(3 downto 0);
signal a: std_logic;
signal b: std_logic;
signal c: std_logic;
signal d: std_logic;
signal e: std_logic;
signal f: std_logic;
signal g: std_logic;
signal dp: std_logic;
component bcd_controller is
port(
clk: in std_logic;
anod_out: out std_logic_vector(3 downto 0);
a: out std_logic;
b: out std_logic;
c: out std_logic;
d: out std_logic;
e: out std_logic;
f: out std_logic;
g: out std_logic;
dp: out std_logic
);
end component;
begin
clk_in <= not(clk_in) after 20 ns;
bcd_controllerMap: bcd_controller
port map(
clk => clk_in,
anod_out => anod_out,
a => a,
b => b,
c => c,
d => d,
e => e,
f => f,
g => g,
dp => dp
);
end architecture;
|
gpl-3.0
|
7ea34289a9d920f972fbd23cb9cf9217
| 0.578635 | 2.717742 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/number_expander/number_expander.vhd
| 1 | 616 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--STEP 2.5
--This component expands the number so that we can work and operate with extra bits.
--It also adds the implicit 1 in the most significant bit
entity number_expander is
generic(
BITS : natural := 16
);
port(
number_in : in std_logic_vector(BITS - 1 downto 0) := (others => '0');
number_out : out std_logic_vector(BITS downto 0) := (others => '0')
);
end number_expander;
architecture number_expander_arq of number_expander is
begin
process(number_in) is
begin
number_out <= '1' & number_in;
end process;
end;
|
gpl-3.0
|
e5f1a92296dc5801ce0618b2441d1654
| 0.691558 | 3.034483 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/ram_double_bank_file.vhd
| 1 | 4,990 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Essentials
-- Module Name: RAM Double Bank
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavior of a RAM Double Bank behavioral, where it can output
-- number_of_memories at once and have 2 interfaces, so it can read and write on the same cycle
-- Only used for tests.
--
-- The circuits parameters
--
-- number_of_memories :
--
-- Number of memories in the RAM Double Bank
--
-- ram_address_size :
-- Address size of the RAM Double Bank used on the circuit.
--
-- ram_word_size :
-- The size of internal word on the RAM Double Bank.
--
-- file_ram_word_size :
-- The size of the word used in the file to be loaded on the RAM Double Bank.(ARCH: FILE_LOAD)
--
-- load_file_name :
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
-- The name of the file to be used to dump the memory.
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
architecture file_load of ram_double_bank is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
pure function load_ram (ram_file_name : in string) return ramtype is
FILE ram_file : text is in ram_file_name;
variable line_n : line;
variable memory_ram : ramtype;
variable file_read_buffer : std_logic_vector((file_ram_word_size - 1) downto 0);
variable file_buffer_amount : integer;
variable ram_buffer_amount : integer;
begin
file_buffer_amount := file_ram_word_size;
for I in ramtype'range loop
ram_buffer_amount := 0;
if (not endfile(ram_file) or (file_buffer_amount /= file_ram_word_size)) then
while ram_buffer_amount /= ram_word_size loop
if file_buffer_amount = file_ram_word_size then
if (not endfile(ram_file)) then
readline (ram_file, line_n);
read (line_n, file_read_buffer);
else
file_read_buffer := (others => '0');
end if;
file_buffer_amount := 0;
end if;
memory_ram(I)(ram_buffer_amount) := file_read_buffer(file_buffer_amount);
ram_buffer_amount := ram_buffer_amount + 1;
file_buffer_amount := file_buffer_amount + 1;
end loop;
else
memory_ram(I) := (others => '0');
end if;
end loop;
return memory_ram;
end function;
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype := load_ram(load_file_name);
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
memory_ram <= load_ram(load_file_name);
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw_a = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address_a) + index)) <= data_in_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
if rw_b = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address_b) + index)) <= data_in_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
for index in 0 to (number_of_memories - 1) loop
data_out_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_a)) + index);
data_out_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_b)) + index);
end loop;
end if;
end process;
end file_load;
|
bsd-2-clause
|
817b2bff6d99b6eb277bca7cfc844cad
| 0.517435 | 3.80916 | false | false | false | false |
hitomi2500/wasca
|
fpga_firmware/heartbeat.vhd
| 1 | 5,233 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity heartbeat is
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
heartbeat_out : out std_logic := '0';
avalon_regs_read : in std_logic := '0'; -- avalon_master.read
avalon_regs_write : in std_logic := '0'; -- .write
avalon_regs_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_regs_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_regs_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_regs_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_regs_readdatavalid : out std_logic := '0' -- .readdatavalid
);
end entity heartbeat;
architecture rtl of heartbeat is
signal heartbeat_counter : unsigned(31 downto 0) := (others => '0');
signal heartbeat_counter_logic : std_logic_vector(31 downto 0) := (others => '0');
signal heartbeat_divider : unsigned(4 downto 0) := to_unsigned(27,5); --initial division is 2^27 = 0.86Hz
signal heartbeat_divider_16 : std_logic_vector(15 downto 0) := (others => '0');
signal heartbeat_divider_int : integer range 31 downto 0 := 27;
signal heartbeat_force_flag : std_logic := '0';
signal heartbeat_force_value : std_logic := '0';
signal led_flash_cntr : unsigned(27 downto 0) := (others => '0');
signal led_flash_limit : unsigned(27 downto 0) := (others => '0');
signal led_flash_enable : std_logic := '0';
signal led_flash_sig : std_logic := '0';
begin
heartbeat_divider_16 <= std_logic_vector(resize(heartbeat_divider,16));
heartbeat_divider_int <= to_integer(heartbeat_divider);
heartbeat_counter_logic <= std_logic_vector(heartbeat_counter);
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_regs_readdatavalid <= '0';
if avalon_regs_read = '1' then
avalon_regs_readdatavalid <= '1';
case avalon_regs_address(7 downto 0) is
when X"00" =>
avalon_regs_readdata <= heartbeat_divider_16;
when X"04" =>
avalon_regs_readdata <= std_logic_vector(heartbeat_counter(15 downto 0));
when X"06" =>
avalon_regs_readdata <= std_logic_vector(heartbeat_counter(31 downto 16));
when others =>
avalon_regs_readdata <= X"0000";
end case;
end if;
end if;
end process;
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_regs_write= '1' then
case avalon_regs_address(7 downto 0) is
when X"00" => -- LED heartbeat control
heartbeat_divider <= unsigned(avalon_regs_writedata(4 downto 0));
heartbeat_force_value <= avalon_regs_writedata(6);
heartbeat_force_flag <= avalon_regs_writedata(7);
led_flash_enable <= '0';
when X"10" => -- LED flash control
led_flash_limit <= unsigned(avalon_regs_writedata(11 downto 0) & X"FFFF");
led_flash_cntr <= X"0000000";
heartbeat_force_flag <= '0';
led_flash_enable <= '1';
when others =>
null;
end case;
elsif led_flash_cntr < led_flash_limit then -- LED flash ON
led_flash_cntr <= led_flash_cntr + 1;
led_flash_sig <= '1';
else -- LED flash OFF
led_flash_cntr <= X"FFFFFFF";
led_flash_sig <= '0';
end if;
end if;
end process;
--Avalon regs interface is only regs, so always ready to write.
avalon_regs_waitrequest <= '0';
--Counter
heartbeat_counter <= heartbeat_counter + 1 when rising_edge(clock);
--Heartbeat selector
process (clock)
begin
if rising_edge(clock) then
if heartbeat_force_flag = '1' then
heartbeat_out <= heartbeat_force_value;
elsif led_flash_enable = '1' then
heartbeat_out <= led_flash_sig;
else
case heartbeat_divider_int is
when 21 =>
heartbeat_out <= heartbeat_counter_logic(20); -- 54 Hz
when 22 =>
heartbeat_out <= heartbeat_counter_logic(21); -- 28 Hz
when 23 =>
heartbeat_out <= heartbeat_counter_logic(22); -- 14 Hz
when 24 =>
heartbeat_out <= heartbeat_counter_logic(23); -- 7 Hz
when 25 =>
heartbeat_out <= heartbeat_counter_logic(24); --3.2 Hz
when 26 =>
heartbeat_out <= heartbeat_counter_logic(25); --1.6 Hz
when 27 =>
heartbeat_out <= heartbeat_counter_logic(26); --0.8 Hz
when 28 =>
heartbeat_out <= heartbeat_counter_logic(27);
when 29 =>
heartbeat_out <= heartbeat_counter_logic(28);
when 30 =>
heartbeat_out <= heartbeat_counter_logic(29);
when 31 =>
heartbeat_out <= heartbeat_counter_logic(30);
when others =>
heartbeat_out <= heartbeat_counter_logic(26);
end case;
end if;
end if;
end process;
end architecture rtl;
|
gpl-2.0
|
4db5a89ee4ea4bae4565ba6b5ef88b44
| 0.576916 | 3.454125 | false | false | false | false |
hitomi2500/wasca
|
fpga_firmware/wasca/synthesis/submodules/heartbeat.vhd
| 1 | 4,435 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity heartbeat is
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
heartbeat_out : out std_logic := '0';
avalon_regs_read : in std_logic := '0'; -- avalon_master.read
avalon_regs_write : in std_logic := '0'; -- .write
avalon_regs_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_regs_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_regs_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_regs_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_regs_readdatavalid : out std_logic := '0' -- .readdatavalid
);
end entity heartbeat;
architecture rtl of heartbeat is
signal heartbeat_counter : unsigned(31 downto 0) := (others => '0');
signal heartbeat_counter_logic : std_logic_vector(31 downto 0) := (others => '0');
signal heartbeat_divider : unsigned(4 downto 0) := to_unsigned(27,5); --initial division is 2^27 = 0.86Hz
signal heartbeat_divider_16 : std_logic_vector(15 downto 0) := (others => '0');
signal heartbeat_divider_int : integer range 31 downto 0 := 27;
signal heartbeat_force_flag : std_logic := '0';
signal heartbeat_force_value : std_logic := '0';
begin
heartbeat_divider_16 <= std_logic_vector(resize(heartbeat_divider,16));
heartbeat_divider_int <= to_integer(heartbeat_divider);
heartbeat_counter_logic <= std_logic_vector(heartbeat_counter);
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_regs_readdatavalid <= '0';
if avalon_regs_read = '1' then
avalon_regs_readdatavalid <= '1';
case avalon_regs_address(7 downto 0) is
when X"00" =>
avalon_regs_readdata <= heartbeat_divider_16;
when X"04" =>
avalon_regs_readdata <= std_logic_vector(heartbeat_counter(15 downto 0));
when X"06" =>
avalon_regs_readdata <= std_logic_vector(heartbeat_counter(31 downto 16));
when others =>
avalon_regs_readdata <= X"0000";
end case;
end if;
end if;
end process;
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_regs_write= '1' then
case avalon_regs_address(7 downto 0) is
when X"00" =>
heartbeat_divider <= unsigned(avalon_regs_writedata(4 downto 0));
heartbeat_force_value <= avalon_regs_writedata(6);
heartbeat_force_flag <= avalon_regs_writedata(7);
when others =>
null;
end case;
end if;
end if;
end process;
--Avalon regs interface is only regs, so always ready to write.
avalon_regs_waitrequest <= '0';
--Counter
heartbeat_counter <= heartbeat_counter + 1 when rising_edge(clock);
--Heartbeat selector
process (clock)
begin
if rising_edge(clock) then
if heartbeat_force_flag = '1' then
heartbeat_out <= heartbeat_force_value;
else
case heartbeat_divider_int is
when 21 =>
heartbeat_out <= heartbeat_counter_logic(20); -- 54 Hz
when 22 =>
heartbeat_out <= heartbeat_counter_logic(21); -- 28 Hz
when 23 =>
heartbeat_out <= heartbeat_counter_logic(22); -- 14 Hz
when 24 =>
heartbeat_out <= heartbeat_counter_logic(23); -- 7 Hz
when 25 =>
heartbeat_out <= heartbeat_counter_logic(24); --3.2 Hz
when 26 =>
heartbeat_out <= heartbeat_counter_logic(25); --1.6 Hz
when 27 =>
heartbeat_out <= heartbeat_counter_logic(26); --0.8 Hz
when 28 =>
heartbeat_out <= heartbeat_counter_logic(27);
when 29 =>
heartbeat_out <= heartbeat_counter_logic(28);
when 30 =>
heartbeat_out <= heartbeat_counter_logic(29);
when 31 =>
heartbeat_out <= heartbeat_counter_logic(30);
when others =>
heartbeat_out <= heartbeat_counter_logic(26);
end case;
end if;
end if;
end process;
end architecture rtl;
|
gpl-2.0
|
57e1fdc091755fc26f146ea7ac6c2d3a
| 0.572717 | 3.550841 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/tp1/led_display_controller.vhd
| 1 | 2,499 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity led_display_controller is
port (
clk_in: in std_logic;
bcd0: in std_logic_vector(3 downto 0);
bcd1: in std_logic_vector(3 downto 0);
bcd2: in std_logic_vector(3 downto 0);
bcd3: in std_logic_vector(3 downto 0);
anode_output: out std_logic_vector(3 downto 0);
led_output: out std_logic_vector(7 downto 0)
);
end;
architecture led_display_controller_arq of led_display_controller is
signal counter_enabler: std_logic:= '1';
signal counter_output: std_logic_vector(1 downto 0);
signal multiplex_output: std_logic_vector(3 downto 0);
component generic_counter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end component;
component generic_enabler is
generic(PERIOD:natural := 1000000 );
port(
clk: in std_logic;
rst: in std_logic;
ena_out: out std_logic
);
end component;
component bcd_mux IS
port(
bcd0_i : IN std_logic_vector(3 DOWNTO 0);
bcd1_i : IN std_logic_vector(3 DOWNTO 0);
bcd2_i : IN std_logic_vector(3 DOWNTO 0);
bcd3_i : IN std_logic_vector(3 DOWNTO 0);
m_sel : IN std_logic_vector(1 DOWNTO 0);
m_out : OUT std_logic_vector(3 DOWNTO 0));
end component;
component anode_sel IS
PORT(
sel_in : IN std_logic_vector(1 DOWNTO 0);
sel_out : OUT std_logic_vector(3 DOWNTO 0));
END component;
component led_enabler IS
PORT(
ena_in : IN std_logic_vector(3 DOWNTO 0);
ena_out : OUT std_logic_vector(7 DOWNTO 0));
END component;
begin
genericCounterMap: generic_counter generic map (2,4)
port map(
clk => clk_in,
rst => '0',
ena => counter_enabler,
count => counter_output
);
generic_enabler_map: generic_enabler generic map (100000)
port map(
clk => clk_in,
rst => '0',
ena_out => counter_enabler
);
bcd_muxMap: bcd_mux port map(
bcd0_i => bcd0,
bcd1_i => bcd1,
bcd2_i => bcd2,
bcd3_i => bcd3,
m_sel => counter_output,
m_out => multiplex_output
);
anode_selMap: anode_sel port map(
sel_in => counter_output,
sel_out => anode_output
);
led_enablerMap: led_enabler port map(
ena_in => multiplex_output,
ena_out => led_output
);
end;
|
gpl-3.0
|
e2d6c933874d032447509dd82407e358
| 0.617847 | 3.032767 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/tp1/led_enabler.vhd
| 1 | 1,033 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY led_enabler IS
PORT(
ena_in : IN std_logic_vector(3 DOWNTO 0);
ena_out : OUT std_logic_vector(7 DOWNTO 0));
END led_enabler;
ARCHITECTURE led_enabler_arq OF led_enabler IS
BEGIN
PROCESS (ena_in) IS
BEGIN
CASE ena_in IS
WHEN "0000" => ena_out <= b"11111100"; ---A->G
WHEN "0001" => ena_out <= b"01100000";
WHEN "0010" => ena_out <= b"11011010";
WHEN "0011" => ena_out <= b"11110010";
WHEN "0100" => ena_out <= b"01100110";
WHEN "0101" => ena_out <= b"10110110";
WHEN "0110" => ena_out <= b"10111110";
WHEN "0111" => ena_out <= b"11100000";
WHEN "1000" => ena_out <= b"11111110";
WHEN "1001" => ena_out <= b"11100110";
WHEN OTHERS => ena_out <= b"01111100"; ---U
END CASE;
END PROCESS;
END led_enabler_arq;
|
gpl-3.0
|
f9b7f496b6fd11f5bfdf642d5bb9a561
| 0.496612 | 3.375817 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/find_correct_errors_n.vhd
| 1 | 11,052 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Find_Correct_Errors_N
-- Module Name: Find_Correct_Errors_N
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 3rd step in Goppa Code Decoding.
--
-- This circuit should be used along side polynomial_evaluator_n or polynomial_evaluator_n_v2.
-- This circuit when used along side follows the same number of stages of polynomial evaluators.
-- It receives the values of messages and when it is detected to be last evaluation.
-- During the last evaluations with the result is 0 then it write on memory the inverted value,
-- if not it writes on the memory the original value.
--
-- This circuit is optimized. A newer version with both polynomial evaluator and this unit were
-- constructed in order to optimize syndrome generation.
-- This circuit is polynomial_syndrome_computing_n
--
--
-- The circuits parameters
--
-- number_of_pipelines :
--
-- Number of pipelines used in the circuit to test the support elements and
-- correct the message. Each pipeline needs at least 2 memory ram to store
-- intermediate results.
--
-- pipeline_size :
--
-- The number of stages of the pipeline. More stages means more values of sigma
-- are tested at once.
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- length_support_elements :
--
-- The number of support elements. This parameter depends of the Goppa code used.
--
-- size_support_elements :
--
-- The size of the memory that holds all support elements. This parameter
-- depends of the Goppa code used.
-- This is ceil(log2(length_support_elements))
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- controller_find_correct_errors_n Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_load_nbits Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- shift_register_nbits Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity find_correct_errors_n is
Generic (
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 28;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_support_elements: integer := 2048;
-- size_support_elements : integer := 11
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 51;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_support_elements: integer := 2048;
-- size_support_elements : integer := 11
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 67;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_support_elements: integer := 3307;
-- size_support_elements : integer := 12
-- QD-GOPPA [2528, 2144, 32, 12] --
number_of_pipelines : integer := 1;
pipeline_size : integer := 33;
gf_2_m : integer range 1 to 20 := 12;
length_support_elements: integer := 2528;
size_support_elements : integer := 12
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_support_elements: integer := 2816;
-- size_support_elements : integer := 12
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_support_elements: integer := 3328;
-- size_support_elements : integer := 12
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 129;
-- gf_2_m : integer range 1 to 20 := 13;
-- length_support_elements: integer := 7296;
-- size_support_elements : integer := 13
);
Port(
value_message : in STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_evaluated : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
address_value_evaluated : in STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
enable_correction : in STD_LOGIC;
evaluation_finalized : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
correction_finalized : out STD_LOGIC;
address_new_value_message : out STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
address_value_error : out STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
write_enable_new_value_message : out STD_LOGIC;
write_enable_value_error : out STD_LOGIC;
new_value_message : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_error : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0)
);
end find_correct_errors_n;
architecture RTL of find_correct_errors_n is
component controller_find_correct_errors_n
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable_correction : in STD_LOGIC;
evaluation_finalized : in STD_LOGIC;
reg_value_evaluated_ce : out STD_LOGIC;
reg_address_store_new_value_message_ce : out STD_LOGIC;
reg_address_store_new_value_message_rst : out STD_LOGIC;
reg_write_enable_new_value_message_ce : out STD_LOGIC;
reg_write_enable_new_value_message_rst : out STD_LOGIC;
correction_finalized : out STD_LOGIC
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_load_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component shift_register_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
signal is_error_position : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
constant error_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_value_evaluated_d : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal reg_value_evaluated_ce : STD_LOGIC;
signal reg_value_evaluated_q : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal reg_address_store_new_value_message_d : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal reg_address_store_new_value_message_ce : STD_LOGIC;
signal reg_address_store_new_value_message_rst : STD_LOGIC;
constant reg_address_store_new_value_message_rst_value : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0) := (others => '0');
signal reg_address_store_new_value_message_q : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal reg_write_enable_new_value_message_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_write_enable_new_value_message_ce : STD_LOGIC;
signal reg_write_enable_new_value_message_rst : STD_LOGIC;
constant reg_write_enable_new_value_message_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_write_enable_new_value_message_q : STD_LOGIC_VECTOR(0 downto 0);
signal message_data_in : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal message_data_out : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
begin
pipelines : for I in 0 to (number_of_pipelines - 1) generate
reg_value_evaluated_I : register_nbits
Generic Map( size => gf_2_m )
Port Map(
d => reg_value_evaluated_d(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
clk => clk,
ce => reg_value_evaluated_ce,
q => reg_value_evaluated_q(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)))
);
shift_message : shift_register_nbits
Generic Map(size => pipeline_size + 1)
Port Map(
data_in => message_data_in(I),
clk => clk,
ce => '1',
q => open,
data_out => message_data_out(I)
);
is_error_position(I) <= '1' when reg_value_evaluated_q(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) = error_value else '0';
message_data_in(I) <= value_message(I);
new_value_message(I) <= (not message_data_out(I)) when is_error_position(I) = '1' else message_data_out(I);
value_error(I) <= is_error_position(I);
reg_value_evaluated_d(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= value_evaluated(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)));
end generate;
controller : controller_find_correct_errors_n
Port Map(
clk => clk,
rst => rst,
enable_correction => enable_correction,
evaluation_finalized => evaluation_finalized,
reg_value_evaluated_ce => reg_value_evaluated_ce,
reg_address_store_new_value_message_ce => reg_address_store_new_value_message_ce,
reg_address_store_new_value_message_rst => reg_address_store_new_value_message_rst,
reg_write_enable_new_value_message_ce => reg_write_enable_new_value_message_ce,
reg_write_enable_new_value_message_rst => reg_write_enable_new_value_message_rst,
correction_finalized => correction_finalized
);
reg_address_store_new_message : register_rst_nbits
Generic Map( size => size_support_elements )
Port Map(
d => reg_address_store_new_value_message_d,
clk => clk,
ce => reg_address_store_new_value_message_ce,
rst => reg_address_store_new_value_message_rst,
rst_value => reg_address_store_new_value_message_rst_value,
q => reg_address_store_new_value_message_q
);
reg_write_enable_new_message : register_rst_nbits
Generic Map( size => 1 )
Port Map(
d => reg_write_enable_new_value_message_d,
clk => clk,
ce => reg_write_enable_new_value_message_ce,
rst => reg_write_enable_new_value_message_rst,
rst_value => reg_write_enable_new_value_message_rst_value,
q => reg_write_enable_new_value_message_q
);
reg_address_store_new_value_message_d <= address_value_evaluated;
reg_write_enable_new_value_message_d(0) <= enable_correction;
address_new_value_message <= reg_address_store_new_value_message_q;
address_value_error <= reg_address_store_new_value_message_q;
write_enable_new_value_message <= reg_write_enable_new_value_message_q(0);
write_enable_value_error <= reg_write_enable_new_value_message_q(0);
end RTL;
|
bsd-2-clause
|
beaf0855b12da30d7d8c09c22fa41db1
| 0.6711 | 3.00163 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/codic_commander/cordic_commander.vhd
| 1 | 1,662 |
Library IEEE;
use IEEE.STD_Logic_1164.all;
use ieee.numeric_std.all;
entity cordic_commander is
generic(TOTAL_BITS : integer := 32);
port(
clk : in std_logic := '0';
enable : in std_logic := '0';
mode : in std_logic_vector(1 downto 0) := (others => '0');
angle : out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end cordic_commander;
architecture cordic_commander_arq of cordic_commander is
constant CONSTANT_ROTATION_ANGLE_LEFT : std_logic_vector(31 downto 0) := "00000000000000001011010000000000"; --0.703125 degrees
constant CONSTANT_ROTATION_ANGLE_RIGHT : std_logic_vector(31 downto 0) := "11111111111111110100110000000000"; --(-0.703125) degrees
begin
process(clk)
variable tmp_angle : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
variable rotating_mode : integer := 0; -- -1: constant rotation left, 0 rotate angle, 1: constant rotation right
variable rotated : boolean := false;
variable mode_int : integer := 0;
begin
mode_int := to_integer(signed(mode));
if(rising_edge(clk)) then
case( mode_int ) is
when 0 =>
if(not rotated) then
angle <= tmp_angle;
rotated := true;
else
angle <= (others => '0');
end if;
when 1 =>
angle <= CONSTANT_ROTATION_ANGLE_LEFT;
rotated := false;
when -1 =>
angle <= CONSTANT_ROTATION_ANGLE_RIGHT;
rotated := false;
when others =>
angle <= (others => '0');
rotated := false;
end case ;
end if;
end process;
end architecture;
|
gpl-3.0
|
b0a137f5da3d2221e0583256b205a202
| 0.593261 | 3.865116 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/syndrome_calculator_n_pipe_v3.vhd
| 1 | 27,697 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Syndrome_Calculator_N_Pipe_v3
-- Module Name: Syndrome_Calculator_N_Pipe_v3
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st step in Goppa Code Decoding.
--
-- This circuit computes the syndrome from the ciphertext, support elements and
-- inverted evaluation of support elements into polynomial g, aka g(L)^(-1).
-- This circuit works by computing the syndrome of only the positions where the ciphertext
-- has value 1.
--
-- This is circuit version with a variable number of computation units, pipeline and
-- a variable number of pipelines. This circuit is the master and the variable is done through
-- the slaves circuits.
--
-- The circuits parameters
--
-- number_of_syndrome_calculators :
--
-- The number of pipelines that compute parts of syndrome from
-- different parts of the ciphertext. This number must be 1 or greater.
--
-- syndrome_calculator_size :
--
-- The number of units that compute each syndrome at the same time
-- from the same ciphertext. This number must be 1 or greater.
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword or in this case the ciphertext. Both the codeword
-- and ciphertext has the same size.
--
-- size_codeword :
--
-- The number of bits necessary to hold the ciphertext/codeword.
-- This is ceil(log2(length_codeword)).
--
-- length_syndrome :
--
-- The size of the syndrome array. This parameter depends of the
-- Goppa code used.
--
-- size_syndrome :
--
-- The number of bits necessary to hold the array syndrome.
-- This is ceil(log2(length_syndrome)).
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- syndrome_calculator_n_pipe_v3_slave Rev 1.0
-- controller_syndrome_calculator_2_pipe_v3_master Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_decrement_rst_nbits Rev 1.0
-- shift_register_rst_nbits Rev 1.0
-- mult_gf_2_m Rev 1.0
-- adder_gf_2_m Rev 1.0
-- and_reduce Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity syndrome_calculator_n_pipe_v3 is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_syndrome_calculators : integer := 1;
-- syndrome_calculator_size : integer := 32;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- length_syndrome : integer := 54;
-- size_syndrome : integer := 6
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_syndrome_calculators : integer := 1;
-- syndrome_calculator_size : integer := 32;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- length_syndrome : integer := 100;
-- size_syndrome : integer := 7
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_syndrome_calculators : integer := 1;
-- syndrome_calculator_size : integer := 32;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3307;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 132;
-- size_syndrome : integer := 8
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_syndrome_calculators : integer := 1;
-- syndrome_calculator_size : integer := 32;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 64;
-- size_syndrome : integer := 6
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_syndrome_calculators : integer := 1;
-- syndrome_calculator_size : integer := 32;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 128;
-- size_syndrome : integer := 7
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_syndrome_calculators : integer := 1;
-- syndrome_calculator_size : integer := 32;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3200;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 256;
-- size_syndrome : integer := 8
-- QD-GOPPA [7296, 5632, 128, 13] --
number_of_syndrome_calculators : integer := 1;
syndrome_calculator_size : integer := 32;
gf_2_m : integer range 1 to 20 := 15;
length_codeword : integer := 8320;
size_codeword : integer := 14;
length_syndrome : integer := 256;
size_syndrome : integer := 8
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(gf_2_m) - 1) downto 0);
value_L : in STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(gf_2_m) - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((number_of_syndrome_calculators - 1) downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_h : out STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(size_codeword) - 1) downto 0);
address_L : out STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(size_codeword) - 1) downto 0);
address_codeword : out STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(size_codeword) - 1) downto 0);
address_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
address_new_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0)
);
end syndrome_calculator_n_pipe_v3;
architecture Behavioral of syndrome_calculator_n_pipe_v3 is
component syndrome_calculator_n_pipe_v3_slave
Generic(
initial_address : integer;
increment_address : integer;
syndrome_calculator_size : integer;
gf_2_m : integer range 1 to 20;
length_codeword : integer;
size_codeword : integer;
length_syndrome : integer;
size_syndrome : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_L : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR(0 downto 0);
start_calculation : in STD_LOGIC;
last_syndrome : in STD_LOGIC;
ready_calculation : out STD_LOGIC;
finished_calculation : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_h : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_L : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0)
);
end component;
component controller_syndrome_calculator_2_pipe_v3_master
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
almost_units_ready : in STD_LOGIC;
empty_units : in STD_LOGIC;
limit_ctr_codeword_q : in STD_LOGIC;
limit_ctr_syndrome_q : in STD_LOGIC;
reg_first_syndrome_q : in STD_LOGIC_VECTOR(0 downto 0);
reg_codeword_q : in STD_LOGIC_VECTOR(0 downto 0);
start_calculation : in STD_LOGIC;
slaves_finished : in STD_LOGIC;
ready_calculation : out STD_LOGIC;
finished_calculation : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
control_units_ce : out STD_LOGIC;
control_units_rst : out STD_LOGIC;
int_reg_L_ce : out STD_LOGIC;
square_h : out STD_LOGIC;
int_reg_h_ce : out STD_LOGIC;
int_reg_h_rst : out STD_LOGIC;
int_sel_reg_h : out STD_LOGIC;
reg_load_L_ce : out STD_LOGIC;
reg_load_h_ce : out STD_LOGIC;
reg_load_h_rst : out STD_LOGIC;
reg_load_syndrome_ce : out STD_LOGIC;
reg_load_syndrome_rst : out STD_LOGIC;
reg_new_value_syndrome_ce : out STD_LOGIC;
reg_new_value_master_syndrome_ce : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_first_syndrome_ce : out STD_LOGIC;
reg_first_syndrome_rst : out STD_LOGIC;
ctr_load_address_syndrome_ce : out STD_LOGIC;
ctr_load_address_syndrome_rst : out STD_LOGIC;
ctr_store_address_syndrome_ce : out STD_LOGIC;
ctr_store_address_syndrome_rst : out STD_LOGIC;
ctr_load_address_codeword_ce : out STD_LOGIC;
ctr_load_address_codeword_rst : out STD_LOGIC;
reg_load_limit_codeword_rst : out STD_LOGIC;
reg_load_limit_codeword_ce : out STD_LOGIC;
reg_calc_limit_codeword_rst : out STD_LOGIC;
reg_calc_limit_codeword_ce : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_decrement_rst_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component shift_register_rst_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component mult_gf_2_m
Generic (gf_2_m : integer range 1 to 20 := 11);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component adder_gf_2_m
Generic(
gf_2_m : integer := 1;
number_of_elements : integer range 2 to integer'high := 2
);
Port(
a : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_elements) - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component and_reduce
Generic(
vector_size : integer := 1;
number_of_vectors : integer range 2 to integer'high := 2
);
Port(
a : in STD_LOGIC_VECTOR(((vector_size)*(number_of_vectors) - 1) downto 0);
o : out STD_LOGIC_VECTOR((vector_size - 1) downto 0)
);
end component;
signal reg_L_d : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal reg_L_ce : STD_LOGIC_VECTOR((syndrome_calculator_size - 1) downto 0);
signal reg_L_q : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal reg_h_d :STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal reg_h_ce : STD_LOGIC_VECTOR((syndrome_calculator_size - 1) downto 0);
signal reg_h_rst : STD_LOGIC_VECTOR((syndrome_calculator_size - 1) downto 0);
constant reg_h_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_h_q : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal sel_reg_h : STD_LOGIC_VECTOR((syndrome_calculator_size - 1) downto 0);
signal square_h : STD_LOGIC;
signal reg_load_L_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_load_L_ce : STD_LOGIC;
signal reg_load_L_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_load_h_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_load_h_ce : STD_LOGIC;
signal reg_load_h_rst : STD_LOGIC;
constant reg_load_h_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
signal reg_load_h_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_load_syndrome_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_load_syndrome_ce : STD_LOGIC;
signal reg_load_syndrome_rst : STD_LOGIC;
constant reg_load_syndrome_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
signal reg_load_syndrome_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_master_syndrome_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_master_syndrome_ce : STD_LOGIC;
signal reg_new_value_master_syndrome_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_intermediate_syndrome : STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*gf_2_m - 1) downto 0);
signal reg_new_value_syndrome_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_syndrome_ce : STD_LOGIC;
signal reg_new_value_syndrome_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_codeword_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_codeword_ce : STD_LOGIC;
signal reg_codeword_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_first_syndrome_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_first_syndrome_ce : STD_LOGIC;
signal reg_first_syndrome_rst : STD_LOGIC;
constant reg_first_syndrome_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "1";
signal reg_first_syndrome_q : STD_LOGIC_VECTOR(0 downto 0);
signal mult_a : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal mult_b : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal mult_o : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal adder_a : STD_LOGIC_VECTOR(((syndrome_calculator_size+1)*gf_2_m - 1) downto 0);
signal adder_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal final_adder_a : STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*gf_2_m - 1) downto 0);
signal final_adder_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_load_address_syndrome_ce : STD_LOGIC;
signal ctr_load_address_syndrome_rst : STD_LOGIC;
constant ctr_load_address_syndrome_rst_value : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0) := std_logic_vector(to_unsigned(length_syndrome - 1, size_syndrome));
signal ctr_load_address_syndrome_q : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal ctr_store_address_syndrome_ce : STD_LOGIC;
signal ctr_store_address_syndrome_rst : STD_LOGIC;
constant ctr_store_address_syndrome_rst_value : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0) := std_logic_vector(to_unsigned(length_syndrome - 1, size_syndrome));
signal ctr_store_address_syndrome_q : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal ctr_load_address_codeword_ce : STD_LOGIC;
signal ctr_load_address_codeword_rst : STD_LOGIC;
constant ctr_load_address_codeword_rst_value : STD_LOGIC_VECTOR((size_codeword - 1) downto 0) := std_logic_vector(to_unsigned(0, size_codeword));
signal ctr_load_address_codeword_q : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal reg_load_limit_codeword_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_load_limit_codeword_ce : STD_LOGIC;
signal reg_load_limit_codeword_rst : STD_LOGIC;
constant reg_load_limit_codeword_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_load_limit_codeword_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_calc_limit_codeword_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_calc_limit_codeword_ce : STD_LOGIC;
signal reg_calc_limit_codeword_rst : STD_LOGIC;
constant reg_calc_limit_codeword_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_calc_limit_codeword_q : STD_LOGIC_VECTOR(0 downto 0);
signal control_units_ce : STD_LOGIC;
signal control_units_rst : STD_LOGIC;
constant control_units_rst_value0 : STD_LOGIC_VECTOR((syndrome_calculator_size - 1) downto 0) := (others => '0');
constant control_units_rst_value1 : STD_LOGIC_VECTOR((syndrome_calculator_size) downto (syndrome_calculator_size)) := "1";
constant control_units_rst_value : STD_LOGIC_VECTOR((syndrome_calculator_size) downto 0) := control_units_rst_value1 & control_units_rst_value0;
signal control_units_q : STD_LOGIC_VECTOR((syndrome_calculator_size) downto 0);
signal control_units_data_out : STD_LOGIC;
signal int_reg_L_ce : STD_LOGIC;
signal int_reg_h_ce : STD_LOGIC;
signal int_reg_h_rst: STD_LOGIC;
signal int_sel_reg_h : STD_LOGIC;
signal almost_units_ready : STD_LOGIC;
signal empty_units : STD_LOGIC;
signal limit_ctr_codeword_q : STD_LOGIC;
signal limit_ctr_syndrome_q : STD_LOGIC;
signal start_calculation : STD_LOGIC;
signal last_syndrome : STD_LOGIC;
signal slaves_finished : STD_LOGIC;
signal ready_calculation : STD_LOGIC_VECTOR((number_of_syndrome_calculators - 1) downto 0);
signal finished_calculation : STD_LOGIC_VECTOR((number_of_syndrome_calculators - 1) downto 0);
begin
controller : controller_syndrome_calculator_2_pipe_v3_master
Port Map(
clk => clk,
rst => rst,
almost_units_ready => almost_units_ready,
empty_units => empty_units,
limit_ctr_codeword_q => reg_calc_limit_codeword_q(0),
limit_ctr_syndrome_q => limit_ctr_syndrome_q,
reg_first_syndrome_q => reg_first_syndrome_q,
reg_codeword_q => reg_codeword_q,
start_calculation => start_calculation,
slaves_finished => slaves_finished,
ready_calculation => ready_calculation(0),
finished_calculation => finished_calculation(0),
write_enable_new_syndrome => write_enable_new_syndrome,
control_units_ce => control_units_ce,
control_units_rst => control_units_rst,
int_reg_L_ce => int_reg_L_ce,
square_h => square_h,
int_reg_h_ce => int_reg_h_ce,
int_reg_h_rst => int_reg_h_rst,
int_sel_reg_h => int_sel_reg_h,
reg_load_L_ce => reg_load_L_ce,
reg_load_h_ce => reg_load_h_ce,
reg_load_h_rst => reg_load_h_rst,
reg_load_syndrome_ce => reg_load_syndrome_ce,
reg_load_syndrome_rst => reg_load_syndrome_rst,
reg_new_value_master_syndrome_ce => reg_new_value_master_syndrome_ce,
reg_new_value_syndrome_ce => reg_new_value_syndrome_ce,
reg_codeword_ce => reg_codeword_ce,
reg_first_syndrome_ce => reg_first_syndrome_ce,
reg_first_syndrome_rst => reg_first_syndrome_rst,
ctr_load_address_syndrome_ce => ctr_load_address_syndrome_ce,
ctr_load_address_syndrome_rst => ctr_load_address_syndrome_rst,
ctr_store_address_syndrome_ce => ctr_store_address_syndrome_ce,
ctr_store_address_syndrome_rst => ctr_store_address_syndrome_rst,
ctr_load_address_codeword_ce => ctr_load_address_codeword_ce,
ctr_load_address_codeword_rst => ctr_load_address_codeword_rst,
reg_load_limit_codeword_ce => reg_load_limit_codeword_ce,
reg_load_limit_codeword_rst => reg_load_limit_codeword_rst,
reg_calc_limit_codeword_ce => reg_calc_limit_codeword_ce,
reg_calc_limit_codeword_rst => reg_calc_limit_codeword_rst
);
calculator_units : for I in 0 to (syndrome_calculator_size - 1) generate
reg_L_I : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_L_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
clk => clk,
ce => reg_L_ce(I),
q => reg_L_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
reg_h_I : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_h_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
clk => clk,
ce => reg_h_ce(I),
rst => reg_h_rst(I),
rst_value => reg_h_rst_value,
q => reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
mult_I : mult_gf_2_m
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => mult_a(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
b => mult_b(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
o => mult_o(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
reg_L_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_load_L_q;
reg_h_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= mult_o(((I + 1)*gf_2_m - 1) downto I*gf_2_m) when sel_reg_h(I) = '1' else
reg_load_h_q;
mult_a(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m) when square_h = '1' else
reg_L_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m);
mult_b(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m);
reg_L_ce(I) <= int_reg_L_ce and control_units_q(I);
reg_h_ce(I) <= int_reg_h_ce and (control_units_q(I) or int_sel_reg_h);
reg_h_rst(I) <= int_reg_h_rst and control_units_q(I);
sel_reg_h(I) <= int_sel_reg_h;
end generate;
more_than_1 : if(number_of_syndrome_calculators > 1) generate
slave_units : for I in 1 to (number_of_syndrome_calculators - 1) generate
slave_I : syndrome_calculator_n_pipe_v3_slave
Generic Map(
initial_address => I,
increment_address => number_of_syndrome_calculators,
syndrome_calculator_size => syndrome_calculator_size,
gf_2_m => gf_2_m,
length_codeword => length_codeword,
size_codeword => size_codeword,
length_syndrome => length_syndrome,
size_syndrome => size_syndrome
)
Port Map(
clk => clk,
rst => rst,
value_h => value_h(((I+1)*(gf_2_m) - 1) downto (I)*(gf_2_m)),
value_L => value_L(((I+1)*(gf_2_m) - 1) downto (I)*(gf_2_m)),
value_codeword => value_codeword(I downto I),
start_calculation => start_calculation,
last_syndrome => last_syndrome,
ready_calculation => ready_calculation(I),
finished_calculation => finished_calculation(I),
new_value_syndrome => new_value_intermediate_syndrome(((I+1)*(gf_2_m) - 1) downto (I)*(gf_2_m)),
address_h => address_h(((I+1)*(size_codeword) - 1) downto (I)*(size_codeword)),
address_L => address_L(((I+1)*(size_codeword) - 1) downto (I)*(size_codeword)),
address_codeword => address_codeword(((I+1)*(size_codeword) - 1) downto (I)*(size_codeword))
);
end generate;
everyone_ready : and_reduce
Generic Map(
vector_size => 1,
number_of_vectors => number_of_syndrome_calculators
)
Port Map(
a => ready_calculation,
o(0) => start_calculation
);
final_adder : adder_gf_2_m
Generic Map(
gf_2_m => gf_2_m,
number_of_elements => number_of_syndrome_calculators
)
Port Map(
a => final_adder_a,
o => final_adder_o
);
final_adder_a <= new_value_intermediate_syndrome;
reg_new_value_syndrome_d <= final_adder_o;
syndrome_finalized <= slaves_finished and finished_calculation(0);
one_slave : if(number_of_syndrome_calculators = 2) generate
slaves_finished <= finished_calculation(1);
end generate;
more_than_one_slave : if(number_of_syndrome_calculators > 2) generate
all_slaves_finished : and_reduce
Generic Map(
vector_size => 1,
number_of_vectors => number_of_syndrome_calculators - 1
)
Port Map(
a => finished_calculation((number_of_syndrome_calculators - 1) downto 1),
o(0) => slaves_finished
);
end generate;
end generate;
just_master : if(number_of_syndrome_calculators = 1) generate
slaves_finished <= '1';
reg_new_value_syndrome_d <= new_value_intermediate_syndrome((gf_2_m - 1) downto 0);
start_calculation <= ready_calculation(0);
syndrome_finalized <= finished_calculation(0);
end generate;
control_units : shift_register_rst_nbits
Generic Map(
size => syndrome_calculator_size+1
)
Port Map(
data_in => control_units_data_out,
clk => clk,
ce => control_units_ce,
rst => control_units_rst,
rst_value => control_units_rst_value,
q => control_units_q,
data_out => control_units_data_out
);
adder : adder_gf_2_m
Generic Map(
gf_2_m => gf_2_m,
number_of_elements => syndrome_calculator_size+1
)
Port Map(
a => adder_a,
o => adder_o
);
reg_load_L : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_load_L_d,
clk => clk,
ce => reg_load_L_ce,
q => reg_load_L_q
);
reg_load_h : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_load_h_d,
clk => clk,
ce => reg_load_h_ce,
rst => reg_load_h_rst,
rst_value => reg_load_h_rst_value,
q => reg_load_h_q
);
reg_load_syndrome : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_load_syndrome_d,
clk => clk,
ce => reg_load_syndrome_ce,
rst => reg_load_syndrome_rst,
rst_value => reg_load_syndrome_rst_value,
q => reg_load_syndrome_q
);
reg_new_value_master_syndrome : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_master_syndrome_d,
clk => clk,
ce => reg_new_value_master_syndrome_ce,
q => reg_new_value_master_syndrome_q
);
reg_new_value_syndrome : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_syndrome_d,
clk => clk,
ce => reg_new_value_syndrome_ce,
q => reg_new_value_syndrome_q
);
reg_codeword : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_codeword_d,
clk => clk,
ce => reg_codeword_ce,
q => reg_codeword_q
);
reg_first_syndrome : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_first_syndrome_d,
clk => clk,
ce => reg_first_syndrome_ce,
rst => reg_first_syndrome_rst,
rst_value => reg_first_syndrome_rst_value,
q => reg_first_syndrome_q
);
ctr_load_address_syndrome : counter_decrement_rst_nbits
Generic Map(
size => size_syndrome,
decrement_value => 1
)
Port Map(
clk => clk,
ce => ctr_load_address_syndrome_ce,
rst => ctr_load_address_syndrome_rst,
rst_value => ctr_load_address_syndrome_rst_value,
q => ctr_load_address_syndrome_q
);
ctr_store_address_syndrome : counter_decrement_rst_nbits
Generic Map(
size => size_syndrome,
decrement_value => 1
)
Port Map(
clk => clk,
ce => ctr_store_address_syndrome_ce,
rst => ctr_store_address_syndrome_rst,
rst_value => ctr_store_address_syndrome_rst_value,
q => ctr_store_address_syndrome_q
);
ctr_load_address_codeword : counter_rst_nbits
Generic Map(
size => size_codeword,
increment_value => number_of_syndrome_calculators
)
Port Map(
clk => clk,
ce => ctr_load_address_codeword_ce,
rst => ctr_load_address_codeword_rst,
rst_value => ctr_load_address_codeword_rst_value,
q => ctr_load_address_codeword_q
);
reg_load_limit_codeword : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_load_limit_codeword_d,
clk => clk,
ce => reg_load_limit_codeword_ce,
rst => reg_load_limit_codeword_rst,
rst_value => reg_load_limit_codeword_rst_value,
q => reg_load_limit_codeword_q
);
reg_calc_limit_codeword : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_calc_limit_codeword_d,
clk => clk,
ce => reg_calc_limit_codeword_ce,
rst => reg_calc_limit_codeword_rst,
rst_value => reg_calc_limit_codeword_rst_value,
q => reg_calc_limit_codeword_q
);
reg_load_limit_codeword_d(0) <= limit_ctr_codeword_q;
reg_calc_limit_codeword_d <= reg_load_limit_codeword_q;
adder_a <= reg_h_q & reg_load_syndrome_q;
reg_load_L_d <= value_L((gf_2_m - 1) downto 0);
reg_load_h_d <= value_h((gf_2_m - 1) downto 0);
reg_load_syndrome_d <= value_syndrome;
reg_codeword_d <= value_codeword(0 downto 0);
reg_first_syndrome_d <= "0";
reg_new_value_master_syndrome_d <= adder_o;
new_value_intermediate_syndrome((gf_2_m - 1) downto 0) <= reg_new_value_master_syndrome_q;
new_value_syndrome <= reg_new_value_syndrome_q;
address_h((size_codeword - 1) downto 0) <= ctr_load_address_codeword_q;
address_L((size_codeword - 1) downto 0) <= ctr_load_address_codeword_q;
address_codeword((size_codeword - 1) downto 0) <= ctr_load_address_codeword_q;
address_syndrome <= ctr_load_address_syndrome_q;
address_new_syndrome <= ctr_store_address_syndrome_q;
almost_units_ready <= control_units_q(syndrome_calculator_size - 1);
empty_units <= control_units_q(0);
limit_ctr_codeword_q <= '1' when (unsigned(ctr_load_address_codeword_q) >= (to_unsigned(length_codeword - number_of_syndrome_calculators, ctr_load_address_codeword_q'length))) else '0';
limit_ctr_syndrome_q <= '1' when (ctr_store_address_syndrome_q = std_logic_vector(to_unsigned(0, ctr_load_address_syndrome_q'length))) else '0';
last_syndrome <= limit_ctr_syndrome_q;
end Behavioral;
|
bsd-2-clause
|
af5a18e11c596302bf226c7e916fabd1
| 0.672961 | 2.787821 | false | false | false | false |
ruygargar/LCSE_lab
|
rs232/tb_RS232_RX.vhd
| 1 | 2,886 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:22:05 11/15/2013
-- Design Name:
-- Module Name: C:/Users/Silvia/Desktop/RS232 project/RS232/tb_RS232_RX.vhd
-- Project Name: RS232
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: RS232_RX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_RS232_RX IS
END tb_RS232_RX;
ARCHITECTURE behavior OF tb_RS232_RX IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RS232_RX
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
LineRD_in : IN std_logic;
Valid_out : OUT std_logic;
Code_out : OUT std_logic;
Store_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal LineRD_in : std_logic := '1';
--Outputs
signal Valid_out : std_logic;
signal Code_out : std_logic;
signal Store_out : std_logic;
-- Clock period definitions
constant Clk_period : time := 50 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RS232_RX PORT MAP (
Clk => Clk,
Reset => Reset,
LineRD_in => LineRD_in,
Valid_out => Valid_out,
Code_out => Code_out,
Store_out => Store_out
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc_1: process
begin
Reset <= '0';
wait for 200 ns;
Reset <= '1';
wait for 117800 ns;
end process;
stim_proc_2: process
begin
LineRD_in <= '1',
'0' after 500 ns, -- StartBit
'1' after 9150 ns, -- LSb
'0' after 17800 ns,
'1' after 26450 ns,
'0' after 35100 ns,
'1' after 43750 ns,
'0' after 52400 ns,
'1' after 61050 ns,
'1' after 69700 ns, -- MSb
'0' after 78350 ns, -- Stopbit
'1' after 87000 ns;
wait for 100000 ns;
end process;
END;
|
gpl-3.0
|
f3377a6d6bb8c39450bd10b6e10784ce
| 0.563063 | 3.657795 | false | true | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/arctg_lut/arctg_lut.vhd
| 1 | 1,742 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--Lookup table for the arctg values according to the step index of the CORDIC execution.
entity arctg_lut is
generic(TOTAL_BITS: integer := 32);
port(
step_index: in integer := 0;
angle: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end arctg_lut;
architecture arctg_lut_arq of arctg_lut is
constant max_index: integer := 15;
type arctgs_table is array (natural range <>) of std_logic_vector(TOTAL_BITS - 1 downto 0);
constant arctgs : arctgs_table := (
"00000000001011010000000000000000", ---45.0
"00000000000110101001000010100111", ---26.5650482178
"00000000000011100000100101000111", ---14.036239624
"00000000000001110010000000000001", ---7.12501525879
"00000000000000111001001110001010", ---3.57632446289
"00000000000000011100101000110111", ---1.7899017334
"00000000000000001110010100101010", ---0.895172119141
"00000000000000000111001010010110", ---0.447601318359
"00000000000000000011100101001011", ---0.22380065918
"00000000000000000001110010100101", ---0.111892700195
"00000000000000000000111001010010", ---0.0559387207031
"00000000000000000000011100101001", ---0.0279693603516
"00000000000000000000001110010100", ---0.0139770507812
"00000000000000000000000111001010", ---0.00698852539062
"00000000000000000000000011100101", ---0.00349426269531
"00000000000000000000000001110010" ---0.00173950195312
);
begin
process (step_index) is
begin
if(step_index > max_index) then
report "STEP NOT ALLOWED!!!" severity failure;
else
angle <= arctgs(step_index);
end if;
end process;
end architecture;
|
gpl-3.0
|
b41692ac33282287a7a8b4212f8cd65a
| 0.716418 | 3.995413 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/counter_decrement_rst_nbits.vhd
| 1 | 1,796 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_decrement_rst_n_bits
-- Module Name: Counter_decrement_rst_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Counter of size bits with reset signal, that only decrements when ce equals to 1.
-- The reset is synchronous and the value loaded during reset is defined by reset_value.
--
-- The circuits parameters
--
-- size :
--
-- The size of the counter in bits.
--
-- decrement_value :
--
-- The amount will be decremented each cycle.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_decrement_rst_nbits is
Generic (
size : integer;
decrement_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end counter_decrement_rst_nbits;
architecture Behavioral of counter_decrement_rst_nbits is
signal internal_value : UNSIGNED((size - 1) downto 0);
begin
process(clk, ce, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= unsigned(rst_value);
elsif(ce = '1') then
internal_value <= internal_value - to_unsigned(decrement_value, internal_value'Length);
else
null;
end if;
end if;
end process;
q <= std_logic_vector(internal_value);
end Behavioral;
|
bsd-2-clause
|
e4ceeceab23a8a0ff621efb67bba6570
| 0.618597 | 3.460501 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/cordic/cordic.vhd
| 1 | 3,829 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--This component applies CORDIC algorithm with STEPS steps. Keep in mind that the max valid steps is limited by the resolution of
--the fixed point representation and implementation of the angle_step_applier. In this case is 16
entity cordic is
generic(TOTAL_BITS: integer := 32; STEPS: integer := 16);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
angle: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end cordic;
architecture cordic_arq of cordic is
constant MAX_STEPS: integer := 16;
constant ZERO : std_logic_vector(TOTAL_BITS - 1 downto 0 ) := (others => '0');
type cordic_step is record
x: std_logic_vector(TOTAL_BITS - 1 downto 0);
y: std_logic_vector(TOTAL_BITS - 1 downto 0);
z: std_logic_vector(TOTAL_BITS -1 downto 0);
end record;
type cordic_steps_array is array (natural range <>) of cordic_step;
signal cordic_steps : cordic_steps_array(STEPS downto 0);
signal normalized_x : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
signal normalized_y : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
component angle_step_applier is
generic(TOTAL_BITS: integer := 32);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
z_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
step_index : in integer := 0;
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
z_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
component normalizer is
generic(TOTAL_BITS: integer := 32);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
steps_applied : in integer := 0;
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
begin
cordic_steps(0).x <= x_in;
cordic_steps(0).y <= y_in;
cordic_steps(0).z <= angle;
all_steps: for i in 0 to (STEPS - 1) generate
step : angle_step_applier
generic map(TOTAL_BITS => TOTAL_BITS)
port map(
x_in => cordic_steps(i).x,
y_in => cordic_steps(i).y,
z_in => cordic_steps(i).z,
step_index => i,
x_out => cordic_steps(i+1).x,
y_out => cordic_steps(i+1).y,
z_out => cordic_steps(i+1).z
);
end generate all_steps;
normalizer_0 : normalizer
generic map(TOTAL_BITS => TOTAL_BITS)
port map(
x_in => cordic_steps(STEPS).x,
y_in => cordic_steps(STEPS).y,
steps_applied => STEPS,
x_out => normalized_x,
y_out => normalized_y
);
x_out <= normalized_x when angle /= ZERO else x_in;
y_out <= normalized_y when angle /= ZERO else y_in;
end architecture;
|
gpl-3.0
|
3b7995617bde576fb3569ea19e212690
| 0.541656 | 3.595305 | false | false | false | false |
laurivosandi/hdl
|
zynq/src/ov7670_controller/ov7670_registers.vhd
| 1 | 5,263 |
-- Company:
-- Engineer: Mike Field <[email protected]>
--
-- Description: Register settings for the OV7670 Caamera (partially from OV7670.c
-- in the Linux Kernel
-- Edited by : Christopher Wilson <[email protected]>
------------------------------------------------------------------------------------
--
-- Notes:
-- 1) Regarding the WITH SELECT Statement:
-- WITH sreg(sel) SELECT
-- finished <= '1' when x"FFFF",
-- '0' when others;
-- This means the transfer is finished the first time sreg ends up as "FFFF",
-- I.E. Need Sequential Addresses in the below case statements
--
-- Common Debug Issues:
--
-- Red Appearing as Green / Green Appearing as Pink
-- Solution: Register Corrections Below
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_registers is
Port ( clk : in STD_LOGIC;
resend : in STD_LOGIC;
advance : in STD_LOGIC;
command : out std_logic_vector(15 downto 0);
finished : out STD_LOGIC);
end ov7670_registers;
architecture Behavioral of ov7670_registers is
signal sreg : std_logic_vector(15 downto 0);
signal address : std_logic_vector(7 downto 0) := (others => '0');
begin
command <= sreg;
with sreg select finished <= '1' when x"FFFF", '0' when others;
process(clk)
begin
if rising_edge(clk) then
if resend = '1' then
address <= (others => '0');
elsif advance = '1' then
address <= std_logic_vector(unsigned(address)+1);
end if;
case address is
when x"00" => sreg <= x"1280"; -- COM7 Reset
when x"01" => sreg <= x"1280"; -- COM7 Reset
when x"02" => sreg <= x"1204"; -- COM7 Size & RGB output
when x"03" => sreg <= x"1100"; -- CLKRC Prescaler - Fin/(1+1)
when x"04" => sreg <= x"0C00"; -- COM3 Lots of stuff, enable scaling, all others off
when x"05" => sreg <= x"3E00"; -- COM14 PCLK scaling off
when x"06" => sreg <= x"8C00"; -- RGB444 Set RGB format
when x"07" => sreg <= x"0400"; -- COM1 no CCIR601
when x"08" => sreg <= x"4010"; -- COM15 Full 0-255 output, RGB 565
when x"09" => sreg <= x"3a04"; -- TSLB Set UV ordering, do not auto-reset window
when x"0A" => sreg <= x"1438"; -- COM9 - AGC Celling
when x"0B" => sreg <= x"4f40"; --x"4fb3"; -- MTX1 - colour conversion matrix
when x"0C" => sreg <= x"5034"; --x"50b3"; -- MTX2 - colour conversion matrix
when x"0D" => sreg <= x"510C"; --x"5100"; -- MTX3 - colour conversion matrix
when x"0E" => sreg <= x"5217"; --x"523d"; -- MTX4 - colour conversion matrix
when x"0F" => sreg <= x"5329"; --x"53a7"; -- MTX5 - colour conversion matrix
when x"10" => sreg <= x"5440"; --x"54e4"; -- MTX6 - colour conversion matrix
when x"11" => sreg <= x"581e"; --x"589e"; -- MTXS - Matrix sign and auto contrast
when x"12" => sreg <= x"3dc0"; -- COM13 - Turn on GAMMA and UV Auto adjust
when x"13" => sreg <= x"1100"; -- CLKRC Prescaler - Fin/(1+1)
when x"14" => sreg <= x"1711"; -- HSTART HREF start (high 8 bits)
when x"15" => sreg <= x"1861"; -- HSTOP HREF stop (high 8 bits)
when x"16" => sreg <= x"32A4"; -- HREF Edge offset and low 3 bits of HSTART and HSTOP
when x"17" => sreg <= x"1903"; -- VSTART VSYNC start (high 8 bits)
when x"18" => sreg <= x"1A7b"; -- VSTOP VSYNC stop (high 8 bits)
when x"19" => sreg <= x"030a"; -- VREF VSYNC low two bits
when x"1A" => sreg <= x"0e61"; -- COM5(0x0E) 0x61
when x"1B" => sreg <= x"0f4b"; -- COM6(0x0F) 0x4B
when x"1C" => sreg <= x"1602"; --
when x"1D" => sreg <= x"1e37"; -- MVFP (0x1E) 0x07 -- FLIP AND MIRROR IMAGE 0x3x
when x"1E" => sreg <= x"2102";
when x"1F" => sreg <= x"2291";
when x"20" => sreg <= x"2907";
when x"21" => sreg <= x"330b";
when x"22" => sreg <= x"350b";
when x"23" => sreg <= x"371d";
when x"24" => sreg <= x"3871";
when x"25" => sreg <= x"392a";
when x"26" => sreg <= x"3c78"; -- COM12 (0x3C) 0x78
when x"27" => sreg <= x"4d40";
when x"28" => sreg <= x"4e20";
when x"29" => sreg <= x"6900"; -- GFIX (0x69) 0x00
when x"2A" => sreg <= x"6b4a";
when x"2B" => sreg <= x"7410";
when x"2C" => sreg <= x"8d4f";
when x"2D" => sreg <= x"8e00";
when x"2E" => sreg <= x"8f00";
when x"2F" => sreg <= x"9000";
when x"30" => sreg <= x"9100";
when x"31" => sreg <= x"9600";
when x"32" => sreg <= x"9a00";
when x"33" => sreg <= x"b084";
when x"34" => sreg <= x"b10c";
when x"35" => sreg <= x"b20e";
when x"36" => sreg <= x"b382";
when x"37" => sreg <= x"b80a";
when others => sreg <= x"ffff";
end case;
end if;
end process;
end Behavioral;
|
mit
|
80e2bc9d0a76372cf224c81d2ee25e97
| 0.497815 | 3.248765 | false | false | false | false |
ruygargar/LCSE_lab
|
alu/tb_alu.vhd
| 1 | 5,439 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:48:33 01/13/2014
-- Design Name:
-- Module Name: C:/Users/Ruy/Desktop/LCSE_lab/alu/tb_alu.vhd
-- Project Name: alu
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: alu
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.PIC_pkg.all;
ENTITY tb_alu IS
END tb_alu;
ARCHITECTURE behavior OF tb_alu IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT alu
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
u_instruction : IN alu_op;
FlagZ : OUT std_logic;
FlagC : OUT std_logic;
FlagN : OUT std_logic;
FlagE : OUT std_logic;
Index : OUT std_logic_vector(7 downto 0);
Databus : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal u_instruction : alu_op := nop;
--BiDirs
signal Databus : std_logic_vector(7 downto 0) := X"00";
--Outputs
signal FlagZ : std_logic;
signal FlagC : std_logic;
signal FlagN : std_logic;
signal FlagE : std_logic;
signal Index : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: alu PORT MAP (
Clk => Clk,
Reset => Reset,
u_instruction => u_instruction,
FlagZ => FlagZ,
FlagC => FlagC,
FlagN => FlagN,
FlagE => FlagE,
Index => Index,
Databus => Databus
);
Clk <= not Clk after Clk_period;
-- Stimulus process
stim_proc: process
begin
wait for 100 ns; -- Quitar reset y cargar A desde el bus de datos
Reset <= '1' after 1 ns;
wait for 25 ns;
Databus <= X"05" after 1 ns; -- 5
u_instruction <= op_lda after 1 ns;
wait for 50 ns; -- Cargar B desde el bus de datos
Databus <= X"FB" after 1 ns; -- -5
u_instruction <= op_ldb after 1 ns;
wait for 50 ns; -- Cargar ACC desde el bus de datos
Databus <= X"55" after 1 ns;
u_instruction <= op_ldacc after 1 ns;
wait for 50 ns; -- Cargar INDEX desde el bus de datos
Databus <= X"AA" after 1 ns;
u_instruction <= op_ldid after 1 ns;
wait for 50 ns; -- Suma
Databus <= X"00" after 1 ns;
u_instruction <= op_add after 1 ns;
wait for 50 ns; -- Resta
Databus <= X"00" after 1 ns;
u_instruction <= op_sub after 1 ns;
wait for 50 ns; -- Mueve ACC a INDEX
Databus <= X"00" after 1 ns;
u_instruction <= op_mvacc2id after 1 ns;
wait for 50 ns; -- Mueve ACC a A
Databus <= X"00" after 1 ns;
u_instruction <= op_mvacc2a after 1 ns;
wait for 50 ns; -- Mueve ACC a B
Databus <= X"00" after 1 ns;
u_instruction <= op_mvacc2b after 1 ns;
wait for 50 ns; -- XOR
Databus <= X"00" after 1 ns;
u_instruction <= op_xor after 1 ns;
wait for 50 ns; -- Compare <
Databus <= X"00" after 1 ns;
u_instruction <= op_cmpl after 1 ns;
wait for 50 ns; -- Compare =
Databus <= X"00" after 1 ns;
u_instruction <= op_cmpe after 1 ns;
wait for 50 ns; -- Carga en A
Databus <= X"FF" after 1 ns; -- FF
u_instruction <= op_lda after 1 ns;
wait for 50 ns; -- Carga en B
Databus <= X"80" after 1 ns; -- 80
u_instruction <= op_ldb after 1 ns;
wait for 50 ns; -- OR
Databus <= X"00" after 1 ns;
u_instruction <= op_or after 1 ns;
wait for 50 ns; -- AND
Databus <= X"00" after 1 ns;
u_instruction <= op_and after 1 ns;
wait for 50 ns; -- SUM
Databus <= X"00" after 1 ns;
u_instruction <= op_add after 1 ns;
wait for 50 ns; -- Compare >
Databus <= X"00" after 1 ns;
u_instruction <= op_cmpg after 1 ns;
wait for 50 ns; -- BIN 2 ASCII (con error)
Databus <= X"00" after 1 ns;
u_instruction <= op_bin2ascii after 1 ns;
wait for 50 ns; -- Carga en A
Databus <= X"08" after 1 ns;
u_instruction <= op_lda after 1 ns;
wait for 50 ns; -- BIN 2 ASCII (sin error)
Databus <= X"00" after 1 ns;
u_instruction <= op_bin2ascii after 1 ns;
wait for 50 ns; -- Carga ACC en A
Databus <= X"00" after 1 ns;
u_instruction <= op_mvacc2a after 1 ns;
wait for 50 ns; -- ASCII 2 BIN (sin error)
Databus <= X"00" after 1 ns;
u_instruction <= op_ascii2bin after 1 ns;
wait for 50 ns; -- Carga ACC en A
Databus <= X"00" after 1 ns;
u_instruction <= op_mvacc2a after 1 ns;
wait for 50 ns; -- Carga ACC en B
Databus <= X"00" after 1 ns;
u_instruction <= op_mvacc2b after 1 ns;
wait for 50 ns; -- Suma con acarreo de nibble
Databus <= X"00" after 1 ns;
u_instruction <= op_add after 1 ns;
wait for 50 ns; -- Saca ACC por el bus de datos
Databus <= (others => 'Z');
u_instruction <= op_oeacc after 1 ns;
wait;
end process;
END;
|
gpl-3.0
|
5b622e45a9e4985aba91d105505a16db
| 0.594043 | 3.218343 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/counter_rst_set_nbits.vhd
| 1 | 1,985 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_rst_set_n_bits
-- Module Name: Counter_rst_set_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Counter of size bits with reset and set signal, that only increments when ce equals to 1.
-- The reset and set are synchronous.
-- The value loaded during reset is defined by reset_value.
-- The value loaded during set is defined by set_value.
--
-- The circuits parameters
--
-- size :
--
-- The size of the counter in bits.
--
-- increment_value :
--
-- The amount will be incremented each cycle.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_rst_set_nbits is
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
set : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
set_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end counter_rst_set_nbits;
architecture Behavioral of counter_rst_set_nbits is
signal internal_value : UNSIGNED((size - 1) downto 0);
begin
process(clk, ce, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= unsigned(rst_value);
elsif(set = '1') then
internal_value <= unsigned(set_value);
elsif(ce = '1') then
internal_value <= internal_value + to_unsigned(increment_value, internal_value'Length);
else
null;
end if;
end if;
end process;
q <= std_logic_vector(internal_value);
end Behavioral;
|
bsd-2-clause
|
a3f0c273beff6f1242d5d8419518af8e
| 0.616625 | 3.358714 | false | false | false | false |
rodrigoazs/-7-5-Reed-Solomon
|
code/symbol_multiplier.vhd
| 1 | 2,678 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity SymbolMultiplier is
port( uncoded_a, uncoded_b:
in std_logic_vector(2 downto 0);
uncoded_multab: out std_logic_vector(2 downto 0)
);
end SymbolMultiplier;
architecture Behavioral of SymbolMultiplier is
component BinaryAdderSubtractor is
port( a,b: in std_logic_vector(3 downto 0);
fnc: in std_logic;
s_or_d: out std_logic_vector(3 downto 0)
);
end component;
component Mux6x3 is
Port ( a : in std_logic_vector(2 downto 0) ;
b : in std_logic_vector(2 downto 0) ;
s : in std_logic ;
f : out std_logic_vector(2 downto 0));
end component ;
component SymbolPowerDecoder is
Port ( n1 : in std_logic_vector(2 downto 0);
n1c : out std_logic_vector(2 downto 0));
end component;
component SymbolPowerEncoder is
Port ( n1 : in std_logic_vector(2 downto 0);
n1c : out std_logic_vector(2 downto 0));
end component;
signal iszero: std_logic;
signal zerov: std_logic_vector(2 downto 0);
signal s_or_d: std_logic_vector(3 downto 0);
signal a: std_logic_vector(2 downto 0);
signal b: std_logic_vector(2 downto 0);
signal uncoded_multab_poly: std_logic_vector(2 downto 0);
signal multab: std_logic_vector(2 downto 0);
signal sa: std_logic_vector(3 downto 0);
signal sb: std_logic_vector(3 downto 0);
signal tt: std_logic;
signal t7: std_logic_vector(3 downto 0);
signal tres: std_logic_vector(3 downto 0);
signal sa2: std_logic_vector(2 downto 0);
signal sb2: std_logic_vector(2 downto 0);
begin
iszero <= (uncoded_a(0) or uncoded_a(1) or uncoded_a(2))
and (uncoded_b(0) or uncoded_b(1) or uncoded_b(2));
encode1: SymbolPowerEncoder port map(uncoded_a, a);
encode2: SymbolPowerEncoder port map(uncoded_b, b);
sa(0) <= a(0);
sa(1) <= a(1);
sa(2) <= a(2);
sa(3) <= '0';
sb(0) <= b(0);
sb(1) <= b(1);
sb(2) <= b(2);
sb(3) <= '0';
fa0: BinaryAdderSubtractor port map(sa, sb, '0', s_or_d);
tt <= s_or_d(3) or (s_or_d(0) and s_or_d(1) and s_or_d(2));
t7(0) <= '1';
t7(1) <= '1';
t7(2) <= '1';
t7(3) <= '0';
fa1: BinaryAdderSubtractor port map(s_or_d, t7,'1',tres);
sa2(0) <= tres(0);
sa2(1) <= tres(1);
sa2(2) <= tres(2);
sb2(0) <= s_or_d(0);
sb2(1) <= s_or_d(1);
sb2(2) <= s_or_d(2);
mux1: Mux6x3 port map(sa2, sb2, tt, multab);
decode1: SymbolPowerDecoder port map(multab, uncoded_multab_poly);
zerov(0) <= '0';
zerov(1) <= '0';
zerov(2) <= '0';
mux2: Mux6x3 port map(uncoded_multab_poly, zerov, iszero, uncoded_multab);
end Behavioral;
|
mit
|
f77f7b9bacf6d6dd1a1af1747c5163e8
| 0.668783 | 2.575 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/multiplication/mantissa_multiplier/mantissa_multiplier.vhd
| 1 | 950 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mantissa_multiplier is
generic(
BITS:natural := 16
);
port (
man1_in: in std_logic_vector(BITS - 1 downto 0);
man2_in: in std_logic_vector(BITS - 1 downto 0);
result: out std_logic_vector(BITS + 1 downto 0) --Add one to shift if necessary
);
end;
architecture mantissa_multiplier_arq of mantissa_multiplier is
begin
process(man1_in, man2_in)
variable expanded_mantissa_1 : std_logic_vector(BITS downto 0) := (others => '0');
variable expanded_mantissa_2 : std_logic_vector(BITS downto 0) := (others => '0');
variable tmp_result: std_logic_vector((BITS*2) + 1 downto 0) := (others => '0');
begin
expanded_mantissa_1 := '1' & man1_in;
expanded_mantissa_2 := '1' & man2_in;
tmp_result := std_logic_vector(unsigned(expanded_mantissa_1) * unsigned(expanded_mantissa_2));
result <= tmp_result(BITS*2 + 1 downto BITS);
end process;
end architecture;
|
gpl-3.0
|
5fb2866b0ad34cc49b8fb1c77539d69b
| 0.693684 | 2.941176 | false | false | false | false |
jgibbard/fir_filter
|
fir_filter.vhd
| 1 | 8,080 |
---------------------------------------------------------------------------
-- Project : FIR Filter
-- Author : James Gibbard ([email protected])
-- Date : 2017-03-26
-- File : fir_filter.vhd
-- Module : fir_filter
---------------------------------------------------------------------------
-- Description : FIR filter sharing a single multipler.
-- Ready signal
---------------------------------------------------------------------------
-- Change Log
-- Version 0.0.1 : Initial version
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all; --Only used for log2/ceil calc for constant (not synthesised)
use work.signed_array_pkg.all;
entity fir_filter is
generic (
data_in_width_g : integer := 16;
data_out_width_g : integer := 16;
--If num_taps_g is changed the type of the taps port must also be changed to match.
--num_taps_g should not exceed 256. Above this size block ram should be used to store coefficients and delay pipeline
num_taps_g : integer := 15
);
port (
clk : in std_logic;
rst : in std_logic;
en_in : in std_logic;
data_in : in signed(data_in_width_g - 1 downto 0);
taps_in : in signed_array_15;
scale_factor_in : in unsigned(5 downto 0); --Set to >= log2(accumulator_size)
data_valid_in : in std_logic;
data_out : out signed(data_out_width_g - 1 downto 0);
data_valid_out : out std_logic;
ready_out : out std_logic
);
end fir_filter;
architecture behavioural of fir_filter is
--For worst case accumulator_size must be >= data_in_width_g + pkg_coefficient_width + log2(num_taps_g)
constant accumulator_size : integer := data_in_width_g + pkg_coefficient_width + integer(ceil(log2(real(num_taps_g))));
--Delay pipeline to store input sample history
type delay_array_t is array (0 to num_taps_g - 1) of signed(data_in_width_g - 1 downto 0);
signal delay_pipeline : delay_array_t;
--Counter to drive MUX address lines
signal tap_counter : unsigned(7 downto 0);
--State machine signals
type state_t is (idle_s, go_s, wait_s, done_s);
signal next_state, current_state : state_t;
--Internal signals to control module's operation
signal done : std_logic;
signal ready : std_logic;
signal counter_en : std_logic;
signal mac_clear : std_logic;
--Output of MAC unit.
signal accum : signed(accumulator_size - 1 downto 0);
--Mux output signals
signal current_tap : signed(data_in_width_g - 1 downto 0);
signal current_delay : signed(data_in_width_g - 1 downto 0);
begin
--Synchronously advance the state machine
state_machine_advance_p : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
current_state <= idle_s;
else
current_state <= next_state;
end if;
end if;
end process;
state_machine_p : process(current_state, data_valid_in, tap_counter)
begin
next_state <= current_state;
counter_en <= '0';
ready <= '0';
done <= '0';
case current_state is
when idle_s =>
--Wait until a valid input is recieved
ready <= '1';
if data_valid_in = '1' then
next_state <= go_s;
end if;
when go_s =>
--Start the tap counter
counter_en <= '1';
if tap_counter = num_taps_g - 1 then
next_state <= wait_s;
end if;
when wait_s =>
--Wait one clock cycle for MAC to finish
next_state <= done_s;
when done_s =>
--Set the done signal high for one clock cycle
--The MAC unit is reset in this state
ready <= '1';
done <= '1';
next_state <= idle_s;
when others =>
next_state <= idle_s;
end case;
end process;
--To avoid feeding in 2 values everytime ready is set it is ANDed with
--the inverse of data_valid_in. Infact, the next_state signal is used instead as it changes to go_s
--when data_valid_in is high and stays at go_s for multiple clock cycles
--reducing the risk of glitches.
ready_out <= '1' when ready = '1' and next_state /= go_s else '0';
--While waiting for more samples hold the module in reset
mac_clear <= ready;
--Stores the last num_taps_g inputs for use in the FIR calculation
delay_pipeline_p : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
delay_pipeline <= (others => (others => '0'));
else
if data_valid_in = '1' then
--Add new value to pipeline
delay_pipeline(0) <= data_in;
--Shift rest of pipeline
for i in 1 to num_taps_g-1 loop
delay_pipeline(i) <= delay_pipeline(i-1);
end loop;
--else
--Shift whole pipeline (ring buffer)
-- delay_pipeline(0) <= delay_pipeline(num_taps_g - 1);
-- for i in 1 to num_taps_g-1 loop
-- delay_pipeline(i) <= delay_pipeline(i-1);
-- end loop;
end if;
end if;
end if;
end process;
--Counts from 0 to num_taps_g - 1
--Used to set address lines of MUX to select which
--Tap and delay values to multiply
counter_p : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
tap_counter <= (others => '0');
else
if counter_en = '1' then
if tap_counter = num_taps_g - 1 then
tap_counter <= (others => '0');
else
tap_counter <= tap_counter + 1;
end if;
end if;
end if;
end if;
end process;
--Multiplexer to select tap and delay values to pass to the MAC unit
current_tap <= taps_in(to_integer(tap_counter));
current_delay <= delay_pipeline(to_integer(tap_counter));
--Instantiates the MAC unit
--Uint has a 2 cycle latency (both multiply and sum operations are registered)
multiply_accumulate_i : entity work.mac_module
generic map (
a_in_size => data_in_width_g,
b_in_size => pkg_coefficient_width,
accumulator_size => accumulator_size
)
port map (
clk => clk,
rst => mac_clear,
en_in => '1',
a_in => current_delay,
b_in => current_tap,
accum_out => accum
);
--Register the output for the FIR filter
output_reg_p : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
data_out <= (others => '0');
data_valid_out <= '0';
else
--Divide output by 2^scale_factor
data_out <= accum(to_integer(scale_factor_in) + data_out_width_g - 1 downto to_integer(scale_factor_in));
data_valid_out <= done;
end if;
end if;
end process;
end behavioural;
|
unlicense
|
423361ef87c64d34ae5aa40f78ce415f
| 0.483416 | 4.304742 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/ram_bank_file.vhd
| 1 | 4,773 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: RAM_Bank
-- Module Name: RAM_Bank_File
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavioral of a memory RAM bank. Only used for tests.
-- In this bank all memories are accessed at the same time, therefore it is like
-- to access one big memory with memory word multiplied by number of memories in the bank.
-- It is useful when you want to access more than one location at the same time.
--
-- The circuits parameters
--
-- number_of_memories :
--
-- The total number of memories inside of the memory bank.
--
-- ram_address_size :
--
-- Address size of each RAM in the RAM bank used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word of each RAM in the RAM bank.
--
-- file_ram_word_size :
--
-- The size of the word used in the file to be loaded on each RAM.(ARCH: FILE_LOAD)
--
-- load_file_name :
--
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
--
-- The name of the file to be used to dump the memory.(ARCH: FILE_LOAD)
--
-- Dependencies:
-- VHDL-93
--
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
architecture file_load of ram_bank is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
pure function load_ram (ram_file_name : in string) return ramtype is
FILE ram_file : text is in ram_file_name;
variable line_n : line;
variable memory_ram : ramtype;
variable file_read_buffer : std_logic_vector((file_ram_word_size - 1) downto 0);
variable file_buffer_amount : integer;
variable ram_buffer_amount : integer;
begin
file_buffer_amount := file_ram_word_size;
for I in ramtype'range loop
ram_buffer_amount := 0;
if (not endfile(ram_file) or (file_buffer_amount /= file_ram_word_size)) then
while ram_buffer_amount /= ram_word_size loop
if file_buffer_amount = file_ram_word_size then
if (not endfile(ram_file)) then
readline (ram_file, line_n);
read (line_n, file_read_buffer);
else
file_read_buffer := (others => '0');
end if;
file_buffer_amount := 0;
end if;
memory_ram(I)(ram_buffer_amount) := file_read_buffer(file_buffer_amount);
ram_buffer_amount := ram_buffer_amount + 1;
file_buffer_amount := file_buffer_amount + 1;
end loop;
else
memory_ram(I) := (others => '0');
end if;
end loop;
return memory_ram;
end function;
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype := load_ram(load_file_name);
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
memory_ram <= load_ram(load_file_name);
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address)) + index) <= data_in(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
for index in 0 to (number_of_memories - 1) loop
data_out(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address)) + index);
end loop;
end if;
end process;
end file_load;
|
bsd-2-clause
|
144f18b072e0511ca9a0dfebeee975f2
| 0.514142 | 3.921939 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/pipeline_polynomial_calc_v3.vhd
| 1 | 5,082 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Pipeline_Polynomial_Calc_v3
-- Module Name: Pipeline_Polynomial_Calc_v3
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st and 3rd step in Goppa Code Decoding.
--
-- This circuit is to be used inside polynomial_syndrome_computing_n to evaluate polynomials
-- or generate the syndrome.
-- This circuit is the essential for 1 pipeline, therefor all stages are composed in here.
-- For more than 1 pipeline, only in polynomial_syndrome_computing_n with the shared components
-- for all pipelines.
--
-- For the computation this circuit applies the Horner scheme, where at each stage
-- an accumulator is multiplied by respective x and then added accumulated with coefficient.
-- In Horner scheme algorithm, it begin from the most significative coefficient until reaches
-- lesser significative coefficient.
--
-- For area reduction this circuit were optimized in version pipeline_polynomial_calc_v3
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- size :
--
-- The number of stages the pipeline has. More stages means more values of value_polynomial
-- are tested at once.
--
-- Dependencies:
-- VHDL-93
--
-- stage_polynomial_calc_v3 Rev 1.0
-- register_nbits Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pipeline_polynomial_calc_v3 is
Generic (
gf_2_m : integer range 1 to 20;
size : integer
);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((((gf_2_m)*size) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((size - 1) downto 0);
reg_x_rst : in STD_LOGIC_VECTOR((size - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((((gf_2_m)*size) - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end pipeline_polynomial_calc_v3;
architecture Behavioral of pipeline_polynomial_calc_v3 is
component stage_polynomial_calc_v3
Generic(gf_2_m : integer range 1 to 20 := 11);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial_coefficient : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC;
mode_polynomial_syndrome : in STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component register_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
type array_std_logic_vector is array(integer range <>) of STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal acc_d : array_std_logic_vector((size) downto 0);
signal acc_q : array_std_logic_vector((size) downto 0);
signal x_d : array_std_logic_vector((size) downto 0);
signal x_q : array_std_logic_vector((size - 1) downto 0);
constant reg_x_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(1, gf_2_m));
begin
x_d(0) <= value_x;
acc_d(0) <= value_acc;
pipeline : for I in 0 to (size - 1) generate
reg_x_I : register_rst_nbits
Generic Map(size => gf_2_m)
Port Map(
d => x_d(I),
clk => clk,
ce => '1',
rst => reg_x_rst(I),
rst_value => reg_x_rst_value,
q => x_q(I)
);
reg_acc_I : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => acc_d(I),
clk => clk,
ce => '1',
q => acc_q(I)
);
stage_I : stage_polynomial_calc_v3
Generic Map(gf_2_m => gf_2_m)
Port Map (
value_x => x_q(I),
value_polynomial_coefficient => value_polynomial(((gf_2_m)*(I+1) - 1) downto ((gf_2_m)*(I))),
mode_polynomial_syndrome => mode_polynomial_syndrome,
value_acc => acc_q(I),
value_codeword => value_codeword(I),
new_value_syndrome => new_value_syndrome(((gf_2_m)*(I+1) - 1) downto ((gf_2_m)*(I))),
new_value_acc => acc_d(I+1)
);
x_d(I+1) <= x_q(I);
end generate;
reg_acc_last : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => acc_d(size),
clk => clk,
ce => '1',
q => acc_q(size)
);
new_value_acc <= acc_q(size);
end Behavioral;
|
bsd-2-clause
|
ab70616c1bd68ea16864643802dd1b12
| 0.644038 | 2.94438 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/tb_mceliece_qd_goppa_decrypt_v2.vhd
| 1 | 32,099 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_McEliece_QD-Goppa_Decrypt_v2
-- Module Name: Tb_McEliece_QD-Goppa_Decrypt_v2
-- Project Name: McEliece Goppa Decryption
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This test bench tests mceliece_qd_goppa_decrypt_v2 circuit.
-- The test is done only for one value loaded into memories, and in the end the output
-- memories are verified.
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- number_of_polynomial_evaluator_syndrome_pipelines :
--
-- The number of pipelines in polynomial_syndrome_computing_n circuit.
-- This number can be 1 or greater.
--
-- polynomial_evaluator_syndrome_pipeline_size :
--
-- This is the number of stages on polynomial_syndrome_computing_n circuit.
-- This number can be 2 or greater.
--
-- polynomial_evaluator_syndrome_size_pipeline_size :
--
-- The number of bits necessary to hold the number of stages on the pipeline.
-- This is ceil(log2(polynomial_evaluator_syndrome_pipeline_size))
--
-- gf_2_m :
--
-- The size of the finite field extension used in this circuit.
-- This values depends of the Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword in this Goppa code.
-- This values depends of the Goppa code used.
--
-- size_codeword :
--
-- The number of bits necessary to store an array of codeword lengths.
-- This is ceil(log2(length_codeword))
--
-- number_of_errors :
--
-- The number of errors the Goppa code is able to decode.
-- This values depends of the Goppa code used.
--
-- size_number_of_errors :
--
-- The number of bits necessary to store an array of number of errors + 1 length.
-- This is ceil(log2(number_of_errors+1))
--
-- file_memory_L :
--
-- This file stores the private key, support elements L.
--
-- file_memory_h :
--
-- This file stores the private key, the inverted evaluation of all support elements L
-- into polynomial g, aka g(L)^(-1)
--
-- file_memory_codeword :
--
-- This file stores the ciphertext that will be decrypted.
--
-- file_memory_message :
--
-- This file stores the plaintext obtained by decrypting the ciphertext.
-- This is necessary to verify if the circuit decrypted correctly the ciphertext.
--
-- file_memory_error :
--
-- This file stores the error array added to the codeword to transform into the ciphertext.
-- This is necessary to verify if the circuit decrypted correctly the ciphertext.
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- mceliece_qd_goppa_decrypt_v2 Rev 1.0
-- ram Rev 1.0
-- ram_double Rev 1.0
-- ram_bank Rev 1.0
-- ram_double_bank Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_mceliece_qd_goppa_decrypt_v2 is
Generic(
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 18;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 6;
-- length_codeword : integer := 52;
-- size_codeword : integer := 6;
-- number_of_errors : integer := 4;
-- size_number_of_errors : integer := 3;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_52_28_4_6.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_52_28_4_6.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_52_28_4_6.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_52_28_4_6.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_52_28_4_6.dat"
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 2;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 8;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 4;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 27;
-- size_number_of_errors : integer := 5;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_2048_1751_27_11.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_2048_1751_27_11.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_2048_1751_27_11.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_goppa_2048_1751_27_11.dat";
-- file_memory_error : string := "mceliece/data_tests/error_goppa_2048_1751_27_11.dat"
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 18;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 50;
-- size_number_of_errors : integer := 6;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_2048_1498_50_11.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_2048_1498_50_11.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_2048_1498_50_11.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_goppa_2048_1498_50_11.dat";
-- file_memory_error : string := "mceliece/data_tests/error_goppa_2048_1498_50_11.dat"
-- GOPPA [3307, 2515, 66, 12] --
number_of_polynomial_evaluator_syndrome_pipelines : integer := 2;
polynomial_evaluator_syndrome_pipeline_size : integer := 17;
polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
gf_2_m : integer range 1 to 20 := 12;
length_codeword : integer := 3307;
size_codeword : integer := 12;
number_of_errors : integer := 66;
size_number_of_errors : integer := 7;
file_memory_L : string := "mceliece/data_tests/L_goppa_3307_2515_66_12.dat";
file_memory_h : string := "mceliece/data_tests/h_goppa_3307_2515_66_12.dat";
file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_3307_2515_66_12.dat";
file_memory_message : string := "mceliece/data_tests/plaintext_goppa_3307_2515_66_12.dat";
file_memory_error : string := "mceliece/data_tests/error_goppa_3307_2515_66_12.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 32;
-- size_number_of_errors : integer := 6;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_2528_2144_32_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_2528_2144_32_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_2528_2144_32_12.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_2528_2144_32_12.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_2528_2144_32_12.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 18;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_2816_2048_64_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_2816_2048_64_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_2816_2048_64_12.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_2816_2048_64_12.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 18;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_3328_2560_64_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_3328_2560_64_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_3328_2560_64_12.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_3328_2560_64_12.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 2;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 18;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- number_of_errors : integer := 128;
-- size_number_of_errors : integer := 8;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_7296_5632_128_13.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_7296_5632_128_13.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_7296_5632_128_13.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_7296_5632_128_13.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_7296_5632_128_13.dat"
);
end tb_mceliece_qd_goppa_decrypt_v2;
architecture Behavioral of tb_mceliece_qd_goppa_decrypt_v2 is
component ram
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component ram_double
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component ram_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component ram_double_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component mceliece_qd_goppa_decrypt_v2
Generic(
number_of_polynomial_evaluator_syndrome_pipelines : integer;
polynomial_evaluator_syndrome_pipeline_size : integer;
polynomial_evaluator_syndrome_size_pipeline_size : integer;
gf_2_m : integer range 1 to 20;
length_codeword : integer;
size_codeword : integer;
number_of_errors : integer;
size_number_of_errors : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_L : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
value_G : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_B : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma_evaluated : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
syndrome_generation_finalized : out STD_LOGIC;
key_equation_finalized : out STD_LOGIC;
decryption_finalized : out STD_LOGIC;
address_value_h : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_L : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_codeword : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_G : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_B : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_G : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_B : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_sigma : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_error : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_G : out STD_LOGIC;
write_enable_new_value_B : out STD_LOGIC;
write_enable_new_value_sigma : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_new_value_error : out STD_LOGIC;
write_enable_new_value_sigma_evaluated : out STD_LOGIC;
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_G : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_B : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_error : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal value_h : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal value_L : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_codeword : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_sigma : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_sigma_evaluated : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal syndrome_generation_finalized : STD_LOGIC;
signal key_equation_finalized : STD_LOGIC;
signal decryption_finalized : STD_LOGIC;
signal address_value_h : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_value_L : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_value_syndrome : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_codeword : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_sigma : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_sigma_evaluated : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_sigma : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_message : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal new_value_error : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal new_value_sigma_evaluated : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal write_enable_new_value_syndrome : STD_LOGIC;
signal write_enable_new_value_G : STD_LOGIC;
signal write_enable_new_value_B : STD_LOGIC;
signal write_enable_new_value_sigma : STD_LOGIC;
signal write_enable_new_value_message : STD_LOGIC;
signal write_enable_new_value_error : STD_LOGIC;
signal write_enable_new_value_sigma_evaluated : STD_LOGIC;
signal address_new_value_syndrome : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_sigma : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_message : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_new_value_error : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_new_value_sigma_evaluated : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal true_address_new_value_message : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal true_value_message : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal test_value_message : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal true_address_new_value_error : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal true_value_error : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal test_value_error : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal error_value_message : STD_LOGIC;
signal error_value_error : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
begin
test : mceliece_qd_goppa_decrypt_v2
Generic Map(
number_of_polynomial_evaluator_syndrome_pipelines => number_of_polynomial_evaluator_syndrome_pipelines,
polynomial_evaluator_syndrome_pipeline_size => polynomial_evaluator_syndrome_pipeline_size,
polynomial_evaluator_syndrome_size_pipeline_size => polynomial_evaluator_syndrome_size_pipeline_size,
gf_2_m => gf_2_m,
length_codeword => length_codeword,
size_codeword => size_codeword,
number_of_errors => number_of_errors,
size_number_of_errors => size_number_of_errors
)
Port Map(
clk => clk,
rst => rst,
value_h => value_h,
value_L => value_L,
value_syndrome => value_syndrome,
value_codeword => value_codeword,
value_G => value_G,
value_B => value_B,
value_sigma => value_sigma,
value_sigma_evaluated => value_sigma_evaluated,
syndrome_generation_finalized => syndrome_generation_finalized,
key_equation_finalized => key_equation_finalized,
decryption_finalized => decryption_finalized,
address_value_h => address_value_h,
address_value_L => address_value_L,
address_value_syndrome => address_value_syndrome,
address_value_codeword => address_value_codeword,
address_value_G => address_value_G,
address_value_B => address_value_B,
address_value_sigma => address_value_sigma,
address_value_sigma_evaluated => address_value_sigma_evaluated,
new_value_syndrome => new_value_syndrome,
new_value_G => new_value_G,
new_value_B => new_value_B,
new_value_sigma => new_value_sigma,
new_value_message => new_value_message,
new_value_error => new_value_error,
new_value_sigma_evaluated => new_value_sigma_evaluated,
write_enable_new_value_syndrome => write_enable_new_value_syndrome,
write_enable_new_value_G => write_enable_new_value_G,
write_enable_new_value_B => write_enable_new_value_B,
write_enable_new_value_sigma => write_enable_new_value_sigma,
write_enable_new_value_message => write_enable_new_value_message,
write_enable_new_value_error => write_enable_new_value_error,
write_enable_new_value_sigma_evaluated => write_enable_new_value_sigma_evaluated,
address_new_value_syndrome => address_new_value_syndrome,
address_new_value_G => address_new_value_G,
address_new_value_B => address_new_value_B,
address_new_value_sigma => address_new_value_sigma,
address_new_value_message => address_new_value_message,
address_new_value_error => address_new_value_error,
address_new_value_sigma_evaluated => address_new_value_sigma_evaluated
);
mem_L : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => file_memory_L,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_value_L,
rst_value => (others => '0'),
data_out => value_L
);
mem_h : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => file_memory_h,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_value_h,
rst_value => (others => '0'),
data_out => value_h
);
mem_codeword : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => file_memory_codeword,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_value_codeword,
rst_value => (others => '0'),
data_out => value_codeword
);
mem_sigma_evaluated : entity work.ram_double_bank(simple)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_sigma_evaluated,
rw_a => '0',
rw_b => write_enable_new_value_sigma_evaluated,
clk => clk,
rst => rst,
dump => '0',
address_a => address_value_sigma_evaluated,
address_b => address_new_value_sigma_evaluated,
rst_value => (others => '0'),
data_out_a => value_sigma_evaluated,
data_out_b => open
);
test_mem_message : entity work.ram_double_bank(simple)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => new_value_message,
data_in_b => (others => '0'),
rw_a => write_enable_new_value_message,
rw_b => '0',
clk => clk,
rst => rst,
dump => '0',
address_a => address_new_value_message,
address_b => true_address_new_value_message,
rst_value => (others => '0'),
data_out_a => open,
data_out_b => test_value_message
);
test_mem_error : entity work.ram_double_bank(simple)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => new_value_error,
data_in_b => (others => '0'),
rw_a => write_enable_new_value_error,
rw_b => '0',
clk => clk,
rst => rst,
dump => '0',
address_a => address_new_value_error,
address_b => true_address_new_value_error,
rst_value => (others => '0'),
data_out_a => open,
data_out_b => test_value_error
);
true_mem_message : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => file_memory_message,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => true_address_new_value_message,
rst_value => (others => '0'),
data_out => true_value_message
);
true_mem_error : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => file_memory_error,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => true_address_new_value_error,
rst_value => (others => '0'),
data_out => true_value_error
);
mem_syndrome : entity work.ram_double(simple)
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_syndrome,
rw_a => '0',
rw_b => write_enable_new_value_syndrome,
clk => clk,
rst => rst,
dump => '0',
address_a => address_value_syndrome,
address_b => address_new_value_syndrome,
rst_value => (others => '0'),
data_out_a => value_syndrome,
data_out_b => open
);
mem_G : entity work.ram_double(simple)
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_G,
rw_a => '0',
rw_b => write_enable_new_value_G,
clk => clk,
rst => rst,
dump => '0',
address_a => address_value_G,
address_b => address_new_value_G,
rst_value => (others => '0'),
data_out_a => value_G,
data_out_b => open
);
mem_B : entity work.ram_double(simple)
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_B,
rw_a => '0',
rw_b => write_enable_new_value_B,
clk => clk,
rst => rst,
dump => '0',
address_a => address_value_B,
address_b => address_new_value_B,
rst_value => (others => '0'),
data_out_a => value_B,
data_out_b => open
);
mem_sigma : entity work.ram_double(simple)
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_sigma,
rw_a => '0',
rw_b => write_enable_new_value_sigma,
clk => clk,
rst => rst,
dump => '0',
address_a => address_value_sigma,
address_b => address_new_value_sigma,
rst_value => (others => '0'),
data_out_a => value_sigma,
data_out_b => open
);
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
--clk <= not clk after PERIOD/2;
process
variable i : integer;
variable syndrome_cycle_count : integer range 0 to 2000000000 := 0;
variable key_equation_cycle_count : integer range 0 to 2000000000 := 0;
variable correct_errors_cycle_count : integer range 0 to 2000000000 := 0;
begin
true_address_new_value_message <= (others => '0');
true_address_new_value_error <= (others => '0');
rst <= '1';
error_value_message <= '0';
error_value_error <= '0';
wait for PERIOD*2;
rst <= '0';
wait until syndrome_generation_finalized = '1';
syndrome_cycle_count := cycle_count - 2;
report "Circuit finish Syndrome = " & integer'image(syndrome_cycle_count/2) & " cycles";
wait until key_equation_finalized = '1';
key_equation_cycle_count := cycle_count - syndrome_cycle_count;
report "Circuit finish Key Equation = " & integer'image(key_equation_cycle_count/2) & " cycles";
wait until decryption_finalized = '1';
correct_errors_cycle_count := cycle_count - key_equation_cycle_count - syndrome_cycle_count;
report "Circuit finish Correct Errors = " & integer'image(correct_errors_cycle_count/2) & " cycles";
report "Circuit finish = " & integer'image(cycle_count/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (length_codeword)) loop
true_address_new_value_message(size_codeword - 1 downto 0) <= std_logic_vector(to_unsigned(i, size_codeword));
true_address_new_value_error(size_codeword - 1 downto 0) <= std_logic_vector(to_unsigned(i, size_codeword));
wait for PERIOD*2;
if (true_value_message(0) = test_value_message(0)) then
error_value_message <= '0';
else
error_value_message <= '1';
report "Computed values do not match expected ones";
end if;
if (true_value_error(0) = test_value_error(0)) then
error_value_error <= '0';
else
error_value_error <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
error_value_message <= '0';
error_value_error <= '0';
wait for PERIOD;
i := i + number_of_polynomial_evaluator_syndrome_pipelines;
end loop;
wait for PERIOD;
test_bench_finish <= '1';
wait;
end process;
end Behavioral;
|
bsd-2-clause
|
1af2ad2194e193ea986f7622fe19dd6e
| 0.675286 | 2.906728 | false | true | false | false |
dtysky/3D_Displayer_Controller
|
VHDL_PLANB/DECODER/ROM.vhd
| 1 | 6,162 |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ROM IS
PORT
(
address : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END ROM;
ARCHITECTURE SYN OF rom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../DECODER/ROM.mif",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 8192,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 13,
width_a => 16,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../DECODER/ROM.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
-- Retrieval info: PRIVATE: WidthData NUMERIC "16"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../DECODER/ROM.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
106eba982943ea27d50c6f9fe54a559c
| 0.666991 | 3.56391 | false | false | false | false |
alainmarcel/Surelog
|
third_party/tests/ariane/fpga/src/apb_uart/src/slib_clock_div.vhd
| 5 | 2,036 |
--
-- Clock divider (clock enable generator)
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_clock_div is
generic (
RATIO : integer := 4 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end slib_clock_div;
architecture rtl of slib_clock_div is
-- Signals
signal iQ : std_logic; -- Internal Q
signal iCounter : integer range 0 to RATIO-1; -- Counter
begin
-- Main process
CD_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= 0;
iQ <= '0';
elsif (CLK'event and CLK='1') then
iQ <= '0';
if (CE = '1') then
if (iCounter = (RATIO-1)) then
iQ <= '1';
iCounter <= 0;
else
iCounter <= iCounter + 1;
end if;
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
|
apache-2.0
|
ce9be20fb1d168ad31333d2a3a370011
| 0.565324 | 4.063872 | false | false | false | false |
hitomi2500/wasca
|
fpga_firmware/sniff_fifo.vhd
| 1 | 7,040 |
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: sniff_fifo.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2018 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sniff_fifo IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
END sniff_fifo;
ARCHITECTURE SYN OF sniff_fifo IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (10 DOWNTO 0);
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
END COMPONENT;
BEGIN
empty <= sub_wire0;
full <= sub_wire1;
q <= sub_wire2(15 DOWNTO 0);
usedw <= sub_wire3(10 DOWNTO 0);
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "MAX 10",
lpm_numwords => 2048,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => 16,
lpm_widthu => 11,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
empty => sub_wire0,
full => sub_wire1,
q => sub_wire2,
usedw => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "2048"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "16"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "16"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: usedw 0 0 11 0 OUTPUT NODEFVAL "usedw[10..0]"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-- Retrieval info: CONNECT: usedw 0 0 11 0 @usedw 0 0 11 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
07ed31bf7d66f399427db8553fd38ddb
| 0.665909 | 3.532363 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/ram_multiple_access_file.vhd
| 1 | 5,089 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: RAM_multiple_access
-- Module Name: RAM_multiple_access_file
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavioral of multiple memory RAM that shares the same content.
-- It is useful when you want to access more than one location at the same time, and
-- the locations for each access can be anywhere in the memory, where in banks in most
-- time is one address after another.
-- It can be seen as one single with multiple I/O operating at the same time.
--
-- The circuits parameters
--
-- number_of_memories :
--
-- The total number of memories or the total number of I/O's applied.
--
-- ram_address_size :
--
-- Address size of the RAM used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word of the RAM.
--
-- file_ram_word_size :
--
-- The size of the word used in the file to be loaded on the RAM.(ARCH: FILE_LOAD)
--
-- load_file_name :
--
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
--
-- The name of the file to be used to dump the memory.(ARCH: FILE_LOAD)
--
-- Dependencies:
-- VHDL-93
--
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
architecture file_load of ram_multiple_access is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
pure function load_ram (ram_file_name : in string) return ramtype is
FILE ram_file : text is in ram_file_name;
variable line_n : line;
variable memory_ram : ramtype;
variable file_read_buffer : std_logic_vector((file_ram_word_size - 1) downto 0);
variable file_buffer_amount : integer;
variable ram_buffer_amount : integer;
begin
file_buffer_amount := file_ram_word_size;
for I in ramtype'range loop
ram_buffer_amount := 0;
if (not endfile(ram_file) or (file_buffer_amount /= file_ram_word_size)) then
while ram_buffer_amount /= ram_word_size loop
if file_buffer_amount = file_ram_word_size then
if (not endfile(ram_file)) then
readline (ram_file, line_n);
read (line_n, file_read_buffer);
else
file_read_buffer := (others => '0');
end if;
file_buffer_amount := 0;
end if;
memory_ram(I)(ram_buffer_amount) := file_read_buffer(file_buffer_amount);
ram_buffer_amount := ram_buffer_amount + 1;
file_buffer_amount := file_buffer_amount + 1;
end loop;
else
memory_ram(I) := (others => '0');
end if;
end loop;
return memory_ram;
end function;
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype := load_ram(load_file_name);
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
memory_ram <= load_ram(load_file_name);
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))) <= data_in(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
for index in 0 to (number_of_memories - 1) loop
data_out(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index)))));
end loop;
end if;
end process;
end file_load;
|
bsd-2-clause
|
8d265931f360d9effed771edb611bde8
| 0.527019 | 3.84947 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/controller_syndrome_calculator_2_pipe_v3_slave.vhd
| 1 | 18,645 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Syndrome_Calculator_2_pipe_v3_slave
-- Module Name: Controller_Syndrome_Calculator_2_pipe_v3_slave
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st step in Goppa Code Decoding.
--
-- This circuit is the state machine that controls the syndrome_calculator_n_pipe_v3_slave
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_syndrome_calculator_2_pipe_v3_slave is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
almost_units_ready : in STD_LOGIC;
empty_units : in STD_LOGIC;
limit_ctr_codeword_q : in STD_LOGIC;
reg_codeword_q : in STD_LOGIC_VECTOR(0 downto 0);
start_calculation : in STD_LOGIC;
last_syndrome : in STD_LOGIC;
ready_calculation : out STD_LOGIC;
finished_calculation : out STD_LOGIC;
control_units_ce : out STD_LOGIC;
control_units_rst : out STD_LOGIC;
int_reg_L_ce : out STD_LOGIC;
square_h : out STD_LOGIC;
int_reg_h_ce : out STD_LOGIC;
int_reg_h_rst : out STD_LOGIC;
int_sel_reg_h : out STD_LOGIC;
reg_load_L_ce : out STD_LOGIC;
reg_load_h_ce : out STD_LOGIC;
reg_load_h_rst : out STD_LOGIC;
reg_new_value_syndrome_ce : out STD_LOGIC;
reg_new_value_syndrome_rst : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
ctr_load_address_codeword_ce : out STD_LOGIC;
ctr_load_address_codeword_rst : out STD_LOGIC;
reg_load_limit_codeword_rst : out STD_LOGIC;
reg_load_limit_codeword_ce : out STD_LOGIC;
reg_calc_limit_codeword_rst : out STD_LOGIC;
reg_calc_limit_codeword_ce : out STD_LOGIC
);
end controller_syndrome_calculator_2_pipe_v3_slave;
architecture Behavioral of controller_syndrome_calculator_2_pipe_v3_slave is
type State is (reset, load_counters, prepare_values, load_values, jump_codeword, clear_remaining_units, wait_for_other_units, prepare_synd, prepare_synd_2, prepare_synd_3, load_store_synd, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, limit_ctr_codeword_q, reg_codeword_q, start_calculation, last_syndrome, almost_units_ready, empty_units)
begin
case (actual_state) is
when reset =>
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
reg_load_limit_codeword_rst <= '1';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '1';
reg_calc_limit_codeword_ce <= '0';
when load_counters =>
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
reg_load_limit_codeword_rst <= '1';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '1';
reg_calc_limit_codeword_ce <= '0';
when prepare_values =>
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
when load_values =>
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '1';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
when jump_codeword =>
if(reg_codeword_q(0) = '1') then
if(almost_units_ready = '1') then
ready_calculation <= '1';
finished_calculation <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '1';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '1';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
elsif(limit_ctr_codeword_q = '1') then
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '1';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '1';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
else
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '1';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '1';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
end if;
elsif(limit_ctr_codeword_q = '1') then
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '1';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
else
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '1';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
end if;
when clear_remaining_units =>
if(almost_units_ready = '1') then
ready_calculation <= '1';
finished_calculation <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '1';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
else
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '1';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
end if;
when wait_for_other_units =>
ready_calculation <= '1';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
when prepare_synd =>
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '1';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
when prepare_synd_2 =>
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
when prepare_synd_3 =>
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
when load_store_synd =>
if(last_syndrome = '1') then
if(limit_ctr_codeword_q = '1') then
ready_calculation <= '0';
finished_calculation <= '1';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
else
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
end if;
else
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_new_value_syndrome_rst <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
end if;
when final =>
ready_calculation <= '1';
finished_calculation <= '1';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_new_value_syndrome_rst <= '1';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '1';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '1';
reg_calc_limit_codeword_ce <= '0';
when others =>
ready_calculation <= '0';
finished_calculation <= '0';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
reg_load_limit_codeword_rst <= '1';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '1';
reg_calc_limit_codeword_ce <= '0';
end case;
end process;
NewState: process (actual_state, limit_ctr_codeword_q, reg_codeword_q, start_calculation, last_syndrome, almost_units_ready, empty_units)
begin
case (actual_state) is
when reset =>
next_state <= load_counters;
when load_counters =>
next_state <= prepare_values;
when prepare_values =>
next_state <= load_values;
when load_values =>
next_state <= jump_codeword;
when jump_codeword =>
if(reg_codeword_q(0) = '1') then
if(almost_units_ready = '1') then
if(start_calculation = '1') then
next_state <= prepare_synd;
else
next_state <= wait_for_other_units;
end if;
elsif(limit_ctr_codeword_q = '1') then
next_state <= clear_remaining_units;
else
next_state <= jump_codeword;
end if;
elsif(limit_ctr_codeword_q = '1') then
if(empty_units = '1') then
next_state <= final;
else
next_state <= clear_remaining_units;
end if;
else
next_state <= jump_codeword;
end if;
when clear_remaining_units =>
if(almost_units_ready = '1') then
if(start_calculation = '1') then
next_state <= prepare_synd;
else
next_state <= wait_for_other_units;
end if;
else
next_state <= clear_remaining_units;
end if;
when wait_for_other_units =>
if(start_calculation = '1') then
next_state <= prepare_synd;
else
next_state <= wait_for_other_units;
end if;
when prepare_synd =>
next_state <= prepare_synd_2;
when prepare_synd_2 =>
next_state <= prepare_synd_3;
when prepare_synd_3 =>
next_state <= load_store_synd;
when load_store_synd =>
if(last_syndrome = '1') then
if(limit_ctr_codeword_q = '1') then
next_state <= final;
else
next_state <= jump_codeword;
end if;
else
next_state <= load_store_synd;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
ba30949cbf9c411888915ae4bd1c0eb6
| 0.565192 | 2.593907 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/multiplication/rounder/rounder.vhd
| 1 | 2,231 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rounder is
generic(
TOTAL_BITS:natural := 23;
EXP_BITS: natural := 6
);
port (
exponent_addition_cout: in std_logic;
man_in: in std_logic_vector(TOTAL_BITS - EXP_BITS downto 0);
exp_in: in std_logic_vector(EXP_BITS - 1 downto 0);
man_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_out : out std_logic_vector(EXP_BITS - 1 downto 0)
);
end;
architecture rounder_arq of rounder is
begin
process(man_in, exp_in, exponent_addition_cout)
variable tmp_exp : integer := 0;
variable bias_vector : std_logic_vector(EXP_BITS - 2 downto 0) := (others => '1');
variable bias : integer := 0;
variable extended_exponent : std_logic_vector(EXP_BITS downto 0) := (others => '0');
variable zero_man : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
variable zero_exp : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '0');
variable infinity_man : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '1');
variable infinity_exp : std_logic_vector(EXP_BITS - 2 downto 0) := (others => '1');
variable max_exp_vector : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '1');
variable max_exp : integer := 0;
variable out_man : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
begin
extended_exponent := exponent_addition_cout & exp_in;
tmp_exp := to_integer(unsigned(extended_exponent));
bias := to_integer(unsigned('0' & bias_vector));
tmp_exp := tmp_exp - bias;
max_exp := to_integer(unsigned(max_exp_vector));
--Check if the exponent needs to be modified and the mantissa shifted
if(man_in(TOTAL_BITS - EXP_BITS) = '1') then
out_man := man_in(TOTAL_BITS - EXP_BITS - 1 downto 1);
tmp_exp := tmp_exp + 1;
else
out_man := man_in(TOTAL_BITS - EXP_BITS - 2 downto 0);
end if;
if(tmp_exp <= 0) then --round to 0
exp_out <= zero_exp;
man_out <= zero_man;
elsif(tmp_exp >= max_exp) then --round to infinity
exp_out <= infinity_exp & '0';
man_out <= infinity_man;
else
exp_out <= std_logic_vector(to_unsigned(tmp_exp, EXP_BITS));
man_out <= out_man;
end if;
end process;
end architecture;
|
gpl-3.0
|
0a7d0f460e9692a18f7a7e546b879507
| 0.653519 | 2.87871 | false | false | false | false |
alainmarcel/Surelog
|
third_party/tests/ariane/fpga/src/apb_uart/src/uart_transmitter.vhd
| 5 | 8,726 |
--
-- UART transmitter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART transmitter
entity uart_transmitter is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
TXCLK : in std_logic; -- Transmitter clock (2x baudrate)
TXSTART : in std_logic; -- Start transmitter
CLEAR : in std_logic; -- Clear transmitter state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
BC : in std_logic; -- Break control
DIN : in std_logic_vector(7 downto 0); -- Input data
TXFINISHED : out std_logic; -- Transmitter operation finished
SOUT : out std_logic -- Transmitter output
);
end uart_transmitter;
architecture rtl of uart_transmitter is
-- FSM
type state_type is (IDLE, START, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5, BIT6, BIT7, PAR, STOP, STOP2);
signal CState, NState : state_type;
-- Signals
signal iTx2 : std_logic; -- Next TX step
signal iSout : std_logic; -- Transmitter output
signal iParity : std_logic; -- Parity
signal iFinished : std_logic; -- TX finished
begin
-- Transmitter FSM update process
TX_PROC: process (RST, CLK)
begin
if (RST = '1') then
CState <= IDLE;
iTx2 <= '0';
elsif (CLK'event and CLK='1') then
if (TXCLK = '1') then -- TX clock
if (iTx2 = '0') then -- Two TX clocks per step
CState <= NState; -- Next step
iTx2 <= '1';
else
if ((WLS = "00") and (STB = '1') and CState = STOP2) then
CState <= NState; -- 1.5 stop bits for 5 bit word mode
iTx2 <= '1';
else
CState <= CState; -- First TX clock, wait
iTx2 <= '0';
end if;
end if;
end if;
end if;
end process;
-- Transmitter FSM
TX_FSM: process (CState, TXSTART, DIN, WLS, PEN, SP, EPS, STB, iParity)
begin
-- Defaults
NState <= IDLE;
iSout <= '1';
case CState is
when IDLE => if (TXSTART = '1') then
NState <= START;
end if;
when START => iSout <= '0';
NState <= BIT0;
when BIT0 => iSout <= DIN(0);
NState <= BIT1;
when BIT1 => iSout <= DIN(1);
NState <= BIT2;
when BIT2 => iSout <= DIN(2);
NState <= BIT3;
when BIT3 => iSout <= DIN(3);
NState <= BIT4;
when BIT4 => iSout <= DIN(4);
if (WLS = "00") then -- 5 bits
if (PEN = '1') then
NState <= PAR; -- Parity enabled
else
NState <= STOP; -- No parity
end if;
else
NState <= BIT5;
end if;
when BIT5 => iSout <= DIN(5);
if (WLS = "01") then -- 6 bits
if (PEN = '1') then
NState <= PAR; -- Parity enabled
else
NState <= STOP; -- No parity
end if;
else
NState <= BIT6;
end if;
when BIT6 => iSout <= DIN(6);
if (WLS = "10") then -- 7 bits
if (PEN = '1') then
NState <= PAR; -- Parity enabled
else
NState <= STOP; -- No parity
end if;
else
NState <= BIT7;
end if;
when BIT7 => iSout <= DIN(7);
if (PEN = '1') then
NState <= PAR; -- Parity enabled
else
NState <= STOP; -- No parity
end if;
when PAR => if (SP = '1') then -- Sticky parity
if (EPS = '1') then
iSout <= '0'; -- Even parity -> cleared
else
iSout <= '1'; -- Odd parity -> set
end if;
else
if (EPS = '1') then
iSout <= iParity; -- Even parity
else
iSout <= not iParity; -- Odd parity
end if;
end if;
NState <= STOP;
when STOP => if (STB = '1') then -- 2 stop bits
NState <= STOP2;
else
if (TXSTART = '1') then -- Next transmission
NState <= START;
end if;
end if;
when STOP2 => if (TXSTART = '1') then -- Next transmission
NState <= START;
end if;
when others => null;
end case;
end process;
-- Parity generation
TX_PAR: process (DIN, WLS)
variable iP40, iP50, iP60, iP70 : std_logic;
begin
iP40 := DIN(4) xor DIN(3) xor DIN(2) xor DIN(1) xor DIN(0);
iP50 := DIN(5) xor iP40;
iP60 := DIN(6) xor iP50;
iP70 := DIN(7) xor iP60;
case WLS is
when "00" => iParity <= iP40;
when "01" => iParity <= iP50;
when "10" => iParity <= iP60;
when others => iParity <= iP70;
end case;
end process;
-- Signal TX finished on STOP bit transmission
TX_FIN: process (CLK, RST)
variable iLast : std_logic;
begin
if (RST = '1') then
iFinished <= '0';
iLast := '0';
elsif (CLK'event and CLK = '1') then
iFinished <= '0';
if (iLast = '0' and CState = STOP) then
iFinished <= '1';
end if;
if (CState = STOP) then
iLast := '1';
else
iLast := '0';
end if;
end if;
end process;
-- Output signals
SOUT <= iSout when BC = '0' else '0';
TXFINISHED <= iFinished;
end rtl;
|
apache-2.0
|
792eb0e4df71c26901c15de3506e963b
| 0.380931 | 5.067364 | false | false | false | false |
hitomi2500/wasca
|
fpga_firmware/buffered_spi_tb.vhd
| 1 | 6,438 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21.09.2020 23:17:28
-- Design Name:
-- Module Name: buffered_spi_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity buffered_spi_tb is
-- Port ( );
end buffered_spi_tb;
architecture Behavioral of buffered_spi_tb is
component buffered_spi is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
avalon_read : in STD_LOGIC;
avalon_write : in STD_LOGIC;
avalon_address : in STD_LOGIC_VECTOR (13 downto 0);
avalon_waitrequest : out std_logic := '0';
avalon_writedata : in STD_LOGIC_VECTOR (15 downto 0);
avalon_readdata : out STD_LOGIC_VECTOR (15 downto 0);
avalon_readdatavalid : out std_logic := '0';
spi_mosi : out STD_LOGIC;
spi_clk : out STD_LOGIC;
spi_miso : in STD_LOGIC;
spi_cs : out STD_LOGIC);
end component;
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal avalon_read : std_logic := '0';
signal avalon_write : std_logic := '0';
signal avalon_waitrequest : std_logic := '0';
signal avalon_address : std_logic_vector(13 downto 0) := (others => '0');
signal avalon_writedata : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_readdata : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_readdatavalid : std_logic := '0';
signal spi_mosi : std_logic := '0';
signal spi_clk : std_logic := '0';
signal spi_miso : std_logic := '0';
signal spi_cs : std_logic := '0';
procedure write_avalon_16 (addry : in std_logic_vector(13 downto 0);
datty : in std_logic_vector(15 downto 0);
signal Ava_Ad : out std_logic_vector(13 downto 0);
signal Ava_Da : out std_logic_vector(15 downto 0);
signal Ava_Wri : out std_logic
) is
begin
Ava_Ad <= addry;
Ava_Da <= datty;
wait for 10 ns;
Ava_Wri <= '1';
wait for 10 ns;
Ava_Wri <= '0';
wait for 10 ns;
end write_avalon_16;
procedure read_avalon_16 (addry : in std_logic_vector(13 downto 0);
signal Ava_Ad : out std_logic_vector(13 downto 0);
signal Ava_Re : out std_logic
) is
begin
Ava_Ad <= addry;
wait for 10 ns;
Ava_Re <= '1';
wait for 10 ns;
Ava_Re <= '0';
wait for 10 ns;
end read_avalon_16;
begin
--clock <= not clock after 4310 ps; --116 MHz clock
clock <= not clock after 5000 ps; --100 MHz clock
UUT: buffered_spi
port map(
clock => clock,
reset => reset,
avalon_read => avalon_read,
avalon_write => avalon_write,
avalon_address => avalon_address,
avalon_waitrequest => avalon_waitrequest,
avalon_writedata => avalon_writedata,
avalon_readdata => avalon_readdata,
avalon_readdatavalid => avalon_readdatavalid,
spi_mosi => spi_mosi,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_cs => spi_cs
);
process
begin
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for 300 ns;
reset <= '1';
wait for 300 ns;
--write
write_avalon_16("10"&X"001",X"0200",avalon_address,avalon_writedata,avalon_write); --len
wait for 100 ns;
--write_avalon_16("10"&X"003",X"0000",avalon_address,avalon_writedata,avalon_write); --cs
--write_avalon_16("10"&X"003",X"0010",avalon_address,avalon_writedata,avalon_write); --cs, /10 clock
--write_avalon_16("10"&X"003",X"0020",avalon_address,avalon_writedata,avalon_write); --cs, /12 clock
write_avalon_16("10"&X"003",X"0030",avalon_address,avalon_writedata,avalon_write); --cs, /16 clock
wait for 100 ns;
write_avalon_16("10"&X"004",X"0000",avalon_address,avalon_writedata,avalon_write); --delay
wait for 100 ns;
write_avalon_16("10"&X"005",X"0000",avalon_address,avalon_writedata,avalon_write); --bufselect
wait for 100 ns;
for i in 0 to 511 loop
write_avalon_16(std_logic_vector(to_unsigned(i,14)),std_logic_vector(to_unsigned(i*3,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+2048,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+4096,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+6144,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
end loop;
wait for 100 ns;
--read
wait for 500 ns;
read_avalon_16("00"&X"312",avalon_address,avalon_read);
wait for 500 ns;
--start spi
write_avalon_16("10"&X"000",X"0001",avalon_address,avalon_writedata,avalon_write);
--toggle miso
for i in 0 to 5000 loop
spi_miso <= not spi_miso;
--wait for 320 ns;
wait for 160 ns;
end loop;
--switch to buf2
write_avalon_16("10"&X"005",X"0001",avalon_address,avalon_writedata,avalon_write); --bufselect
--start spi
write_avalon_16("10"&X"000",X"0001",avalon_address,avalon_writedata,avalon_write);
wait;
end process;
end Behavioral;
|
gpl-2.0
|
512681bc3c440c973051318099d9b064
| 0.554986 | 3.687285 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/sign_computer/sign_computer.vhd
| 1 | 1,421 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sign_computer is
generic(
BITS : natural := 16
);
port(
man_1_in: in std_logic_vector(BITS - 1 downto 0) := (others => '0');
man_2_in: in std_logic_vector(BITS - 1 downto 0) := (others => '0');
sign_1_in: in std_logic := '0';
sign_2_in: in std_logic := '0';
man_greater_in: in std_logic_vector(BITS - 1 downto 0) := (others => '0');
pre_complemented_result: in std_logic_vector(BITS downto 0) := (others => '0');
complemented_result: in std_logic_vector(BITS downto 0) := (others => '0');
sign_out: out std_logic := '0'
);
end sign_computer;
architecture sign_computer_arq of sign_computer is
begin
process (man_1_in, man_2_in, sign_1_in, sign_2_in, man_greater_in, pre_complemented_result, complemented_result) is
begin
if sign_1_in = sign_2_in then
sign_out <= sign_1_in; --If the operands had the same sign, return it
elsif man_1_in /= man_greater_in then --There was an operand switch
sign_out <= sign_2_in;
else
if(pre_complemented_result = complemented_result) then --Result was not complemented
sign_out <= sign_1_in;
else --result was complemented
sign_out <= sign_2_in;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
afe02c4eaeb186318fffea1840ad6ec6
| 0.588318 | 3.343529 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/tb_solving_key_equation_1_v2.vhd
| 1 | 12,203 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Solving_Key_Equation_1_v2
-- Module Name: Tb_Solving_Key_Equation_1_v2
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Test bench for solving_key_equation_1_v2 circuit.
--
-- Circuit Parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- final_degree :
--
-- The final degree size expected for polynomial sigma to have. This parameter depends
-- of the Goppa code used.
--
-- size_final_degree :
--
-- The number of bits necessary to hold the polynomial with degree of final_degree, which
-- has final_degree + 1 coefficients. This is ceil(log2(final_degree+1)).
--
-- sigma_memory_file :
--
-- File that holds polynomial sigma coefficients.
-- This file is necessary to verify if the output of this circuit is correct.
--
-- dump_sigma_memory_file :
--
-- File that will hold the output of this circuit, polynomial sigma.
--
-- syndrome_memory_file :
--
-- File that holds the syndrome that is needed to compute polynomial sigma.
--
--
-- Dependencies:
--
-- VHDL-93
--
-- solving_key_equation_1_v2 Rev 1.0
-- inv_gf_2_m_pipeline Rev 1.0
-- ram Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_solving_key_equation_1_v2 is
Generic(
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
gf_2_m : integer range 1 to 20 := 6;
final_degree : integer := 4;
size_final_degree : integer := 2;
sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_52_28_4_6.dat";
dump_sigma_memory_file : string := "mceliece/data_tests/dump_sigma_qdgoppa_52_28_4_6.dat";
syndrome_memory_file : string := "mceliece/data_tests/syndrome_qdgoppa_52_28_4_6.dat"
-- GOPPA [2048, 1751, 27, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 27;
-- size_final_degree : integer := 5;
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_2048_1751_27_11.dat";
-- dump_sigma_memory_file : string := "mceliece/data_tests/dump_sigma_goppa_2048_1751_27_11.dat";
-- syndrome_memory_file : string := "mceliece/data_tests/syndrome_goppa_2048_1751_27_11.dat"
-- GOPPA [2048, 1498, 50, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6;
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_2048_1498_50_11.dat";
-- dump_sigma_memory_file : string := "mceliece/data_tests/dump_sigma_goppa_2048_1498_50_11.dat";
-- syndrome_memory_file : string := "mceliece/data_tests/syndrome_goppa_2048_1498_50_11.dat"
-- GOPPA [3307, 2515, 66, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 66;
-- size_final_degree : integer := 7;
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_3307_2515_66_12.dat";
-- dump_sigma_memory_file : string := "mceliece/data_tests/dump_sigma_goppa_3307_2515_66_12.dat";
-- syndrome_memory_file : string := "mceliece/data_tests/syndrome_goppa_3307_2515_66_12.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 32;
-- size_final_degree : integer := 5;
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_2528_2144_32_12.dat";
-- dump_sigma_memory_file : string := "mceliece/data_tests/dump_sigma_qdgoppa_2528_2144_32_12.dat";
-- syndrome_memory_file : string := "mceliece/data_tests/syndrome_qdgoppa_2528_2144_32_12.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6;
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_2816_2048_64_12.dat";
-- dump_sigma_memory_file : string := "mceliece/data_tests/dump_sigma_qdgoppa_2816_2048_64_12.dat";
-- syndrome_memory_file : string := "mceliece/data_tests/syndrome_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6;
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_3328_2560_64_12.dat";
-- dump_sigma_memory_file : string := "mceliece/data_tests/dump_sigma_qdgoppa_3328_2560_64_12.dat";
-- syndrome_memory_file : string := "mceliece/data_tests/syndrome_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- gf_2_m : integer range 1 to 20 := 13;
-- final_degree : integer := 128;
-- size_final_degree : integer := 7;
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_7296_5632_128_13.dat";
-- dump_sigma_memory_file : string := "mceliece/data_tests/dump_sigma_qdgoppa_7296_5632_128_13.dat";
-- syndrome_memory_file : string := "mceliece/data_tests/syndrome_qdgoppa_7296_5632_128_13.dat"
);
end tb_solving_key_equation_1_v2;
architecture Behavioral of tb_solving_key_equation_1_v2 is
component solving_key_equation_1_v2
Generic(
gf_2_m : integer range 1 to 20 := 11;
final_degree : integer;
size_final_degree : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_FB : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_GC : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_FB : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_GC : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_FB : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_GC : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end component;
component ram
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component inv_gf_2_m_pipeline
Generic(gf_2_m : integer range 1 to 20 := 20);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
flag : in STD_LOGIC;
clk : in STD_LOGIC;
oflag : out STD_LOGIC;
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal ready_inv : STD_LOGIC;
signal test_value_FB : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal test_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_inv : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal signal_inv : STD_LOGIC;
signal key_equation_found : STD_LOGIC;
signal test_write_enable_FB : STD_LOGIC;
signal test_write_enable_GC : STD_LOGIC;
signal new_value_inv : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_FB : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal test_address_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal test_address_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal write_enable_FB : STD_LOGIC;
signal write_enable_GC : STD_LOGIC;
signal true_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal true_address_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal true_address_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal test_error : STD_LOGIC;
signal dump_sigma_memory : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
for syndrome_memory : ram use entity work.ram(file_load);
for test_sigma_memory : ram use entity work.ram(simple);
for true_sigma_memory : ram use entity work.ram(file_load);
begin
test : solving_key_equation_1_v2
Generic Map(
gf_2_m => gf_2_m,
final_degree => final_degree,
size_final_degree => size_final_degree
)
Port Map(
clk => clk,
rst => rst,
ready_inv => ready_inv,
value_FB => test_value_FB,
value_GC => test_value_GC,
value_inv => value_inv,
signal_inv => signal_inv,
key_equation_found => key_equation_found,
write_enable_FB => test_write_enable_FB,
write_enable_GC => test_write_enable_GC,
new_value_inv => new_value_inv,
new_value_FB => new_value_FB,
new_value_GC => new_value_GC,
address_FB => test_address_FB,
address_GC => test_address_GC
);
syndrome_memory : ram
Generic Map(
ram_address_size => size_final_degree+2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => syndrome_memory_file,
dump_file_name => ""
)
Port Map(
data_in => new_value_FB,
rw => test_write_enable_FB,
clk => clk,
rst => rst,
dump => '0',
address => address_FB,
rst_value => (others => '0'),
data_out => test_value_FB
);
test_sigma_memory : ram
Generic Map(
ram_address_size => size_final_degree+2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => dump_sigma_memory_file
)
Port Map(
data_in => new_value_GC,
rw => write_enable_GC,
clk => clk,
rst => rst,
dump => dump_sigma_memory,
address => address_GC,
rst_value => (others => '0'),
data_out => test_value_GC
);
true_sigma_memory : ram
Generic Map(
ram_address_size => size_final_degree+2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => sigma_memory_file,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => true_address_GC,
rst_value => (others => '0'),
data_out => true_value_GC
);
inverter : inv_gf_2_m_pipeline
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => new_value_inv,
flag => signal_inv,
clk => clk,
oflag => ready_inv,
o => value_inv
);
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
address_FB <= true_address_FB when key_equation_found = '1' else test_address_FB;
address_GC <= true_address_GC when key_equation_found = '1' else test_address_GC;
write_enable_FB <= '0' when key_equation_found = '1' else test_write_enable_FB;
write_enable_GC <= '0' when key_equation_found = '1' else test_write_enable_GC;
process
variable i : integer;
begin
true_address_FB <= (others => '0');
true_address_GC <= (others => '0');
rst <= '1';
test_error <= '0';
dump_sigma_memory <= '0';
wait for PERIOD*2;
rst <= '0';
wait until key_equation_found = '1';
report "Circuit finish = " & integer'image((cycle_count - 2)/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (final_degree + 1)) loop
true_address_FB <= std_logic_vector(to_unsigned(i, true_address_FB'Length));
true_address_GC <= std_logic_vector(to_unsigned(i, true_address_GC'Length));
wait for PERIOD*2;
if (true_value_GC = test_value_GC) then
test_error <= '0';
else
test_error <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
test_error <= '0';
wait for PERIOD;
i := i + 1;
end loop;
dump_sigma_memory <= '1';
wait for PERIOD;
dump_sigma_memory <= '0';
test_bench_finish <= '1';
wait;
end process;
end Behavioral;
|
bsd-2-clause
|
994c7553c21bb07f4e3f429e02fa542e
| 0.647054 | 2.772149 | false | true | false | false |
hitomi2500/wasca
|
fpga_firmware/wasca/synthesis/submodules/buffered_spi.vhd
| 2 | 20,445 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity buffered_spi is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
avalon_read : in STD_LOGIC;
avalon_write : in STD_LOGIC;
avalon_address : in STD_LOGIC_VECTOR (13 downto 0);
avalon_waitrequest : out std_logic := '0';
avalon_writedata : in STD_LOGIC_VECTOR (15 downto 0);
avalon_readdata : out STD_LOGIC_VECTOR (15 downto 0);
avalon_readdatavalid : out std_logic := '0';
spi_sync_miso : in std_logic := '0';
spi_sync_mosi : out std_logic := '0';
spi_mosi : out STD_LOGIC := '0';
spi_clk : out STD_LOGIC := '0';
spi_miso : in STD_LOGIC;
spi_cs : out STD_LOGIC := '1');
end buffered_spi;
architecture Behavioral of buffered_spi is
signal transaction_active : std_logic := '0';
signal transaction_active_p1 : std_logic := '0';
signal transaction_active_readreg : std_logic := '0';
signal writebuffer_write1 : std_logic := '0';
signal writebuffer_write2 : std_logic := '0';
signal readbuffer_write1 : std_logic := '0';
signal readbuffer_write2 : std_logic := '0';
signal readbuffer_transaction_write1 : std_logic := '0';
signal readbuffer_transaction_write2 : std_logic := '0';
signal transaction_prestart_1 : std_logic := '0';
signal transaction_prestart_2 : std_logic := '0';
signal transaction_start : std_logic := '0';
signal transaction_bit_counter : unsigned (15 downto 0) := (others => '1');
signal transaction_bit_counter_p1 : unsigned (15 downto 0) := (others => '1');
signal transaction_byte_counter : unsigned (11 downto 0) := (others => '1');
signal transaction_byte_counter_p1 : unsigned (11 downto 0) := (others => '1');
signal transaction_data_read : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_data_write1 : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_data_write2 : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_buf_write1 : std_logic := '0';
signal transaction_buf_write2 : std_logic := '0';
signal transaction_clkdiv_counter : std_logic_vector (3 downto 0) := (others => '0');
signal transaction_clkdiv_limit : std_logic_vector (3 downto 0) := (others => '0');
signal transaction_clkdiv_latch : std_logic_vector (3 downto 0) := (others => '0');
signal transaction_clkdiv_prelatch : std_logic_vector (3 downto 0) := (others => '0');
signal spi_cs_constant : std_logic := '1';
signal spi_cs_gappy : std_logic := '1';
signal length_register : std_logic_vector(10 downto 0) := (others => '0');
signal cs_mode_register : std_logic := '0';
signal delay_register : std_logic_vector(15 downto 0) := (others => '0');
signal buffer_select_register : std_logic := '0';
signal freq_divider_register : std_logic_vector(1 downto 0) := (others => '0');
signal avalon_readdata_readbuf1 : std_logic_vector (15 downto 0);
signal avalon_readdata_writebuf1 : std_logic_vector (15 downto 0);
signal avalon_readdata_readbuf2 : std_logic_vector (15 downto 0);
signal avalon_readdata_writebuf2 : std_logic_vector (15 downto 0);
--signal avalon_address_f1 : std_logic_vector (13 downto 0);
signal avalon_readdata_p1 : std_logic_vector (15 downto 0);
signal avalon_read_f1 : STD_LOGIC;
signal avalon_read_f2 : STD_LOGIC;
signal avalon_address_latched : std_logic_vector (13 downto 0);
signal avalon_readdatavalid_p1 : STD_LOGIC;
signal spi_sync_miso_register : std_logic := '1';
signal spi_sync_mosi_register : std_logic := '1';
--inferred ram, quartus fails to recognize'em like bram
--type spi_buf_type is array(0 to 511) of std_logic_vector(15 downto 0);
--signal write_buffer1 : spi_buf_type;
--signal read_buffer1 : spi_buf_type;
--signal write_buffer2 : spi_buf_type;
--signal read_buffer2 : spi_buf_type;
--using core-generated bram instead
component buff_spi_ram IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;
begin
avalon_address_latched <= avalon_address when rising_edge(clock) and (avalon_read = '1' or avalon_write = '1');
avalon_read_f1 <= avalon_read when rising_edge(clock);
avalon_read_f2 <= avalon_read_f1 when rising_edge(clock);
spi_sync_miso_register <= spi_sync_miso;
spi_sync_mosi <= spi_sync_mosi_register;
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_readdatavalid_p1 <= '0';
if avalon_read_f2 = '1' then
avalon_readdatavalid_p1 <= '1';
case avalon_address_latched(13 downto 11) is
when "000" =>
avalon_readdata_p1 <= avalon_readdata_writebuf1;
when "001" =>
avalon_readdata_p1 <= avalon_readdata_writebuf2;
when "010" =>
avalon_readdata_p1 <= avalon_readdata_readbuf1;
when "011" =>
avalon_readdata_p1 <= avalon_readdata_readbuf2;
when "100" =>
case avalon_address_latched(2 downto 0) is
when "000" =>
avalon_readdata_p1 <= X"000"&"000"&transaction_active_readreg;
when "001" =>
avalon_readdata_p1 <= X"0"&"0"&length_register;
when "010" =>
avalon_readdata_p1 <= X"0"&std_logic_vector(transaction_byte_counter);
when "011" =>
avalon_readdata_p1 <= X"00"&"00"&freq_divider_register&"000"&cs_mode_register;
when "100" =>
avalon_readdata_p1 <= delay_register;
when "101" =>
avalon_readdata_p1 <= X"000"&"000"&buffer_select_register;
when "110" =>
avalon_readdata_p1 <= X"000"&"000"&spi_sync_miso_register;
when "111" =>
avalon_readdata_p1 <= X"000"&"000"&spi_sync_mosi_register;
when others =>
avalon_readdata_p1 <= X"ABBA";
end case;
when others =>
null;
end case;
end if;
end if;
end process;
avalon_readdata <= avalon_readdata_p1 when rising_edge(clock);
avalon_readdatavalid <= avalon_readdatavalid_p1 when rising_edge(clock);
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
transaction_prestart_1 <= '0';
writebuffer_write1 <= '0';
writebuffer_write2 <= '0';
readbuffer_write1 <= '0';
readbuffer_write2 <= '0';
if avalon_write= '1' then
case avalon_address(13 downto 11) is
when "000" =>
writebuffer_write1 <= '1';
when "001" =>
writebuffer_write2 <= '1';
when "010" =>
readbuffer_write1 <= '1';
when "011" =>
readbuffer_write2 <= '1';
when "100" =>
case avalon_address(2 downto 0) is
when "000" =>
transaction_prestart_1 <= avalon_writedata(0);
when "001" =>
length_register <= avalon_writedata(10 downto 0);
when "010" =>
null;
when "011" =>
cs_mode_register <= avalon_writedata(0);
freq_divider_register <= avalon_writedata(5 downto 4);
when "100" =>
delay_register <= avalon_writedata;
when "101" =>
buffer_select_register <= avalon_writedata(0);
when "111" =>
spi_sync_mosi_register <= avalon_writedata(0);
when others =>
null;
end case;
when others =>
null;
end case;
end if;
end if;
end process;
--async avalon write decoders
--writebuffer_write1 <= avalon_write when avalon_address(13 downto 11) = "000" else '0';
--writebuffer_write2 <= avalon_write when avalon_address(13 downto 11) = "001" else '0';
--readbuffer_write1 <= avalon_write when avalon_address(13 downto 11) = "010" else '0';
--readbuffer_write2 <= avalon_write when avalon_address(13 downto 11) = "011" else '0';
--delaying transaction_start cor a clock cycle to wait for cs
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
transaction_prestart_2 <= '1';
elsif transaction_clkdiv_counter = "0001" then
transaction_prestart_2 <= '0';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if transaction_clkdiv_counter = "0000" then
transaction_start<= transaction_prestart_2;
end if;
end if;
end process;
transaction_byte_counter_p1 <= transaction_byte_counter when rising_edge(clock);
-- --read buffer1, should be inferred as 1.5-port block ram
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (readbuffer_write1 = '1') then
-- read_buffer1(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- avalon_readdata_readbuf1 <= read_buffer1(to_integer(unsigned(avalon_address(8 downto 0))));
-- if (readbuffer_transaction_write1 = '1') then
-- read_buffer1(to_integer(unsigned(transaction_byte_counter_p1(8 downto 0)))) <= transaction_data_read;
-- end if;
-- end if;
-- end process;
-- --read buffer2
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (readbuffer_write2 = '1') then
-- read_buffer2(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- avalon_readdata_readbuf2 <= read_buffer2(to_integer(unsigned(avalon_address(8 downto 0))));
-- if (readbuffer_transaction_write2 = '1') then
-- read_buffer2(to_integer(unsigned(transaction_byte_counter_p1(8 downto 0)))) <= transaction_data_read;
-- end if;
-- end if;
-- end process;
-- --write buffer1
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (writebuffer_write1 = '1') then
-- write_buffer1(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- transaction_data_write1 <= write_buffer1(to_integer(unsigned(transaction_byte_counter(8 downto 0))));
-- avalon_readdata_writebuf1 <= write_buffer1(to_integer(unsigned(avalon_address(8 downto 0))));
-- end if;
-- end process;
-- --write buffer2
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (writebuffer_write2 = '1') then
-- write_buffer2(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- transaction_data_write2 <= write_buffer2(to_integer(unsigned(transaction_byte_counter(8 downto 0))));
-- avalon_readdata_writebuf2 <= write_buffer2(to_integer(unsigned(avalon_address(8 downto 0))));
-- end if;
-- end process;
--using bram cores instead
read1_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter_p1(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => transaction_data_read,
wren_a => readbuffer_write1,
wren_b => readbuffer_transaction_write1,
q_a => avalon_readdata_readbuf1,
q_b => open --write-only port
);
read2_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter_p1(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => transaction_data_read,
wren_a => readbuffer_write2,
wren_b => readbuffer_transaction_write2,
q_a => avalon_readdata_readbuf2,
q_b => open --write-only port
);
write1_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => X"0000",
wren_a => writebuffer_write1,
wren_b => '0', --read-only port
q_a => avalon_readdata_writebuf1,
q_b => transaction_data_write1
);
write2_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => X"0000",
wren_a => writebuffer_write2,
wren_b => '0', --read-only port
q_a => avalon_readdata_writebuf2,
q_b => transaction_data_write2
);
--Avalon interface is only regs, so always ready to write.
avalon_waitrequest <= '0';
--transaction bit counter
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_bit_counter <= to_unsigned(0,16);
elsif (transaction_clkdiv_counter = transaction_clkdiv_prelatch) and transaction_active = '1' then
if transaction_bit_counter < 16 + unsigned(delay_register) then
transaction_bit_counter <= transaction_bit_counter + 1;
else
transaction_bit_counter <= to_unsigned(0,16);
end if;
end if;
end if;
end process;
--transaction byte counter
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_byte_counter <= to_unsigned(0,12);
elsif transaction_clkdiv_counter = transaction_clkdiv_latch and transaction_active = '1' then
if transaction_byte_counter <= unsigned(length_register) then
if transaction_bit_counter = to_unsigned(16,16) then --16 bits per frame
transaction_byte_counter <= transaction_byte_counter + 1;
end if;
end if;
end if;
end if;
end process;
--transaction active flag
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_active <= '1';
elsif transaction_byte_counter = unsigned(length_register) then
transaction_active <= '0';
end if;
end if;
end process;
--transaction active flag for nios to read
process (clock)
begin
if rising_edge(clock) then
if (transaction_prestart_1 = '1') then
transaction_active_readreg <= '1';
elsif transaction_byte_counter = unsigned(length_register) then
transaction_active_readreg <= '0';
end if;
end if;
end process;
--transaction clock divider
--controlled by freq_divider_register
-- 0 => clockspeed is 1/8, 14.5 Mhz for 116Mhz base clock
-- 1 => clockspeed is 1/10, 11.6 Mhz for 116Mhz base clock
-- 2 => clockspeed is 1/12, 9.67 Mhz for 116Mhz base clock
-- 3 => clockspeed is 1/16, 7.25 Mhz for 116Mhz base clock
transaction_clkdiv_limit <= X"7" when freq_divider_register = "00" else
X"9" when freq_divider_register = "01" else
X"B" when freq_divider_register = "10" else
X"F";
transaction_clkdiv_latch <= X"5" when freq_divider_register = "00" else
X"6" when freq_divider_register = "01" else
X"7" when freq_divider_register = "10" else
X"9";
transaction_clkdiv_prelatch <= X"4" when freq_divider_register = "00" else
X"5" when freq_divider_register = "01" else
X"6" when freq_divider_register = "10" else
X"8";
process (clock)
begin
if rising_edge(clock) then
if (transaction_prestart_1 = '1') then
transaction_clkdiv_counter <= transaction_clkdiv_prelatch;
elsif unsigned(transaction_clkdiv_counter) < unsigned(transaction_clkdiv_limit) then
transaction_clkdiv_counter <= std_logic_vector(unsigned(transaction_clkdiv_counter) + 1);
else
transaction_clkdiv_counter <= "0000";
end if;
end if;
end process;
-- SPI CLK output
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '1') and transaction_bit_counter <= to_unsigned(15,16) then
if (transaction_clkdiv_counter = "0001") and (transaction_start = '0') then
spi_clk <= '1';
elsif (transaction_clkdiv_counter = transaction_clkdiv_latch) then
spi_clk <= '0';
end if;
else
spi_clk <= '0';
end if;
end if;
end process;
-- SPI MOSI output
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '0') then
spi_mosi <= '0';
elsif (buffer_select_register = '0') then
spi_mosi <= transaction_data_write1(15-to_integer(transaction_bit_counter(3 downto 0)));
else
spi_mosi <= transaction_data_write2(15-to_integer(transaction_bit_counter(3 downto 0)));
end if;
end if;
end process;
-- SPI CS output
transaction_active_p1 <= transaction_active when rising_edge(clock);
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
spi_cs_gappy <= '0';
elsif (transaction_bit_counter = to_unsigned(16,16)) then
spi_cs_gappy <= '1';
elsif (transaction_bit_counter = to_unsigned(0,16)) then
spi_cs_gappy <= '0';
elsif transaction_active = '0' and transaction_active_p1 = '1' then
spi_cs_gappy <= '1';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
spi_cs_constant <= '0';
elsif transaction_active = '0' and transaction_active_p1 = '1' then
spi_cs_constant <= '1';
end if;
end if;
end process;
spi_cs <= spi_cs_gappy when cs_mode_register = '1' else
spi_cs_constant;
-- SPI MISO input
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '1') and transaction_bit_counter <= to_unsigned(15,16) and transaction_clkdiv_counter = "0001" then
transaction_data_read(15-to_integer(transaction_bit_counter(3 downto 0))) <= spi_miso;
end if;
end if;
end process;
transaction_bit_counter_p1 <= transaction_bit_counter when rising_edge(clock);
process (clock)
begin
if rising_edge(clock) then
readbuffer_transaction_write1 <= '0';
readbuffer_transaction_write2 <= '0';
if (transaction_active = '1') and transaction_bit_counter = to_unsigned(16,16) and transaction_bit_counter_p1 = to_unsigned(15,16) then
if (buffer_select_register = '0') then
readbuffer_transaction_write1 <= '1';
else
readbuffer_transaction_write2 <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
5dfd163d162ed8e2cfea3b4fd68778a4
| 0.571484 | 3.702463 | false | false | false | false |
rajvinjamuri/ECE385_VHDL
|
bouncing_ball.vhd
| 1 | 21,339 |
---------------------------------------------------------------------------
-- BouncingBall.vhd --
-- --
-- Modeled off bouncing_ball.vhd by Stephen Kempf and Viral Mehta --
-- --
-- by Raj Vinjamuri and Sai Koppula --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
---------------------------------------------------------------------------
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Body_mapper is
Port ( Up, Do, Le, Ri : in std_logic; --input signals used by ball for movement
Clk : in std_logic;
Reset : in std_logic;
Start : in std_logic;
Seed : in std_logic_vector(17 downto 0);
ResScore : in std_logic;
Red : out std_logic_vector(9 downto 0);
Green : out std_logic_vector(9 downto 0);
Blue : out std_logic_vector(9 downto 0);
VGA_clk : out std_logic;
sync : out std_logic;
blank : out std_logic;
vs : out std_logic;
hs : out std_logic;
game_statusOut : out std_logic_vector(3 downto 0);
scoreOutH, scoreOutL : out std_logic_vector(3 downto 0));
end Body_mapper;
architecture Behavioral of Body_mapper is
-----------------------------------------------------
component game_handler is
Port ( frame_clk : in std_logic;
paddle_loss_statusIn : in std_logic_vector(1 downto 0);
win_statusIn, ResetIn, ResetScore : in std_logic;
brick_hitIn : in std_logic_vector(19 downto 0);
score: out std_logic_vector(7 downto 0);
game_status : out std_logic_vector(3 downto 0));
end component;
-----------------------------------------------------
component ball is
Port ( --Up, Do : in std_logic;
Le, Ri : in std_logic;
clk : in std_logic;
Reset : in std_logic;
frame_clk : in std_logic;
StartMove : in std_logic;
seedIn : in std_logic_vector(17 downto 0);
BallX : out std_logic_vector(10 downto 0);
BallY : out std_logic_vector(10 downto 0);
BallS : out std_logic_vector(10 downto 0);
PaddleX : in std_logic_vector(10 downto 0);
PaddleY : in std_logic_vector(10 downto 0);
PaddleS : in std_logic_vector(10 downto 0);
BricksX : in std_logic_vector(219 downto 0);
BricksY : in std_logic_vector(219 downto 0);
BricksOn : in std_logic_vector(19 downto 0);
paddle_loss_status : out std_logic_vector(1 downto 0));
end component;
-----------------------------------------------------
component paddle is
Port ( Up, Do, Le, Ri : in std_logic; --where those movement signals go, yo :)
Reset : in std_logic;
frame_clk : in std_logic;
PaddleX : out std_logic_vector(10 downto 0);
PaddleY : out std_logic_vector(10 downto 0);
PaddleS : out std_logic_vector(10 downto 0));
end component;
-----------------------------------------------------
component vga_controller is
Port ( clk : in std_logic;
reset : in std_logic;
hs : out std_logic;
vs : out std_logic;
pixel_clk : out std_logic;
blank : out std_logic;
sync : out std_logic;
DrawX : out std_logic_vector(10 downto 0);
DrawY : out std_logic_vector(10 downto 0));
end component;
-----------------------------------------------------
component Color_Mapper is
Port ( game_status : in std_logic_vector(3 downto 0);
BallX, BallY : in std_logic_vector(10 downto 0);
PaddleX, PaddleY : in std_logic_vector (10 downto 0);
BricksX, BricksY : in std_logic_vector(219 downto 0);
BricksOn : in std_logic_vector(19 downto 0);
DrawX, DrawY : in std_logic_vector(10 downto 0);
Ball_size : in std_logic_vector(10 downto 0);
Paddle_size : in std_logic_vector(10 downto 0);
-- Brick_size : in std_logic_vector(9 downto 0);
Red : out std_logic_vector(9 downto 0);
Green : out std_logic_vector(9 downto 0);
Blue : out std_logic_vector(9 downto 0));
end component;
-----------------------------------------------------
component Brick is
Port ( clk, Reset, frame_clk : in std_logic;
BallX, BallY, BallS : in std_logic_vector(10 downto 0);
BrickXIn, BrickYIn : in std_logic_vector(10 downto 0);
--BrickX, BrickY: out std_logic_vector(10 downto 0);
brick_hit: out std_logic;
BrickOn: out std_logic);
end component;
-----------------------------------------------------
-----------------------------------------------------
signal Reset_h, vsSig, StartSig, win_statusSig : std_logic;
signal BallXSig, BallYSig, BallSSig, PaddleXSig, PaddleYSig, PaddleSSig : std_logic_vector(10 downto 0);
signal DrawXSig, DrawYSig : std_logic_vector(10 downto 0);
signal statusSig : std_logic_vector(3 downto 0);
signal BricksXsig, BricksYsig : std_logic_vector(219 downto 0);
signal BricksOn, brick_hitSig : std_logic_vector(19 downto 0) ;
signal paddle_loss_statusSig : std_logic_vector(1 downto 0);
signal scoreOutSig : std_logic_vector (7 downto 0);
begin
Reset_h <= Reset; -- The push buttons are active low
StartSig <= Start;
find_win: process(BricksOn)
begin
win_statusSig <= '0';
if (BricksOn = "00000000000000000000") then
win_statusSig <= '1';
end if;
end process;
----------------Brick 0----------------------------------------
BricksXsig(10 downto 0) <= CONV_STD_LOGIC_VECTOR(90, 11);
BricksYsig(10 downto 0) <= CONV_STD_LOGIC_VECTOR(20, 11);
----------------Brick 1----------------------------------------
BricksXsig(21 downto 11) <= CONV_STD_LOGIC_VECTOR(190, 11);
BricksYsig(21 downto 11) <= CONV_STD_LOGIC_VECTOR(20, 11);
----------------Brick 2----------------------------------------
BricksXsig(32 downto 22) <= CONV_STD_LOGIC_VECTOR(290, 11);
BricksYsig(32 downto 22) <= CONV_STD_LOGIC_VECTOR(20, 11);
----------------Brick 3----------------------------------------
BricksXsig(43 downto 33) <= CONV_STD_LOGIC_VECTOR(390, 11);
BricksYsig(43 downto 33) <= CONV_STD_LOGIC_VECTOR(20, 11);
----------------Brick 4----------------------------------------
BricksXsig(54 downto 44) <= CONV_STD_LOGIC_VECTOR(490, 11);
BricksYsig(54 downto 44) <= CONV_STD_LOGIC_VECTOR(20, 11);
----------------Brick 5----------------------------------------
BricksXsig(65 downto 55) <= CONV_STD_LOGIC_VECTOR(90, 11);
BricksYsig(65 downto 55) <= CONV_STD_LOGIC_VECTOR(70, 11);
----------------Brick 6----------------------------------------
BricksXsig(76 downto 66) <= CONV_STD_LOGIC_VECTOR(190, 11);
BricksYsig(76 downto 66) <= CONV_STD_LOGIC_VECTOR(70, 11);
----------------Brick 7----------------------------------------
BricksXsig(87 downto 77) <= CONV_STD_LOGIC_VECTOR(290, 11);
BricksYsig(87 downto 77) <= CONV_STD_LOGIC_VECTOR(70, 11);
----------------Brick 8----------------------------------------
BricksXsig(98 downto 88) <= CONV_STD_LOGIC_VECTOR(390, 11);
BricksYsig(98 downto 88) <= CONV_STD_LOGIC_VECTOR(70, 11);
----------------Brick 9----------------------------------------
BricksXsig(109 downto 99) <= CONV_STD_LOGIC_VECTOR(490, 11);
BricksYsig(109 downto 99) <= CONV_STD_LOGIC_VECTOR(70, 11);
----------------Brick 10---------------------------------------
BricksXsig(120 downto 110) <= CONV_STD_LOGIC_VECTOR(90, 11);
BricksYsig(120 downto 110) <= CONV_STD_LOGIC_VECTOR(120, 11);
----------------Brick 11---------------------------------------
BricksXsig(131 downto 121) <= CONV_STD_LOGIC_VECTOR(190, 11);
BricksYsig(131 downto 121) <= CONV_STD_LOGIC_VECTOR(120, 11);
----------------Brick 12---------------------------------------
BricksXsig(142 downto 132) <= CONV_STD_LOGIC_VECTOR(290, 11);
BricksYsig(142 downto 132) <= CONV_STD_LOGIC_VECTOR(120, 11);
----------------Brick 13---------------------------------------
BricksXsig(153 downto 143) <= CONV_STD_LOGIC_VECTOR(390, 11);
BricksYsig(153 downto 143) <= CONV_STD_LOGIC_VECTOR(120, 11);
----------------Brick 14---------------------------------------
BricksXsig(164 downto 154) <= CONV_STD_LOGIC_VECTOR(490, 11);
BricksYsig(164 downto 154) <= CONV_STD_LOGIC_VECTOR(120, 11);
----------------Brick 15---------------------------------------
BricksXsig(175 downto 165) <= CONV_STD_LOGIC_VECTOR(90, 11);
BricksYsig(175 downto 165) <= CONV_STD_LOGIC_VECTOR(170, 11);
----------------Brick 16---------------------------------------
BricksXsig(186 downto 176) <= CONV_STD_LOGIC_VECTOR(190, 11);
BricksYsig(186 downto 176) <= CONV_STD_LOGIC_VECTOR(170, 11);
----------------Brick 17---------------------------------------
BricksXsig(197 downto 187) <= CONV_STD_LOGIC_VECTOR(290, 11);
BricksYsig(197 downto 187) <= CONV_STD_LOGIC_VECTOR(170, 11);
----------------Brick 18---------------------------------------
BricksXsig(208 downto 198) <= CONV_STD_LOGIC_VECTOR(390, 11);
BricksYsig(208 downto 198) <= CONV_STD_LOGIC_VECTOR(170, 11);
----------------Brick 19---------------------------------------
BricksXsig(219 downto 209) <= CONV_STD_LOGIC_VECTOR(490, 11);
BricksYsig(219 downto 209) <= CONV_STD_LOGIC_VECTOR(170, 11);
----------------End of Bricks----------------------------------
--Brick1Xsig <= CONV_STD_LOGIC_VECTOR(0, 11);
--Brick1Ysig <= CONV_STD_LOGIC_VECTOR(0, 11);
-----------------------------------------------------
game_handler_instance : game_handler
Port map(frame_clk => vsSig,
paddle_loss_statusIn => paddle_loss_statusSig,
brick_hitIn => brick_hitSig,
win_statusIn => win_statusSig,
ResetIn => Reset_h,
ResetScore => ResScore,
game_status => statusSig,
score => scoreOutSig);
-----------------------------------------------------
vgaSync_instance : vga_controller
Port map(clk => clk,
reset => Reset_h,
hs => hs,
vs => vsSig,
pixel_clk => VGA_clk,
blank => blank,
sync => sync,
DrawX => DrawXSig,
DrawY => DrawYSig);
-----------------------------------------------------
ball_instance : ball
Port map(Le => Le,
Ri => Ri,
clk => clk,
paddle_loss_status => paddle_loss_statusSig,
Reset => Reset_h,
frame_clk => vsSig, -- Vertical Sync used as an "ad hoc" 60 Hz clock signal
StartMove => StartSig,
seedIn => Seed,
BallX => BallXSig, -- (This is why we registered it in the vga controller!)
BallY => BallYSig,
BallS => BallSSig,
BricksX => BricksXSig,
BricksY => BricksYSig,
BricksOn => BricksOn,
PaddleX => PaddleXSig,
PaddleY => PaddleYSig,
PaddleS => PaddleSSig);
-----------------------------------------------------
paddle_instance : paddle
Port map(Up => Up, --connecting the signals like magic
Do => Do,
Le => Le,
Ri => Ri,
Reset => Reset_h,
frame_clk => vsSig, -- Vertical Sync used as an "ad hoc" 60 Hz clock signal
PaddleX => PaddleXSig, -- (This is why we registered it in the vga controller!)
PaddleY => PaddleYSig,
PaddleS => PaddleSSig);
-----------------------------------------------------
Color_instance : Color_Mapper
Port Map(game_status => statusSig,
BallX => BallXSig,
BallY => BallYSig,
PaddleX => PaddleXSig,
PaddleY => PaddleYSig,
BricksX => BricksXSig,
BricksY => BricksYSig,
BricksOn => BricksOn,
DrawX => DrawXSig,
DrawY => DrawYSig,
Ball_size => BallSSig,
Paddle_size => PaddleSSig,
Red => Red,
Green => Green,
Blue => Blue);
------------------Start Bricks-----------------------
-----------------------------------------------------
Brick0 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(10 downto 0),
BrickYIn => BricksYSig(10 downto 0),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(0),
BrickOn => BricksOn(0) );
-----------------------------------------------------
Brick1 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(21 downto 11),
BrickYIn => BricksYSig(21 downto 11),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(1),
BrickOn => BricksOn(1) );
-----------------------------------------------------
Brick2 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(32 downto 22),
BrickYIn => BricksYSig(32 downto 22),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(2),
BrickOn => BricksOn(2) );
-----------------------------------------------------
Brick3 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(43 downto 33),
BrickYIn => BricksYSig(43 downto 33),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(3),
BrickOn => BricksOn(3) );
-----------------------------------------------------
Brick4 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(54 downto 44),
BrickYIn => BricksYSig(54 downto 44),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(4),
BrickOn => BricksOn(4) );
-----------------------------------------------------
Brick5 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(65 downto 55),
BrickYIn => BricksYSig(65 downto 55),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(5),
BrickOn => BricksOn(5) );
-----------------------------------------------------
Brick6 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(76 downto 66),
BrickYIn => BricksYSig(76 downto 66),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(6),
BrickOn => BricksOn(6) );
-----------------------------------------------------
Brick7 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(87 downto 77),
BrickYIn => BricksYSig(87 downto 77),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(7),
BrickOn => BricksOn(7) );
-----------------------------------------------------
Brick8 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(98 downto 88),
BrickYIn => BricksYSig(98 downto 88),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(8),
BrickOn => BricksOn(8) );
-----------------------------------------------------
Brick9 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(109 downto 99),
BrickYIn => BricksYSig(109 downto 99),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(9),
BrickOn => BricksOn(9) );
-----------------------------------------------------
Brick10 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(120 downto 110),
BrickYIn => BricksYSig(120 downto 110),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(10),
BrickOn => BricksOn(10) );
-----------------------------------------------------
Brick11 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(131 downto 121),
BrickYIn => BricksYSig(131 downto 121),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(11),
BrickOn => BricksOn(11) );
-----------------------------------------------------
Brick12 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(142 downto 132),
BrickYIn => BricksYSig(142 downto 132),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(12),
BrickOn => BricksOn(12) );
-----------------------------------------------------
Brick13 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(153 downto 143),
BrickYIn => BricksYSig(153 downto 143),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(13),
BrickOn => BricksOn(13) );
-----------------------------------------------------
Brick14 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(164 downto 154),
BrickYIn => BricksYSig(164 downto 154),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(14),
BrickOn => BricksOn(14) );
-----------------------------------------------------
Brick15 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(175 downto 165),
BrickYIn => BricksYSig(175 downto 165),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(15),
BrickOn => BricksOn(15) );
-----------------------------------------------------
Brick16 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(186 downto 176),
BrickYIn => BricksYSig(186 downto 176),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(16),
BrickOn => BricksOn(16) );
-----------------------------------------------------
Brick17 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(197 downto 187),
BrickYIn => BricksYSig(197 downto 187),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(17),
BrickOn => BricksOn(17) );
-----------------------------------------------------
Brick18 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(208 downto 198),
BrickYIn => BricksYSig(208 downto 198),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(18),
BrickOn => BricksOn(18) );
-----------------------------------------------------
Brick19 : Brick
Port Map(
clk => clk,
Reset => Reset_h,
frame_clk => vsSig,
BallX => BallXSig,
BallY => BallYSig,
BallS => BallSSig,
BrickXIn => BricksXSig(219 downto 209),
BrickYIn => BricksYSig(219 downto 209),
--BrickX => BricksXSig(10 downto 0),
--BrickY => BricksYSig(10 downto 0),
brick_hit => brick_hitSig(19),
BrickOn => BricksOn(19) );
-----------------------------------------------------
vs <= vsSig;
game_statusOut <= statusSig;
scoreOutH <= scoreOutSig(7 downto 4);
scoreOutL <= scoreOutSig(3 downto 0);
end Behavioral;
|
mit
|
5ff61ade17f9a3eba14e984c4fbcebe1
| 0.509115 | 4.121089 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/controller_polynomial_syndrome_computing.vhd
| 1 | 37,642 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Polynomial_Syndrome_Computing
-- Module Name: Controller_Polynomial_Syndrome_Computing
-- Project Name: McEliece Goppa decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st and 3rd step in Goppa Decoding.
--
-- This circuit is the state machine for polynomial_syndrome_computing_n_v2.
-- This state machine is for both during syndrome computation and polynomial sigma
-- evaluation and roots search.
--
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_polynomial_syndrome_computing is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
mode_polynomial_syndrome : in STD_LOGIC;
last_load_x_values : in STD_LOGIC;
last_store_x_values : in STD_LOGIC;
limit_polynomial_degree : in STD_LOGIC;
last_syndrome_value : in STD_LOGIC;
final_syndrome_evaluation : in STD_LOGIC;
pipeline_ready : in STD_LOGIC;
evaluation_data_in : out STD_LOGIC;
reg_write_enable_rst : out STD_LOGIC;
ctr_load_x_address_ce : out STD_LOGIC;
ctr_load_x_address_rst : out STD_LOGIC;
ctr_store_x_address_ce : out STD_LOGIC;
ctr_store_x_address_rst : out STD_LOGIC;
reg_first_values_ce : out STD_LOGIC;
reg_first_values_rst : out STD_LOGIC;
ctr_address_polynomial_syndrome_ce : out STD_LOGIC;
ctr_address_polynomial_syndrome_load : out STD_LOGIC;
ctr_address_polynomial_syndrome_increment_decrement : out STD_LOGIC;
ctr_address_polynomial_syndrome_rst : out STD_LOGIC;
reg_x_rst_rst : out STD_LOGIC;
reg_store_temporary_syndrome_ce : out STD_LOGIC;
reg_final_syndrome_evaluation_ce : out STD_LOGIC;
reg_final_syndrome_evaluation_rst : out STD_LOGIC;
shift_polynomial_ce_ce : out STD_LOGIC;
shift_polynomial_ce_rst : out STD_LOGIC;
shift_syndrome_mode_data_in : out STD_LOGIC;
shift_syndrome_mode_rst : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
finalize_syndrome : out STD_LOGIC;
last_coefficients : out STD_LOGIC;
computation_finalized : out STD_LOGIC
);
end controller_polynomial_syndrome_computing;
architecture Behavioral of controller_polynomial_syndrome_computing is
type State is (reset, poly_load_counter, poly_load_first_polynomial_coefficient, poly_reset_first_polynomial_coefficient, poly_prepare_load_polynomial_coefficient, poly_load_polynomial_coefficient, poly_reset_polynomial_coefficient, poly_load_x, poly_load_x_write_x, poly_last_load_x_write_x, poly_write_x, poly_final,
synd_load_counter, synd_load_L_syndrome_values, synd_prepare_write_load_L_values, synd_write_load_L_values, synd_prepare_write_L_values, synd_write_L_values, synd_write_syndrome_values, synd_last_write_syndrome_values, synd_final_write_syndrome_values, synd_final_last_write_syndrome_values, synd_final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, last_load_x_values, last_store_x_values, last_syndrome_value, final_syndrome_evaluation, limit_polynomial_degree, pipeline_ready)
begin
case (actual_state) is
when reset =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '1';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '1';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '1';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '1';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_load_counter =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_load_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
elsif(limit_polynomial_degree = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
end if;
when poly_reset_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '1';
computation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '1';
computation_finalized <= '0';
end if;
when poly_prepare_load_polynomial_coefficient =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '1';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_load_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
elsif(limit_polynomial_degree = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
end if;
when poly_reset_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '1';
computation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '1';
computation_finalized <= '0';
end if;
when poly_load_x =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_load_x_write_x =>
if(last_load_x_values = '1' and limit_polynomial_degree = '0') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
end if;
when poly_last_load_x_write_x =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_write_x =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when poly_final =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '1';
when synd_load_counter =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '1';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '1';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '1';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '1';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_load_L_syndrome_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_prepare_write_load_L_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_write_load_L_values =>
if(last_load_x_values = '1') then
ctr_load_x_address_ce <= '0';
else
ctr_load_x_address_ce <= '1';
end if;
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_prepare_write_L_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '1';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_write_L_values =>
if(last_syndrome_value = '1') then
reg_final_syndrome_evaluation_ce <= '1';
else
reg_final_syndrome_evaluation_ce <= '0';
end if;
if(last_store_x_values = '1') then
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
reg_store_temporary_syndrome_ce <= '1';
shift_polynomial_ce_rst <= '1';
else
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_increment_decrement <= '1';
reg_store_temporary_syndrome_ce <= '0';
shift_polynomial_ce_rst <= '0';
end if;
evaluation_data_in <= '1';
ctr_load_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '0';
shift_polynomial_ce_ce <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_write_syndrome_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '1';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_last_write_syndrome_values =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '1';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_final_write_syndrome_values =>
if(final_syndrome_evaluation = '1' and last_syndrome_value = '0') then
write_enable_new_value_syndrome <= '0';
else
write_enable_new_value_syndrome <= '1';
end if;
if(last_syndrome_value = '1') then
reg_final_syndrome_evaluation_rst <= '1';
else
reg_final_syndrome_evaluation_rst <= '0';
end if;
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '1';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_final_last_write_syndrome_values =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
when synd_final =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '1';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '1';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '1';
finalize_syndrome <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '1';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
last_coefficients <= '0';
computation_finalized <= '1';
when others =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_syndrome_ce <= '0';
ctr_address_polynomial_syndrome_load <= '0';
ctr_address_polynomial_syndrome_increment_decrement <= '0';
ctr_address_polynomial_syndrome_rst <= '0';
reg_store_temporary_syndrome_ce <= '0';
reg_x_rst_rst <= '0';
reg_final_syndrome_evaluation_ce <= '0';
reg_final_syndrome_evaluation_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
shift_syndrome_mode_data_in <= '0';
shift_syndrome_mode_rst <= '0';
write_enable_new_value_syndrome <= '0';
finalize_syndrome <= '1';
last_coefficients <= '0';
last_coefficients <= '0';
computation_finalized <= '0';
end case;
end process;
NewState: process (actual_state, mode_polynomial_syndrome, last_load_x_values, last_store_x_values, last_syndrome_value, final_syndrome_evaluation, limit_polynomial_degree, pipeline_ready)
begin
case (actual_state) is
when reset =>
if(mode_polynomial_syndrome = '1') then
next_state <= synd_load_counter;
else
next_state <= poly_load_counter;
end if;
when poly_load_counter =>
next_state <= poly_load_first_polynomial_coefficient;
when poly_load_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= poly_load_x;
elsif(limit_polynomial_degree = '1') then
next_state <= poly_reset_first_polynomial_coefficient;
else
next_state <= poly_load_first_polynomial_coefficient;
end if;
when poly_reset_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= poly_load_x;
else
next_state <= poly_reset_first_polynomial_coefficient;
end if;
when poly_prepare_load_polynomial_coefficient =>
next_state <= poly_load_polynomial_coefficient;
when poly_load_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= poly_load_x;
elsif(limit_polynomial_degree = '1') then
next_state <= poly_reset_polynomial_coefficient;
else
next_state <= poly_load_polynomial_coefficient;
end if;
when poly_reset_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= poly_load_x;
else
next_state <= poly_reset_polynomial_coefficient;
end if;
when poly_load_x =>
next_state <= poly_load_x_write_x;
when poly_load_x_write_x =>
if(last_load_x_values = '1') then
if(limit_polynomial_degree = '1') then
next_state <= poly_last_load_x_write_x;
else
next_state <= poly_prepare_load_polynomial_coefficient;
end if;
else
next_state <= poly_load_x_write_x;
end if;
when poly_last_load_x_write_x =>
next_state <= poly_write_x;
when poly_write_x =>
if(last_store_x_values = '1') then
next_state <= poly_final;
else
next_state <= poly_write_x;
end if;
when poly_final =>
next_state <= poly_final;
when synd_load_counter =>
next_state <= synd_load_L_syndrome_values;
when synd_load_L_syndrome_values =>
if(pipeline_ready = '1') then
next_state <= synd_prepare_write_load_L_values;
else
next_state <= synd_load_L_syndrome_values;
end if;
when synd_prepare_write_load_L_values =>
next_state <= synd_write_load_L_values;
when synd_write_load_L_values =>
if(last_load_x_values = '1') then
next_state <= synd_prepare_write_L_values;
else
next_state <= synd_write_load_L_values;
end if;
when synd_prepare_write_L_values =>
next_state <= synd_write_L_values;
when synd_write_L_values =>
if(last_store_x_values = '1') then
if(final_syndrome_evaluation = '1' or last_syndrome_value = '1') then
next_state <= synd_final_write_syndrome_values;
else
next_state <= synd_write_syndrome_values;
end if;
else
next_state <= synd_write_L_values;
end if;
when synd_write_syndrome_values =>
if(pipeline_ready = '1') then
next_state <= synd_last_write_syndrome_values;
else
next_state <= synd_write_syndrome_values;
end if;
when synd_last_write_syndrome_values =>
next_state <= synd_write_load_L_values;
when synd_final_write_syndrome_values =>
if(pipeline_ready = '1') then
next_state <= synd_final_last_write_syndrome_values;
else
next_state <= synd_final_write_syndrome_values;
end if;
when synd_final_last_write_syndrome_values =>
next_state <= synd_final;
when synd_final =>
next_state <= synd_final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
1f30177c5e783ecb84f7104c17ab8afc
| 0.627092 | 2.858597 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/solving_key_equation_4.vhd
| 1 | 41,759 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Solving_Key_Equation_4
-- Module Name: Solving_Key_Equation_4
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 2nd step in Goppa Code Decoding.
--
-- This circuit solves the polynomial key equation sigma with the polynomial syndrome.
-- To solve the key equation, this circuit employs a modified extended euclidean algorithm
-- The modification is made to stop the algorithm when polynomial, represented here as G, has
-- degree less or equal than the polynomial key equation sigma desired degree.
-- The syndrome is the input and expected to be of degree 2*final_degree, and after computations
-- polynomial C, will hold sigma with degree less or equal to final_degree.
--
-- This is pipeline circuit version that can operate all four polynomials at the same time.
--
-- Parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- final_degree :
--
-- The final degree size expected for polynomial sigma to have. This parameter depends
-- of the Goppa code used.
--
-- size_final_degree :
--
-- The number of bits necessary to hold the polynomial with degree of final_degree, which
-- has final_degree + 1 coefficients. This is ceil(log2(final_degree+1)).
--
-- Dependencies:
--
-- VHDL-93
--
-- controller_FG_solving_key_equation_4 Rev 1.0
-- controller_BC_solving_key_equation_4 Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_decrement_load_nbits Rev 1.0
-- counter_decrement_load_rst_nbits Rev 1.0
-- mult_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity solving_key_equation_4 is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 27;
-- size_final_degree : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 66;
-- size_final_degree : integer := 7
-- QD-GOPPA [2528, 2144, 32, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 32;
-- size_final_degree : integer := 5
-- QD-GOPPA [2816, 2048, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [3328, 2560, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [7296, 5632, 128, 13] --
gf_2_m : integer range 1 to 20 := 13;
final_degree : integer := 128;
size_final_degree : integer := 7
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_F : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_G : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_B : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_C : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_F : out STD_LOGIC;
write_enable_G : out STD_LOGIC;
write_enable_B : out STD_LOGIC;
write_enable_C : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_F : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_B : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_G : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_C : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_value_F : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_G : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_B : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_C : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_F : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_G : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_B : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_C : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end solving_key_equation_4;
architecture Behavioral of solving_key_equation_4 is
component controller_FG_solving_key_equation_4
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
F_equal_zero : in STD_LOGIC;
i_FG_equal_zero : in STD_LOGIC;
i_FG_minus_j_less_than_zero : in STD_LOGIC;
degree_G_less_equal_final_degree : in STD_LOGIC;
degree_F_less_than_degree_G : in STD_LOGIC;
reg_looking_degree_FG_q : in STD_LOGIC_VECTOR(0 downto 0);
ready_controller_BC : in STD_LOGIC;
ready_controller_FG : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
signal_inv : out STD_LOGIC;
write_enable_F : out STD_LOGIC;
write_enable_G : out STD_LOGIC;
sel_base_mul_FG : out STD_LOGIC;
reg_h_ce : out STD_LOGIC;
ctr_i_FG_ce : out STD_LOGIC;
ctr_i_FG_load : out STD_LOGIC;
ctr_i_FG_rst : out STD_LOGIC;
reg_j_ce : out STD_LOGIC;
reg_j_rst : out STD_LOGIC;
reg_F_ce : out STD_LOGIC;
reg_F_rst : out STD_LOGIC;
reg_new_value_F_ce : out STD_LOGIC;
reg_new_value_F_rst : out STD_LOGIC;
sel_load_new_value_F : out STD_LOGIC;
reg_G_ce : out STD_LOGIC;
reg_G_rst : out STD_LOGIC;
reg_new_value_G_ce : out STD_LOGIC;
reg_new_value_G_rst : out STD_LOGIC;
sel_reg_new_value_G : out STD_LOGIC;
ctr_degree_F_ce : out STD_LOGIC;
ctr_degree_F_load : out STD_LOGIC;
ctr_degree_F_rst : out STD_LOGIC;
reg_degree_G_ce : out STD_LOGIC;
reg_degree_G_rst : out STD_LOGIC;
reg_looking_degree_FG_d : out STD_LOGIC_VECTOR(0 downto 0);
reg_looking_degree_FG_ce : out STD_LOGIC;
reg_swap_ce : out STD_LOGIC;
reg_swap_rst : out STD_LOGIC;
ctr_load_address_F_ce : out STD_LOGIC;
ctr_load_address_F_load : out STD_LOGIC;
ctr_load_address_G_ce : out STD_LOGIC;
ctr_load_address_G_load : out STD_LOGIC;
reg_bus_address_F_ce : out STD_LOGIC;
reg_bus_address_G_ce : out STD_LOGIC;
reg_calc_address_F_ce : out STD_LOGIC;
reg_calc_address_G_ce : out STD_LOGIC;
reg_store_address_F_ce : out STD_LOGIC;
reg_store_address_F_rst : out STD_LOGIC;
reg_store_address_G_ce : out STD_LOGIC;
reg_store_address_G_rst : out STD_LOGIC;
enable_external_swap : out STD_LOGIC
);
end component;
component controller_BC_solving_key_equation_4
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
B_equal_zero : in STD_LOGIC;
i_BC_equal_zero : in STD_LOGIC;
i_BC_minus_j_less_than_zero : in STD_LOGIC;
degree_G_less_equal_final_degree : in STD_LOGIC;
degree_F_less_than_degree_G : in STD_LOGIC;
degree_B_equal_degree_C_plus_j : in STD_LOGIC;
degree_B_less_than_degree_C_plus_j : in STD_LOGIC;
reg_looking_degree_BC_q : in STD_LOGIC_VECTOR(0 downto 0);
ready_controller_FG : in STD_LOGIC;
ready_controller_BC : out STD_LOGIC;
write_enable_B : out STD_LOGIC;
write_enable_C : out STD_LOGIC;
ctr_i_BC_ce : out STD_LOGIC;
ctr_i_BC_load : out STD_LOGIC;
ctr_i_BC_rst : out STD_LOGIC;
reg_B_ce : out STD_LOGIC;
reg_B_rst : out STD_LOGIC;
reg_new_value_B_ce : out STD_LOGIC;
reg_new_value_B_rst : out STD_LOGIC;
sel_reg_new_value_B : out STD_LOGIC;
sel_load_new_value_B : out STD_LOGIC;
reg_C_ce : out STD_LOGIC;
reg_C_rst : out STD_LOGIC;
reg_new_value_C_ce : out STD_LOGIC;
reg_new_value_C_rst : out STD_LOGIC;
ctr_degree_B_ce : out STD_LOGIC;
ctr_degree_B_load : out STD_LOGIC;
ctr_degree_B_rst : out STD_LOGIC;
sel_ctr_degree_B : out STD_LOGIC;
reg_degree_C_ce : out STD_LOGIC;
reg_degree_C_rst : out STD_LOGIC;
reg_looking_degree_BC_d : out STD_LOGIC_VECTOR(0 downto 0);
reg_looking_degree_BC_ce : out STD_LOGIC;
ctr_load_address_B_ce : out STD_LOGIC;
ctr_load_address_B_load : out STD_LOGIC;
ctr_load_address_B_rst : out STD_LOGIC;
ctr_load_address_C_ce : out STD_LOGIC;
ctr_load_address_C_load : out STD_LOGIC;
ctr_load_address_C_rst : out STD_LOGIC;
reg_bus_address_B_ce : out STD_LOGIC;
reg_bus_address_C_ce : out STD_LOGIC;
reg_calc_address_B_ce : out STD_LOGIC;
reg_calc_address_C_ce : out STD_LOGIC;
reg_store_address_B_ce : out STD_LOGIC;
reg_store_address_B_rst : out STD_LOGIC;
reg_store_address_C_ce : out STD_LOGIC;
reg_store_address_C_rst : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_decrement_load_rst_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component counter_decrement_load_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component mult_gf_2_m
Generic (gf_2_m : integer range 1 to 20 := 11);
Port (
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal base_mult_FG_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal base_mult_FG_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal base_mult_FG_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal base_mult_BC_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal base_mult_BC_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal base_mult_BC_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_base_mul_FG : STD_LOGIC;
signal reg_h_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_h_ce : STD_LOGIC;
signal reg_h_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_ce : STD_LOGIC;
signal reg_inv_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_i_FG_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_i_FG_ce : STD_LOGIC;
signal ctr_i_FG_load : STD_LOGIC;
signal ctr_i_FG_rst : STD_LOGIC;
constant ctr_i_FG_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree - 1,size_final_degree + 2));
signal ctr_i_FG_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_i_BC_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_i_BC_ce : STD_LOGIC;
signal ctr_i_BC_load : STD_LOGIC;
signal ctr_i_BC_rst : STD_LOGIC;
constant ctr_i_BC_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(final_degree,size_final_degree + 2));
signal ctr_i_BC_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_j_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_j_ce : STD_LOGIC;
signal reg_j_rst : STD_LOGIC;
constant reg_j_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal reg_j_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_F_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_F_ce : STD_LOGIC;
signal reg_F_rst : STD_LOGIC;
constant reg_F_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_F_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_G_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_G_ce : STD_LOGIC;
signal reg_G_rst : STD_LOGIC;
constant reg_G_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_G_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_B_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_B_ce : STD_LOGIC;
signal reg_B_rst : STD_LOGIC;
constant reg_B_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_B_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_C_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_C_ce : STD_LOGIC;
signal reg_C_rst : STD_LOGIC;
constant reg_C_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_C_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_F_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_F_ce : STD_LOGIC;
signal reg_new_value_F_rst : STD_LOGIC;
constant reg_new_value_F_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_new_value_F_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_G_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_G_ce : STD_LOGIC;
signal reg_new_value_G_rst : STD_LOGIC;
constant reg_new_value_G_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_new_value_G_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_reg_new_value_G : STD_LOGIC;
signal reg_new_value_B_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_B_ce : STD_LOGIC;
signal reg_new_value_B_rst : STD_LOGIC;
constant reg_new_value_B_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_new_value_B_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_reg_new_value_B : STD_LOGIC;
signal reg_new_value_C_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_C_ce : STD_LOGIC;
signal reg_new_value_C_rst : STD_LOGIC;
constant reg_new_value_C_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_new_value_C_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_degree_F_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_degree_F_ce : STD_LOGIC;
signal ctr_degree_F_load : STD_LOGIC;
signal ctr_degree_F_rst : STD_LOGIC;
constant ctr_degree_F_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree - 1,size_final_degree + 2));
signal ctr_degree_F_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_G_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_G_ce : STD_LOGIC;
signal reg_degree_G_rst : STD_LOGIC;
constant reg_degree_G_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree,size_final_degree + 2));
signal reg_degree_G_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_degree_B_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_degree_B_ce : STD_LOGIC;
signal ctr_degree_B_load : STD_LOGIC;
signal ctr_degree_B_rst : STD_LOGIC;
constant ctr_degree_B_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal ctr_degree_B_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_ctr_degree_B : STD_LOGIC;
signal reg_degree_C_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_C_ce : STD_LOGIC;
signal reg_degree_C_rst : STD_LOGIC;
constant reg_degree_C_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal reg_degree_C_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_looking_degree_FG_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_looking_degree_FG_ce : STD_LOGIC;
signal reg_looking_degree_FG_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_looking_degree_BC_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_looking_degree_BC_ce : STD_LOGIC;
signal reg_looking_degree_BC_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_swap_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_swap_ce : STD_LOGIC;
signal reg_swap_rst : STD_LOGIC;
constant reg_swap_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_swap_q : STD_LOGIC_VECTOR(0 downto 0);
signal i_FG_minus_j : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal i_BC_minus_j : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal degree_C_plus_j : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal int_value_F : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_value_C : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_load_new_value_F : STD_LOGIC;
signal sel_load_new_value_B : STD_LOGIC;
signal int_write_enable_F : STD_LOGIC;
signal int_write_enable_G : STD_LOGIC;
signal int_write_enable_B : STD_LOGIC;
signal int_write_enable_C : STD_LOGIC;
signal address_degree_F : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_degree_C_plus_J : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_degree_G : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_degree_C : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_load_address_F_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_load_address_F_ce : STD_LOGIC;
signal ctr_load_address_F_load : STD_LOGIC;
signal ctr_load_address_F_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_load_address_G_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_load_address_G_ce : STD_LOGIC;
signal ctr_load_address_G_load : STD_LOGIC;
signal ctr_load_address_G_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_load_address_B_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_load_address_B_ce : STD_LOGIC;
signal ctr_load_address_B_load : STD_LOGIC;
signal ctr_load_address_B_rst : STD_LOGIC;
constant ctr_load_address_B_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(final_degree,size_final_degree + 2));
signal ctr_load_address_B_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_load_address_C_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_load_address_C_ce : STD_LOGIC;
signal ctr_load_address_C_load : STD_LOGIC;
signal ctr_load_address_C_rst : STD_LOGIC;
constant ctr_load_address_C_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(final_degree,size_final_degree + 2));
signal ctr_load_address_C_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_bus_address_F_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_bus_address_F_ce : STD_LOGIC;
signal reg_bus_address_F_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_bus_address_G_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_bus_address_G_ce : STD_LOGIC;
signal reg_bus_address_G_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_bus_address_B_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_bus_address_B_ce : STD_LOGIC;
signal reg_bus_address_B_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_bus_address_C_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_bus_address_C_ce : STD_LOGIC;
signal reg_bus_address_C_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_calc_address_F_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_calc_address_F_ce : STD_LOGIC;
signal reg_calc_address_F_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_calc_address_G_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_calc_address_G_ce : STD_LOGIC;
signal reg_calc_address_G_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_calc_address_B_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_calc_address_B_ce : STD_LOGIC;
signal reg_calc_address_B_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_calc_address_C_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_calc_address_C_ce : STD_LOGIC;
signal reg_calc_address_C_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_store_address_F_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_store_address_F_ce : STD_LOGIC;
signal reg_store_address_F_rst : STD_LOGIC;
constant reg_store_address_F_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := (others => '0');
signal reg_store_address_F_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_store_address_G_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_store_address_G_ce : STD_LOGIC;
signal reg_store_address_G_rst : STD_LOGIC;
constant reg_store_address_G_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := (others => '0');
signal reg_store_address_G_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_store_address_B_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_store_address_B_ce : STD_LOGIC;
signal reg_store_address_B_rst : STD_LOGIC;
constant reg_store_address_B_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := (others => '0');
signal reg_store_address_B_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_store_address_C_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_store_address_C_ce : STD_LOGIC;
signal reg_store_address_C_rst : STD_LOGIC;
constant reg_store_address_C_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := (others => '0');
signal reg_store_address_C_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ready_controller_BC : STD_LOGIC;
signal ready_controller_FG : STD_LOGIC;
signal enable_external_swap : STD_LOGIC;
signal F_equal_zero : STD_LOGIC;
signal B_equal_zero : STD_LOGIC;
signal i_FG_equal_zero : STD_LOGIC;
signal i_BC_equal_zero : STD_LOGIC;
signal i_FG_minus_j_less_than_zero : STD_LOGIC;
signal i_BC_minus_j_less_than_zero : STD_LOGIC;
signal degree_G_less_equal_final_degree : STD_LOGIC;
signal degree_F_less_than_degree_G : STD_LOGIC;
signal degree_B_equal_degree_C_plus_j : STD_LOGIC;
signal degree_B_less_than_degree_C_plus_j : STD_LOGIC;
begin
controller_FG : controller_FG_solving_key_equation_4
Port Map(
clk => clk,
rst => rst,
F_equal_zero => F_equal_zero,
i_FG_equal_zero => i_FG_equal_zero,
i_FG_minus_j_less_than_zero => i_FG_minus_j_less_than_zero,
degree_G_less_equal_final_degree => degree_G_less_equal_final_degree,
degree_F_less_than_degree_G => degree_F_less_than_degree_G,
reg_looking_degree_FG_q => reg_looking_degree_FG_q,
ready_controller_BC => ready_controller_BC,
ready_controller_FG => ready_controller_FG,
key_equation_found => key_equation_found,
signal_inv => signal_inv,
write_enable_F => int_write_enable_F,
write_enable_G => int_write_enable_G,
sel_base_mul_FG => sel_base_mul_FG,
reg_h_ce => reg_h_ce,
ctr_i_FG_ce => ctr_i_FG_ce,
ctr_i_FG_load => ctr_i_FG_load,
ctr_i_FG_rst => ctr_i_FG_rst,
reg_j_ce => reg_j_ce,
reg_j_rst => reg_j_rst,
reg_F_ce => reg_F_ce,
reg_F_rst => reg_F_rst,
reg_new_value_F_ce => reg_new_value_F_ce,
reg_new_value_F_rst => reg_new_value_F_rst,
sel_load_new_value_F => sel_load_new_value_F,
reg_G_ce => reg_G_ce,
reg_G_rst => reg_G_rst,
reg_new_value_G_ce => reg_new_value_G_ce,
reg_new_value_G_rst => reg_new_value_G_rst,
sel_reg_new_value_G => sel_reg_new_value_G,
ctr_degree_F_ce => ctr_degree_F_ce,
ctr_degree_F_load => ctr_degree_F_load,
ctr_degree_F_rst => ctr_degree_F_rst,
reg_degree_G_ce => reg_degree_G_ce,
reg_degree_G_rst => reg_degree_G_rst,
reg_looking_degree_FG_d => reg_looking_degree_FG_d,
reg_looking_degree_FG_ce => reg_looking_degree_FG_ce,
reg_swap_ce => reg_swap_ce,
reg_swap_rst => reg_swap_rst,
ctr_load_address_F_ce => ctr_load_address_F_ce,
ctr_load_address_F_load => ctr_load_address_F_load,
ctr_load_address_G_ce => ctr_load_address_G_ce,
ctr_load_address_G_load => ctr_load_address_G_load,
reg_bus_address_F_ce => reg_bus_address_F_ce,
reg_bus_address_G_ce => reg_bus_address_G_ce,
reg_calc_address_F_ce => reg_calc_address_F_ce,
reg_calc_address_G_ce => reg_calc_address_G_ce,
reg_store_address_F_ce => reg_store_address_F_ce,
reg_store_address_F_rst => reg_store_address_F_rst,
reg_store_address_G_ce => reg_store_address_G_ce,
reg_store_address_G_rst => reg_store_address_G_rst,
enable_external_swap => enable_external_swap
);
controller_BC : controller_BC_solving_key_equation_4
Port Map(
clk => clk,
rst => rst,
B_equal_zero => B_equal_zero,
i_BC_equal_zero => i_BC_equal_zero,
i_BC_minus_j_less_than_zero => i_BC_minus_j_less_than_zero,
degree_G_less_equal_final_degree => degree_G_less_equal_final_degree,
degree_F_less_than_degree_G => degree_F_less_than_degree_G,
degree_B_equal_degree_C_plus_j => degree_B_equal_degree_C_plus_j,
degree_B_less_than_degree_C_plus_j => degree_B_less_than_degree_C_plus_j,
reg_looking_degree_BC_q => reg_looking_degree_BC_q,
ready_controller_FG => ready_controller_FG,
ready_controller_BC => ready_controller_BC,
write_enable_B => int_write_enable_B,
write_enable_C => int_write_enable_C,
ctr_i_BC_ce => ctr_i_BC_ce,
ctr_i_BC_load => ctr_i_BC_load,
ctr_i_BC_rst => ctr_i_BC_rst,
reg_B_ce => reg_B_ce,
reg_B_rst => reg_B_rst,
reg_new_value_B_ce => reg_new_value_B_ce,
reg_new_value_B_rst => reg_new_value_B_rst,
sel_reg_new_value_B => sel_reg_new_value_B,
sel_load_new_value_B => sel_load_new_value_B,
reg_C_ce => reg_C_ce,
reg_C_rst => reg_C_rst,
reg_new_value_C_ce => reg_new_value_C_ce,
reg_new_value_C_rst => reg_new_value_C_rst,
ctr_degree_B_ce => ctr_degree_B_ce,
ctr_degree_B_load => ctr_degree_B_load,
ctr_degree_B_rst => ctr_degree_B_rst,
sel_ctr_degree_B => sel_ctr_degree_B,
reg_degree_C_ce => reg_degree_C_ce,
reg_degree_C_rst => reg_degree_C_rst,
reg_looking_degree_BC_d => reg_looking_degree_BC_d,
reg_looking_degree_BC_ce => reg_looking_degree_BC_ce,
ctr_load_address_B_ce => ctr_load_address_B_ce,
ctr_load_address_B_load => ctr_load_address_B_load,
ctr_load_address_B_rst => ctr_load_address_B_rst,
ctr_load_address_C_ce => ctr_load_address_C_ce,
ctr_load_address_C_load => ctr_load_address_C_load,
ctr_load_address_C_rst => ctr_load_address_C_rst,
reg_bus_address_B_ce => reg_bus_address_B_ce,
reg_bus_address_C_ce => reg_bus_address_C_ce,
reg_calc_address_B_ce => reg_calc_address_B_ce,
reg_calc_address_C_ce => reg_calc_address_C_ce,
reg_store_address_B_ce => reg_store_address_B_ce,
reg_store_address_B_rst => reg_store_address_B_rst,
reg_store_address_C_ce => reg_store_address_C_ce,
reg_store_address_C_rst => reg_store_address_C_rst
);
base_mult_FG : mult_gf_2_m
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => base_mult_FG_a,
b => base_mult_FG_b,
o => base_mult_FG_o
);
base_mult_BC : mult_gf_2_m
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => base_mult_BC_a,
b => base_mult_BC_b,
o => base_mult_BC_o
);
reg_h : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_h_d,
clk => clk,
ce => reg_h_ce,
q => reg_h_q
);
reg_inv : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_inv_d,
clk => clk,
ce => reg_inv_ce,
q => reg_inv_q
);
ctr_i_FG : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_i_FG_d,
clk => clk,
ce => ctr_i_FG_ce,
load => ctr_i_FG_load,
rst => ctr_i_FG_rst,
rst_value => ctr_i_FG_rst_value,
q => ctr_i_FG_q
);
ctr_i_BC : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_i_BC_d,
clk => clk,
ce => ctr_i_BC_ce,
load => ctr_i_BC_load,
rst => ctr_i_BC_rst,
rst_value => ctr_i_BC_rst_value,
q => ctr_i_BC_q
);
reg_j : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_j_d,
clk => clk,
ce => reg_j_ce,
rst => reg_j_rst,
rst_value => reg_j_rst_value,
q => reg_j_q
);
reg_F : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_F_d,
clk => clk,
rst => reg_F_rst,
rst_value => reg_F_rst_value,
ce => reg_F_ce,
q => reg_F_q
);
reg_G : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_G_d,
clk => clk,
rst => reg_G_rst,
rst_value => reg_G_rst_value,
ce => reg_G_ce,
q => reg_G_q
);
reg_B : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_B_d,
clk => clk,
rst => reg_B_rst,
rst_value => reg_B_rst_value,
ce => reg_B_ce,
q => reg_B_q
);
reg_C : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_C_d,
clk => clk,
rst => reg_C_rst,
rst_value => reg_C_rst_value,
ce => reg_C_ce,
q => reg_C_q
);
reg_new_value_F : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_F_d,
clk => clk,
ce => reg_new_value_F_ce,
rst => reg_new_value_F_rst,
rst_value => reg_new_value_F_rst_value,
q => reg_new_value_F_q
);
reg_new_value_G : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_G_d,
clk => clk,
ce => reg_new_value_G_ce,
rst => reg_new_value_G_rst,
rst_value => reg_new_value_G_rst_value,
q => reg_new_value_G_q
);
reg_new_value_B : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_B_d,
clk => clk,
ce => reg_new_value_B_ce,
rst => reg_new_value_B_rst,
rst_value => reg_new_value_B_rst_value,
q => reg_new_value_B_q
);
reg_new_value_C : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_C_d,
clk => clk,
ce => reg_new_value_C_ce,
rst => reg_new_value_C_rst,
rst_value => reg_new_value_C_rst_value,
q => reg_new_value_C_q
);
ctr_degree_F : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_degree_F_d,
clk => clk,
ce => ctr_degree_F_ce,
load => ctr_degree_F_load,
rst => ctr_degree_F_rst,
rst_value => ctr_degree_F_rst_value,
q => ctr_degree_F_q
);
reg_degree_G : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_G_d,
clk => clk,
rst => reg_degree_G_rst,
rst_value => reg_degree_G_rst_value,
ce => reg_degree_G_ce,
q => reg_degree_G_q
);
ctr_degree_B : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_degree_B_d,
clk => clk,
ce => ctr_degree_B_ce,
load => ctr_degree_B_load,
rst => ctr_degree_B_rst,
rst_value => ctr_degree_B_rst_value,
q => ctr_degree_B_q
);
reg_degree_C : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_C_d,
clk => clk,
rst => reg_degree_C_rst,
rst_value => reg_degree_C_rst_value,
ce => reg_degree_C_ce,
q => reg_degree_C_q
);
ctr_load_address_F : counter_decrement_load_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_load_address_F_d,
clk => clk,
ce => ctr_load_address_F_ce,
load => ctr_load_address_F_load,
q => ctr_load_address_F_q
);
ctr_load_address_G : counter_decrement_load_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_load_address_G_d,
clk => clk,
ce => ctr_load_address_G_ce,
load => ctr_load_address_G_load,
q => ctr_load_address_G_q
);
ctr_load_address_B : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_load_address_B_d,
clk => clk,
ce => ctr_load_address_B_ce,
load => ctr_load_address_B_load,
rst => ctr_load_address_B_rst,
rst_value => ctr_load_address_B_rst_value,
q => ctr_load_address_B_q
);
ctr_load_address_C : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_load_address_C_d,
clk => clk,
ce => ctr_load_address_C_ce,
load => ctr_load_address_C_load,
rst => ctr_load_address_C_rst,
rst_value => ctr_load_address_C_rst_value,
q => ctr_load_address_C_q
);
reg_bus_address_F : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_bus_address_F_d,
clk => clk,
ce => reg_bus_address_F_ce,
q => reg_bus_address_F_q
);
reg_bus_address_G : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_bus_address_G_d,
clk => clk,
ce => reg_bus_address_G_ce,
q => reg_bus_address_G_q
);
reg_bus_address_B : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_bus_address_B_d,
clk => clk,
ce => reg_bus_address_B_ce,
q => reg_bus_address_B_q
);
reg_bus_address_C : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_bus_address_C_d,
clk => clk,
ce => reg_bus_address_C_ce,
q => reg_bus_address_C_q
);
reg_calc_address_F : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_calc_address_F_d,
clk => clk,
ce => reg_calc_address_F_ce,
q => reg_calc_address_F_q
);
reg_calc_address_G : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_calc_address_G_d,
clk => clk,
ce => reg_calc_address_G_ce,
q => reg_calc_address_G_q
);
reg_calc_address_B : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_calc_address_B_d,
clk => clk,
ce => reg_calc_address_B_ce,
q => reg_calc_address_B_q
);
reg_calc_address_C : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_calc_address_C_d,
clk => clk,
ce => reg_calc_address_C_ce,
q => reg_calc_address_C_q
);
reg_store_address_F : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_store_address_F_d,
clk => clk,
ce => reg_store_address_F_ce,
rst => reg_store_address_F_rst,
rst_value => reg_store_address_F_rst_value,
q => reg_store_address_F_q
);
reg_store_address_G : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_store_address_G_d,
clk => clk,
ce => reg_store_address_G_ce,
rst => reg_store_address_G_rst,
rst_value => reg_store_address_G_rst_value,
q => reg_store_address_G_q
);
reg_store_address_B : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_store_address_B_d,
clk => clk,
ce => reg_store_address_B_ce,
rst => reg_store_address_B_rst,
rst_value => reg_store_address_B_rst_value,
q => reg_store_address_B_q
);
reg_store_address_C : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_store_address_C_d,
clk => clk,
ce => reg_store_address_C_ce,
rst => reg_store_address_C_rst,
rst_value => reg_store_address_C_rst_value,
q => reg_store_address_C_q
);
reg_looking_degree_FG : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_looking_degree_FG_d,
clk => clk,
ce => reg_looking_degree_FG_ce,
q => reg_looking_degree_FG_q
);
reg_looking_degree_BC : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_looking_degree_BC_d,
clk => clk,
ce => reg_looking_degree_BC_ce,
q => reg_looking_degree_BC_q
);
reg_swap : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_swap_d,
clk => clk,
ce => reg_swap_ce,
rst => reg_swap_rst,
rst_value => reg_swap_rst_value,
q => reg_swap_q
);
base_mult_FG_a <= reg_inv_q when sel_base_mul_FG = '1' else
reg_h_q;
base_mult_FG_b <= reg_F_q when sel_base_mul_FG = '1' else
reg_G_q;
base_mult_BC_a <= reg_h_q;
base_mult_BC_b <= reg_C_q;
reg_h_d <= base_mult_FG_o;
reg_inv_d <= value_inv;
reg_inv_ce <= ready_inv;
ctr_i_FG_d <= ctr_degree_F_q;
ctr_i_BC_d <= degree_C_plus_j;
reg_j_d <= std_logic_vector(unsigned(ctr_degree_F_q) - unsigned(reg_degree_G_q));
reg_F_d <= int_value_F;
reg_G_d <= int_value_G;
reg_B_d <= int_value_B;
reg_C_d <= int_value_C;
ctr_degree_F_d <= reg_degree_G_q;
reg_degree_G_d <= ctr_degree_F_q;
ctr_degree_B_d <= degree_C_plus_j when sel_ctr_degree_B = '1' else
reg_degree_C_q;
degree_C_plus_j <= std_logic_vector(unsigned(reg_degree_C_q) + unsigned(reg_j_q));
i_FG_minus_j <= std_logic_vector(unsigned(ctr_i_FG_q) - unsigned(reg_j_q));
i_BC_minus_j <= std_logic_vector(unsigned(ctr_i_BC_q) - unsigned(reg_j_q));
reg_degree_C_d <= ctr_degree_B_q;
reg_swap_d <= not reg_swap_q;
reg_new_value_F_d <= (base_mult_FG_o xor reg_F_q) when sel_load_new_value_F = '1' else
reg_F_q;
reg_new_value_G_d <= std_logic_vector(to_unsigned(1, reg_G_d'length)) when sel_reg_new_value_G = '1' else
reg_G_q;
reg_new_value_B_d <= (base_mult_BC_o xor reg_B_q) when sel_load_new_value_B = '1' else
std_logic_vector(to_unsigned(1, reg_B_d'length)) when sel_reg_new_value_B = '1' else
reg_B_q;
reg_new_value_C_d <= reg_C_q;
int_value_F <= value_G when reg_swap_q = "1" else value_F;
int_value_G <= value_F when reg_swap_q = "1" else value_G;
int_value_B <= value_C when reg_swap_q = "1" else value_B;
int_value_C <= value_B when reg_swap_q = "1" else value_C;
new_value_inv <= reg_new_value_F_q;
new_value_F <= reg_new_value_G_q when (reg_swap_q(0) and enable_external_swap) = '1' else reg_new_value_F_q;
new_value_G <= reg_new_value_F_q when (reg_swap_q(0) and enable_external_swap) = '1' else reg_new_value_G_q;
new_value_B <= reg_new_value_C_q when (reg_swap_q(0) and enable_external_swap) = '1' else reg_new_value_B_q;
new_value_C <= reg_new_value_B_q when (reg_swap_q(0) and enable_external_swap) = '1' else reg_new_value_C_q;
write_enable_F <= int_write_enable_G when (reg_swap_q(0) and enable_external_swap) = '1' else int_write_enable_F;
write_enable_G <= int_write_enable_F when (reg_swap_q(0) and enable_external_swap) = '1' else int_write_enable_G;
write_enable_B <= int_write_enable_C when (reg_swap_q(0) and enable_external_swap) = '1' else int_write_enable_B;
write_enable_C <= int_write_enable_B when (reg_swap_q(0) and enable_external_swap) = '1' else int_write_enable_C;
address_degree_F <= ctr_degree_F_q;
address_degree_C_plus_j <= degree_C_plus_j;
address_degree_G <= reg_degree_G_q;
address_degree_C <= reg_degree_C_q;
ctr_load_address_F_d <= address_degree_F;
ctr_load_address_G_d <= address_degree_G;
ctr_load_address_B_d <= address_degree_C_plus_j;
ctr_load_address_C_d <= address_degree_C;
reg_bus_address_F_d <= ctr_load_address_F_q;
reg_bus_address_G_d <= ctr_load_address_G_q;
reg_bus_address_B_d <= ctr_load_address_B_q;
reg_bus_address_C_d <= ctr_load_address_C_q;
reg_calc_address_F_d <= reg_bus_address_F_q;
reg_calc_address_G_d <= reg_bus_address_G_q;
reg_calc_address_B_d <= reg_bus_address_B_q;
reg_calc_address_C_d <= reg_bus_address_C_q;
reg_store_address_F_d <= reg_calc_address_F_q;
reg_store_address_G_d <= reg_calc_address_G_q;
reg_store_address_B_d <= reg_calc_address_B_q;
reg_store_address_C_d <= reg_calc_address_C_q;
address_value_F <= ctr_load_address_G_q when reg_swap_q(0) = '1' else ctr_load_address_F_q;
address_value_G <= ctr_load_address_F_q when reg_swap_q(0) = '1' else ctr_load_address_G_q;
address_value_B <= ctr_load_address_C_q when reg_swap_q(0) = '1' else ctr_load_address_B_q;
address_value_C <= ctr_load_address_B_q when reg_swap_q(0) = '1' else ctr_load_address_C_q;
address_new_value_F <= reg_store_address_G_q when (reg_swap_q(0) and enable_external_swap) = '1' else reg_store_address_F_q;
address_new_value_G <= reg_store_address_F_q when (reg_swap_q(0) and enable_external_swap) = '1' else reg_store_address_G_q;
address_new_value_B <= reg_store_address_C_q when (reg_swap_q(0) and enable_external_swap) = '1' else reg_store_address_B_q;
address_new_value_C <= reg_store_address_B_q when (reg_swap_q(0) and enable_external_swap) = '1' else reg_store_address_C_q;
F_equal_zero <= '1' when (reg_new_value_F_q = std_logic_vector(to_unsigned(0,reg_F_q'length))) else '0';
B_equal_zero <= '1' when (reg_new_value_B_q = std_logic_vector(to_unsigned(0,reg_B_q'length))) else '0';
i_FG_equal_zero <= '1' when (ctr_i_FG_q = std_logic_vector(to_unsigned(0,ctr_i_FG_q'length))) else '0';
i_BC_equal_zero <= '1' when (ctr_i_BC_q = std_logic_vector(to_unsigned(0,ctr_i_BC_q'length))) else '0';
i_FG_minus_j_less_than_zero <= '1' when (signed(i_FG_minus_j) < to_signed(0,i_FG_minus_j'length)) else '0';
i_BC_minus_j_less_than_zero <= '1' when (signed(i_BC_minus_j) < to_signed(0,i_FG_minus_j'length)) else '0';
degree_G_less_equal_final_degree <= '1' when (unsigned(reg_degree_G_q) <= to_unsigned(final_degree-1,reg_degree_G_q'length)) else '0';
degree_F_less_than_degree_G <= '1' when (unsigned(ctr_degree_F_q) < unsigned(reg_degree_G_q)) else '0';
degree_B_equal_degree_C_plus_j <= '1' when (ctr_degree_B_q = degree_C_plus_j) else '0';
degree_B_less_than_degree_C_plus_j <= '1' when (unsigned(ctr_degree_B_q) < unsigned(degree_C_plus_j)) else '0';
end Behavioral;
|
bsd-2-clause
|
bfd9f440a9c035790660fcbb0518c99a
| 0.658517 | 2.478132 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/scaling_values_lut/scaling_values_lut_tb.vhd
| 1 | 1,477 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity scaling_values_lut_tb is
end entity;
architecture scaling_values_lut_tb_arq of scaling_values_lut_tb is
signal steps : integer := 0;
signal scaling_value : std_logic_vector(31 downto 0) := (others => '0');
component scaling_values_lut is
generic(TOTAL_BITS: integer := 32);
port(
steps: in integer := 0;
scaling_value: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
for scaling_values_lut_0 : scaling_values_lut use entity work.scaling_values_lut;
begin
scaling_values_lut_0 : scaling_values_lut
generic map(TOTAL_BITS => 32)
port map(
steps => steps,
scaling_value => scaling_value
);
process
type pattern_type is record
i : integer;
sv : std_logic_vector(31 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
(1,"00000000000000001011010100000100"),
(6,"00000000000000001001101101111011"),
(20,"00000000000000001001101101110100")
);
begin
for i in patterns'range loop
-- Set the inputs.
steps <= patterns(i).i;
wait for 1 ns;
assert patterns(i).sv = scaling_value report "BAD SCALING VALUE, GOT: " & integer'image(to_integer(unsigned(scaling_value)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
edbc40f74be756f9abc57567406abed4
| 0.68585 | 3.246154 | false | false | false | false |
sakolkar/4BitSorter
|
Synopsis/sorter_top.vhd
| 1 | 3,216 |
----------------------------------------------------------
-- ECE403 Lab3 Sorter Toplevel - 4 4-bit unsigned sorter
-- Jiawei Wu
-- Satyen Akolkar
-- Top level: sorter_top.vhd
-- Maps the multiplier core to the input and output pads
----------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sorter_top IS
Port (
padA, padB, padC, padD : IN STD_LOGIC_VECTOR(3 downto 0);
padClk : IN STD_LOGIC;
padS1reg, padS2reg, padS3reg, padS4reg : OUT STD_LOGIC_VECTOR(3 downto 0)
);
END sorter_top;
ARCHITECTURE Structure of sorter_top IS
component sorter IS
Port (
Clk : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(3 downto 0);
B : IN STD_LOGIC_VECTOR(3 downto 0);
C : IN STD_LOGIC_VECTOR(3 downto 0);
D : IN STD_LOGIC_VECTOR(3 downto 0);
S1reg : OUT STD_LOGIC_VECTOR(3 downto 0);
S2reg : OUT STD_LOGIC_VECTOR(3 downto 0);
S3reg : OUT STD_LOGIC_VECTOR(3 downto 0);
S4reg : OUT STD_LOGIC_VECTOR(3 downto 0)
);
END component;
component PDO12CDG
port(A : in std_logic;
PAD : out std_logic);
end component;
component PDUDGZ
port(Y : out std_logic;
PAD : in std_logic);
end component;
signal A, B, C, D : STD_LOGIC_VECTOR(3 downto 0);
signal S1reg, S2reg, S3reg, S4reg : STD_LOGIC_VECTOR(3 downto 0);
signal clk : STD_LOGIC;
begin
-- Input A pad mapping
padAGen: for i in 3 downto 0 generate
begin
inpA: PDUDGZ port map (Y => A(i), PAD => padA(i));
end generate;
-- Input B pad mapping
padBGen: for i in 3 downto 0 generate
begin
inpB: PDUDGZ port map (Y => B(i), PAD => padB(i));
end generate;
-- Input C pad mapping
padCGen: for i in 3 downto 0 generate
begin
inpC: PDUDGZ port map (Y => C(i), PAD => padC(i));
end generate;
-- Input D pad mapping
padDGen: for i in 3 downto 0 generate
begin
inpD: PDUDGZ port map (Y => D(i), PAD => padD(i));
end generate;
-- Output result pad mapping
padS1Gen: for i in 3 downto 0 generate
begin
opResS1: PDO12CDG port map (PAD => padS1reg(i), A => S1reg(i));
end generate;
padS2Gen: for i in 3 downto 0 generate
begin
opResS2: PDO12CDG port map (PAD => padS2reg(i), A => S2reg(i));
end generate;
padS3Gen: for i in 3 downto 0 generate
begin
opResS3: PDO12CDG port map (PAD => padS3reg(i), A => S3reg(i));
end generate;
padS4Gen: for i in 3 downto 0 generate
begin
opResS4: PDO12CDG port map (PAD => padS4reg(i), A => S4reg(i));
end generate;
-- Misc pad mapping
padClkG: PDUDGZ port map (Y => Clk, PAD => padClk);
-- Sorter mapping
coreG: sorter port map (Clk => Clk, A => A, B => B, C => C, D => D, S1reg => S1reg,
S2reg => S2reg, S3reg => S3reg, S4reg => S4reg);
END Structure;
|
apache-2.0
|
cfb5108f8639cb3d816dbda74237f43d
| 0.534515 | 3.522453 | false | false | false | false |
laurivosandi/hdl
|
arithmetic/src/carry_lookahead_adder.vhd
| 1 | 1,002 |
library ieee;
use ieee.std_logic_1164.all;
-- 15-bit carry look-ahead adder
entity carry_lookahead_adder is
port (
a : in std_logic_vector (14 downto 0);
b : in std_logic_vector (14 downto 0);
ci : in std_logic;
s : out std_logic_vector (14 downto 0);
co : out std_logic
);
end carry_lookahead_adder;
architecture behavioral of carry_lookahead_adder is
signal t : std_logic_vector(14 DOWNTO 0);
signal g : std_logic_vector(14 DOWNTO 0);
signal p : std_logic_vector(14 DOWNTO 0);
signal c : std_logic_vector(14 DOWNTO 1);
begin
-- Product stage
g <= a and b;
p <= a or b;
-- Sum stage
t <= a xor b;
-- Carry stage
c(1) <= g(0) or (p(0) and ci);
carry_loop: for i in 1 to 13 generate
c(i+1) <= g(i) or (p(i) and c(i));
end generate;
co <= g(14) or (p(14) and c(14));
s(0) <= t(0) xor ci;
s(14 downto 1) <= t(14 downto 1) xor c(14 downto 1);
end behavioral;
|
mit
|
d93a81481fa7d81891b2b59e8baaa52d
| 0.566866 | 3.06422 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/controller_BC_solving_key_equation_4.vhd
| 1 | 41,230 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_BC_Solving_Key_Equation_4
-- Module Name: Controller_BC_Solving_Key_Equation_4
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 2nd step in Goppa Code Decoding.
--
-- This is a state machine circuit that controls the part of computing
-- polynomials BC in solving_key_equation_4. This state machine is synchronized
-- with the Controller_FG_Solving_Key_Equation_4, in some states it waits for the other
-- machine to finish.
-- This state machine have 3 phases: first phase variable initialization,
-- second computation of polynomial sigma, third step writing the polynomial sigma
-- on a specific memory position.
--
-- Dependencies:
--
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_BC_solving_key_equation_4 is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
B_equal_zero : in STD_LOGIC;
i_BC_equal_zero : in STD_LOGIC;
i_BC_minus_j_less_than_zero : in STD_LOGIC;
degree_G_less_equal_final_degree : in STD_LOGIC;
degree_F_less_than_degree_G : in STD_LOGIC;
degree_B_equal_degree_C_plus_j : in STD_LOGIC;
degree_B_less_than_degree_C_plus_j : in STD_LOGIC;
reg_looking_degree_BC_q : in STD_LOGIC_VECTOR(0 downto 0);
ready_controller_FG : in STD_LOGIC;
ready_controller_BC : out STD_LOGIC;
write_enable_B : out STD_LOGIC;
write_enable_C : out STD_LOGIC;
ctr_i_BC_ce : out STD_LOGIC;
ctr_i_BC_load : out STD_LOGIC;
ctr_i_BC_rst : out STD_LOGIC;
reg_B_ce : out STD_LOGIC;
reg_B_rst : out STD_LOGIC;
reg_new_value_B_ce : out STD_LOGIC;
reg_new_value_B_rst : out STD_LOGIC;
sel_reg_new_value_B : out STD_LOGIC;
sel_load_new_value_B : out STD_LOGIC;
reg_C_ce : out STD_LOGIC;
reg_C_rst : out STD_LOGIC;
reg_new_value_C_ce : out STD_LOGIC;
reg_new_value_C_rst : out STD_LOGIC;
ctr_degree_B_ce : out STD_LOGIC;
ctr_degree_B_load : out STD_LOGIC;
ctr_degree_B_rst : out STD_LOGIC;
sel_ctr_degree_B : out STD_LOGIC;
reg_degree_C_ce : out STD_LOGIC;
reg_degree_C_rst : out STD_LOGIC;
reg_looking_degree_BC_d : out STD_LOGIC_VECTOR(0 downto 0);
reg_looking_degree_BC_ce : out STD_LOGIC;
ctr_load_address_B_ce : out STD_LOGIC;
ctr_load_address_B_load : out STD_LOGIC;
ctr_load_address_B_rst : out STD_LOGIC;
ctr_load_address_C_ce : out STD_LOGIC;
ctr_load_address_C_load : out STD_LOGIC;
ctr_load_address_C_rst : out STD_LOGIC;
reg_bus_address_B_ce : out STD_LOGIC;
reg_bus_address_C_ce : out STD_LOGIC;
reg_calc_address_B_ce : out STD_LOGIC;
reg_calc_address_C_ce : out STD_LOGIC;
reg_store_address_B_ce : out STD_LOGIC;
reg_store_address_B_rst : out STD_LOGIC;
reg_store_address_C_ce : out STD_LOGIC;
reg_store_address_C_rst : out STD_LOGIC
);
end controller_BC_solving_key_equation_4;
architecture Behavioral of controller_BC_solving_key_equation_4 is
type State is (reset, load_counter, load_counter_2, prepare_store_B_C, prepare_store_B_C_2, store_B_C, last_store_B_C, swap_F_G_B_C, wait_j_controller_FG, prepare_degree_B, finalize_i, prepare_i, prepare_load_B_C, load_store_B_C, wait_finalize_controller_FG, prepare_final_swap, preparel_swap_address, prepare_load_sigma, prepare_load_sigma_2, load_sigma, load_store_sigma, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process(actual_state, B_equal_zero, i_BC_equal_zero, i_BC_minus_j_less_than_zero, degree_G_less_equal_final_degree, degree_F_less_than_degree_G, degree_B_equal_degree_C_plus_j, degree_B_less_than_degree_C_plus_j, reg_looking_degree_BC_q)
begin
case (actual_state) is
when reset =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '1';
reg_B_ce <= '0';
reg_B_rst <= '1';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '1';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '1';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '0';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '1';
ctr_load_address_C_ce <= '0';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '1';
reg_bus_address_B_ce <= '0';
reg_bus_address_C_ce <= '0';
reg_calc_address_B_ce <= '0';
reg_calc_address_C_ce <= '0';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '1';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '1';
ready_controller_BC <= '0';
when load_counter =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '1';
reg_B_ce <= '0';
reg_B_rst <= '0';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '0';
reg_new_value_C_ce <= '1';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '0';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '1';
ctr_load_address_C_ce <= '0';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '1';
reg_bus_address_B_ce <= '0';
reg_bus_address_C_ce <= '0';
reg_calc_address_B_ce <= '0';
reg_calc_address_C_ce <= '0';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
ready_controller_BC <= '0';
when load_counter_2 =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '0';
reg_B_rst <= '0';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '1';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '0';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '1';
reg_bus_address_C_ce <= '1';
reg_calc_address_B_ce <= '0';
reg_calc_address_C_ce <= '0';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
when prepare_store_B_C =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '0';
reg_B_rst <= '0';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '1';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '0';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '1';
reg_bus_address_C_ce <= '1';
reg_calc_address_B_ce <= '1';
reg_calc_address_C_ce <= '1';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
when prepare_store_B_C_2 =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '0';
reg_B_rst <= '0';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '1';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '0';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '1';
reg_bus_address_C_ce <= '1';
reg_calc_address_B_ce <= '1';
reg_calc_address_C_ce <= '1';
reg_store_address_B_ce <= '1';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '1';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
when store_B_C =>
if(i_BC_equal_zero = '1') then
write_enable_B <= '1';
write_enable_C <= '1';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '0';
reg_B_rst <= '0';
reg_new_value_B_ce <= '1';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '1';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '0';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '0';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '0';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '0';
reg_bus_address_C_ce <= '0';
reg_calc_address_B_ce <= '0';
reg_calc_address_C_ce <= '0';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
else
write_enable_B <= '1';
write_enable_C <= '1';
ctr_i_BC_ce <= '1';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '0';
reg_B_rst <= '0';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '1';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '0';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '1';
reg_bus_address_C_ce <= '1';
reg_calc_address_B_ce <= '1';
reg_calc_address_C_ce <= '1';
reg_store_address_B_ce <= '1';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '1';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
end if;
when last_store_B_C =>
write_enable_B <= '1';
write_enable_C <= '1';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '0';
reg_B_rst <= '0';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '0';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '0';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '0';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '0';
reg_bus_address_C_ce <= '0';
reg_calc_address_B_ce <= '0';
reg_calc_address_C_ce <= '0';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
when swap_F_G_B_C =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '0';
reg_B_rst <= '0';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '0';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '1';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '1';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '0';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '0';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '0';
reg_bus_address_C_ce <= '0';
reg_calc_address_B_ce <= '0';
reg_calc_address_C_ce <= '0';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '1';
when wait_j_controller_FG =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '0';
reg_B_rst <= '0';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '0';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '0';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '0';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '0';
reg_bus_address_C_ce <= '0';
reg_calc_address_B_ce <= '0';
reg_calc_address_C_ce <= '0';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '1';
when prepare_degree_B =>
if(degree_B_equal_degree_C_plus_j = '1') then
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '0';
reg_B_rst <= '0';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '0';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "1";
reg_looking_degree_BC_ce <= '1';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '1';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '1';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '0';
reg_bus_address_C_ce <= '0';
reg_calc_address_B_ce <= '0';
reg_calc_address_C_ce <= '0';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
elsif(degree_B_less_than_degree_C_plus_j = '1') then
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '0';
reg_B_rst <= '0';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '0';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '1';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '1';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '1';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '1';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '1';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '0';
reg_bus_address_C_ce <= '0';
reg_calc_address_B_ce <= '0';
reg_calc_address_C_ce <= '0';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
else
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '0';
reg_B_rst <= '0';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '0';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '1';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '1';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '1';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '0';
reg_bus_address_C_ce <= '0';
reg_calc_address_B_ce <= '0';
reg_calc_address_C_ce <= '0';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
end if;
when prepare_i =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '1';
ctr_i_BC_load <= '1';
ctr_i_BC_rst <= '0';
reg_B_ce <= '0';
reg_B_rst <= '0';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '0';
sel_load_new_value_B <= '0';
sel_reg_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '0';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '1';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '1';
reg_bus_address_C_ce <= '1';
reg_calc_address_B_ce <= '0';
reg_calc_address_C_ce <= '0';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
when finalize_i =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '1';
reg_B_rst <= '0';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '1';
reg_C_rst <= '0';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '1';
reg_bus_address_C_ce <= '1';
reg_calc_address_B_ce <= '1';
reg_calc_address_C_ce <= '1';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '1';
when prepare_load_B_C =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '1';
reg_B_rst <= '0';
reg_new_value_B_ce <= '1';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '1';
reg_C_ce <= '1';
reg_C_rst <= '0';
reg_new_value_C_ce <= '1';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '1';
reg_bus_address_C_ce <= '1';
reg_calc_address_B_ce <= '1';
reg_calc_address_C_ce <= '1';
reg_store_address_B_ce <= '1';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '1';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
when load_store_B_C =>
if(i_BC_equal_zero = '1') then
ready_controller_BC <= '1';
else
ready_controller_BC <= '0';
end if;
if(i_BC_minus_j_less_than_zero = '1') then
if(reg_looking_degree_BC_q(0) = '1' and B_equal_zero = '1') then
write_enable_B <= '1';
write_enable_C <= '0';
ctr_i_BC_ce <= '1';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '1';
reg_B_rst <= '0';
reg_new_value_B_ce <= '1';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '1';
reg_C_ce <= '0';
reg_C_rst <= '1';
reg_new_value_C_ce <= '1';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '1';
reg_bus_address_C_ce <= '1';
reg_calc_address_B_ce <= '1';
reg_calc_address_C_ce <= '1';
reg_store_address_B_ce <= '1';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '1';
reg_store_address_C_rst <= '0';
else
write_enable_B <= '1';
write_enable_C <= '0';
ctr_i_BC_ce <= '1';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '1';
reg_B_rst <= '0';
reg_new_value_B_ce <= '1';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '1';
reg_C_ce <= '0';
reg_C_rst <= '1';
reg_new_value_C_ce <= '1';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '1';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '1';
reg_bus_address_C_ce <= '1';
reg_calc_address_B_ce <= '1';
reg_calc_address_C_ce <= '1';
reg_store_address_B_ce <= '1';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '1';
reg_store_address_C_rst <= '0';
end if;
elsif(reg_looking_degree_BC_q(0) = '1' and B_equal_zero = '1') then
write_enable_B <= '1';
write_enable_C <= '0';
ctr_i_BC_ce <= '1';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '1';
reg_B_rst <= '0';
reg_new_value_B_ce <= '1';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '1';
reg_C_ce <= '1';
reg_C_rst <= '0';
reg_new_value_C_ce <= '1';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '1';
reg_bus_address_C_ce <= '1';
reg_calc_address_B_ce <= '1';
reg_calc_address_C_ce <= '1';
reg_store_address_B_ce <= '1';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '1';
reg_store_address_C_rst <= '0';
else
write_enable_B <= '1';
write_enable_C <= '0';
ctr_i_BC_ce <= '1';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '1';
reg_B_rst <= '0';
reg_new_value_B_ce <= '1';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '1';
reg_C_ce <= '1';
reg_C_rst <= '0';
reg_new_value_C_ce <= '1';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '1';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '1';
reg_bus_address_C_ce <= '1';
reg_calc_address_B_ce <= '1';
reg_calc_address_C_ce <= '1';
reg_store_address_B_ce <= '1';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '1';
reg_store_address_C_rst <= '0';
end if;
when wait_finalize_controller_FG =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '0';
reg_B_rst <= '0';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '0';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '0';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '0';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '0';
reg_bus_address_C_ce <= '0';
reg_calc_address_B_ce <= '0';
reg_calc_address_C_ce <= '0';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '1';
when prepare_final_swap =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '1';
reg_B_ce <= '0';
reg_B_rst <= '1';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '1';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '0';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '0';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '0';
reg_bus_address_C_ce <= '0';
reg_calc_address_B_ce <= '0';
reg_calc_address_C_ce <= '0';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
when preparel_swap_address =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '0';
reg_B_rst <= '0';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '0';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '1';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '1';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '0';
reg_bus_address_C_ce <= '0';
reg_calc_address_B_ce <= '0';
reg_calc_address_C_ce <= '0';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
when prepare_load_sigma =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '0';
reg_B_rst <= '0';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '0';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '1';
reg_bus_address_C_ce <= '1';
reg_calc_address_B_ce <= '0';
reg_calc_address_C_ce <= '0';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
when prepare_load_sigma_2 =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '1';
reg_B_rst <= '0';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '1';
reg_C_rst <= '0';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '1';
reg_bus_address_C_ce <= '1';
reg_calc_address_B_ce <= '1';
reg_calc_address_C_ce <= '1';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
when load_sigma =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '1';
reg_B_rst <= '0';
reg_new_value_B_ce <= '1';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '1';
reg_C_rst <= '0';
reg_new_value_C_ce <= '1';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '1';
reg_bus_address_C_ce <= '1';
reg_calc_address_B_ce <= '1';
reg_calc_address_C_ce <= '1';
reg_store_address_B_ce <= '1';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '1';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
when load_store_sigma =>
write_enable_B <= '0';
write_enable_C <= '1';
ctr_i_BC_ce <= '1';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '0';
reg_B_ce <= '1';
reg_B_rst <= '0';
reg_new_value_B_ce <= '1';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '1';
reg_C_rst <= '0';
reg_new_value_C_ce <= '1';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '1';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '1';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '1';
reg_bus_address_C_ce <= '1';
reg_calc_address_B_ce <= '1';
reg_calc_address_C_ce <= '1';
reg_store_address_B_ce <= '1';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '1';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
when final =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '1';
reg_B_ce <= '0';
reg_B_rst <= '1';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '1';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '0';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '0';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '0';
reg_bus_address_C_ce <= '0';
reg_calc_address_B_ce <= '0';
reg_calc_address_C_ce <= '0';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
when others =>
write_enable_B <= '0';
write_enable_C <= '0';
ctr_i_BC_ce <= '0';
ctr_i_BC_load <= '0';
ctr_i_BC_rst <= '1';
reg_B_ce <= '0';
reg_B_rst <= '1';
reg_new_value_B_ce <= '0';
reg_new_value_B_rst <= '0';
sel_reg_new_value_B <= '0';
sel_load_new_value_B <= '0';
reg_C_ce <= '0';
reg_C_rst <= '1';
reg_new_value_C_ce <= '0';
reg_new_value_C_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_BC_d <= "0";
reg_looking_degree_BC_ce <= '0';
ctr_load_address_B_ce <= '0';
ctr_load_address_B_load <= '0';
ctr_load_address_B_rst <= '0';
ctr_load_address_C_ce <= '0';
ctr_load_address_C_load <= '0';
ctr_load_address_C_rst <= '0';
reg_bus_address_B_ce <= '0';
reg_bus_address_C_ce <= '0';
reg_calc_address_B_ce <= '0';
reg_calc_address_C_ce <= '0';
reg_store_address_B_ce <= '0';
reg_store_address_B_rst <= '0';
reg_store_address_C_ce <= '0';
reg_store_address_C_rst <= '0';
ready_controller_BC <= '0';
end case;
end process;
New_State : process(actual_state, ready_controller_FG, B_equal_zero, i_BC_equal_zero, i_BC_minus_j_less_than_zero, degree_G_less_equal_final_degree, degree_F_less_than_degree_G, degree_B_equal_degree_C_plus_j, degree_B_less_than_degree_C_plus_j, reg_looking_degree_BC_q)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= load_counter_2;
when load_counter_2 =>
next_state <= prepare_store_B_C;
when prepare_store_B_C =>
next_state <= prepare_store_B_C_2;
when prepare_store_B_C_2 =>
next_state <= store_B_C;
when store_B_C =>
if(i_BC_equal_zero = '1') then
next_state <= last_store_B_C;
else
next_state <= store_B_C;
end if;
when last_store_B_C =>
next_state <= swap_F_G_B_C;
when swap_F_G_B_C =>
if(ready_controller_FG = '1') then
next_state <= prepare_degree_B;
else
next_state <= wait_j_controller_FG;
end if;
when wait_j_controller_FG =>
if(degree_G_less_equal_final_degree = '1') then
next_state <= prepare_final_swap;
elsif(ready_controller_FG = '1') then
next_state <= prepare_degree_B;
else
next_state <= wait_j_controller_FG;
end if;
when prepare_degree_B =>
next_state <= prepare_i;
when prepare_i =>
next_state <= finalize_i;
when finalize_i =>
next_state <= prepare_load_B_C;
when prepare_load_B_C =>
next_state <= load_store_B_C;
when load_store_B_C =>
if(i_BC_equal_zero = '1') then
if(ready_controller_FG = '0') then
next_state <= wait_finalize_controller_FG;
elsif(degree_G_less_equal_final_degree = '1') then
next_state <= prepare_final_swap;
elsif(degree_F_less_than_degree_G = '1') then
next_state <= swap_F_G_B_C;
else
next_state <= wait_j_controller_FG;
end if;
else
next_state <= load_store_B_C;
end if;
when wait_finalize_controller_FG =>
if(ready_controller_FG = '0') then
next_state <= wait_finalize_controller_FG;
elsif(degree_G_less_equal_final_degree = '1') then
next_state <= prepare_final_swap;
elsif(degree_F_less_than_degree_G = '1') then
next_state <= swap_F_G_B_C;
else
next_state <= wait_j_controller_FG;
end if;
when prepare_final_swap =>
next_state <= preparel_swap_address;
when preparel_swap_address =>
next_state <= prepare_load_sigma;
when prepare_load_sigma =>
next_state <= prepare_load_sigma_2;
when prepare_load_sigma_2 =>
next_state <= load_sigma;
when load_sigma =>
next_state <= load_store_sigma;
when load_store_sigma =>
if(i_BC_equal_zero = '1') then
next_state <= final;
else
next_state <= load_store_sigma;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
011b8f3eea27d52e6aeccd94b9fdb868
| 0.538103 | 2.276768 | false | false | false | false |
BogdanArdelean/FPWAM
|
hardware/src/hdl/DerefUnit.vhd
| 1 | 3,807 |
-------------------------------------------------------------------------------
-- FILE NAME : DerefUnit.vhd
-- MODULE NAME : DerefUnit
-- AUTHOR : Bogdan Ardelean
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2016-05-2 Bogdan Ardelean Created
-------------------------------------------------------------------------------
-- DESCRIPTION : Unit that executes the deref(x) WAM ancillary operation
--
-------------------------------------------------------------------------------
library ieee;
library xil_defaultlib;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FpwamPkg.all;
entity DerefUnit is
generic
(
kAddressWidth : natural := kWamAddressWidth; -- 16
kWordWidth : natural := kWamWordWidth -- 18
);
port
(
clk : in std_logic;
rst : in std_logic;
start_deref : in std_logic;
start_word : in std_logic_vector(kWordWidth -1 downto 0);
memory_in : in std_logic_vector(kWordWidth -1 downto 0);
addr_out : out std_logic_vector(kAddressWidth -1 downto 0);
rd_mem : out std_logic;
res_out : out std_logic_vector(kWordWidth -1 downto 0);
res_addr : out std_logic_vector(kWordWidth -1 downto 0);
done : out std_logic
);
end DerefUnit;
architecture Behavioral of DerefUnit is
type state_t is (idle_t, read_t, check_t, done_t);
signal cr_state, nx_state : state_t;
signal word_reg : std_logic_vector(kWordWidth -1 downto 0);
signal word_reg_addr : std_logic_vector(kWordWidth -1 downto 0);
signal word_comb : std_logic_vector(kWordWidth -1 downto 0);
signal wr_word : std_logic;
begin
res_addr <= word_reg_addr;
WORDREG: process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
word_reg <= (others => '0');
elsif wr_word = '1' then
word_reg <= word_comb;
if cr_state = idle_t then
word_reg_addr <= start_word;
else
word_reg_addr <= word_reg;
end if;
end if;
end if;
end process;
FSM: process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
cr_state <= idle_t;
else
cr_state <= nx_state;
end if;
end if;
end process;
NEXT_STATE: process(cr_state, start_deref, start_word, memory_in, word_reg, rst)
begin
nx_state <= cr_state;
case cr_state is
when idle_t =>
if start_deref = '1' then
if fpwam_tag(start_word) = tag_ref_t then
nx_state <= read_t;
else
nx_state <= done_t;
end if;
end if;
when read_t =>
nx_state <= check_t;
when check_t =>
if fpwam_tag(memory_in) = tag_ref_t and fpwam_value(memory_in) /= fpwam_value(word_reg) then
nx_state <= read_t;
else
nx_state <= done_t;
end if;
when done_t =>
nx_state <= idle_t;
when others =>
null;
end case;
end process;
OUTPUT_DECODE: process(cr_state, start_deref, start_word, memory_in, word_reg, rst)
begin
addr_out <= fpwam_value(word_reg);
word_comb <= (others => '0');
rd_mem <= '0';
res_out <= word_reg;
done <= '0';
wr_word <= '0';
case cr_state is
when idle_t =>
if start_deref = '1' then
wr_word <= '1';
word_comb <= start_word;
end if;
when read_t =>
rd_mem <= '1';
when check_t =>
word_comb <= memory_in;
wr_word <= '1';
when done_t =>
done <= '1';
when others =>
null;
end case;
end process;
end Behavioral;
|
apache-2.0
|
5113246bf59f236b89cb28d5defacf65
| 0.514053 | 3.594901 | false | false | false | false |
lowRISC/greth-library
|
greth_library/techmap/gencomp/gencomp.vhd
| 2 | 5,253 |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Definition of the gencomp package.
--! @details This file defines constants that are used to enable/disable
--! target dependable modules.
--! This file inherits values from the \e grlib library that
--! that are published under GPL license. All unused values may
--! freely removed or reassigned on others values.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
--! @brief Technologies names definition
--! @details This package must be built first in a case of manual compilation
--! order (\e ModelSim).
package gencomp is
--! @brief Total number of the known technologies.
--! @details These values was inherited from the \e grlib library.
constant NTECH : integer := 53;
--! Prototype of the data type for mapping name on certain index.
type tech_ability_type is array (0 to NTECH) of integer;
--! @name Techologies names.
--! @brief Set of the predefined technology names.
--! @{
constant inferred : integer := 0; --! Behaviour simulation target.
constant virtex : integer := 1; --! Not implemented.
constant virtex2 : integer := 2; --! Not implemented.
constant memvirage : integer := 3; --! Not implemented.
constant axcel : integer := 4; --! Not implemented.
constant proasic : integer := 5; --! Not implemented.
constant atc18s : integer := 6; --! Not implemented.
constant altera : integer := 7; --! Not implemented.
constant umc : integer := 8; --! Not implemented.
constant rhumc : integer := 9; --! Not implemented.
constant apa3 : integer := 10; --! Not implemented.
constant spartan3 : integer := 11; --! Not implemented.
constant ihp25 : integer := 12; --! Not implemented.
constant rhlib18t : integer := 13; --! Not implemented.
constant virtex4 : integer := 14; --! Not implemented.
constant lattice : integer := 15; --! Not implemented.
constant ut25 : integer := 16; --! Not implemented.
constant spartan3e : integer := 17; --! Not implemented.
constant peregrine : integer := 18; --! Not implemented.
constant memartisan : integer := 19; --! Not implemented.
constant virtex5 : integer := 20; --! Not implemented.
constant custom1 : integer := 21; --! Not implemented.
constant ihp25rh : integer := 22; --! Not implemented.
constant stratix1 : integer := 23; --! Not implemented.
constant stratix2 : integer := 24; --! Not implemented.
constant eclipse : integer := 25; --! Not implemented.
constant stratix3 : integer := 26; --! Not implemented.
constant cyclone3 : integer := 27; --! Not implemented.
constant memvirage90 : integer := 28; --! Not implemented.
constant tsmc90 : integer := 29; --! Not implemented.
constant easic90 : integer := 30; --! Not implemented.
constant atc18rha : integer := 31; --! Not implemented.
constant smic013 : integer := 32; --! Not implemented.
constant tm65gpl : integer := 33; --! Not implemented.
constant axdsp : integer := 34; --! Not implemented.
constant spartan6 : integer := 35; --! Supported. Use files with the '_s6' suffix.
constant virtex6 : integer := 36; --! Supported. Use files with the '_v6' suffix.
constant actfus : integer := 37; --! Not implemented.
constant stratix4 : integer := 38; --! Not implemented.
constant st65lp : integer := 39; --! Not implemented.
constant st65gp : integer := 40; --! Not implemented.
constant easic45 : integer := 41; --! Not implemented.
constant cmos9sf : integer := 42; --! Not implemented.
constant apa3e : integer := 43; --! Not implemented.
constant apa3l : integer := 44; --! Not implemented.
constant ut130 : integer := 45; --! Not implemented.
constant ut90 : integer := 46; --! Not implemented.
constant gf65 : integer := 47; --! Not implemented.
constant virtex7 : integer := 48; --! Not implemented.
constant kintex7 : integer := 49; --! Supported. Use files with the '_k7' suffix.
constant artix7 : integer := 50; --! Partially implemented.
constant zynq7000 : integer := 51; --! Not implemented.
constant rhlib13t : integer := 52; --! Not implemented.
constant micron180 : integer := 53; --! Mikron 180nm. Use files with the '_micron180' suffix.
--! @}
--! @name FPGAs technologies group.
--! @details It is convinient sometimes to implement one module for a group of
--! technologies, this array specifies FPGA group.
constant is_fpga : tech_ability_type :=
(inferred => 1, virtex => 1, virtex2 => 1, axcel => 1,
proasic => 1, altera => 1, apa3 => 1, spartan3 => 1,
virtex4 => 1, lattice => 1, spartan3e => 1, virtex5 => 1,
stratix1 => 1, stratix2 => 1, eclipse => 1,
stratix3 => 1, cyclone3 => 1, axdsp => 1,
spartan6 => 1, virtex6 => 1, actfus => 1,
stratix4 => 1, apa3e => 1, apa3l => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1,
others => 0);
end;
|
bsd-2-clause
|
5c93f709c93cf123813854da46897baf
| 0.625547 | 4.103906 | false | false | false | false |
IAIK/ascon_hardware
|
generic_implementation/top.vhdl
| 1 | 3,527 |
-------------------------------------------------------------------------------
-- Title : Ascon
-- Project :
-------------------------------------------------------------------------------
-- File : top.vhdl
-- Author : Hannes Gross <[email protected]>
-- Company :
-- Created : 2016-05-25
-- Last update: 2016-06-14
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Copyright 2014 Graz University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-25 1.0 Hannes Gross created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top is
generic (
-- Select Ascon variant:
-- DATA_BUS_WIDTH = 64 ... Ascon-128 with 1,2,3 or 6 unrolled rounds
-- DATA_BUS_WIDTH = 128 ... Ascon-128a with 1,2 or 4 untrolled rounds
DATA_BUS_WIDTH : integer := 128;
UNROLED_ROUNDS : integer := 4;
ADDR_BUS_WIDTH : integer := 8);
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
CSxSI : in std_logic;
WExSI : in std_logic;
AddressxDI : in std_logic_vector(ADDR_BUS_WIDTH-1 downto 0);
DataWritexDI : in std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
DataReadxDO : out std_logic_vector(DATA_BUS_WIDTH-1 downto 0));
end entity top;
architecture structural of top is
begin -- architecture structural
-- Ascon 128 Variant
ascon128_gen : if DATA_BUS_WIDTH = 64 generate
ascon_1 : entity work.ascon
generic map (
UNROLED_ROUNDS => UNROLED_ROUNDS, -- 1,2,3 or 6
DATA_BLOCK_SIZE => DATA_BUS_WIDTH,
ROUNDS_A => 12,
ROUNDS_B => 6,
DATA_BUS_WIDTH => DATA_BUS_WIDTH,
ADDR_BUS_WIDTH => ADDR_BUS_WIDTH)
port map (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
CSxSI => CSxSI,
WExSI => WExSI,
AddressxDI => AddressxDI,
DataWritexDI => DataWritexDI,
DataReadxDO => DataReadxDO);
end generate ascon128_gen;
-- Ascon 128a Variant
ascon128a_gen : if DATA_BUS_WIDTH = 128 generate
ascon_1 : entity work.ascon
generic map (
UNROLED_ROUNDS => UNROLED_ROUNDS, -- 1,2 or 4
DATA_BLOCK_SIZE => DATA_BUS_WIDTH,
ROUNDS_A => 12,
ROUNDS_B => 8,
DATA_BUS_WIDTH => DATA_BUS_WIDTH,
ADDR_BUS_WIDTH => ADDR_BUS_WIDTH)
port map (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
CSxSI => CSxSI,
WExSI => WExSI,
AddressxDI => AddressxDI,
DataWritexDI => DataWritexDI,
DataReadxDO => DataReadxDO);
end generate ascon128a_gen;
end architecture structural;
|
apache-2.0
|
3f8297589fbdbd3d6eca7e3e73737e8a
| 0.53615 | 4.188836 | false | false | false | false |
RussGlover/381-module-1
|
project/hardware/vhdl/pixel_drawer.vhd
| 1 | 8,094 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pixel_drawer is
generic(
pixel_buffer_base : std_logic_vector := x"00080000"
);
port (
clk: in std_logic;
reset_n: in std_logic;
slave_addr: in std_logic_vector(2 downto 0);
slave_rd_en: in std_logic;
slave_wr_en: in std_logic;
slave_readdata: out std_logic_vector(31 downto 0);
slave_writedata: in std_logic_vector(31 downto 0);
master_addr : out std_logic_vector(31 downto 0);
master_rd_en : out std_logic;
master_wr_en : out std_logic;
master_be : out std_logic_vector(1 downto 0);
master_readdata : in std_logic_vector(15 downto 0);
master_writedata: out std_logic_vector(15 downto 0);
master_waitrequest : in std_logic);
end pixel_drawer;
architecture rtl of pixel_drawer is
signal x1,x2 : std_logic_vector(8 downto 0);
signal y1,y2 : std_logic_vector(7 downto 0);
signal colour : std_logic_vector(15 downto 0);
signal done : std_logic := '0';
-- constant pixel_buffer_base : std_logic_vector(31 downto 0) := x"00080000";
begin
-- This synchronous process is triggered on a rising clock edge.
-- There are two things we might do on a rising clock edge. We might
-- respond to write operations on the slave bus, or we might step through
-- the state machine to draw something to the pixel buffer. We could
-- have separated these into two processes.
process(clk, reset_n)
variable processing : bit := '0'; -- Used to indicate whether we are drawing
variable state : integer; -- Current state. We could use enumerated types.
-- The following are local copies of the coordinates and colour. When the user
-- starts a drawing operation, we immediately copy the coordinates here, so that
-- if the user tries to change the coordinates while the draw operation is running,
-- the draw operation completes with the old value of the coordinates. This is
-- not strictly required, but perhaps provides a more “natural” operation for
-- whoever is writing the C code.
variable x1_local,x2_local : std_logic_vector(8 downto 0);
variable y1_local,y2_local : std_logic_vector(7 downto 0);
variable colour_local : std_logic_vector(15 downto 0);
-- This is used to remember the left-most x point as we draw the box.
variable savedx : std_logic_vector(8 downto 0);
begin
if (reset_n = '0') then
master_wr_en<= '0';
master_rd_en<= '0';
processing := '0';
state := 0;
done <= '0';
elsif rising_edge(clk) then
-- on a rising clock edge, if we are currently in the middle of a
-- drawing operation, step through the drawing state machine.
if processing = '1' then
-- Initiate a write operation on the master bus. The address of
-- of the write operation points to the pixel buffer plus an offset
-- that is computed from the x1_local and y1_local. The final ‘0’
-- is because each pixel takes 16 bits in memory. The data of the
-- write operation is the colour value (16 bits).
if state = 0 then
-- master_addr <= std_logic_vector(unsigned(pixel_buffer_base) + steve +
-- unsigned( y1_local & x1_local & '0'));
master_addr <= std_logic_vector(unsigned(pixel_buffer_base) +
unsigned( y1_local & x1_local & '0'));
master_writedata <= colour_local;
master_be <= "11"; -- byte enable
master_wr_en <= '1';
master_rd_en <= '0';
state := 1; -- on the next rising clock edge, do state 1 operations
-- After starting a write operation, we need to wait until
-- master_waitrequest is 0. If it is 1, stay in state 1.
elsif state = 1 and master_waitrequest = '0' then
master_wr_en <= '0';
state := 0;
if (x1_local = x2_local) then
if (y1_local = y2_local) then
done <= '1'; -- box is done
processing := '0';
else
x1_local := savedx;
y1_local := std_logic_vector(unsigned(y1_local)+1);
end if;
else
x1_local := std_logic_vector(unsigned(x1_local)+1);
end if;
end if;
end if;
-- We should also check if there is a write on the slave bus. If so, copy the
-- written value into one of our internal registers.
if (slave_wr_en = '1') then
case slave_addr is
-- These four should be self-explantory
when "000" => x1 <= slave_writedata(8 downto 0);
when "001" => y1 <= slave_writedata(7 downto 0);
when "010" => x2 <= slave_writedata(8 downto 0);
when "011" => y2 <= slave_writedata(7 downto 0);
when "100" => colour <= slave_writedata(15 downto 0);
-- If the user tries to write to offset 5, we are to start drawing
when "101" =>
if processing = '0' then
processing := '1'; -- start drawing on next rising clk edge
state := 0;
done <= '0';
-- The above drawing code assumes x1<x2 and y1<y2, however the
-- user may give us points with x1>x2 or y1>y2. If so, swap
-- the x and y values. In any case, copy to our internal _local
-- variables. This ensures that if the user changes a coordinate
-- while a drawing is occurring, it continues to draw the box
-- as originally requested.
if (x1 < x2) then
x1_local := x1;
savedx := x1;
x2_local := x2;
else
x2_local := x1;
savedx := x2;
x1_local := x2;
end if;
if (y1 < y2) then
y1_local := y1;
y2_local := y2;
else
y2_local := y1;
y1_local := y2;
end if;
colour_local := colour;
end if;
when others => null;
end case;
end if;
end if;
end process;
-- This process is used to describe what to do when a “read” operation occurs on the
-- slave interface (this is because the C program does a memory read). Depending
-- on the address read, we return x1, x2, y1, y2, the colour, or the done flag.
process (slave_rd_en, slave_addr, x1,x2,y1,y2,colour,done)
begin
slave_readdata <= (others => '-');
if (slave_rd_en = '1') then
case slave_addr is
when "000" => slave_readdata <= "00000000000000000000000" & x1;
when "001" => slave_readdata <= "000000000000000000000000" & y1;
when "010" => slave_readdata <= "00000000000000000000000" & x2;
when "011" => slave_readdata <= "000000000000000000000000" & y2;
when "100" => slave_readdata <= "0000000000000000" & colour;
when "101" => slave_readdata <= (0=>done, others=>'0');
when others => null;
end case;
end if;
end process;
end rtl;
|
mit
|
6db5fb03834797f7da4bc3c63f9d4de2
| 0.513858 | 4.28072 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/synth/design_1_dlmb_bram_if_cntlr_0.vhd
| 2 | 13,330 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_bram_if_cntlr_v4_0;
USE lmb_bram_if_cntlr_v4_0.lmb_bram_if_cntlr;
ENTITY design_1_dlmb_bram_if_cntlr_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
);
END design_1_dlmb_bram_if_cntlr_0;
ARCHITECTURE design_1_dlmb_bram_if_cntlr_0_arch OF design_1_dlmb_bram_if_cntlr_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_bram_if_cntlr IS
GENERIC (
C_FAMILY : STRING;
C_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_NUM_LMB : INTEGER;
C_MASK : STD_LOGIC_VECTOR(0 TO 31);
C_MASK1 : STD_LOGIC_VECTOR(0 TO 31);
C_MASK2 : STD_LOGIC_VECTOR(0 TO 31);
C_MASK3 : STD_LOGIC_VECTOR(0 TO 31);
C_LMB_AWIDTH : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_ECC : INTEGER;
C_INTERCONNECT : INTEGER;
C_FAULT_INJECT : INTEGER;
C_CE_FAILING_REGISTERS : INTEGER;
C_UE_FAILING_REGISTERS : INTEGER;
C_ECC_STATUS_REGISTERS : INTEGER;
C_ECC_ONOFF_REGISTER : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER;
C_CE_COUNTER_WIDTH : INTEGER;
C_WRITE_ACCESS : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_AddrStrobe : IN STD_LOGIC;
LMB1_ReadStrobe : IN STD_LOGIC;
LMB1_WriteStrobe : IN STD_LOGIC;
LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl1_Ready : OUT STD_LOGIC;
Sl1_Wait : OUT STD_LOGIC;
Sl1_UE : OUT STD_LOGIC;
Sl1_CE : OUT STD_LOGIC;
LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_AddrStrobe : IN STD_LOGIC;
LMB2_ReadStrobe : IN STD_LOGIC;
LMB2_WriteStrobe : IN STD_LOGIC;
LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl2_Ready : OUT STD_LOGIC;
Sl2_Wait : OUT STD_LOGIC;
Sl2_UE : OUT STD_LOGIC;
Sl2_CE : OUT STD_LOGIC;
LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_AddrStrobe : IN STD_LOGIC;
LMB3_ReadStrobe : IN STD_LOGIC;
LMB3_WriteStrobe : IN STD_LOGIC;
LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl3_Ready : OUT STD_LOGIC;
Sl3_Wait : OUT STD_LOGIC;
Sl3_UE : OUT STD_LOGIC;
Sl3_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
S_AXI_CTRL_ACLK : IN STD_LOGIC;
S_AXI_CTRL_ARESETN : IN STD_LOGIC;
S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_AWVALID : IN STD_LOGIC;
S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_CTRL_WVALID : IN STD_LOGIC;
S_AXI_CTRL_WREADY : OUT STD_LOGIC;
S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_BVALID : OUT STD_LOGIC;
S_AXI_CTRL_BREADY : IN STD_LOGIC;
S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_ARVALID : IN STD_LOGIC;
S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_RVALID : OUT STD_LOGIC;
S_AXI_CTRL_RREADY : IN STD_LOGIC;
UE : OUT STD_LOGIC;
CE : OUT STD_LOGIC;
Interrupt : OUT STD_LOGIC
);
END COMPONENT lmb_bram_if_cntlr;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "lmb_bram_if_cntlr,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_dlmb_bram_if_cntlr_0_arch : ARCHITECTURE IS "design_1_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "design_1_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_HIGHADDR=0x00007FFF,C_BASEADDR=0x00000000,C_NUM_LMB=1,C_MASK=0x40000000,C_MASK1=0x00800000,C_MASK2=0x00800000,C_MASK3=0x00800000,C_LMB_AWIDTH=32,C_LMB_DWIDTH=32,C_ECC=0,C_INTERCONNECT=0,C_FAULT_INJECT=0,C_CE_FAILING_REGISTERS=0,C_UE_FAILING_REGISTERS=0,C_ECC_STATUS_REGISTERS=0,C_ECC_ONOFF_REGISTER=0,C_ECC_ONOFF_RESET_VALUE=1,C_CE_COUNTER_WIDTH=0,C_WRITE_ACCESS=2,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
BEGIN
U0 : lmb_bram_if_cntlr
GENERIC MAP (
C_FAMILY => "artix7",
C_HIGHADDR => X"00007FFF",
C_BASEADDR => X"00000000",
C_NUM_LMB => 1,
C_MASK => X"40000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
PORT MAP (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_AddrStrobe => '0',
LMB1_ReadStrobe => '0',
LMB1_WriteStrobe => '0',
LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_AddrStrobe => '0',
LMB2_ReadStrobe => '0',
LMB2_WriteStrobe => '0',
LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_AddrStrobe => '0',
LMB3_ReadStrobe => '0',
LMB3_WriteStrobe => '0',
LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Din_A => BRAM_Din_A,
S_AXI_CTRL_ACLK => '0',
S_AXI_CTRL_ARESETN => '0',
S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_AWVALID => '0',
S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_CTRL_WVALID => '0',
S_AXI_CTRL_BREADY => '0',
S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_ARVALID => '0',
S_AXI_CTRL_RREADY => '0'
);
END design_1_dlmb_bram_if_cntlr_0_arch;
|
gpl-3.0
|
61f4401d8e7a42f0bb85875ff85aa835
| 0.66159 | 3.149067 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/cdd36762/hdl/vhdl/lmb_bram_if_primitives.vhd
| 4 | 10,204 |
-------------------------------------------------------------------------------
-- primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: primitives.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_primitives.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
--
-- History:
-- rolandp 2015-01-22 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
----- entity LUT6 -----
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end entity MB_LUT6;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_LUT6 is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
constant INIT_reg : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT);
begin
process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
variable I0_v, I1_v, I2_v, I3_v, I4_v, I5_v : std_logic;
begin
-- Filter unknowns
if I0 = '0' then I0_v := '0'; else I0_v := '1'; end if;
if I1 = '0' then I1_v := '0'; else I1_v := '1'; end if;
if I2 = '0' then I2_v := '0'; else I2_v := '1'; end if;
if I3 = '0' then I3_v := '0'; else I3_v := '1'; end if;
if I4 = '0' then I4_v := '0'; else I4_v := '1'; end if;
if I5 = '0' then I5_v := '0'; else I5_v := '1'; end if;
I_reg := TO_STDLOGICVECTOR(I5_v & I4_v & I3_v & I2_v & I1_v & I0_v);
O <= INIT_reg(TO_INTEGER(unsigned(I_reg)));
end process;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: LUT6
generic map(
INIT => INIT
)
port map(
O => O,
I0 => I0,
I1 => I1,
I2 => I2,
I3 => I3,
I4 => I4,
I5 => I5
);
end generate Using_FPGA;
end architecture IMP;
----- entity MUXCY -----
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end entity MB_MUXCY;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_MUXCY is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
LO <= DI when S = '0' else CI;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: MUXCY_L
port map(
LO => LO,
CI => CI,
DI => DI,
S => S
);
end generate Using_FPGA;
end architecture IMP;
----- entity XORCY -----
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity MB_XORCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end entity MB_XORCY;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_XORCY is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
O <= (CI xor LI);
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: XORCY
port map(
O => O,
CI => CI,
LI => LI
);
end generate Using_FPGA;
end architecture IMP;
----- entity MUXF7 -----
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity MB_MUXF7 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end entity MB_MUXF7;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_MUXF7 is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
O <= I0 when S = '0' else I1;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: MUXF7
port map(
O => O,
I0 => I0,
I1 => I1,
S => S
);
end generate Using_FPGA;
end architecture IMP;
----- entity MUXF8 -----
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity MB_MUXF8 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end entity MB_MUXF8;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_MUXF8 is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
O <= I0 when S = '0' else I1;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: MUXF8
port map(
O => O,
I0 => I0,
I1 => I1,
S => S
);
end generate Using_FPGA;
end architecture IMP;
----- entity FDRE -----
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity MB_FDRE is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end entity MB_FDRE;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_FDRE is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
function To_StdLogic(A : in bit ) return std_logic is
begin
if( A = '1' ) then
return '1';
end if;
return '0';
end;
signal q_o : std_logic := To_StdLogic(INIT);
begin
Q <= q_o;
process(C)
begin
if (rising_edge(C)) then
if (R = '1') then
q_o <= '0';
elsif (CE = '1') then
q_o <= D;
end if;
end if;
end process;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: FDRE
generic map(
INIT => INIT
)
port map(
Q => Q,
C => C,
CE => CE,
D => D,
R => R
);
end generate Using_FPGA;
end architecture IMP;
|
gpl-3.0
|
c2ac9019ba448295efd7142d05811962
| 0.550372 | 3.528354 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/I2CTest/I2CTest.srcs/sources_1/new/FIFO.vhd
| 2 | 2,048 |
--http://www.deathbylogic.com/2013/07/vhdl-standard-fifo/
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity STD_FIFO is
Generic (
constant DATA_WIDTH : positive := 8;
constant FIFO_DEPTH : positive := 256
);
Port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
WriteEn : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
ReadEn : in STD_LOGIC;
DataOut : out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
Empty : out STD_LOGIC := '1';
Full : out STD_LOGIC
);
end STD_FIFO;
architecture Behavioral of STD_FIFO is
begin
-- Memory Pointer Process
fifo_proc : process (CLK)
type FIFO_Memory is array (0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
variable Memory : FIFO_Memory;
variable Head : natural range 0 to FIFO_DEPTH - 1;
variable Tail : natural range 0 to FIFO_DEPTH - 1;
variable Looped : boolean;
begin
if rising_edge(CLK) then
if RST = '1' then
Head := 0;
Tail := 0;
Looped := false;
Full <= '0';
Empty <= '1';
else
if (ReadEn = '1') then
if ((Looped = true) or (Head /= Tail)) then
-- Update data output
DataOut <= Memory(Tail);
-- Update Tail pointer as needed
if (Tail = FIFO_DEPTH - 1) then
Tail := 0;
Looped := false;
else
Tail := Tail + 1;
end if;
end if;
end if;
if (WriteEn = '1') then
if ((Looped = false) or (Head /= Tail)) then
-- Write Data to Memory
Memory(Head) := DataIn;
-- Increment Head pointer as needed
if (Head = FIFO_DEPTH - 1) then
Head := 0;
Looped := true;
else
Head := Head + 1;
end if;
end if;
end if;
-- Update Empty and Full flags
if (Head = Tail) then
if Looped then
Full <= '1';
else
Empty <= '1';
end if;
else
Empty <= '0';
Full <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
5ff400d29c851f8728724f7ced467ae9
| 0.555664 | 3.121951 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/xemac.vhd
| 4 | 63,822 |
-------------------------------------------------------------------------------
-- xemac.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : xemac.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC with
-- IPIF elements included.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-- PVK 07/21/2010
-- ^^^^^^
-- Updated local register decoding logic to fix the issue related with read.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_FAMILY -- Target device family (spartan3e, spartan3a,
-- spartan3an, spartan3af, virtex4 or virtex6)
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width - allowed value - 32 only
-- C_S_AXI_DATA_WIDTH -- AXI data bus width - allowed value - 32 only
-- C_S_AXI_ACLK_PERIOD_PS -- The period of the AXI clock in ps
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- C_TX_PING_PONG -- 1 = ping-pong memory used for transmit buffer
-- C_RX_PING_PONG -- 1 = ping-pong memory used for receive buffer
-- C_INCLUDE_MDIO -- 1 = Include MDIO Innterface, 0 = No MDIO Interface
-- NODE_MAC -- = Default MAC address of the core
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- System signals
-- Clk -- System clock
-- Rst -- System Reset
-- IP2INTC_Irpt -- System Interrupt
-- IPIC signals
-- IP2Bus_Data -- IP to Bus data
-- IP2Bus_Error -- IP to Bus error
-- Bus2IP_Addr -- Bus to IP address
-- Bus2IP_Data -- Bus to IP data
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- Bus2IP_Burst -- Bus to IP burst
-- Ethernet
-- PHY_tx_clk -- Ethernet tranmit clock
-- PHY_rx_clk -- Ethernet receive clock
-- PHY_crs -- Ethernet carrier sense
-- PHY_dv -- Ethernet receive data valid
-- PHY_rx_data -- Ethernet receive data
-- PHY_col -- Ethernet collision indicator
-- PHY_rx_er -- Ethernet receive error
-- PHY_rst_n -- Ethernet PHY Reset
-- PHY_tx_en -- Ethernet transmit enable
-- PHY_tx_data -- Ethernet transmit data
-- Loopback -- Internal Loopback enable
-- PHY_MDIO_I -- Ethernet PHY MDIO data input
-- PHY_MDIO_O -- Ethernet PHY MDIO data output
-- PHY_MDIO_T -- Ethernet PHY MDIO data 3-state control
-- PHY_MDC -- Ethernet PHY management clock
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity xemac is
generic (
C_FAMILY : string := "virtex6";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ACLK_PERIOD_PS : integer := 10000;
C_DUPLEX : integer := 1; -- 1 = full duplex, 0 = half duplex
C_RX_PING_PONG : integer := 0; -- 1 = ping-pong memory used for
-- receive buffer
C_TX_PING_PONG : integer := 0; -- 1 = ping-pong memory used for
-- transmit buffer
C_INCLUDE_MDIO : integer := 1; -- 1 = Include MDIO interface
-- 0 = No MDIO interface
NODE_MAC : bit_vector := x"00005e00FACE"
-- power up defaul MAC address
);
port (
Clk : in std_logic;
Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
-- Controls to the IP/IPIF modules
IP2Bus_Data : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0 );
IP2Bus_Error : out std_logic;
Bus2IP_Addr : in std_logic_vector(12 downto 0);
Bus2IP_Data : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
Bus2IP_BE : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1)downto 0);
Bus2IP_RdCE : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Burst : in std_logic;
-- Ethernet Interface
PHY_tx_clk : in std_logic;
PHY_rx_clk : in std_logic;
PHY_crs : in std_logic;
PHY_dv : in std_logic;
PHY_rx_data : in std_logic_vector (3 downto 0);
PHY_col : in std_logic;
PHY_rx_er : in std_logic;
PHY_tx_en : out std_logic;
PHY_tx_data : out std_logic_vector (3 downto 0);
Loopback : out std_logic;
-- MDIO Interface
PHY_MDIO_I : in std_logic;
PHY_MDIO_O : out std_logic;
PHY_MDIO_T : out std_logic;
PHY_MDC : out std_logic
);
end xemac;
architecture imp of xemac is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant MDIO_CNT : integer := ((200000/C_S_AXI_ACLK_PERIOD_PS)+1);
constant IP2BUS_DATA_ZERO : std_logic_vector(0 to 31) := X"00000000";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal phy_rx_data_i : std_logic_vector (3 downto 0);
signal phy_tx_data_i : std_logic_vector (3 downto 0);
signal tx_DPM_ce : std_logic;
signal tx_DPM_ce_i : std_logic; -- added 03-03-05 MSH
signal tx_DPM_adr : std_logic_vector (11 downto 0);
signal tx_DPM_wr_data : std_logic_vector (3 downto 0);
signal tx_DPM_rd_data : std_logic_vector (3 downto 0);
signal tx_ping_rd_data : std_logic_vector (3 downto 0);
signal tx_pong_rd_data : std_logic_vector (3 downto 0) := (others => '0');
signal tx_DPM_wr_rd_n : std_logic;
signal rx_DPM_ce : std_logic;
signal rx_DPM_ce_i : std_logic; -- added 03-03-05 MSH
signal rx_DPM_adr : std_logic_vector (11 downto 0);
signal rx_DPM_wr_data : std_logic_vector (3 downto 0);
signal rx_DPM_rd_data : std_logic_vector (3 downto 0);
signal rx_ping_rd_data : std_logic_vector (3 downto 0);
signal rx_pong_rd_data : std_logic_vector (3 downto 0) := (others => '0');
signal rx_DPM_wr_rd_n : std_logic;
signal IPIF_tx_Ping_CE : std_logic;
signal IPIF_tx_Pong_CE : std_logic := '0';
signal IPIF_rx_Ping_CE : std_logic;
signal IPIF_rx_Pong_CE : std_logic := '0';
signal tx_ping_data_out : std_logic_vector (31 downto 0);
signal tx_pong_data_out : std_logic_vector (31 downto 0) := (others => '0');
signal rx_ping_data_out : std_logic_vector (31 downto 0);
signal rx_pong_data_out : std_logic_vector (31 downto 0) := (others => '0');
signal dpm_wr_ack : std_logic;
signal dpm_rd_ack : std_logic;
signal rx_done : std_logic;
signal rx_done_d1 : std_logic := '0';
signal tx_done : std_logic;
signal tx_done_d1 : std_logic := '0';
signal tx_done_d2 : std_logic := '0';
signal tx_ping_ce : std_logic;
signal tx_pong_ping_l : std_logic := '0';
signal tx_idle : std_logic;
signal rx_idle : std_logic;
signal rx_ping_ce : std_logic;
signal rx_pong_ping_l : std_logic := '0';
signal reg_access : std_logic;
signal reg_en : std_logic;
signal tx_ping_reg_en : std_logic;
signal tx_pong_reg_en : std_logic;
signal rx_ping_reg_en : std_logic;
signal rx_pong_reg_en : std_logic;
signal tx_ping_ctrl_reg_en : std_logic;
signal tx_ping_length_reg_en : std_logic;
signal tx_pong_ctrl_reg_en : std_logic;
signal tx_pong_length_reg_en : std_logic;
signal rx_ping_ctrl_reg_en : std_logic;
signal rx_pong_ctrl_reg_en : std_logic;
signal loopback_en : std_logic;
signal tx_intr_en : std_logic;
signal ping_mac_program : std_logic;
signal pong_mac_program : std_logic;
signal ping_tx_status : std_logic;
signal pong_tx_status : std_logic;
signal ping_pkt_lenth : std_logic_vector(15 downto 0);
signal pong_pkt_lenth : std_logic_vector(15 downto 0);
signal rx_intr_en : std_logic;
signal ping_rx_status : std_logic;
signal pong_rx_status : std_logic;
signal ping_tx_done : std_logic;
signal mdio_data_out : std_logic_vector(31 downto 0);
signal reg_data_out : std_logic_vector(31 downto 0);
signal mdio_reg_en : std_logic;
signal gie_reg : std_logic;
signal gie_reg_en : std_logic;
signal gie_enable : std_logic;
signal tx_packet_length : std_logic_vector(15 downto 0);
signal stat_reg_en : std_logic;
signal status_reg : std_logic_vector(5 downto 0);
signal ping_mac_prog_done : std_logic;
signal transmit_start : std_logic;
signal mac_program_start : std_logic;
signal rx_buffer_ready : std_logic;
signal dpm_addr_ack : std_logic;
signal control_reg : std_logic;
signal length_reg : std_logic;
signal word_access : std_logic;
signal reg_access_i : std_logic;
signal ip2intc_irpt_i : std_logic;
signal reg_access_d1 : std_logic;
signal ping_soft_status : std_logic;
signal pong_soft_status : std_logic;
signal rx_pong_ce_en : std_logic;
signal tx_pong_ce_en : std_logic;
-------------------------------------------------------------------------------
-- New ipif_ssp1 signal declaration --
-------------------------------------------------------------------------------
signal bus2ip_ce : std_logic;
signal tx_ping_ce_en : std_logic;
signal rx_ping_ce_en : std_logic;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component SRL16E
generic (
INIT : bit_vector := X"0000"
);
port (
Q : out std_logic; --[out]
A0 : in std_logic; --[in]
A1 : in std_logic; --[in]
A2 : in std_logic; --[in]
A3 : in std_logic; --[in]
CE : in std_logic; --[in]
CLK : in std_logic; --[in]
D : in std_logic --[in]
);
end component;
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDRE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component LUT4
generic(INIT : bit_vector);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component;
begin
IP2Bus_Error <= '0';
-- IP2INTC_Irpt generation if global interrupt is enable
ip2intc_irpt_i <= gie_enable and ((rx_done and rx_intr_en) or
(tx_done and tx_intr_en));
----------------------------------------------------------------------------
-- IP2INTC_IRPT register
----------------------------------------------------------------------------
IP2INTC_IRPT_REG_I: FDR
port map (
Q => IP2INTC_Irpt , --[out]
C => Clk , --[in]
D => ip2intc_irpt_i, --[in]
R => Rst --[in]
);
-- ----------------------------------------------------------------------------
-- -- IPIF interface
-- ----------------------------------------------------------------------------
-- PHY_tx_data conversion
PHY_tx_data(0) <= phy_tx_data_i(0);
PHY_tx_data(1) <= phy_tx_data_i(1);
PHY_tx_data(2) <= phy_tx_data_i(2);
PHY_tx_data(3) <= phy_tx_data_i(3);
-- PHY_rx_data conversion
phy_rx_data_i(0) <= PHY_rx_data(0);
phy_rx_data_i(1) <= PHY_rx_data(1);
phy_rx_data_i(2) <= PHY_rx_data(2);
phy_rx_data_i(3) <= PHY_rx_data(3);
----------------------------------------------------------------------------
-- EMAC
----------------------------------------------------------------------------
EMAC_I: entity axi_ethernetlite_v3_0.emac
generic map (
C_DUPLEX => C_DUPLEX,
NODE_MAC => NODE_MAC,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Rst => Rst,
Phy_tx_clk => PHY_tx_clk,
Phy_rx_clk => PHY_rx_clk,
Phy_crs => phy_crs,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data_i,
Phy_col => Phy_col,
Phy_rx_er => Phy_rx_er,
Phy_tx_en => Phy_tx_en,
Phy_tx_data => Phy_tx_data_i,
Tx_DPM_ce => tx_DPM_ce_i,
Tx_DPM_adr => tx_DPM_adr,
Tx_DPM_wr_data => tx_DPM_wr_data,
Tx_DPM_rd_data => tx_DPM_rd_data,
Tx_DPM_wr_rd_n => tx_DPM_wr_rd_n,
Tx_done => tx_done,
Tx_pong_ping_l => tx_pong_ping_l,
Tx_idle => tx_idle,
Rx_idle => rx_idle,
Rx_DPM_ce => rx_DPM_ce_i,
Rx_DPM_adr => rx_DPM_adr,
Rx_DPM_wr_data => rx_DPM_wr_data,
Rx_DPM_rd_data => rx_DPM_rd_data,
Rx_DPM_wr_rd_n => rx_DPM_wr_rd_n ,
Rx_done => rx_done,
Rx_pong_ping_l => rx_pong_ping_l,
Tx_packet_length => tx_packet_length,
Transmit_start => transmit_start,
Mac_program_start => mac_program_start,
Rx_buffer_ready => rx_buffer_ready
);
----------------------------------------------------------------------------
-- This core only supports word access
word_access <= '1' when bus2ip_be="1111" else '0';
-- DPRAM buffer chip enable generation
bus2ip_ce <= (Bus2IP_RdCE or (Bus2IP_WrCE and word_access));
tx_ping_ce_en <= not Bus2IP_Addr(12) and not Bus2IP_Addr(11);
rx_ping_ce_en <= Bus2IP_Addr(12) and not Bus2IP_Addr(11);
IPIF_tx_Ping_CE <= bus2ip_ce and tx_ping_ce_en;
IPIF_rx_Ping_CE <= bus2ip_ce and rx_ping_ce_en;
-- IP2Bus_Data generation
IP2BUS_DATA_GENERATE: for i in 31 downto 0 generate
IP2Bus_Data(i) <= ((
(tx_ping_data_out(i) and tx_ping_ce_en) or
(tx_pong_data_out(i) and tx_pong_ce_en) or
(rx_ping_data_out(i) and rx_ping_ce_en) or
(rx_pong_data_out(i) and rx_pong_ce_en)
) and not reg_access)
or
((
(reg_data_out(i) and not mdio_reg_en) or
(mdio_data_out(i) and mdio_reg_en)
) and reg_access) ;
end generate IP2BUS_DATA_GENERATE;
----------------------------------------------------------------------------
-- DPM_TX_RD_DATA_GENERATE
----------------------------------------------------------------------------
-- This logic generates tx_DPM_rd_data for transmit section from
-- tx_ping_buffer and tx_pong_buffer.
----------------------------------------------------------------------------
DPM_TX_RD_DATA_GENERATE: for i in 0 to 3 generate
tx_DPM_rd_data(i) <= (tx_ping_rd_data(i) and not tx_pong_ping_l
and (not tx_idle)) or
(tx_pong_rd_data(i) and tx_pong_ping_l
and (not tx_idle));
end generate DPM_TX_RD_DATA_GENERATE;
----------------------------------------------------------------------------
-- DPM_RX_RD_DATA_GENERATE
----------------------------------------------------------------------------
-- This logic generates rx_DPM_rd_data for receive section from
-- rx_ping_buffer and rx_pong_buffer.
----------------------------------------------------------------------------
DPM_RX_RD_DATA_GENERATE: for i in 0 to 3 generate
rx_DPM_rd_data(i) <= (rx_ping_rd_data(i) and not rx_pong_ping_l) or
(rx_pong_rd_data(i) and rx_pong_ping_l);
end generate DPM_RX_RD_DATA_GENERATE;
-- Chip enable generation
tx_ping_ce <= tx_DPM_ce and not tx_pong_ping_l;
tx_DPM_ce <= tx_DPM_ce_i;
rx_DPM_ce <= rx_DPM_ce_i;
rx_ping_ce <= rx_DPM_ce and not rx_pong_ping_l;
----------------------------------------------------------------------------
-- TX_PING Buffer
----------------------------------------------------------------------------
TX_PING: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => tx_ping_ce ,
Wr_rd_n_a => tx_DPM_wr_rd_n ,
Adr_a => tx_DPM_adr ,
Data_in_a => tx_DPM_wr_data ,
Data_out_a => tx_ping_rd_data ,
Ce_b => IPIF_tx_Ping_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => tx_ping_data_out
);
----------------------------------------------------------------------------
-- RX_PING Buffer
----------------------------------------------------------------------------
RX_PING: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => rx_ping_ce ,
Wr_rd_n_a => rx_DPM_wr_rd_n ,
Adr_a => rx_DPM_adr ,
Data_in_a => rx_DPM_wr_data ,
Data_out_a => rx_ping_rd_data ,
Ce_b => IPIF_rx_Ping_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => rx_ping_data_out
);
----------------------------------------------------------------------------
-- TX Done register
----------------------------------------------------------------------------
TX_DONE_D1_I: FDR
port map (
Q => tx_done_d1 , --[out]
C => Clk , --[in]
D => tx_done , --[in]
R => Rst --[in]
);
TX_DONE_D2_I: FDR
port map (
Q => tx_done_d2 , --[out]
C => Clk , --[in]
D => tx_done_d1 , --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Transmit Pong memory generate
----------------------------------------------------------------------------
TX_PONG_GEN: if C_TX_PING_PONG = 1 generate
signal tx_pong_ce : std_logic;
signal pp_tog_ce : std_logic;
attribute INIT : string;
-- attribute INIT of PP_TOG_LUT_I: label is "1111";
Begin
TX_PONG_I: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => tx_pong_ce ,
Wr_rd_n_a => tx_DPM_wr_rd_n ,
Adr_a => tx_DPM_adr ,
Data_in_a => tx_DPM_wr_data ,
Data_out_a => tx_pong_rd_data ,
Ce_b => IPIF_tx_Pong_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => tx_pong_data_out
);
-- TX Pong Buffer Chip enable
tx_pong_ce <= tx_DPM_ce and tx_pong_ping_l;
--IPIF_tx_Pong_CE <= bus2ip_ce and not Bus2IP_Addr(12) Bus2IP_Addr(11);
IPIF_tx_Pong_CE <= bus2ip_ce and tx_pong_ce_en;
tx_pong_ce_en <= not Bus2IP_Addr(12) and Bus2IP_Addr(11);
-------------------------------------------------------------------------
-- TX_PONG_PING_L_PROCESS
-------------------------------------------------------------------------
-- This process generate tx_pong_ping_l for TX PING/PONG buffer access
-------------------------------------------------------------------------
TX_PONG_PING_L_PROCESS:process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_pong_ping_l <= '0';
elsif (tx_done_d1 = '1' ) then
tx_pong_ping_l <= not tx_pong_ping_l;
elsif (pong_tx_status = '1' and ping_tx_status = '0' ) then
tx_pong_ping_l <= '1';
elsif (pong_tx_status = '0' and ping_tx_status = '1' ) then
tx_pong_ping_l <= '0';
else
tx_pong_ping_l <= tx_pong_ping_l;
end if;
end if;
end process;
end generate TX_PONG_GEN;
----------------------------------------------------------------------------
-- RX Done register
----------------------------------------------------------------------------
RX_DONE_D1_I: FDR
port map (
Q => rx_done_d1 , --[out]
C => Clk , --[in]
D => rx_done , --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Receive Pong memory generate
----------------------------------------------------------------------------
RX_PONG_GEN: if C_RX_PING_PONG = 1 generate
signal rx_pong_ce : std_logic;
Begin
RX_PONG_I: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => rx_pong_ce ,
Wr_rd_n_a => rx_DPM_wr_rd_n ,
Adr_a => rx_DPM_adr ,
Data_in_a => rx_DPM_wr_data ,
Data_out_a => rx_pong_rd_data ,
Ce_b => IPIF_rx_Pong_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => rx_pong_data_out
);
-- RX Pong Buffer enable
rx_pong_ce <= rx_DPM_ce and rx_pong_ping_l;
--IPIF_rx_Pong_CE <= bus2ip_ce and Bus2IP_Addr(12) and Bus2IP_Addr(11);
IPIF_rx_Pong_CE <= bus2ip_ce and rx_pong_ce_en;
rx_pong_ce_en <= Bus2IP_Addr(12) and Bus2IP_Addr(11);
-------------------------------------------------------------------------
-- RX_PONG_PING_L_PROCESS
-------------------------------------------------------------------------
-- This process generate rx_pong_ping_l for RX PING/PONG buffer access
-------------------------------------------------------------------------
RX_PONG_PING_L_PROCESS:process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
rx_pong_ping_l <= '0';
elsif (rx_done_d1 = '1') then
if rx_pong_ping_l = '0' then
rx_pong_ping_l <= '1';
else
rx_pong_ping_l <= '0';
end if;
else
rx_pong_ping_l <= rx_pong_ping_l;
end if;
end if;
end process;
end generate RX_PONG_GEN;
----------------------------------------------------------------------------
-- Regiter Address Decoding
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-- Register Address Space
-----------------------------------------
-- **** MDIO Registers offset ****
-- Address Register => 0x07E4
-- Write Data Register => 0x07E8
-- Read Data Register => 0x07Ec
-- Control Register => 0x07F0
-----------------------------------------
-- **** Transmit Registers offset ****
-- Ping Length Register => 0x07F4
-- Ping Control Register => 0x07FC
-- Pong Length Register => 0x0FF4
-- Pong Control Register => 0x0FFC
-----------------------------------------
-- **** Receive Registers offset ****
-- Ping Control Register => 0x17FC
-- Pong Control Register => 0x1FFC
------------------------------------------
-- bus2ip_addr(12 downto 0)= axi_addr (12 downto 0)
----------------------------------------------------------------------------
reg_access_i <= '1' when bus2ip_addr(10 downto 5) = "111111"
else '0';
-- Register access enable
reg_en <= reg_access_i and (not Bus2IP_Burst);
-- TX/RX PING/PONG address decode
tx_ping_reg_en <= reg_en and (not bus2ip_addr(12)) and (not bus2ip_addr(11));
rx_ping_reg_en <= reg_en and ( bus2ip_addr(12)) and (not bus2ip_addr(11));
-- Status/Control/Length address decode
stat_reg_en <= not (bus2ip_addr(4) and bus2ip_addr(3) and bus2ip_addr(2));
control_reg <= bus2ip_addr(4) and bus2ip_addr(3) and bus2ip_addr(2);
length_reg <= bus2ip_addr(4) and (not bus2ip_addr(3)) and bus2ip_addr(2);
gie_reg <= bus2ip_addr(4) and bus2ip_addr(3) and (not bus2ip_addr(2));
---- TX/RX Ping/Pong Control/Length reg enable
tx_ping_ctrl_reg_en <= tx_ping_reg_en and control_reg;
tx_ping_length_reg_en <= tx_ping_reg_en and length_reg;
rx_ping_ctrl_reg_en <= rx_ping_reg_en and control_reg;
gie_reg_en <= tx_ping_reg_en and gie_reg;
----------------------------------------------------------------------------
-- REG_ACCESS_PROCESS
----------------------------------------------------------------------------
-- Registering the reg_access to break long timing path
----------------------------------------------------------------------------
REG_ACCESS_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
reg_access <= '0';
reg_access_d1 <= '0';
elsif Bus2IP_RdCE='1' then
-- TX/RX Ping/Pong Control/Length reg enable
reg_access <= reg_access_i;
reg_access_d1 <= reg_access;
end if;
end if;
end process REG_ACCESS_PROCESS;
----------------------------------------------------------------------------
-- TX_PONG_REG_GEN : Receive Pong Register generate
----------------------------------------------------------------------------
-- This Logic is included only if both the buffers are enabled.
----------------------------------------------------------------------------
TX_PONG_REG_GEN: if C_TX_PING_PONG = 1 generate
tx_pong_reg_en <= reg_en and (not bus2ip_addr(12))
and (bus2ip_addr(11));
tx_pong_ctrl_reg_en <= '1' when (tx_pong_reg_en='1') and
(control_reg='1') else
'0';
tx_pong_length_reg_en <= '1' when (tx_pong_reg_en='1') and
(length_reg='1') else
'0';
-------------------------------------------------------------------------
-- TX_PONG_CTRL_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-------------------------------------------------------------------------
TX_PONG_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_mac_program <= '0';
pong_tx_status <= '0';
pong_soft_status <= '0';
elsif (Bus2IP_WrCE = '1' and tx_pong_ctrl_reg_en = '1') then
-- Load Pong Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
pong_soft_status <= Bus2IP_Data(31);
pong_mac_program <= Bus2IP_Data(1);
pong_tx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (tx_done_d1 = '1' and tx_pong_ping_l = '1') then
pong_tx_status <= '0';
pong_mac_program <= '0';
end if;
end if;
end process TX_PONG_CTRL_REG_PROCESS;
-------------------------------------------------------------------------
-- TX_PONG_LENGTH_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the length register is enabled.
-------------------------------------------------------------------------
TX_PONG_LENGTH_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_pkt_lenth <= (others=>'0');
elsif (Bus2IP_WrCE = '1' and tx_pong_length_reg_en = '1') then
-- Load Packet length Register with AXI
-- data if there is a write request
-- and the length register is enabled
pong_pkt_lenth <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process TX_PONG_LENGTH_REG_PROCESS;
end generate TX_PONG_REG_GEN;
----------------------------------------------------------------------------
-- NO_TX_PING_SIG :No Pong registers
----------------------------------------------------------------------------
NO_TX_PING_SIG: if C_TX_PING_PONG = 0 generate
tx_pong_ping_l <= '0';
tx_pong_length_reg_en <= '0';
tx_pong_ctrl_reg_en <= '0';
pong_pkt_lenth <= (others=>'0');
pong_mac_program <= '0';
pong_tx_status <= '0';
IPIF_tx_Pong_CE <= '0';
tx_pong_data_out <= (others=>'0');
tx_pong_rd_data <= (others=>'0');
end generate NO_TX_PING_SIG;
----------------------------------------------------------------------------
-- RX_PONG_REG_GEN: Receive Pong Register generate
----------------------------------------------------------------------------
-- This Logic is included only if both the buffers are enabled.
----------------------------------------------------------------------------
RX_PONG_REG_GEN: if C_RX_PING_PONG = 1 generate
rx_pong_reg_en <= reg_en and (bus2ip_addr(12)) and (bus2ip_addr(11));
rx_pong_ctrl_reg_en <= '1' when (rx_pong_reg_en='1') and
(control_reg='1') else
'0';
-- Receive frame indicator
rx_buffer_ready <= not (ping_rx_status and pong_rx_status);
-------------------------------------------------------------------------
-- RX_PONG_CTRL_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Pong control register is enabled.
-------------------------------------------------------------------------
RX_PONG_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_rx_status <= '0';
elsif (Bus2IP_WrCE = '1' and rx_pong_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
pong_rx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
--elsif (rx_done_d1 = '1' and rx_pong_ping_l = '1') then
elsif (rx_done = '1' and rx_pong_ping_l = '1') then
pong_rx_status <= '1';
end if;
end if;
end process RX_PONG_CTRL_REG_PROCESS;
end generate RX_PONG_REG_GEN;
----------------------------------------------------------------------------
-- No Pong registers
----------------------------------------------------------------------------
NO_RX_PING_SIG: if C_RX_PING_PONG = 0 generate
rx_pong_ping_l <= '0';
rx_pong_reg_en <= '0';
rx_pong_ctrl_reg_en <= '0';
pong_rx_status <= '0';
IPIF_rx_Pong_CE <= '0';
rx_pong_rd_data <= (others=>'0');
rx_pong_data_out <= (others=>'0');
-- Receive frame indicator
rx_buffer_ready <= not ping_rx_status ;
end generate NO_RX_PING_SIG;
----------------------------------------------------------------------------
-- TX_PING_CTRL_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_PING_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_intr_en <= '0';
ping_mac_program <= '0';
ping_tx_status <= '0';
ping_soft_status <= '0';
elsif (Bus2IP_WrCE = '1' and tx_ping_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
ping_soft_status <= Bus2IP_Data(31);
tx_intr_en <= Bus2IP_Data(3);
ping_mac_program <= Bus2IP_Data(1);
ping_tx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (tx_done_d1 = '1' and tx_pong_ping_l = '0') then
ping_tx_status <= '0';
ping_mac_program <= '0';
end if;
end if;
end process TX_PING_CTRL_REG_PROCESS;
----------------------------------------------------------------------------
-- TX_LOOPBACK_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_LOOPBACK_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
loopback_en <= '0';
elsif (Bus2IP_WrCE = '1' and tx_ping_ctrl_reg_en = '1'
and tx_idle='1' ) then
-- Load loopback Register with AXI
-- data if there is a write request
-- and the Loopback register is enabled
loopback_en <= Bus2IP_Data(4);
-- Clear the status bit when trnasmit complete
end if;
end if;
end process TX_LOOPBACK_REG_PROCESS;
----------------------------------------------------------------------------
-- CDC module for syncing tx_en_i in fifo_empty domain
----------------------------------------------------------------------------
-- CDC_LOOPBACK: entity proc_common_v4_0.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_FLOP_INPUT => 0,
-- C_VECTOR_WIDTH => 1,
-- C_MTBF_STAGES => 4
-- )
-- port map(
-- prmry_aclk => '1',
-- prmry_resetn => '1',
-- prmry_in => loopback_en,
-- prmry_ack => open,
-- scndry_out => Loopback,
-- scndry_aclk => PHY_rx_clk,
-- scndry_resetn => '1',
-- prmry_vect_in => (OTHERS => '0'),
-- scndry_vect_out => open
-- );
Loopback <= loopback_en; --added the cdc block to drive the output directly
----------------------------------------------------------------------------
-- TX_PING_LENGTH_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Length register is enabled.
----------------------------------------------------------------------------
TX_PING_LENGTH_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
ping_pkt_lenth <= (others=>'0');
elsif (Bus2IP_WrCE = '1' and tx_ping_length_reg_en = '1') then
-- Load Packet length Register with AXI
-- data if there is a write request
-- and the length register is enabled
ping_pkt_lenth <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process TX_PING_LENGTH_REG_PROCESS;
----------------------------------------------------------------------------
-- GIE_EN_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the GIE register is enabled.
----------------------------------------------------------------------------
GIE_EN_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
gie_enable <= '0';
elsif (Bus2IP_WrCE = '1' and gie_reg_en = '1') then
-- Load Global Interrupt Enable Register with AXI
-- data if there is a write request
-- and the length register is enabled
gie_enable <= Bus2IP_Data(31);
end if;
end if;
end process GIE_EN_REG_PROCESS;
----------------------------------------------------------------------------
-- RX_PING_CTRL_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Ping control register is enabled.
----------------------------------------------------------------------------
RX_PING_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
rx_intr_en <= '0';
ping_rx_status <= '0';
elsif (Bus2IP_WrCE = '1' and rx_ping_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
rx_intr_en <= Bus2IP_Data(3);
ping_rx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (rx_done = '1' and rx_pong_ping_l = '0') then
ping_rx_status <= '1';
end if;
end if;
end process RX_PING_CTRL_REG_PROCESS;
----------------------------------------------------------------------------
-- REGISTER_READ_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
REGISTER_READ_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
reg_data_out <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and tx_ping_ctrl_reg_en = '1') then
-- TX PING Control Register Read through AXI
reg_data_out(0) <= ping_tx_status;
reg_data_out(1) <= ping_mac_program;
reg_data_out(2) <= '0';
reg_data_out(3) <= tx_intr_en;
reg_data_out(4) <= loopback_en;
reg_data_out(31) <= ping_soft_status;
reg_data_out(30 downto 5) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and tx_pong_ctrl_reg_en = '1') then
-- TX PONG Control Register Read through AXI
reg_data_out(0) <= pong_tx_status;
reg_data_out(1) <= pong_mac_program;
reg_data_out(30 downto 2) <= (others=>'0');
reg_data_out(31) <= pong_soft_status;
elsif (Bus2IP_RdCE = '1' and tx_ping_length_reg_en = '1') then
-- TX PING Length Register Read through AXI
reg_data_out(31 downto 16) <= (others=>'0');
reg_data_out(15 downto 0) <= ping_pkt_lenth;
elsif (Bus2IP_RdCE = '1' and tx_pong_length_reg_en = '1') then
-- TX PONG Length Register Read through AXI
reg_data_out(31 downto 16) <= (others=>'0');
reg_data_out(15 downto 0) <= pong_pkt_lenth;
elsif (Bus2IP_RdCE = '1' and rx_ping_ctrl_reg_en = '1') then
-- RX PING Control Register Read through AXI
reg_data_out(0) <= ping_rx_status;
reg_data_out(1) <= '0';
reg_data_out(2) <= '0';
reg_data_out(3) <= rx_intr_en;
reg_data_out(31 downto 4) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and rx_pong_ctrl_reg_en = '1') then
-- RX PONG Control Register Read through AXI
reg_data_out(0) <= pong_rx_status;
reg_data_out(31 downto 1) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and gie_reg_en = '1') then
-- GIE Register Read through AXI
reg_data_out(31) <= gie_enable;
reg_data_out(30 downto 0) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and stat_reg_en = '1') then
-- Common Status Register Read through AXI
reg_data_out(0) <= status_reg(0);
reg_data_out(1) <= status_reg(1);
reg_data_out(2) <= status_reg(2);
reg_data_out(3) <= status_reg(3);
reg_data_out(4) <= status_reg(4);
reg_data_out(5) <= status_reg(5);
reg_data_out(31 downto 6) <= (others=>'0');
--else
-- reg_data_out <= (others=>'0');
end if;
end if;
end process REGISTER_READ_PROCESS;
----------------------------------------------------------------------------
-- COMMON_STATUS_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-- status_reg : std_logic_vector(0 to 5);
-- status reg address = 0x07E0
-- status_reg(5) : Ping TX complete
-- status_reg(4) : Pong TX complete
-- status_reg(3) : Ping RX complete
-- status_reg(2) : Pong RX complete
-- status_reg(1) : Ping MAC program complete
-- status_reg(0) : Pong MAC program complete
-- All Status bit will be cleared after reading this register
----------------------------------------------------------------------------
COMMON_STATUS_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
status_reg <= (others=>'0');
elsif (tx_done = '1') then
if (tx_pong_ping_l = '0' and ping_mac_program='0' ) then
status_reg <= (others=>'0');
status_reg(5) <= '1';
elsif (tx_pong_ping_l = '0' and ping_mac_program='1' ) then
status_reg <= (others=>'0');
status_reg(1) <= '1';
elsif (tx_pong_ping_l = '1' and pong_mac_program='0' ) then
status_reg <= (others=>'0');
status_reg(4) <= '1';
elsif (tx_pong_ping_l = '1' and pong_mac_program='1' ) then
status_reg <= (others=>'0');
status_reg(0) <= '1';
end if;
elsif (rx_done_d1 = '1') then
if (rx_pong_ping_l = '0') then
status_reg <= (others=>'0');
status_reg(3) <= '1';
else
status_reg <= (others=>'0');
status_reg(2) <= '1';
end if;
end if;
end if;
end process COMMON_STATUS_REG_PROCESS;
----------------------------------------------------------------------------
-- TX_LENGTH_MUX_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_LENGTH_MUX_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_packet_length <= (others=>'0');
elsif (tx_pong_ping_l = '1') then
-- Load Control Register with AXI
tx_packet_length <= pong_pkt_lenth;
-- Clear the status bit when trnasmit complete
else
tx_packet_length <= ping_pkt_lenth;
end if;
end if;
end process TX_LENGTH_MUX_PROCESS;
-- Tx Start indicator
transmit_start <= ((ping_tx_status and not ping_mac_program) or
(pong_tx_status and not pong_mac_program)) and
not tx_done_d2;
-- MAC program start indicator
mac_program_start <= (ping_tx_status and ping_mac_program) or
(pong_tx_status and pong_mac_program);
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- MDIO_GEN :- Include MDIO interface if the parameter C_INCLUDE_MDIO = 1
----------------------------------------------------------------------------
MDIO_GEN: if C_INCLUDE_MDIO = 1 generate
signal mdio_addr_en : std_logic;
signal mdio_wr_data_en : std_logic;
signal mdio_rd_data_en : std_logic;
signal mdio_ctrl_en : std_logic;
signal mdio_op_i : std_logic;
signal mdio_en_i : std_logic;
signal mdio_req_i : std_logic;
signal mdio_done_i : std_logic;
signal mdio_wr_data_reg : std_logic_vector(15 downto 0);
signal mdio_rd_data_reg : std_logic_vector(15 downto 0);
signal mdio_phy_addr : std_logic_vector(4 downto 0);
signal mdio_reg_addr : std_logic_vector(4 downto 0);
signal mdio_clk_i : std_logic;
-- signal mdio_ctrl_en_reg : std_logic;
signal clk_cnt : integer range 0 to 63;
begin
-- MDIO reg enable
mdio_reg_en <= --not stat_reg_en_reg and
(mdio_addr_en or
mdio_wr_data_en or
mdio_rd_data_en or
mdio_ctrl_en ) and (not Bus2IP_Burst);
--mdio_ctrl_en or mdio_ctrl_en_reg ) and (not Bus2IP_Burst);
-- MDIO address reg enable
mdio_addr_en <= reg_en and (not bus2ip_addr(4))
and (not bus2ip_addr(3))
and ( bus2ip_addr(2));
-- MDIO write data reg enable
mdio_wr_data_en <= reg_en and (not bus2ip_addr(4))
and ( bus2ip_addr(3))
and (not bus2ip_addr(2));
-- MDIO read data reg enable
mdio_rd_data_en <= reg_en and (not bus2ip_addr(4))
and ( bus2ip_addr(3))
and ( bus2ip_addr(2));
-- MDIO controlreg enable
mdio_ctrl_en <= reg_en and ( bus2ip_addr(4))
and (not bus2ip_addr(3))
and (not bus2ip_addr(2));
-------------------------------------------------------------------------
-- MDIO_CTRL_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the MDIO control register is enabled.
-------------------------------------------------------------------------
MDIO_CTRL_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_en_i <= '0';
mdio_req_i <= '0';
elsif (Bus2IP_WrCE = '1' and mdio_ctrl_en= '1') then
-- Load MDIO Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
mdio_en_i <= Bus2IP_Data(3);
mdio_req_i <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif mdio_done_i = '1' then
mdio_req_i <= '0';
end if;
end if;
end process MDIO_CTRL_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_ADDR_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the MDIO Address register is enabled.
-------------------------------------------------------------------------
MDIO_ADDR_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_phy_addr <= (others =>'0');
mdio_reg_addr <= (others =>'0');
mdio_op_i <= '0';
elsif (Bus2IP_WrCE = '1' and mdio_addr_en= '1') then
-- Load MDIO ADDR Register with AXI
-- data if there is a write request
-- and the Address register is enabled
mdio_phy_addr <= Bus2IP_Data(9 downto 5);
mdio_reg_addr <= Bus2IP_Data(4 downto 0);
mdio_op_i <= Bus2IP_Data(10);
end if;
end if;
end process MDIO_ADDR_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_WRITE_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request
-- and the MDIO Write register is enabled.
-------------------------------------------------------------------------
MDIO_WRITE_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_wr_data_reg <= (others =>'0');
elsif (Bus2IP_WrCE = '1' and mdio_wr_data_en= '1') then
-- Load MDIO Write Data Register with AXI
-- data if there is a write request
-- and the Write Data register is enabled
mdio_wr_data_reg <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process MDIO_WRITE_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_REG_RD_PROCESS
-------------------------------------------------------------------------
-- This process allows MDIO register read from the AXI when there is a
-- read request and the MDIO registers are enabled.
-------------------------------------------------------------------------
MDIO_REG_RD_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_data_out <= (others =>'0');
elsif (Bus2IP_RdCE = '1' and mdio_addr_en= '1') then
-- MDIO Address Register Read through AXI
mdio_data_out(4 downto 0) <= mdio_reg_addr;
mdio_data_out(9 downto 5) <= mdio_phy_addr;
mdio_data_out(10) <= mdio_op_i;
mdio_data_out(31 downto 11) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_wr_data_en= '1') then
-- MDIO Write Data Register Read through AXI
mdio_data_out(15 downto 0) <= mdio_wr_data_reg;
mdio_data_out(31 downto 16) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_rd_data_en= '1') then
-- MDIO Read Data Register Read through AXI
mdio_data_out(15 downto 0) <= mdio_rd_data_reg;
mdio_data_out(31 downto 16) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_ctrl_en= '1') then
-- MDIO Control Register Read through AXI
mdio_data_out(0) <= mdio_req_i;
mdio_data_out(1) <= '0';
mdio_data_out(2) <= '0';
mdio_data_out(3) <= mdio_en_i;
mdio_data_out(31 downto 4) <= (others=>'0');
--else
-- mdio_data_out <= (others =>'0');
end if;
end if;
end process MDIO_REG_RD_PROCESS;
-------------------------------------------------------------------------
-- PROCESS : MDIO_CLK_COUNTER
-------------------------------------------------------------------------
-- Generating MDIO clock. The minimum period for MDC clock is 400 ns.
-------------------------------------------------------------------------
MDIO_CLK_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
clk_cnt <= MDIO_CNT;
mdio_clk_i <= '0';
elsif (clk_cnt = 0) then
clk_cnt <= MDIO_CNT;
mdio_clk_i <= not mdio_clk_i;
else
clk_cnt <= clk_cnt - 1;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- MDIO master interface module
-------------------------------------------------------------------------
MDIO_IF_I: entity axi_ethernetlite_v3_0.mdio_if
port map (
Clk => Clk ,
Rst => Rst ,
MDIO_CLK => mdio_clk_i ,
MDIO_en => mdio_en_i ,
MDIO_OP => mdio_op_i ,
MDIO_Req => mdio_req_i ,
MDIO_PHY_AD => mdio_phy_addr ,
MDIO_REG_AD => mdio_reg_addr ,
MDIO_WR_DATA => mdio_wr_data_reg ,
MDIO_RD_DATA => mdio_rd_data_reg ,
PHY_MDIO_I => PHY_MDIO_I ,
PHY_MDIO_O => PHY_MDIO_O ,
PHY_MDIO_T => PHY_MDIO_T ,
PHY_MDC => PHY_MDC ,
MDIO_done => mdio_done_i
);
end generate MDIO_GEN;
----------------------------------------------------------------------------
-- NO_MDIO_GEN :- Include MDIO interface if the parameter C_INCLUDE_MDIO = 0
----------------------------------------------------------------------------
NO_MDIO_GEN: if C_INCLUDE_MDIO = 0 generate
begin
mdio_data_out <= (others=>'0');
mdio_reg_en <= '0';
PHY_MDIO_O <= '0';
PHY_MDIO_T <= '1';
end generate NO_MDIO_GEN;
end imp;
|
gpl-3.0
|
58ca7188fbfe6a74d17b824a004041d5
| 0.412397 | 4.199092 | false | false | false | false |
IAIK/ascon_hardware
|
caesar_hardware_api/HDL/AEAD/src_rtl/AEAD.vhd
| 1 | 2,127 |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @author Hannes Gross
--! @brief Generic Ascon-128(a) implementation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity AEAD is
generic (
--! I/O width (bits)
G_W : integer := 32; --! Public data input
G_SW : integer := 32; --! Secret data input
--! Reset behavior
G_ASYNC_RSTN : boolean := False; --! Async active low reset
--! Special features parameters
G_ENABLE_PAD : boolean := True; --! Enable padding
G_CIPH_EXP : boolean := False; --! Ciphertext expansion
G_REVERSE_CIPH : boolean := False; --! Reversed ciphertext
G_MERGE_TAG : boolean := False; --! Merge tag with data segment
--! Block size (bits)
G_ABLK_SIZE : integer := 64; --! Associated data 128 or 64
G_DBLK_SIZE : integer := 64; --! Data 128 or 64
G_KEY_SIZE : integer := 32; --! Key
G_TAG_SIZE : integer := 128; --! Tag
--! Padding options
G_PAD_STYLE : integer := 1; --! Pad style
G_PAD_AD : integer := 3; --! Padding behavior for AD
G_PAD_D : integer := 4 --! Padding behavior for Data
);
port (
--! Global ports
clk : in std_logic;
rst : in std_logic;
--! Publica data ports
pdi_data : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Secret data ports
sdi_data : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out ports
do_data : out std_logic_vector(G_W -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD;
|
apache-2.0
|
86a822cd3e8f7f2ef5260e276990ec11
| 0.445228 | 4.228628 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_emc_v3_0/a61d85ec/hdl/src/vhdl/axi_emc_address_decode.vhd
| 4 | 20,642 |
-------------------------------------------------------------------------------
-- emc_emc_address_decoder - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: emc_emc_address_decoder.vhd
-- Version: v2.0
-- Description: This is the address decoder logic file for axi emc core.
-------------------------------------------------------------------------------
-- Structure:
-- axi_emc.vhd
-- -- axi_emc_native_interface.vhd
-- -- axi_emc_addr_gen.vhd
-- -- axi_emc_address_decode.vhd
-- -- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: SK
--
-- History:
-- SK 10/02/10 --
-- ^^^^^^
-- -- Created the new version v1.01.a
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use IEEE.std_logic_misc.or_reduce;
library axi_emc_v3_0;
use axi_emc_v3_0.all;
use axi_emc_v3_0.emc_pkg.all;
entity axi_emc_address_decode is
generic(
C_S_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_ADDR_DECODE_BITS : integer;
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_0FFF", -- IP user0 high address
X"0000_0000_1000_1000", -- IP user1 base address
X"0000_0000_1000_1FFF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0=> 1, -- User0 CE Number-- only 1 is allowed per addr range
1=> 1 -- User1 CE Number-- only 1 is allowed per addr range
);
C_FAMILY : string := "virtex6"
);
port(
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Enable_CS : in std_logic;
Enable_RdCE : in std_logic;
Enable_WrCE : in std_logic;
Rst_CS : in std_logic;
Rst_Wr_CE : in std_logic;
Rst_Rd_CE : in std_logic;
Addr_SM_PS_IDLE : in std_logic;
Addr_int : in std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
RNW : in std_logic;
RdFIFO_Space_two_int : in std_logic;
Bus2IP_CS : out std_logic_vector
((((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1)downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)downto 0);
ORed_cs : out std_logic
);
end entity axi_emc_address_decode;
-------------------------
---------------------------
-- architecture section starts
---------------------------
architecture imp of axi_emc_address_decode is
--------------------
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- constant declaration
-- Reset Active State
constant ACTIVE_LOW_RESET : std_logic := '0';
------------------------------------
-- local type declarations
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to(C_ADDR_DECODE_BITS-1));
----------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
----------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
--coverage off
return(slv_array);
--coverage on
end function slv64_2_slv_awidth;
----------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_ADDR_DECODE_BITS-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_ADDR_DECODE_BITS-1);
begin
addr_nor := x xor y;
for i in 0 to C_ADDR_DECODE_BITS-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_ADDR_DECODE_BITS);
--coverage on
end function Addr_Bits;
----------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
--coverage off
return(num_bits);
--coverage on
end function Get_Addr_Bits;
----------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
----------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := ce_array'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
--coverage off
return(num_addr_bits);
--coverage on
end function NEEDED_ADDR_BITS;
----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
--coverage off
return(ce_num_sum);
--coverage on
end function calc_start_ce_index;
------------------------
-- Constant Declarations
------------------------
-- convert 64 bit address array into 32 bit address array
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_ADDR_DECODE_BITS);
-- get the number of address pairs given in the ARD ADDR RANGE array
constant NUM_BASE_ADDRS : integer :=(C_ARD_ADDR_RANGE_ARRAY'length)/2;
-- 1 decode for 1 address pair from ARD ADDRESS RANGE array, by this
-- get total decode bits
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
----------------------
-- Signal Declarations
----------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal int_pselect : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal CE_reg : std_logic_vector
(0 to (NUM_CE_SIGNALS-1));
signal pselect_hit_reg : std_logic_vector
(0 to (NUM_CE_SIGNALS-1));
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_clear_int : std_logic;
signal rdce_clear_int : std_logic;
signal ored_ce_int : std_logic;
signal decode_addr_int : std_logic_vector(0 to C_ADDR_DECODE_BITS-1);
signal cs_reg : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1)
:=(others => '0');
signal cs_clear_int : std_logic;
----------------------
begin -- architecture imp
----------------------
decode_addr_int <= Addr_int((C_ADDR_DECODE_BITS-1) downto 0);
wrce_clear_int <= not(Bus2IP_Resetn) or Rst_Wr_CE or Rst_CS;
rdce_clear_int <= not(Bus2IP_Resetn) or Rst_Rd_CE or Rst_CS;
cs_clear_int <= not(Bus2IP_Resetn) or Rst_CS;
---------------------------------
-- Universal Address Decode Block
---------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
-- get the individual number of CE's
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE: Integer --range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
signal temp_avalid : std_logic;
------
begin
------
temp_avalid <= (Addr_SM_PS_IDLE and (Enable_CS));-- or S_AXI_MEM_AWVALID));
------------------------------
-- generate multiple chip selects
------------------------------
MULTI_CS_GEN : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_emc_v3_0.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_ADDR_DECODE_BITS,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => decode_addr_int, -- [in]
AValid => temp_avalid, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate MULTI_CS_GEN;
ONE_CS_GEN : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Addr_SM_PS_IDLE;
end generate ONE_CS_GEN;
--------
-- CS_REG_P:-- register Bus2IP_CS signals
--------
CS_REG_P : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Addr_SM_PS_IDLE='1')then
cs_reg(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process CS_REG_P;
--------
-- CS_OUT_P:-- register Bus2IP_CS signals
--------
CS_OUT_P : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(cs_clear_int='1')then
cs_out_i(bar_index) <= '0';
elsif((Addr_SM_PS_IDLE='1') and (Enable_CS='1'))then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process CS_OUT_P;
--------------
-- RDCE_REG_P: Register RdCE signal generation logic
--------------
RDCE_REG_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(rdce_clear_int='1') then
rdce_out_i(bar_index) <= '0';
elsif((Addr_SM_PS_IDLE='1') and
(RNW='1') and
(Enable_CS='1')
)then
rdce_out_i(bar_index) <= pselect_hit_i(bar_index);
elsif(Enable_RdCE='1')then
rdce_out_i(bar_index) <= cs_reg(bar_index);
end if;
end if;
end process RDCE_REG_P;
---------------
-- WRCE_REG_P: Register WrCE signal generation logic
---------------
WRCE_REG_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(wrce_clear_int='1') then
wrce_out_i(bar_index) <= '0';
elsif((Addr_SM_PS_IDLE='1') and
(RNW='0') and
(Enable_CS='1')
)then
wrce_out_i(bar_index) <= pselect_hit_i(bar_index);
elsif(Enable_WrCE='1')then
wrce_out_i(bar_index) <= cs_reg(bar_index);
end if;
end if;
end process WRCE_REG_P;
end generate MEM_DECODE_GEN;
-----------------------------
-- Assign registered output signals
BUS2IP_CS_GEN: for i in 0 to (NUM_BASE_ADDRS-1) generate
Bus2IP_CS(i) <= cs_out_i(i);
end generate BUS2IP_CS_GEN;
-----------------------------
BUS2IP_RDCE_GEN: for i in 0 to (NUM_BASE_ADDRS-1) generate
Bus2IP_RdCE(i) <= rdce_out_i(i) and
(not Rst_Rd_CE);-- and
-- RdFIFO_Space_two_int;
end generate BUS2IP_RDCE_GEN;
-----------------------------
BUS2IP_WRCE_GEN: for i in 0 to (NUM_BASE_ADDRS-1) generate
Bus2IP_WrCE(i) <= wrce_out_i(i);-- and not Rst_Wr_CE;
end generate BUS2IP_WRCE_GEN;
-----------------------------
ored_ce_int <= or_reduce(rdce_out_i) when (RNW='1')
else
or_reduce(wrce_out_i);
ORed_cs <= or_reduce(cs_out_i);
end architecture imp;
|
gpl-3.0
|
292bb3616429f87e10a2f1247a815603
| 0.498401 | 4.161694 | false | false | false | false |
IAIK/ascon_hardware
|
caesar_hardware_api/HDL/AEAD/src_rtl/old/AEAD.vhd
| 1 | 2,855 |
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Entity of authenticated encryption unit.
--!
--! Entity for dummy1 core
--!
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity AEAD is
generic (
--! I/O size (bits)
G_W : integer := 32; --! Public data input
G_SW : integer := 32; --! Secret data input
--! Reset behavior
G_ASYNC_RSTN : boolean := False; --! Async active low reset
--! Special features parameters
G_ENABLE_PAD : boolean := True; --! Enable padding
G_CIPH_EXP : boolean := False; --! Ciphertext expansion
G_REVERSE_CIPH : boolean := False; --! Reversed ciphertext
G_MERGE_TAG : boolean := False; --! Merge tag with data segment
--! Block size (bits)
G_ABLK_SIZE : integer := 128; --! Associated data
G_DBLK_SIZE : integer := 128; --! Data
G_KEY_SIZE : integer := 128; --! Key
G_TAG_SIZE : integer := 128; --! Tag
--! Padding options
G_PAD_STYLE : integer := 1; --! Pad style
G_PAD_AD : integer := 1; --! Padding behavior for AD
G_PAD_D : integer := 1 --! Padding behavior for Data
);
port (
--! Global ports
clk : in std_logic;
rst : in std_logic;
--! Publica data ports
pdi_data : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Secret data ports
sdi_data : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out ports
do_data : out std_logic_vector(G_W -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD;
|
apache-2.0
|
20f90b99098ab05900eb5c4be5849f03
| 0.494217 | 4.382488 | false | false | false | false |
hoangt/PoC
|
src/arith/arith.pkg.vhdl
| 2 | 5,066 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and functions
-- associated to the PoC.arith namespace
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
package arith is
component arith_firstone is
generic (
N : positive -- Length of Token Chain
);
port (
tin : in std_logic := '1'; -- Enable: Fed Token
rqst : in std_logic_vector(N-1 downto 0); -- Request: Token Requests
grnt : out std_logic_vector(N-1 downto 0); -- Grant: Token Output
tout : out std_logic; -- Inactive: Unused Token
bin : out std_logic_vector(log2ceil(N)-1 downto 0) -- Binary Grant Index
);
end component;
component arith_counter_bcd is
generic (
DIGITS : positive);
port (
clk : in std_logic;
rst : in std_logic;
inc : in std_logic;
val : out T_BCD_VECTOR(DIGITS-1 downto 0));
end component;
component arith_counter_gray is
generic (
BITS : positive; -- Bit width of the counter
INIT : natural := 0 -- Initial/reset counter value
);
port (
clk : in std_logic;
rst : in std_logic; -- Reset to INIT value
inc : in std_logic; -- Increment
dec : in std_logic := '0'; -- Decrement
val : out std_logic_vector(BITS-1 downto 0); -- Value output
cry : out std_logic -- Carry output
);
end component;
component arith_div
generic (
N : positive;
RAPOW : positive;
REGISTERED : boolean);
port (
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
rdy : out std_logic;
arg1, arg2 : in std_logic_vector(N-1 downto 0);
res : out std_logic_vector(N-1 downto 0));
end component;
component arith_div_pipelined
generic (
DIVIDEND_BITS : POSITIVE;
DIVISOR_BITS : POSITIVE;
RADIX : POSITIVE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Enable : in STD_LOGIC;
Dividend : in STD_LOGIC_VECTOR(DIVIDEND_BITS - 1 downto 0);
Divisor : in STD_LOGIC_VECTOR(DIVISOR_BITS - 1 downto 0);
Quotient : out STD_LOGIC_VECTOR(DIVIDEND_BITS - 1 downto 0);
Valid : out STD_LOGIC
);
end component;
component arith_prng
generic (
BITS : positive;
SEED : natural := 0
);
port (
clk : in std_logic;
rst : in std_logic;
got : in std_logic;
val : out std_logic_vector(BITS-1 downto 0));
end component;
component arith_muls_wide
generic (
NA : integer range 2 to 18;
NB : integer range 19 to 36;
SPLIT : positive);
port (
a : in signed(NA-1 downto 0);
b : in signed(NB-1 downto 0);
p : out signed(NA+NB-1 downto 0));
end component;
component arith_sqrt
generic (
N : positive);
port (
rst : in std_logic;
clk : in std_logic;
arg : in std_logic_vector(N-1 downto 0);
start : in std_logic;
sqrt : out std_logic_vector((N-1)/2 downto 0);
rdy : out std_logic);
end component;
type tArch is (AAM, CAI, CCA, PAI);
type tBlocking is (DFLT, FIX, ASC, DESC);
type tSkipping is (PLAIN, CCC, PPN_KS, PPN_BK);
component arith_addw is
generic (
N : positive; -- Operand Width
K : positive; -- Block Count
ARCH : tArch := AAM; -- Architecture
BLOCKING : tBlocking := DFLT; -- Blocking Scheme
SKIPPING : tSkipping := CCC; -- Carry Skip Scheme
P_INCLUSIVE : boolean := false -- Use Inclusive Propagate, i.e. c^1
);
port (
a, b : in std_logic_vector(N-1 downto 0);
cin : in std_logic;
s : out std_logic_vector(N-1 downto 0);
cout : out std_logic
);
end component;
end package;
|
apache-2.0
|
4d099c5afeb93d79d91b021496561f53
| 0.579945 | 3.348315 | false | false | false | false |
lowRISC/greth-library
|
greth_library/work/rocket_soc_v6.vhd
| 2 | 14,226 |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Network on Chip design top level.
--! @details RISC-V "Rocket Core" based system with the AMBA AXI4 (NASTI)
--! system bus and integrated peripheries.
------------------------------------------------------------------------------
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library rocketlib;
--! SOC top-level component declaration.
use rocketlib.types_rocket.all;
--! Ethernet related declarations.
use rocketlib.grethpkg.all;
--! GNSS Sensor Ltd proprietary library
library gnsslib;
use gnsslib.types_gnss.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
--! Target independable configuration.
use work.config_common.all;
--! @brief SOC Top-level entity declaration.
--! @details This module implements full SOC functionality and all IO signals
--! are available on FPGA/ASIC IO pins.
entity rocket_soc is port
(
--! Input reset. Active High. Usually assigned to button "Center".
i_rst : in std_logic;
--! @name Clocks:
--! @{
--! Differential clock (LVDS) positive signal.
i_sclk_p : in std_logic;
--! Differential clock (LVDS) negative signal.
i_sclk_n : in std_logic;
--! External ADC clock (default 26 MHz).
i_clk_adc : in std_logic;
--! @}
--! @name User's IOs:
--! @{
--! DIP switch.
i_int_clkrf : in std_logic;
i_dip : in std_logic_vector(3 downto 1);
--! LEDs.
o_led : out std_logic_vector(7 downto 0);
--! @}
--! @name UART1 signals:
--! @{
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
--! @}
--! Ethernet MAC PHY interface signals
--! @{
eth_refclk : out std_ulogic; -- RMII clock out
i_gmiiclk_p : in std_ulogic; -- GMII clock in
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic
);
--! @}
end rocket_soc;
--! @brief SOC top-level architecture declaration.
architecture arch_rocket_soc of rocket_soc is
--! @name Buffered in/out signals.
--! @details All signals that are connected with in/out pads must be passed
--! through the dedicated buffere modules. For FPGA they are implemented
--! as an empty devices but ASIC couldn't be made without buffering.
--! @{
signal ib_rst : std_logic;
signal ib_sclk_p : std_logic;
signal ib_sclk_n : std_logic;
signal ib_clk_adc : std_logic;
signal ib_dip : std_logic_vector(3 downto 0);
signal ib_gmiiclk : std_logic;
--! @}
signal wSysReset : std_ulogic; -- Internal system reset. MUST NOT USED BY DEVICES.
signal wReset : std_ulogic; -- Global reset active HIGH
signal wNReset : std_ulogic; -- Global reset active LOW
signal soft_rst : std_logic; -- reset from exteranl debugger
signal bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal wClkBus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
signal wClkAdc : std_ulogic; -- 26 MHz from the internal PLL
signal wPllLocked : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
signal uart1i : uart_in_type;
signal uart1o : uart_out_type;
--! Arbiter is switching only slaves output signal, data from noc
--! is connected to all slaves and to the arbiter itself.
signal aximi : nasti_master_in_type;
signal aximo : nasti_master_out_vector;
signal axisi : nasti_slave_in_type;
signal axiso : nasti_slaves_out_vector;
signal slv_cfg : nasti_slave_cfg_vector;
signal mst_cfg : nasti_master_cfg_vector;
--! From modules-to-tile requests
signal htifo : host_out_vector;
--! Selected request with the highest priority.
signal htifo_mux : host_out_type;
--! tile-to-module response.
signal htifi : host_in_type;
--! response with the 'grant' signal marking the exact recipient.
signal htifi_grant : host_in_type;
signal gnss_i : gns_in_type;
signal gnss_o : gns_out_type;
signal fse_i : fse_in_type;
signal fse_o : fse_out_type;
signal eth_i : eth_in_type;
signal eth_o : eth_out_type;
signal irq_pins : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
begin
--! PAD buffers:
irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst);
iclkp0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_p, i_sclk_p);
iclkn0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_n, i_sclk_n);
iclk1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_clk_adc, i_clk_adc);
idip0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(0), i_int_clkrf);
dipx : for i in 1 to 3 generate
idipz : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(i), i_dip(i));
end generate;
diffclk: if CFG_RMII = 0 generate
igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map (
i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk);
end generate;
--! @todo all other in/out signals via buffers:
------------------------------------
-- @brief Internal PLL device instance.
pll0 : SysPLL_tech generic map (
tech => CFG_FABTECH,
tmode_always_ena => CFG_TESTMODE_ON
) port map (
i_reset => ib_rst,
i_int_clkrf => ib_dip(0),
i_clkp => ib_sclk_p,
i_clkn => ib_sclk_n,
i_clk_adc => ib_clk_adc,
o_clk_bus => wClkBus,
o_clk_adc => wClkAdc,
o_locked => wPllLocked,
o_clk_50_quad => eth_refclk,
o_clk_50 => eth_i.rmii_clk
);
wSysReset <= ib_rst or not wPllLocked;
------------------------------------
--! @brief System Reset device instance.
rst0 : reset_global port map (
inSysReset => wSysReset,
inSysClk => wClkBus,
inPllLock => wPllLocked,
outReset => wReset
);
wNReset <= not wReset;
bus_nrst <= not (wReset or soft_rst);
--! @brief AXI4 controller.
ctrl0 : axictrl port map (
clk => wClkBus,
nrst => wNReset,
slvoi => axiso,
mstoi => aximo,
slvio => axisi,
mstio => aximi
);
--! @brief HostIO controller.
htif0 : htifctrl port map (
clk => wClkBus,
nrst => wNReset,
srcsi => htifo,
srcso => htifo_mux,
htifii => htifi,
htifio => htifi_grant
);
mst_cfg(CFG_NASTI_MASTER_CACHED) <= nasti_master_config_none;
aximo(CFG_NASTI_MASTER_CACHED) <= nasti_master_out_none;
mst_cfg(CFG_NASTI_MASTER_UNCACHED) <= nasti_master_config_none;
aximo(CFG_NASTI_MASTER_UNCACHED) <= nasti_master_out_none;
dsu_ena : if CFG_DSU_ENABLE generate
------------------------------------
--! @brief Debug Support Unit with access to the CSRs
--! @details Map address:
--! 0x80080000..0x8009ffff (128 KB total)
dsu0 : nasti_dsu generic map (
xindex => CFG_NASTI_SLAVE_DSU,
xaddr => 16#80080#,
xmask => 16#fffe0#,
htif_index => CFG_HTIF_SRC_DSU
) port map (
clk => wClkBus,
nrst => wNReset,
o_cfg => slv_cfg(CFG_NASTI_SLAVE_DSU),
i_axi => axisi,
o_axi => axiso(CFG_NASTI_SLAVE_DSU),
i_host => htifi_grant,
o_host => htifo(CFG_HTIF_SRC_DSU),
o_soft_reset => soft_rst
);
end generate;
dsu_dis : if not CFG_DSU_ENABLE generate
slv_cfg(CFG_NASTI_SLAVE_DSU) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_DSU) <= nasti_slave_out_none;
htifo(CFG_HTIF_SRC_DSU) <= host_out_none;
end generate;
axiso(CFG_NASTI_SLAVE_BOOTROM) <= nasti_slave_out_none;
slv_cfg(CFG_NASTI_SLAVE_BOOTROM) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_ROMIMAGE) <= nasti_slave_out_none;
slv_cfg(CFG_NASTI_SLAVE_ROMIMAGE) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_SRAM) <= nasti_slave_out_none;
slv_cfg(CFG_NASTI_SLAVE_SRAM) <= nasti_slave_config_none;
------------------------------------
--! @brief Controller of the LEDs, DIPs and GPIO with the AXI4 interface.
--! @details Map address:
--! 0x80000000..0x80000fff (4 KB total)
gpio0 : nasti_gpio generic map (
xindex => CFG_NASTI_SLAVE_GPIO,
xaddr => 16#80000#,
xmask => 16#fffff#
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_GPIO),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_GPIO),
i_dip => ib_dip,
o_led => o_led
);
------------------------------------
uart1i.cts <= uart1o.rts;
uart1i.rd <= i_uart1_rd;
--! @brief UART Controller with the AXI4 interface.
--! @details Map address:
--! 0x80001000..0x80001fff (4 KB total)
uart1 : nasti_uart generic map (
xindex => CFG_NASTI_SLAVE_UART1,
xaddr => 16#80001#,
xmask => 16#FFFFF#,
fifosz => 16
) port map (
nrst => wNReset,
clk => wClkbus,
cfg => slv_cfg(CFG_NASTI_SLAVE_UART1),
i_uart => uart1i,
o_uart => uart1o,
i_axi => axisi,
o_axi => axiso(CFG_NASTI_SLAVE_UART1),
o_irq => irq_pins(CFG_IRQ_UART1)
);
o_uart1_td <= uart1o.td;
------------------------------------
--! @brief Interrupt controller with the AXI4 interface.
--! @details Map address:
--! 0x80002000..0x80002fff (4 KB total)
irq0 : nasti_irqctrl generic map (
xindex => CFG_NASTI_SLAVE_IRQCTRL,
xaddr => 16#80002#,
xmask => 16#FFFFF#,
htif_index => CFG_HTIF_SRC_IRQCTRL
) port map (
clk => wClkBus,
nrst => bus_nrst,
i_irqs => irq_pins,
o_cfg => slv_cfg(CFG_NASTI_SLAVE_IRQCTRL),
i_axi => axisi,
o_axi => axiso(CFG_NASTI_SLAVE_IRQCTRL),
i_host => htifi_grant,
o_host => htifo(CFG_HTIF_SRC_IRQCTRL)
);
axiso(CFG_NASTI_SLAVE_ENGINE) <= nasti_slave_out_none;
slv_cfg(CFG_NASTI_SLAVE_ENGINE) <= nasti_slave_config_none;
irq_pins(CFG_IRQ_GNSSENGINE) <= '0';
axiso(CFG_NASTI_SLAVE_RFCTRL) <= nasti_slave_out_none;
slv_cfg(CFG_NASTI_SLAVE_RFCTRL) <= nasti_slave_config_none;
slv_cfg(CFG_NASTI_SLAVE_FSE_GPS) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_FSE_GPS) <= nasti_slave_out_none;
--! @brief Ethernet MAC with the AXI4 interface.
--! @details Map address:
--! 0x80040000..0x8007ffff (256 KB total)
--! EDCL IP: 192.168.0.51 = C0.A8.00.33
eth0_rmii_ena1 : if CFG_RMII = 1 generate
eth_i.rx_crs <= i_erx_dv;
end generate;
eth0_rmii_ena0 : if CFG_RMII = 0 generate -- plain MII
eth_i.rx_dv <= i_erx_dv;
eth_i.rx_crs <= i_erx_crs;
end generate;
eth0_ena : if CFG_ETHERNET_ENABLE generate
eth_i.tx_clk <= i_etx_clk;
eth_i.rx_clk <= i_erx_clk;
eth_i.rx_er <= i_erx_er;
eth_i.rx_col <= i_erx_col;
eth_i.rxd <= i_erxd;
eth_i.mdint <= i_emdint;
mac0 : grethaxi generic map (
xslvindex => CFG_NASTI_SLAVE_ETHMAC,
xmstindex => CFG_NASTI_MASTER_ETHMAC,
xaddr => 16#80040#,
xmask => 16#FFFC0#,
xirq => CFG_IRQ_ETHMAC,
memtech => CFG_MEMTECH,
mdcscaler => 50, --! System Bus clock in MHz
enable_mdio => 1,
fifosize => 16,
nsync => 1,
edcl => 1,
edclbufsz => 16,
macaddrh => 16#20789#,
macaddrl => 16#123#,
ipaddrh => 16#C0A8#,
ipaddrl => 16#0033#,
phyrstadr => 7,
enable_mdint => 1,
maxsize => 1518,
rmii => CFG_RMII
) port map (
rst => wNReset,
clk => wClkBus,
msti => aximi,
msto => aximo(CFG_NASTI_MASTER_ETHMAC),
mstcfg => mst_cfg(CFG_NASTI_MASTER_ETHMAC),
msto2 => open, -- EDCL separate access is disabled
mstcfg2 => open, -- EDCL separate access is disabled
slvi => axisi,
slvo => axiso(CFG_NASTI_SLAVE_ETHMAC),
slvcfg => slv_cfg(CFG_NASTI_SLAVE_ETHMAC),
ethi => eth_i,
etho => eth_o,
irq => irq_pins(CFG_IRQ_ETHMAC)
);
end generate;
--! Ethernet disabled
eth0_dis : if not CFG_ETHERNET_ENABLE generate
slv_cfg(CFG_NASTI_SLAVE_ETHMAC) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_ETHMAC) <= nasti_slave_out_none;
mst_cfg(CFG_NASTI_MASTER_ETHMAC) <= nasti_master_config_none;
aximo(CFG_NASTI_MASTER_ETHMAC) <= nasti_master_out_none;
irq_pins(CFG_IRQ_ETHMAC) <= '0';
eth_o <= eth_out_none;
end generate;
emdio_pad : iobuf_tech generic map(
CFG_PADTECH
) port map (
o => eth_i.mdio_i,
io => io_emdio,
i => eth_o.mdio_o,
t => eth_o.mdio_oe
);
o_egtx_clk <= eth_i.gtx_clk;--eth_i.tx_clk_90;
o_etxd <= eth_o.txd;
o_etx_en <= eth_o.tx_en;
o_etx_er <= eth_o.tx_er;
o_emdc <= eth_o.mdc;
o_erstn <= wNReset;
--! @brief Plug'n'Play controller of the current configuration with the
--! AXI4 interface.
--! @details Map address:
--! 0xfffff000..0xffffffff (4 KB total)
pnp0 : nasti_pnp generic map (
xindex => CFG_NASTI_SLAVE_PNP,
xaddr => 16#fffff#,
xmask => 16#fffff#,
tech => CFG_MEMTECH
) port map (
sys_clk => wClkBus,
adc_clk => wClkAdc,
nrst => wNReset,
mstcfg => mst_cfg,
slvcfg => slv_cfg,
cfg => slv_cfg(CFG_NASTI_SLAVE_PNP),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_PNP)
);
end arch_rocket_soc;
|
bsd-2-clause
|
026768d0e42c90120450615b3e15d522
| 0.600661 | 3.302995 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/cdd36762/hdl/vhdl/parity.vhd
| 4 | 10,694 |
-------------------------------------------------------------------------------
-- parity.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- parity.vhd
-- xor18.vhd
-- parity_recursive_LUT6.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity Parity is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
architecture IMP of Parity is
component MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end component MB_LUT6;
component MB_MUXF7 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF7;
component MB_MUXF8 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF8;
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_FPGA : if (C_TARGET /= RTL) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MB_MUXF8
generic map(
C_TARGET => C_TARGET)
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_FPGA;
Using_RTL: if ( C_TARGET = RTL ) generate
begin
Res <= ParityGen(InA);
end generate Using_RTL;
end architecture IMP;
|
gpl-3.0
|
f4701362efd3ed20eb0337a85b746fdf
| 0.475033 | 4.069254 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/addr_counter_mux.vhd
| 4 | 35,347 |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: addr_counter_mux.vhd-- Description:
-- This file contains the addr_counter and mux for the EMC
-- design.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 02/01/08 First Version
-- ^^^^^^^^^^
-- This file is same as in version v3_01_c - no change in the logic of this
-- module. Deleted the history from version v3_01_c.
-- ~~~~~~
-- NSK 02/12/08 Updated
-- ^^^^^^^^
-- Removed the unused part of code (not supporting C_IPIF_DWIDTH = 64): -
-- 1. Deleted the generate block lebelled "CYCLE_END_CNT_64_GEN".
-- 2. In the process "ADDR_SUFFIX_PROCESS" deleted the part of code as
-- C_ADDR_OFFSET = 3 is valid only when C_IPIF_DWIDTH = 64 is supported.
-- ~~~~~~~~
-- NSK 05/08/08 version v3_00_a
-- ^^^^^^^^
-- 1. This file is same as in version v3_02_a.
-- 2. Upgraded to version v3.00.a to have proper versioning to fix CR #472164.
-- 3. No change in design.
--
-- KSB 05/08/08 version v4_00_a
-- 1. Modified for Page mdoe read
-- 2. Modified for 64 Bit memory address align
-- ~~~~~~~~
-- KSB 22/05/10 version v5_00_a
-- 1. Modified for AXI EMC, PSRAM, Byte parity Memory Support
-- 2. Modified for AXI Slave burst interface
-- ~~~~~~~~
-- SK 02/11/11 version v5_02_a
-- ^^^^^^^^
-- 1. Fixed CR#595758 and CR#606038
-- ~~~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- vcomponents package of the unisim library is used for the FDR and FDCE
-- component declaration
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library emc_common_v3_0;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_ADDR_CNTR_WIDTH -- Width of address counter
-- C_IPIF_AWIDTH -- Width of IPIF address bus
-- C_IPIF_DWIDTH -- Width of IPIF data bus
-- C_ADDR_OFFSET -- Unused lower address bits based on data
-- width
-- C_GLOBAL_DATAWIDTH_MATCH-- Indicates whether any memory bank is
-- supporting data width matching
--
-- Definition of Ports:
-- Bus2IP_Addr -- Processor address bus
-- Bus2IP_BE -- Processor bus byte enables
-- Address_strobe -- Address strobe signal
-- Data_strobe -- Data and BEs strobe signal
-- Mem_width_bytes -- Width in bytes of currently addressed
-- memory bank
-- Datawidth_match -- Data width matching for currently addressed
-- memory bank
-- Addr_cnt_ce -- Address counter count enable
-- Addr_cnt_rst -- Address counter reset
-- Addr_cnt -- Address count
-- Cycle_cnt_ld -- Cycle end counter count load
-- Cycle_cnt_en -- Cycle end counter count enable
-- Cycle_end -- Current cycle end flag
-- Mem_addr -- Address out to memory
-- Mem_Ben -- Memory byte enables
-- Clk -- System Clock
-- Rst -- System Reset
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity addr_counter_mux is
generic(
C_ADDR_CNTR_WIDTH : integer range 1 to 5;
C_IPIF_AWIDTH : integer;
C_IPIF_DWIDTH : integer;
C_ADDR_OFFSET : integer range 0 to 4;
PARITY_TYPE_MEMORY : integer range 0 to 1 := 1;
C_GLOBAL_DATAWIDTH_MATCH : integer range 0 to 1
);
port(
Clk : in std_logic;
Rst : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_AWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
Address_strobe : in std_logic; -- 07-12-2012
--Data_strobe : in std_logic;09-12-2012
Bus2Mem_CS : in std_logic;
Mem_width_bytes : in std_logic_vector(0 to 3);
Datawidth_match : in std_logic;
Addr_cnt_ce : in std_logic;
Addr_cnt_rst : in std_logic;
Addr_cnt : out std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
Addr_align : out std_logic;
Cycle_cnt_ld : in std_logic;
Cycle_cnt_en : in std_logic;
Cycle_End : out std_logic;
CS_par_addr : in std_logic;
Mem_addr : out std_logic_vector(0 to C_IPIF_AWIDTH-1);
par_error_addr : out std_logic_vector(0 to C_IPIF_AWIDTH-1);
Mem_Ben : out std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
Bus2IP_RdReq : in std_logic;
address_strobe_c : in std_logic;
be_strobe_c : in std_logic;
data_strobe_c : in std_logic;
Cre_reg_en : in std_logic; -- 1/16/2013
psram_page_mode : in std_logic;
axi_trans_size_reg : in std_logic_vector(1 downto 0)
);
end entity addr_counter_mux;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of addr_counter_mux is
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-- reset values
constant ZERO_CYCLE_CNT : std_logic_vector(0 to (log2(C_IPIF_DWIDTH/8)-1))
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
signal addr_cnt_i : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal addr_suffix : std_logic_vector(0 to C_ADDR_OFFSET-1)
:= (others => '0');
signal addr_cnt_val : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal cycle_cnt : std_logic_vector(0 to (log2(C_IPIF_DWIDTH/8)-1));
signal cycle_end_cnt : std_logic_vector(0 to (log2(C_IPIF_DWIDTH/8)-1));
signal int_addr : std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal Mem_Ben_i : std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
signal mem_addr_cmb : std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal addr_cnt_cmb : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal addr_align_32_64 : std_logic;
signal reduced_low_be : std_logic;
signal reduced_high_be : std_logic;
signal reduced_16_0_be : std_logic;
signal reduced_16_1_be : std_logic;
signal reduced_16_2_be : std_logic;
signal reduced_16_3_be : std_logic;
signal par_error_addr_reg: std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal Cycle_End_reg : std_logic;
signal Cycle_cnt_en_int : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Store the address coming from bus as address ack and data ack are issued
-- early to make burst appear as continuous on memory side.
---------------------------------------------------------------------------
Mem_Ben <= Mem_Ben_i;
ADDRESS_STORE_GEN: for i in 0 to C_IPIF_AWIDTH - 1 generate
begin
ADDRESS_REG: FDRE
port map (
Q => int_addr(i), --[out]
C => Clk, --[in]
CE => address_strobe_c,--Data_strobe, --[in]
D => Bus2IP_Addr(i), --[in]
R => Rst --[in]
);
end generate ADDRESS_STORE_GEN;
---------------------------------------------------------------------------
-- Store the Byte Enables coming from bus as address ack and data ack are
-- issued early to make burst appear as continuous one on memory side.
---------------------------------------------------------------------------
BEN_STORE_GEN: for i in 0 to C_IPIF_DWIDTH/8-1 generate
begin
BEN_REG: FDRE
port map (
Q => Mem_Ben_i(i), --[out]
C => Clk, --[in]
CE => be_strobe_c,--Data_strobe, --[in]
D => Bus2IP_BE(i), --[in]
R => Rst --[in]
);
end generate BEN_STORE_GEN;
---------------------------------------------------------------------------
-- Address and address count generation logic.
---------------------------------------------------------------------------
Mem_addr <= mem_addr_cmb ;
Addr_cnt <= addr_cnt_cmb;
PARITY_ERROR_GEN: if PARITY_TYPE_MEMORY = 1 generate
par_error_addr <= Bus2IP_Addr when CS_par_addr='1'
else
par_error_addr_reg;
PARITY_ERROR_PROCESS : process(Clk)
begin
if(Clk'EVENT and Clk = '1') then
if(Rst = '1')then
par_error_addr_reg <= (others=>'0');
elsif CS_par_addr = '1' then
par_error_addr_reg <= Bus2IP_Addr;
end if;
end if;
end process PARITY_ERROR_PROCESS;
end generate PARITY_ERROR_GEN;
---------------------------------------------------------------------------
---------------------------- NO DATAWIDTH MATCHING ------------------------
-- If datawidth matching has not been turned on for any memory banks,
-- simplify the logic.
---------------------------------------------------------------------------
NO_DATAWIDTH_MATCH_GEN: if C_GLOBAL_DATAWIDTH_MATCH = 0 generate
begin
addr_cnt_cmb <= (others => '0');
mem_addr_cmb <= int_addr;
Cycle_End <= '1';
end generate NO_DATAWIDTH_MATCH_GEN;
---------------------------------------------------------------------------
---------------------------- DATAWIDTH MATCHING ---------------------------
-- If datawidth matching has been turned on at least 1 memory bank,
-- implement the data width matching logic. Note that an individual bank
-- with datawidth matching turned off will still use this logic.
---------------------------------------------------------------------------
DATAWIDTH_MATCH_GEN: if C_GLOBAL_DATAWIDTH_MATCH = 1 generate
begin
-----------------------------------------------------------------------
-- Assign output signals
-----------------------------------------------------------------------
addr_cnt_cmb <= (others => '0') when Datawidth_match = '0' else
addr_cnt_i;
ADDR_CNT_PROCESS : process(Clk)
begin
if(Clk'EVENT and Clk = '1') then
if(Rst = '1')then
addr_cnt_i <= (others=>'0');
elsif Addr_cnt_rst = '1' then
if(Cre_reg_en = '0') then
addr_cnt_i <= addr_cnt_val;
else
addr_cnt_i <= (others => '0');
end if;
elsif Addr_cnt_ce = '1' then
addr_cnt_i <= addr_cnt_i + 1;
end if;
end if;
end process ADDR_CNT_PROCESS;
-----------------------------------------------------------------------
-- Create cycle termination logic for C_IPIF_DWIDTH = 64.
-----------------------------------------------------------------------
CYCLE_END_CNT_64_GEN : if C_IPIF_DWIDTH = 64 generate
begin
mem_addr_cmb <= int_addr when Datawidth_match = '0' or Cre_reg_en = '1' else
int_addr(0 to C_IPIF_AWIDTH-C_ADDR_OFFSET-1)
& addr_suffix;
Addr_align <= '0';
reduced_high_be <= or_reduce (Bus2IP_BE(0 to 3));
reduced_low_be <= or_reduce (Bus2IP_BE(4 to 7));
reduced_16_0_be <= or_reduce (Bus2IP_BE(6 to 7));
reduced_16_1_be <= or_reduce (Bus2IP_BE(4 to 5));
reduced_16_2_be <= or_reduce (Bus2IP_BE(2 to 3));
reduced_16_3_be <= or_reduce (Bus2IP_BE(0 to 1));
---------------------------------------------------------------------
-- Create the address suffix.
---------------------------------------------------------------------
ADDR_SUFFIX_PROCESS_64: process(Mem_width_bytes,
Bus2IP_Addr,
addr_cnt_i)
begin
addr_suffix <= (others => '0');
addr_cnt_val<= (others => '0');
case Mem_width_bytes is
when "0001" =>
addr_suffix <= addr_cnt_i;
addr_cnt_val <= Bus2IP_Addr(C_IPIF_AWIDTH-C_ADDR_OFFSET
to C_IPIF_AWIDTH - 1);
when "0010" =>
addr_suffix <= addr_cnt_i(1 to C_ADDR_CNTR_WIDTH-1)
& '0';
addr_cnt_val <= '0' & Bus2IP_Addr(C_IPIF_AWIDTH-
C_ADDR_OFFSET to C_IPIF_AWIDTH - 2);
when "0100" =>
addr_suffix <= addr_cnt_i(2 to C_ADDR_CNTR_WIDTH-1)
& "00";
addr_cnt_val<= "00" & Bus2IP_Addr(C_IPIF_AWIDTH-
C_ADDR_OFFSET
to C_IPIF_AWIDTH - 3);
when "1000" =>
addr_suffix <= (others => '0');
addr_cnt_val<= (others => '0');
-- coverage off
when others=>
addr_suffix <= (others => '0');
addr_cnt_val<= (others => '0');
-- coverage on
end case;
end process ADDR_SUFFIX_PROCESS_64;
---------------------------------------------------------------------
-- Create the cycle_end_cnt
---------------------------------------------------------------------
CYCLE_END_CNT_PROCESS_64 : process(Mem_width_bytes,
reduced_low_be,
reduced_high_be,
reduced_16_0_be,
reduced_16_1_be,
reduced_16_2_be,
reduced_16_3_be,
Bus2IP_BE,
Bus2IP_RdReq,
Cycle_cnt_en,
axi_trans_size_reg)
variable Mem_width_bytes_rd_req : std_logic_vector(4 downto 0);
begin
Mem_width_bytes_rd_req := Mem_width_bytes & Bus2IP_RdReq ;
case Mem_width_bytes_rd_req is
when "00010" => -- 8 bit memory write access
Cycle_cnt_en_int <= Cycle_cnt_en;
if (Bus2IP_BE(0) = '1' and Bus2IP_BE(7)='1')then
cycle_end_cnt <= "111";
elsif (
(Bus2IP_BE(0) = '1' and Bus2IP_BE(6)='1') or
(Bus2IP_BE(1) = '1' and Bus2IP_BE(7)='1'))
then
cycle_end_cnt <= "110";
elsif (
(Bus2IP_BE(2) = '1' and Bus2IP_BE(7)='1') or
(Bus2IP_BE(1) = '1' and Bus2IP_BE(6)='1') or
(Bus2IP_BE(0) = '1' and Bus2IP_BE(5)='1')) then
cycle_end_cnt <= "101";
elsif (
(Bus2IP_BE(3) = '1' and Bus2IP_BE(7)='1') or
(Bus2IP_BE(2) = '1' and Bus2IP_BE(6)='1') or
(Bus2IP_BE(1) = '1' and Bus2IP_BE(5)='1') or
(Bus2IP_BE(0) = '1' and Bus2IP_BE(4)='1'))
then
cycle_end_cnt <= "100";
elsif (
(Bus2IP_BE(4) = '1' and Bus2IP_BE(7)='1') or
(Bus2IP_BE(3) = '1' and Bus2IP_BE(6)='1') or
(Bus2IP_BE(2) = '1' and Bus2IP_BE(5)='1') or
(Bus2IP_BE(1) = '1' and Bus2IP_BE(4)='1') or
(Bus2IP_BE(0) = '1' and Bus2IP_BE(3)='1'))
then
cycle_end_cnt <= "011";
elsif (
(Bus2IP_BE(5) = '1' and Bus2IP_BE(7)='1') or
(Bus2IP_BE(4) = '1' and Bus2IP_BE(6)='1') or
(Bus2IP_BE(3) = '1' and Bus2IP_BE(5)='1') or
(Bus2IP_BE(2) = '1' and Bus2IP_BE(4)='1') or
(Bus2IP_BE(1) = '1' and Bus2IP_BE(3)='1') or
(Bus2IP_BE(0) = '1' and Bus2IP_BE(2)='1'))
then
cycle_end_cnt <= "010";
elsif (Bus2IP_BE = "00000011" or Bus2IP_BE = "00001100" or
Bus2IP_BE = "00110000" or Bus2IP_BE = "11000000" or
Bus2IP_BE = "01100000" or Bus2IP_BE = "00011000" or
Bus2IP_BE = "00000110") then
cycle_end_cnt <= "001";
else
cycle_end_cnt <= "000";
end if;
when "00100" => -- 16 bit memory write access
Cycle_cnt_en_int <= Cycle_cnt_en;
if (
(reduced_16_0_be = '1' and reduced_16_3_be = '1')) then
cycle_end_cnt <= "011";
elsif (
(reduced_16_0_be = '1' and reduced_16_2_be = '1') or
(reduced_16_1_be = '1' and reduced_16_3_be = '1'))
then
cycle_end_cnt <= "010";
elsif (
(reduced_16_0_be = '1' and reduced_16_1_be = '1') or
(reduced_16_1_be = '1' and reduced_16_2_be = '1') or
(reduced_16_2_be = '1' and reduced_16_3_be = '1'))
then
cycle_end_cnt <= "001";
else
cycle_end_cnt <= "000";
end if;
when "01000" => -- 32 bit memory write access
Cycle_cnt_en_int <= Cycle_cnt_en;
if (
(reduced_low_be = '1' and reduced_high_be = '1')) then
cycle_end_cnt <= "001";
else
cycle_end_cnt <= "000";
end if;
when "00011" => -- 8 bit memory read access
Cycle_cnt_en_int <= Cycle_cnt_en and or_reduce(axi_trans_size_reg);
if (axi_trans_size_reg = "01") then -- size Half word
cycle_end_cnt <= "001";
elsif(axi_trans_size_reg = "10")then -- size word
cycle_end_cnt <= "011";
elsif(axi_trans_size_reg = "11")then -- size double word
cycle_end_cnt <= "111";
else -- size byte - Default
cycle_end_cnt <= "000";
end if;
when "00101" => -- 16 bit memory read access - can be 16 bit, 32 bit or 64 bit
Cycle_cnt_en_int <= Cycle_cnt_en and axi_trans_size_reg(1);
if (axi_trans_size_reg = "00" or
axi_trans_size_reg = "01") then -- Byte or HW word
cycle_end_cnt <= "000";
elsif (axi_trans_size_reg = "10") then -- Word
cycle_end_cnt <= "001";
else --if (axi_trans_size_reg = "11") then -- DWord
cycle_end_cnt <= "011";
end if;
when "01001" => -- 32 bit memory read access - can be 16 bit, 32 bit or 64 bit
Cycle_cnt_en_int <= Cycle_cnt_en and axi_trans_size_reg(1);
if (axi_trans_size_reg = "00") then -- Byte word
cycle_end_cnt <= "000";
elsif (axi_trans_size_reg = "01") then -- HW word
cycle_end_cnt <= "000";
elsif (axi_trans_size_reg = "10") then -- Word
cycle_end_cnt <= "000";
else -- if (axi_trans_size_reg = "11") then -- DWord
cycle_end_cnt <= "001";
end if;
-- coverage off
when others =>
Cycle_cnt_en_int <= '0'; -- 1/21/2013
cycle_end_cnt <= "000" ;
-- coverage on
end case;
end process CYCLE_END_CNT_PROCESS_64;
end generate CYCLE_END_CNT_64_GEN;
-----------------------------------------------------------------------
-- Create cycle termination logic for C_IPIF_DWIDTH = 32.
-----------------------------------------------------------------------
CYCLE_END_CNT_32_GEN : if C_IPIF_DWIDTH = 32 generate
begin
reduced_16_1_be <= or_reduce (Bus2IP_BE(2 to 3));
reduced_16_0_be <= or_reduce (Bus2IP_BE(0 to 1));
-------------------------------------------------------------------
-- Create the address suffix.
-------------------------------------------------------------------
ADDR_SUFFIX_PROCESS_32: process(Mem_width_bytes,
Bus2IP_Addr,
addr_cnt_i)
begin
--addr_suffix <= (others => '0');
--addr_cnt_val <= (others => '0');
case Mem_width_bytes is
when "0001" =>
addr_suffix <= addr_cnt_i;
addr_cnt_val <= Bus2IP_Addr(C_IPIF_AWIDTH-C_ADDR_OFFSET
to C_IPIF_AWIDTH - 1);
when "0010" =>
addr_suffix <= addr_cnt_i(1 to C_ADDR_CNTR_WIDTH-1) & '0';
addr_cnt_val <= '0' & Bus2IP_Addr(C_IPIF_AWIDTH-
C_ADDR_OFFSET to C_IPIF_AWIDTH - 2);
-- coverage off
when others=>
addr_suffix <= (others => '0');
addr_cnt_val <= (others => '0');
-- coverage on
end case;
end process ADDR_SUFFIX_PROCESS_32;
---------------------------------------------------------------------
-- Create the cycle_end_cnt
---------------------------------------------------------------------
MEM_ADDR_PROCESS: process(int_addr, Datawidth_match, addr_suffix, Cre_reg_en)
begin
if (Datawidth_match = '0') or (Cre_reg_en = '1')then
mem_addr_cmb <= int_addr;
else
mem_addr_cmb <= int_addr(0 to C_IPIF_AWIDTH-
C_ADDR_OFFSET-1) & addr_suffix ;
end if;
end process MEM_ADDR_PROCESS;
---------------------------------------------------------------------
-- Create the cycle_end_cnt
---------------------------------------------------------------------
CYCLE_END_CNT_PROCESS_32 : process(Mem_width_bytes,
reduced_16_1_be,
reduced_16_0_be,
Bus2IP_BE,
Cycle_cnt_en,
Bus2IP_RdReq,
axi_trans_size_reg)
variable Mem_width_bytes_rd_req : std_logic_vector(4 downto 0);
begin
Mem_width_bytes_rd_req := Mem_width_bytes & Bus2IP_RdReq ;
case Mem_width_bytes_rd_req is
when "00010" => -- 8 bit memory width write
Cycle_cnt_en_int <= Cycle_cnt_en; -- 1/18/2013
if
(Bus2IP_BE(0) = '1' and Bus2IP_BE(3)='1')then
cycle_end_cnt <= "11";
elsif (
(Bus2IP_BE(0) = '1' and Bus2IP_BE(2)='1') or
(Bus2IP_BE(1) = '1' and Bus2IP_BE(3)='1')) then
cycle_end_cnt <= "10";
elsif (Bus2IP_BE = "0011" or Bus2IP_BE = "1100" or
Bus2IP_BE = "0110") then
cycle_end_cnt <= "01";
else
cycle_end_cnt <= "00";
end if;
when "00100" => -- 16 bit memory width write
Cycle_cnt_en_int <= Cycle_cnt_en; -- 1/18/2013
if (
(reduced_16_0_be = '1' and reduced_16_1_be= '1'))
then
cycle_end_cnt <= "01";
else
cycle_end_cnt <= "00";
end if;
when "00011" => -- 8 bit memory read access
Cycle_cnt_en_int <= Cycle_cnt_en and or_reduce(axi_trans_size_reg);
if (axi_trans_size_reg = "01") then -- size Half word
cycle_end_cnt <= "01";
elsif(axi_trans_size_reg = "10")then -- size word
cycle_end_cnt <= "11";
else -- size byte - Default
cycle_end_cnt <= "00";
end if;
when "00101" => -- 16 bit memory read access - can be 8 bit, 16 bit, 32 bit
Cycle_cnt_en_int <= Cycle_cnt_en and axi_trans_size_reg(1);
--if (axi_trans_size_reg = "00" or
-- axi_trans_size_reg = "01") then -- Byte or HW word
-- cycle_end_cnt <= "00";
--elsif (axi_trans_size_reg = "10") then -- Word
-- cycle_end_cnt <= "01";
--end if;
if(axi_trans_size_reg = "10") then -- Word
cycle_end_cnt <= "01";
else
cycle_end_cnt <= "00";
end if;
when "01001" => -- 32 bit memory read access - can be 8 bit, 16 bit, 32 bit
Cycle_cnt_en_int <= Cycle_cnt_en and axi_trans_size_reg(1);
if (axi_trans_size_reg = "00") then -- Byte word
cycle_end_cnt <= "00";
elsif (axi_trans_size_reg = "01") then -- HW word
cycle_end_cnt <= "00";
elsif (axi_trans_size_reg = "10") then -- Word
cycle_end_cnt <= "00";
else -- if (axi_trans_size_reg = "11") then -- DWord
cycle_end_cnt <= "01";
end if;
-- coverage off
when others =>
Cycle_cnt_en_int <= '0'; -- 1/21/2013
cycle_end_cnt <= "00" ;
-- coverage on
end case;
end process CYCLE_END_CNT_PROCESS_32;
end generate CYCLE_END_CNT_32_GEN;
-----------------------------------------------------------------------
-- Instantiate the cycle_end_counter.
-----------------------------------------------------------------------
CYCLE_END_CNTR_I:entity emc_common_v3_0.ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_ADDR_CNTR_WIDTH,
C_RESET_VALUE => ZERO_CYCLE_CNT,
C_LD_WIDTH => C_ADDR_CNTR_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map (
CK => Clk,
RST => Rst,
Q => cycle_cnt,
LD => cycle_end_cnt,
AD => "1",
LOAD => Cycle_cnt_ld, -- Cycle_cnt_ld,
OP => Cycle_cnt_en_int
);
Cycle_End <= '1' when (conv_integer(cycle_cnt) = 0)
-- else
-- '1' when psram_page_mode = '1'
else
'0';
end generate DATAWIDTH_MATCH_GEN;
end imp;
-------------------------------------------------------------------------------
-- End of File addr_counter_mux.vhd.
-------------------------------------------------------------------------------
|
gpl-3.0
|
df038430a9f25b14b0932a82180f7c6d
| 0.411944 | 4.412859 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/ipic_if.vhd
| 4 | 25,987 |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: ipic_if.vhd
-- Description: IPIC Interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 02/01/08 First Version
-- ^^^^^^^^^^
-- This file is same as in version v3_01_c - no change in the logic of this
-- module. Deleted the history from version v3_01_c.
-- ~~~~~~
-- NSK 05/08/08 version v3_00_a
-- ^^^^^^^^
-- 1. This file is same as in version v3_02_a.
-- 2. Upgraded to version v3.00.a to have proper versioning to fix CR #472164.
-- 3. No change in design.
-- ~~~~~~~~
-- ^^^^^^^^
-- KSB 08/08/08 version v4_00_a
-- 1. This file is same as in version v3_00_a.
-- 2. Upgraded to version v4.00.a
-- ~~~~~~~~
-- SK 10/07/10
-- ^^^^^^^^
-- 1. Added "clear_pend_rdreq <= '1' when ((burst_cnt_i = 0) and (Bus2IP_Burst = '0') and
--(Mem2Bus_RdAddrAck = '1')) or bus2Mem_CS_i = '0'
-- else
--'0' ;
-- 2. condition for "clear_pend_wrreq". This is similar to "clear_pend_rdreq" .
-- ~~~~~~~~
-- SK 25/10/10
-- ^^^^^^^^
-- 1. Registered IP2bus_RdAck and IP2Bus_Data signals.
-- ~~~~~~~~
-- SK 24/11/10
-- ^^^^^^^^
-- 1. Added "Bus2IP_RdReq_emc = '0'" signal to reset the RDREQ_PROCESS.
-- ~~~~~~~~
-- SK 02/11/11 version v5_02_a
-- ^^^^^^^^
-- 1. Fixed CR#595758 and CR#606038
-- ~~~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
library emc_common_v3_0;
-------------------------------------------------------------------------------
-- vcomponents package of the unisim library is used for the FDR component
-- declaration
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BANKS_MEM -- Number of Memory Banks
-- C_IPIF_DWIDTH -- Processor Data Bus Width
--
-- Definition of Ports:
-- Bus2IP_RNW -- Processor read not write (1=Read, 0=Write)
-- Bus2IP_Mem_CS -- Memory Channel Chip Select
-- Mem2Bus_RdAddrAck -- Memory Read Cycle Address Acknowledge
-- Mem2Bus_WrAddrAck -- Memory Write Cycle Address Acknowledge
-- Mem2Bus_RdAck -- Memory Read Cycle Acknowledge
-- Mem2Bus_WrAck -- Memory Write Cycle Acknowledge
-- Mem2Bus_Data -- Memory Read Data
-- Bus2Mem_RdReq -- Read request was seen by mem_state_machine
-- Bus2Mem_WrReq -- Write request was seen by mem_state_machine
-- Bus2Mem_CS -- Memory is being accessed
-- IP2Bus_Data -- Read data from memory device or register
-- IP2Bus_errAck -- Error acknowledge
-- IP2Bus_retry -- Retry indicator
-- IP2Bus_toutSup -- Suppress watch dog timer
-- IP2Bus_RdAck -- Read acknowledge
-- IP2Bus_WrAck -- Write acknowledge
-- IP2Bus_AddrAck -- Address acknowledge
-- Burst_length -- Count of current burst length
-- Transaction_done -- Operation complete indication for current
-- -- transaction
-- Bus2IP_Clk -- System clock
-- Bus2IP_Reset -- System Reset
-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------
entity ipic_if is
generic (
C_NUM_BANKS_MEM : integer := 2;
C_IPIF_DWIDTH : integer := 64
);
port (
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_RNW : in std_logic;
Bus2IP_Mem_CS : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem2Bus_RdAddrAck : in std_logic;
Mem2Bus_WrAddrAck : in std_logic;
Mem2Bus_RdAck : in std_logic;
Mem2Bus_WrAck : in std_logic;
Bus2IP_WrReq : in std_logic;
Bus2IP_RdReq : in std_logic;
Mem2Bus_Data : in std_logic_vector(0 to C_IPIF_DWIDTH - 1);
Bus2IP_Burst : in std_logic;
Bus2IP_RdReq_emc : in std_logic;
Bus2IP_WrReq_emc : in std_logic;
Bus2Mem_CS : out std_logic;
Bus2Mem_RdReq : out std_logic;
Bus2Mem_WrReq : out std_logic;
Parity_err : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_IPIF_DWIDTH - 1);
IP2Bus_errAck : out std_logic;
IP2Bus_retry : out std_logic;
IP2Bus_toutSup : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_AddrAck : out std_logic;
Type_of_xfer : in std_logic;
Burst_length : in std_logic_vector(0 to 7);
Transaction_done : in std_logic;
single_transaction : in std_logic ;
last_burst_cnt : out std_logic;
pr_state_wait_temp_cmb : in std_logic;
synch_mem : in std_logic; -- 10-12-2012
mem_width_bytes : in std_logic_vector(0 to 3);
stop_oen : out std_logic;
axi_trans_size_reg : in std_logic_vector(1 downto 0); -- 1/3/2013
Linear_flash_brst_rd_flag : in std_logic -- 1/28/2013
);
end entity ipic_if;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of ipic_if is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declaration
-------------------------------------------------------------------------------
constant BURST_CNT_WIDTH : integer := 8;
constant ZERO_CNT : std_logic_vector(0 to BURST_CNT_WIDTH -1)
:= (others=>'0');
-------------------------------------------------------------------------------
-- Signal Declaration
-------------------------------------------------------------------------------
signal bus2mem_cs_i : std_logic;
signal burst_cnt_en : std_logic;
signal burst_cnt_ld_cmb : std_logic;
signal pend_wrreq : std_logic;
signal set_pend_wrreq : std_logic;
signal clear_pend_wrreq : std_logic;
signal pend_rdreq : std_logic;
signal set_pend_rdreq : std_logic;
signal clear_pend_rdreq : std_logic;
signal burst_cnt_i : std_logic_vector(0 to BURST_CNT_WIDTH - 1);
signal int_wrreq : std_logic;
signal int_rdreq : std_logic;
---remove this signal once fix is made to ipif
signal burst_length_i :std_logic_vector(0 to BURST_CNT_WIDTH - 1);
signal bus2ip_mem_cs_reg :std_logic;--_vector(0 to C_NUM_BANKS_MEM-1);
signal IP2Bus_AddrAck_d1 :std_logic;
signal burst_rst :std_logic;
signal stop_init_rd :std_logic;
signal reload_address :std_logic;
signal reload_req :std_logic;
signal IP2Bus_WrAck_i :std_logic;
signal IP2Bus_AddrAck_i :std_logic;
signal IP2Bus_RdAck_i :std_logic;
signal reset_fifo :std_logic;
signal burst_cnt_i_rdack : std_logic_vector(0 to BURST_CNT_WIDTH - 1);
signal diff_addr_rd_ack : std_logic;
signal burst_cnt_en_rdack: std_logic;
signal first_rd_ack : std_logic;
signal rd_ack_d1 : std_logic;
signal Bus2Mem_RdReq_int : std_logic;
signal bus2Mem_CS_reduce_reg : std_logic;
signal pr_state_wait_temp_reg: std_logic;
signal rd_cnt : std_logic_vector(3 downto 0);
signal stop_oen_int : std_logic;
-- signal stop_oen : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
---------------------------------------------------------------------------
-- IPIC
---------------------------------------------------------------------------
burst_length_i <= Burst_length(0 to BURST_CNT_WIDTH - 1);
bus2Mem_CS_i <= or_reduce(Bus2IP_Mem_CS); -- (bus2IP_Mem_CS_reg); -- 1/3/2013
Bus2Mem_CS <= bus2Mem_CS_i;
IP2Bus_errAck <= (Parity_err or (not Type_of_xfer)) and
bus2Mem_CS_i;
IP2Bus_retry <= '0';
IP2Bus_toutSup <= bus2Mem_CS_i;
--IP2Bus_Data <= Mem2Bus_Data;
int_wrreq <= Bus2IP_WrReq and bus2Mem_CS_i;
int_rdreq <= Bus2IP_RdReq and bus2Mem_CS_i;
---------------------------------------------------------------------------
-- Register the Bus2IP_Mem_CS
---------------------------------------------------------------------------
CS_REG_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
if(Bus2IP_Reset = '1')then
bus2IP_Mem_CS_reg <= '0';--(others=>'0');
pr_state_wait_temp_reg <= '0';
else
bus2IP_Mem_CS_reg <= or_reduce(Bus2IP_Mem_CS);
pr_state_wait_temp_reg <= pr_state_wait_temp_cmb;
end if;
end if;
end process CS_REG_PROCESS;
ONE_HOT_CS_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
if(Bus2IP_Reset = '1')then
bus2Mem_CS_reduce_reg <= '0';
else
bus2Mem_CS_reduce_reg <= bus2Mem_CS_i;
end if;
end if;
end process ONE_HOT_CS_PROCESS;
---------------------------------------------------------------------------
-- Register the acks signals
---------------------------------------------------------------------------
ACK_REG_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
if(Bus2IP_Reset = '1')then
IP2Bus_Data <= (others => '0');
IP2Bus_RdAck <= '0';
else
IP2Bus_Data <= Mem2Bus_Data;
IP2Bus_RdAck <= Mem2Bus_RdAck and (Bus2Mem_RdReq_int or
single_transaction or
Linear_flash_brst_rd_flag);
end if;
end if;
end process ACK_REG_PROCESS;
IP2Bus_WrAck <= Mem2Bus_WrAck;
IP2Bus_AddrAck <= (Mem2Bus_RdAddrAck or Mem2Bus_WrAddrAck) and
(Bus2IP_WrReq or Bus2IP_RdReq);
---------------------------------------------------------------------------
-- Burst length counter instantiation
---------------------------------------------------------------------------
BURST_CNT: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => BURST_CNT_WIDTH,
C_RESET_VALUE => ZERO_CNT,
C_LD_WIDTH => BURST_CNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Bus2IP_Clk,
RST => reset_fifo,
Q => burst_cnt_i,
LD => burst_length_i,
AD => "1",
LOAD => burst_cnt_ld_cmb,
OP => burst_cnt_en
);
---------------------------------------------------------------------------
-- Burst length counter instantiation -- For Read Ack
---------------------------------------------------------------------------
BURST_CNT_RDACK: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => BURST_CNT_WIDTH,
C_RESET_VALUE => ZERO_CNT,
C_LD_WIDTH => BURST_CNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Bus2IP_Clk,
RST => reset_fifo,
Q => burst_cnt_i_rdack,
LD => burst_length_i,
AD => "1",
LOAD => burst_cnt_ld_cmb,
OP => burst_cnt_en_rdack
);
burst_cnt_en_rdack <= (diff_addr_rd_ack and Mem2Bus_RdAck);
diff_addr_rd_ack <= or_reduce(burst_cnt_i xor burst_cnt_i_rdack);
---------------------------------------------------------------------------
-- Burst length counter control signals
---------------------------------------------------------------------------
burst_cnt_en <= (Mem2Bus_RdAddrAck or Mem2Bus_WrAddrAck) and
(Bus2IP_WrReq or Bus2IP_RdReq);
burst_cnt_ld_cmb <= not(bus2Mem_CS_reduce_reg) and bus2Mem_CS_i;
reset_fifo <= Bus2IP_Reset or (not bus2Mem_CS_i);
last_burst_cnt <= not (or_reduce(burst_cnt_i));
---------------------------------------------------------------------------
-- Generation of pend_wrreq
---------------------------------------------------------------------------
set_pend_wrreq <= (not pend_wrreq) and Transaction_done and int_wrreq;
clear_pend_wrreq <= '1' when ((burst_cnt_i = 0) and (Bus2IP_Burst = '0') and
(Mem2Bus_WrAddrAck = '1'))or bus2Mem_CS_i = '0' else
'0' ;
WRREQ_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
if(Bus2IP_Reset = '1')then
pend_wrreq <= '0';
elsif set_pend_wrreq ='1' then
pend_wrreq <= '1';
--elsif clear_pend_wrreq = '1' then
elsif(Bus2IP_Burst = '0' and (Mem2Bus_WrAddrAck = '1')) or
(bus2Mem_CS_i = '0') then
pend_wrreq <= '0';
end if;
end if;
end process WRREQ_PROCESS;
Bus2Mem_WrReq <= (pend_wrreq and Bus2IP_WrReq);
---------------------------------------------------------------------------
-- Generation of pend_rdreq
---------------------------------------------------------------------------
set_pend_rdreq <= (not pend_rdreq) and Transaction_done
and int_rdreq;
clear_pend_rdreq <= '1' when ((burst_cnt_i = 0) and (Bus2IP_Burst = '0') and
(Mem2Bus_RdAddrAck = '1')) or bus2Mem_CS_i = '0'
else
'0' ;
RDREQ_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
if(Bus2IP_Reset = '1')then
pend_rdreq <= '0';
elsif set_pend_rdreq = '1'then
pend_rdreq <= '1';
elsif clear_pend_rdreq = '1' then -- 1/3/2013
-- elsif ((Bus2IP_Burst = '0') and -- 1/3/2013
-- (Mem2Bus_RdAddrAck = '1') and -- 1/3/2013
-- (Bus2IP_RdReq_emc = '0')) or -- 1/3/2013
-- (bus2Mem_CS_i = '0') then -- 1/3/2013
pend_rdreq <= '0';
end if;
end if;
end process RDREQ_PROCESS;
Bus2Mem_RdReq_int <= (pend_rdreq and (Bus2IP_RdReq or (diff_addr_rd_ack and Synch_mem)))
when (single_transaction = '0' or Synch_mem = '1')
else
Bus2IP_RdReq;
Bus2Mem_RdReq <= Bus2Mem_RdReq_int;
-- 10-12-2012
RD_CNT_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
if(Transaction_done = '1')then
rd_cnt <= (others => '0');
elsif diff_addr_rd_ack ='1' and Bus2IP_RdReq = '0' and stop_oen_int = '0' then
rd_cnt <= rd_cnt + 1;
end if;
end if;
end process RD_CNT_PROCESS;
-- stop_oen_int <= '1' when rd_cnt = "010" and mem_width_bytes = "0001" else -- 8 bit - reduced by 1 here
-- '1' when rd_cnt = "001" and mem_width_bytes = "0010" else -- 16 bit - reduced by 1 here
-- '1' when rd_cnt = "001" and mem_width_bytes = "0100" else -- 32 bit - reduced by 1 here
-- '0';
STOP_OEN_GEN_PROCESS: process(axi_trans_size_reg,
mem_width_bytes,
rd_cnt) is
variable mem_width_and_size : std_logic_vector(5 downto 0);
-----
begin
-----
mem_width_and_size := mem_width_bytes & axi_trans_size_reg;
case mem_width_and_size is
when "000100" => -- axi byte access for 8 bit mem width
--if(rd_cnt = "0001")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(0);
when "000101" => -- axi HW access for 8 bit mem width
--if(rd_cnt = "0010")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(1);
when "000110" => -- axi WORD access for 8 bit mem width
--if(rd_cnt = "0100")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(2);
when "000111" => -- axi Double WORD access for 8 bit mem width
--if(rd_cnt = "1000")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(3);
--------------- for 16 bit mem width
when "001000" => -- axi byte access for 16 bit mem width
--if(rd_cnt = "0001")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(0);
when "001001" => -- axi HW access for 16 bit mem width
--if(rd_cnt = "0001")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(0);
when "001010" => -- axi WORD access for 16 bit mem width
--if(rd_cnt = "0010")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(1);
when "001011" => -- axi DOUBLE WORD access for 16 bit mem width
--if(rd_cnt = "0100")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(2);
--------------- for 32 bit mem width
when "010000" => -- axi byte access for 32 bit mem width
--if(rd_cnt = "0001")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(0);
when "010001" => -- axi HW access for 32 bit mem width
--if(rd_cnt = "0001")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(0);
when "010010" => -- axi WORD access for 32 bit mem width
--if(rd_cnt = "0001")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(0);
when "010011" => -- axi DPOUBLE WORD access for 32 bit mem width
--if(rd_cnt = "0010")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(1);
--------------- for 64 bit mem width
when "100000" | -- axi byte access for 64 bit mem width
"100001" | -- axi HW access for 64 bit mem width
"100010" | -- axi WORD access for 64 bit mem width
"100011" =>-- axi DOUBLE WORD access for 64 bit mem width
--if(rd_cnt = "0001")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(0);
---------------
when others => stop_oen_int <= '0';
end case;
end process STOP_OEN_GEN_PROCESS;
stop_oen <= stop_oen_int;
end imp;
-------------------------------------------------------------------------------
-- End of File ipic_if.vhd
-------------------------------------------------------------------------------
|
gpl-3.0
|
d7dec0166a7acc02d28332313dfc1069
| 0.448955 | 4.081514 | false | false | false | false |
hoangt/PoC
|
src/arith/arith_counter_free.vhdl
| 1 | 2,951 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Module: Poc.arith_counter_free
--
-- Authors: Thomas B. Preusser
--
-- Description:
-- ------------
-- Implements a free-running counter that generates a strobe signal
-- every DIVIDER-th cycle the increment input was asserted.
-- There is deliberately no output or specification of the counter
-- value so as to allow an implementation to optimize as much as
-- possible.
-- The implementation guarantees a strobe output directly from a
-- register. It is asserted exactly for one clock after DIVIDER cycles
-- of an asserted increment input have been observed.
--
-- License:
-- ===========================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ===========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity arith_counter_free is
generic (
DIVIDER : positive
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
inc : in std_logic;
stb : out std_logic -- End-of-Period Strobe
);
end arith_counter_free;
library IEEE;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
architecture rtl of arith_counter_free is
begin
genNoDiv: if DIVIDER = 1 generate
process(clk)
begin
if rising_edge(clk) then
stb <= inc;
end if;
end process;
end generate genNoDiv;
genDoDiv: if DIVIDER > 1 generate
-- Note: For DIVIDER=2**K+1, this could be marginally reduced to log2ceil(DIVIDER-1)
-- if it was known that the increment input inc would never be deasserted.
constant N : natural := log2ceil(DIVIDER);
signal Cnt : unsigned(N downto 0) := (others => '0');
signal cin : unsigned(0 downto 0);
begin
cin(0) <= not inc;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Cnt <= to_unsigned(DIVIDER-2, N+1);
else
Cnt <= Cnt + ite(Cnt(N) = '0', (Cnt'range => '1'), to_unsigned(DIVIDER-1, N+1)) + cin;
end if;
end if;
end process;
stb <= Cnt(N);
end generate genDoDiv;
end rtl;
|
apache-2.0
|
26705a4293169b15a5203b919f67ae87
| 0.627245 | 3.679551 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/mdio_if.vhd
| 4 | 23,285 |
-------------------------------------------------------------------------------
-- mdio_if.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : mdio_if.vhd
-- Version : v2.0
-- Description : This entity provides the interface between the physical layer
-- management control, and the host interface through the MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- MDIO_Clk -- 2.5Mhz clock
-- MDIO_en -- MDIO enable
-- MDIO_OP -- MDIO OP code
-- MDIO_Req -- MDIO transmission request
-- MDIO_PHY_AD -- The physical layer address
-- MDIO_REG_AD -- The individual register address
-- MDIO_WR_DATA -- The data to be written on MDIO
-- MDIO_RD_DATA -- The data read from MDIO
-- PHY_MDIO_I -- MDIO Tri-state input from PHY
-- PHY_MDIO_O -- MDIO Tri-state output to PHY
-- PHY_MDIO_T -- MDIO Tri-state control
-- PHY_MDC -- 2.5Mhz communication clock to PHY
-- MDIO_done -- RX FIFO read ack
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity mdio_if is
port (
Clk : in std_logic; -- System Clock
Rst : in std_logic; -- System Reset
MDIO_Clk : in std_logic; -- 2.5Mhz clock
MDIO_en : in std_logic; -- MDIO enable
MDIO_OP : in std_logic; -- MDIO OP code
MDIO_Req : in std_logic; -- MDIO transmission request
MDIO_PHY_AD : in std_logic_vector(4 downto 0);
-- The physical layer address
MDIO_REG_AD : in std_logic_vector(4 downto 0);
-- The individual register address
MDIO_WR_DATA : in std_logic_vector(15 downto 0);
-- The data to be written on MDIO
MDIO_RD_DATA : out std_logic_vector(15 downto 0);
-- The data read from MDIO
PHY_MDIO_I : in std_logic; -- MDIO Tri-state input from PHY
PHY_MDIO_O : out std_logic; -- MDIO Tri-state output to PHY
PHY_MDIO_T : out std_logic; -- MDIO Tri-state control
PHY_MDC : out std_logic; -- 2.5Mhz communication clock
MDIO_done : out std_logic -- MDIO tranfer done indicator
);
end mdio_if;
architecture imp of mdio_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
type mdio_state_type is (IDLE, PREAMBLE, ST1, ST2, OP1, OP2, TA1, TA2,
PHY_ADDR, REG_ADDR, WRITE, READ, DONE);
signal mdio_state, next_state : mdio_state_type;
signal mdio_xfer_done : std_logic; -- pulse to inidcate end of activity
signal mdio_idle : std_logic; -- internal READY signal
signal rd_data_en : std_logic_vector(15 downto 0); -- decoded write
-- MDIO_en for RD_DATA
signal mdio_en_reg : std_logic; -- MDIO_en signal latched at start of
-- transmission
signal mdio_o_cmb : std_logic; -- rising edge version of MDIO_OUT
signal mdio_t_comb : std_logic; -- combinatorial term to produce
-- MDIO_TRISTATE
signal mdio_clk_reg : std_logic; -- registering MDIO_Clk to use it as a
-- clock MDIO_en
signal mdio_in_reg1 : std_logic; -- compensate in pipeline delay caused
-- by using MDC as a clock MDIO_en
signal mdio_in_reg2 : std_logic; -- compensate in pipeline delay caused by
-- using MDC as a clock MDIO_en
signal clk_cnt : integer range 0 to 32; -- Clk counter
signal ld_cnt_data_cmb : integer range 0 to 32; -- Counter load comb
signal ld_cnt_data_reg : integer range 0 to 32; -- Counter load reg
signal ld_cnt_en_cmb : std_logic; -- Counter load enable
signal clk_cnt_en : std_logic; -- Counter enable
signal mdc_falling : std_logic; -- MDC falling edge
signal mdc_rising : std_logic; -- MDC rising edge
signal ld_cnt_en_reg : std_logic; -- Counter load enable reg
begin
----------------------------------------------------------------------------
-- PROCESS : INPUT_REG_CLK
----------------------------------------------------------------------------
-- Registering PHY_MDIO_I and MDC signals w.r.t SAXI clock.
----------------------------------------------------------------------------
INPUT_REG_CLK: process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_clk_reg <= '0';
mdio_in_reg1 <= '0';
mdio_in_reg2 <= '0';
else
mdio_clk_reg <= MDIO_Clk;
mdio_in_reg1 <= PHY_MDIO_I;
mdio_in_reg2 <= mdio_in_reg1;
end if;
end if;
end process INPUT_REG_CLK;
-- Falling edge and rising edge generation of MDC clock
mdc_falling <= not MDIO_Clk and mdio_clk_reg;
mdc_rising <= MDIO_Clk and not mdio_clk_reg;
-- Enable MDC only when MDIO interface is enabled.
PHY_MDC <= MDIO_Clk; -- making the MDC clk contineous
--PHY_MDC <= MDIO_Clk and mdio_en_reg;
-- Informs MDIO interface about the MDIO transfer complete.
MDIO_done <= mdio_xfer_done;
----------------------------------------------------------------------------
-- PROCESS : REG_MDIO_en
----------------------------------------------------------------------------
-- Latch MDIO_en bit on falling edge of MDC and when MDIO master is IDLE.
-- MDIO Master will complete the existing transfer even if MDIO interface
-- is disable in middle of the transaction.
----------------------------------------------------------------------------
REG_MDIO_en : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_en_reg <= '0';
elsif mdc_falling='1' then
if mdio_idle = '1' then
mdio_en_reg <= MDIO_en;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : PHY_MDIO_T_REG
----------------------------------------------------------------------------
-- The mdio_t_comb signal is driven high only for read operation starting
-- from the Turn arround state.
-- It is driven on falling clock edge to match up with PHY_MDIO_O
----------------------------------------------------------------------------
PHY_MDIO_T_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
PHY_MDIO_T <= '1';
elsif (mdc_falling='1') then -- falling edge of MDC
PHY_MDIO_T <= mdio_t_comb;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : PHY_MDIO_O_REG
----------------------------------------------------------------------------
-- Generating PHY_MDIO_O output singnal on falling edge of MDC
----------------------------------------------------------------------------
PHY_MDIO_O_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
PHY_MDIO_O <= '0';
elsif (mdc_falling='1') then -- falling edge of MDC
PHY_MDIO_O <= mdio_o_cmb;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : MDIO_IDLE_REG
----------------------------------------------------------------------------
-- The mdio_idle signal is used to indicate no activity on the MDIO.
-- Set at reset amd at the end of transmission.
-- Rst at start of transmission as long as device is MDIO_end
----------------------------------------------------------------------------
MDIO_IDLE_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_idle <= '1';
elsif (mdc_rising='1') then -- rising edge of MDC
if (mdio_xfer_done = '1') then
mdio_idle <= '1';
elsif (MDIO_Req = '1' and mdio_en_reg = '1') then
mdio_idle <= '0';
end if;
end if;
end if;
end process ;
----------------------------------------------------------------------------
-- PROCESS : MDIO_CAPTURE_DATA
----------------------------------------------------------------------------
-- This process captures registered PHY_MDIO_i input on rising edge of the
-- MDC clock. The rd_data_en signal is generated in MDIO State machine for
-- respective captured bit.
----------------------------------------------------------------------------
MDIO_CAPTURE_DATA : for i in 15 downto 0 generate
MDIO_DATA_IN : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
MDIO_RD_DATA(i) <= '0';
elsif (mdc_rising='1') then -- rising edge of MDC
if(rd_data_en(i) = '1') then
MDIO_RD_DATA(i) <= mdio_in_reg2;
end if;
end if;
end if;
end process MDIO_DATA_IN;
end generate;
----------------------------------------------------------------------------
-- PROCESS : MDIO_DOWN_COUNTER
----------------------------------------------------------------------------
-- This counter is used in Preamble and PHY_ADDR and REG_ADDR state.
-- This counter is loaded for the required values for each above states.
----------------------------------------------------------------------------
MDIO_DOWN_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
clk_cnt <= 0;
elsif (mdc_rising='1') then -- falling edge of MDC
if (ld_cnt_en_reg = '1') then -- Load counter with load data
clk_cnt <= ld_cnt_data_reg;
elsif (clk_cnt_en='1') then -- Enable Down Counter
clk_cnt <= clk_cnt - 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : MDIO_NEXT_STATE_GEN
----------------------------------------------------------------------------
-- MDIO next state register process
----------------------------------------------------------------------------
MDIO_NEXT_STATE_GEN : process (Clk)
begin
if Clk'event and Clk = '1' then
if (Rst = '1') then
mdio_state <= IDLE;
elsif (mdc_rising='1') then
mdio_state <= next_state;
end if;
end if;
end process MDIO_NEXT_STATE_GEN;
----------------------------------------------------------------------------
-- PROCESS : MDIO_COMB_REG_GEN
----------------------------------------------------------------------------
-- Combinational signal register process
----------------------------------------------------------------------------
MDIO_COMB_REG_GEN : process (Clk)
begin
if Clk'event and Clk = '1' then
if (Rst = '1') then
ld_cnt_data_reg <= 0;
ld_cnt_en_reg <= '0';
else
ld_cnt_data_reg <= ld_cnt_data_cmb;
ld_cnt_en_reg <= ld_cnt_en_cmb;
end if;
end if;
end process MDIO_COMB_REG_GEN;
----------------------------------------------------------------------------
-- PROCESS : MDIO_STATE_COMB
----------------------------------------------------------------------------
-- This process generates mdio_o_cmb signal in command and Write phase as
-- per the required MDIO protocol. This process also generate mdio_t_comb
-- tristate signal and rd_data_en to capture the respective bit in Read
-- operation.
----------------------------------------------------------------------------
MDIO_STATE_COMB : process (mdio_state, mdio_idle, clk_cnt, MDIO_OP,
MDIO_PHY_AD, MDIO_REG_AD, MDIO_WR_DATA)
begin
-- state machine defaults
mdio_o_cmb <= '1';
rd_data_en <= "0000000000000000";
mdio_xfer_done <= '0';
ld_cnt_en_cmb <= '0';
clk_cnt_en <= '0';
mdio_t_comb <= '0';
next_state <= mdio_state;
ld_cnt_data_cmb <= 0;
case mdio_state is
when IDLE =>
mdio_o_cmb <= '1';
mdio_t_comb <= '1';
ld_cnt_en_cmb <= '1';
-- leave IDLE state when new mdio request is received.
if mdio_idle = '0' then
-- Load counter for 32-bit preamble
ld_cnt_data_cmb <= 31;
next_state <= PREAMBLE;
end if;
when PREAMBLE =>
clk_cnt_en <= '1';
-- Move to ST1 after 32-bit preamble.
if clk_cnt = 0 then
next_state <= ST1;
clk_cnt_en <= '0';
end if;
when ST1 => -- Start Code-1
mdio_o_cmb <= '0';
next_state <= ST2;
when ST2 => -- Start Code-2
mdio_o_cmb <= '1';
next_state <= OP1;
when OP1 => -- Opcode-1
next_state <= OP2;
if MDIO_OP='1' then
mdio_o_cmb <= '1';
else
mdio_o_cmb <= '0';
end if;
when OP2 => -- Opcode-2
next_state <= PHY_ADDR;
-- Load counter for 5-bit PHYaddress transfer
ld_cnt_data_cmb <= 4;
ld_cnt_en_cmb <= '1';
if MDIO_OP='1' then
mdio_o_cmb <= '0';
else
mdio_o_cmb <= '1';
end if;
when PHY_ADDR => -- PHY Device Address
clk_cnt_en <= '1';
mdio_o_cmb <= MDIO_PHY_AD(clk_cnt);
-- Send 5-bit PHY device address
if clk_cnt=0 then
next_state <= REG_ADDR;
-- Load counter for 5-bit REG address transfer
ld_cnt_data_cmb <= 4;
ld_cnt_en_cmb <= '1';
end if;
when REG_ADDR => -- PHY Device Address
clk_cnt_en <= '1';
mdio_o_cmb <= MDIO_REG_AD(clk_cnt);
-- Send 5-bit PHY Register address
if clk_cnt=0 then
next_state <= TA1;
clk_cnt_en <= '0';
end if;
when TA1 => -- Turn Around Time-1
mdio_o_cmb <= '1';
next_state <= TA2;
-- For Read operation generate high impedence on
-- MDIO bus
if MDIO_OP='1' then
mdio_t_comb <= '1';
else
mdio_t_comb <= '0';
end if;
when TA2 => -- Turn Around Time-2
mdio_o_cmb <= '0';
-- Load the down counter for 16 bit data transfer
ld_cnt_data_cmb <= 15;
ld_cnt_en_cmb <= '1';
-- Move to Write state if opcode is '0'
if MDIO_OP='0' then
next_state <= WRITE;
mdio_t_comb <= '0';
else
next_state <= READ;
mdio_t_comb <= '1';
end if;
when WRITE => -- MDIO DATA Write
clk_cnt_en <= '1';
-- Send 16-bit Write Data on the MDIO data line
mdio_o_cmb <= MDIO_WR_DATA(clk_cnt);
-- Wait for 16 bit transfer
if clk_cnt=0 then
next_state <= DONE;
clk_cnt_en <= '0';
end if;
when READ => -- MDIO DATA Read
clk_cnt_en <= '1';
mdio_t_comb <= '1';
-- Generate read data enable for respective bit
rd_data_en(clk_cnt) <= '1';
-- Wait for 16 bit transfer
if clk_cnt=0 then
next_state <= DONE;
clk_cnt_en <= '0';
end if;
when DONE => -- MDIO Transfer Done
mdio_o_cmb <= '1';
mdio_t_comb <= '1';
next_state <= IDLE;
-- Mdio trasnfer complete
mdio_xfer_done <= '1';
-- coverage off
when others =>
next_state <= IDLE;
-- coverage on
end case;
end process MDIO_STATE_COMB;
end imp;
|
gpl-3.0
|
d910e95baa2ec1111800ad8e2d04155f
| 0.409362 | 4.688884 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_axi_intc_0/synth/design_1_microblaze_0_axi_intc_0.vhd
| 2 | 11,547 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_intc:4.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_intc_v4_1;
USE axi_intc_v4_1.axi_intc;
ENTITY design_1_microblaze_0_axi_intc_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
intr : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
processor_clk : IN STD_LOGIC;
processor_rst : IN STD_LOGIC;
irq : OUT STD_LOGIC;
processor_ack : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
interrupt_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_microblaze_0_axi_intc_0;
ARCHITECTURE design_1_microblaze_0_axi_intc_0_arch OF design_1_microblaze_0_axi_intc_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_microblaze_0_axi_intc_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_intc IS
GENERIC (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_NUM_INTR_INPUTS : INTEGER;
C_NUM_SW_INTR : INTEGER;
C_KIND_OF_INTR : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_KIND_OF_EDGE : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_KIND_OF_LVL : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_ASYNC_INTR : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_NUM_SYNC_FF : INTEGER;
C_IVAR_RESET_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_ENABLE_ASYNC : INTEGER;
C_HAS_IPR : INTEGER;
C_HAS_SIE : INTEGER;
C_HAS_CIE : INTEGER;
C_HAS_IVR : INTEGER;
C_HAS_ILR : INTEGER;
C_IRQ_IS_LEVEL : INTEGER;
C_IRQ_ACTIVE : STD_LOGIC;
C_DISABLE_SYNCHRONIZERS : INTEGER;
C_MB_CLK_NOT_CONNECTED : INTEGER;
C_HAS_FAST : INTEGER;
C_EN_CASCADE_MODE : INTEGER;
C_CASCADE_MASTER : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
intr : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
processor_clk : IN STD_LOGIC;
processor_rst : IN STD_LOGIC;
irq : OUT STD_LOGIC;
processor_ack : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
interrupt_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
interrupt_address_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
processor_ack_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT axi_intc;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_microblaze_0_axi_intc_0_arch: ARCHITECTURE IS "axi_intc,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_microblaze_0_axi_intc_0_arch : ARCHITECTURE IS "design_1_microblaze_0_axi_intc_0,axi_intc,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_microblaze_0_axi_intc_0_arch: ARCHITECTURE IS "design_1_microblaze_0_axi_intc_0,axi_intc,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_intc,x_ipVersion=4.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_INSTANCE=axi_intc_inst,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_NUM_INTR_INPUTS=2,C_NUM_SW_INTR=0,C_KIND_OF_INTR=0xfffffffe,C_KIND_OF_EDGE=0xffffffff,C_KIND_OF_LVL=0xffffffff,C_ASYNC_INTR=0xFFFFFFFC,C_NUM_SYNC_FF=2,C_IVAR_RESET_VALUE=0x00000010,C_ENABLE_ASYNC=0,C_HAS_IPR=1,C_HAS_SIE=1,C_HAS_CIE=1,C_HAS_IVR=1,C_HAS_ILR=0,C_IRQ_IS_LEVEL=1,C_IRQ_ACTIVE=0x1,C_DISABLE_SYNCHRONIZERS=1,C_MB_CLK_NOT_CONNECTED=1,C_HAS_FAST=1,C_EN_CASCADE_MODE=0,C_CASCADE_MASTER=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_resetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RREADY";
ATTRIBUTE X_INTERFACE_INFO OF intr: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt_input INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF processor_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 proc_clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF processor_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 proc_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF irq: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF processor_ack: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt ACK";
ATTRIBUTE X_INTERFACE_INFO OF interrupt_address: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt ADDRESS";
BEGIN
U0 : axi_intc
GENERIC MAP (
C_FAMILY => "artix7",
C_INSTANCE => "axi_intc_inst",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_NUM_INTR_INPUTS => 2,
C_NUM_SW_INTR => 0,
C_KIND_OF_INTR => X"fffffffe",
C_KIND_OF_EDGE => X"ffffffff",
C_KIND_OF_LVL => X"ffffffff",
C_ASYNC_INTR => X"FFFFFFFC",
C_NUM_SYNC_FF => 2,
C_IVAR_RESET_VALUE => X"00000010",
C_ENABLE_ASYNC => 0,
C_HAS_IPR => 1,
C_HAS_SIE => 1,
C_HAS_CIE => 1,
C_HAS_IVR => 1,
C_HAS_ILR => 0,
C_IRQ_IS_LEVEL => 1,
C_IRQ_ACTIVE => '1',
C_DISABLE_SYNCHRONIZERS => 1,
C_MB_CLK_NOT_CONNECTED => 1,
C_HAS_FAST => 1,
C_EN_CASCADE_MODE => 0,
C_CASCADE_MASTER => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
intr => intr,
processor_clk => processor_clk,
processor_rst => processor_rst,
irq => irq,
processor_ack => processor_ack,
interrupt_address => interrupt_address,
interrupt_address_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_microblaze_0_axi_intc_0_arch;
|
gpl-3.0
|
1ec45f41101b26f5bfc482ca5680eabb
| 0.686325 | 3.204829 | false | false | false | false |
lowRISC/greth-library
|
greth_library/work/simple_soc3.vhd
| 2 | 19,629 |
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Network on Chip design top level.
--! @details RISC-V "Rocket Core" based system with the AMBA AXI4 (NASTI)
--! system bus and integrated peripheries.
------------------------------------------------------------------------------
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library rocketlib;
--! SOC top-level component declaration.
use rocketlib.types_rocket.all;
--! Ethernet related declarations.
use rocketlib.grethpkg.all;
--! GNSS Sensor Ltd proprietary library
library gnsslib;
use gnsslib.types_gnss.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
--! Target independable configuration.
use work.config_common.all;
--! @brief SOC Top-level entity declaration.
--! @details This module implements full SOC functionality and all IO signals
--! are available on FPGA/ASIC IO pins.
entity rocket_soc is port
(
--! Input reset. Active High. Usually assigned to button "Center".
i_rst : in std_logic;
--! @name Clocks:
--! @{
--! Differential clock (LVDS) positive signal.
i_sclk_p : in std_logic;
--! Differential clock (LVDS) negative signal.
i_sclk_n : in std_logic;
--! External ADC clock (default 26 MHz).
i_clk_adc : in std_logic;
--! @}
--! @name User's IOs:
--! @{
--! DIP switch.
i_int_clkrf : in std_logic;
i_dip : in std_logic_vector(3 downto 1);
--! LEDs.
o_led : out std_logic_vector(7 downto 0);
--! @}
--! @name UART1 signals:
--! @{
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! @}
--! @name ADC channel A inputs (1575.4 GHz):
--! @{
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
--! @}
--! @name ADC channel B inputs (1602 GHz):
--! @{
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
--! @}
--! @name MAX2769 SPIs and antenna controls signals:
--! @{
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic;
--! @}
--! Ethernet MAC PHY interface signals
--! @{
i_gmiiclk_p : in std_ulogic;
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic
);
--! @}
end rocket_soc;
--! @brief SOC top-level architecture declaration.
architecture arch_rocket_soc of rocket_soc is
--! @name Buffered in/out signals.
--! @details All signals that are connected with in/out pads must be passed
--! through the dedicated buffere modules. For FPGA they are implemented
--! as an empty devices but ASIC couldn't be made without buffering.
--! @{
signal ib_rst : std_logic;
signal ib_sclk_p : std_logic;
signal ib_sclk_n : std_logic;
signal ib_clk_adc : std_logic;
signal ib_dip : std_logic_vector(3 downto 0);
signal ib_gmiiclk : std_logic;
--! @}
signal wSysReset : std_ulogic; -- Internal system reset. MUST NOT USED BY DEVICES.
signal wReset : std_ulogic; -- Global reset active HIGH
signal wNReset : std_ulogic; -- Global reset active LOW
signal soft_rst : std_logic; -- reset from exteranl debugger
signal bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal wClkBus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
signal wClkAdc : std_ulogic; -- 26 MHz from the internal PLL
signal wPllLocked : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
signal uart1i : uart_in_type;
signal uart1o : uart_out_type;
--! Arbiter is switching only slaves output signal, data from noc
--! is connected to all slaves and to the arbiter itself.
signal aximi : nasti_master_in_type;
signal aximo : nasti_master_out_vector;
signal axisi : nasti_slave_in_type;
signal axiso : nasti_slaves_out_vector;
signal slv_cfg : nasti_slave_cfg_vector;
signal mst_cfg : nasti_master_cfg_vector;
--! From modules-to-tile requests
signal htifo : host_out_vector;
--! Selected request with the highest priority.
signal htifo_mux : host_out_type;
--! tile-to-module response.
signal htifi : host_in_type;
--! response with the 'grant' signal marking the exact recipient.
signal htifi_grant : host_in_type;
signal gnss_i : gns_in_type;
signal gnss_o : gns_out_type;
signal fse_i : fse_in_type;
signal fse_o : fse_out_type;
signal eth_i : eth_in_type;
signal eth_o : eth_out_type;
signal irq_pins : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
begin
--! PAD buffers:
irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst);
iclkp0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_p, i_sclk_p);
iclkn0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_n, i_sclk_n);
iclk1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_clk_adc, i_clk_adc);
idip0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(0), i_int_clkrf);
dipx : for i in 1 to 3 generate
idipz : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(i), i_dip(i));
end generate;
igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map (
i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk);
--! @todo all other in/out signals via buffers:
------------------------------------
-- @brief Internal PLL device instance.
pll0 : SysPLL_tech generic map (
tech => CFG_FABTECH,
tmode_always_ena => CFG_TESTMODE_ON
) port map (
i_reset => ib_rst,
i_int_clkrf => ib_dip(0),
i_clkp => ib_sclk_p,
i_clkn => ib_sclk_n,
i_clk_adc => ib_clk_adc,
o_clk_bus => wClkBus,
o_clk_adc => wClkAdc,
o_locked => wPllLocked
);
wSysReset <= ib_rst or not wPllLocked;
------------------------------------
--! @brief System Reset device instance.
rst0 : reset_global port map (
inSysReset => wSysReset,
inSysClk => wClkBus,
inPllLock => wPllLocked,
outReset => wReset
);
wNReset <= not wReset;
bus_nrst <= not (wReset or soft_rst);
--! @brief AXI4 controller.
ctrl0 : axictrl port map (
clk => wClkBus,
nrst => wNReset,
slvoi => axiso,
mstoi => aximo,
slvio => axisi,
mstio => aximi
);
--! @brief HostIO controller.
htif0 : htifctrl port map (
clk => wClkBus,
nrst => wNReset,
srcsi => htifo,
srcso => htifo_mux,
htifii => htifi,
htifio => htifi_grant
);
mst_cfg(CFG_NASTI_MASTER_CACHED) <= nasti_master_config_none;
aximo(CFG_NASTI_MASTER_CACHED) <= nasti_master_out_none;
mst_cfg(CFG_NASTI_MASTER_UNCACHED) <= nasti_master_config_none;
aximo(CFG_NASTI_MASTER_UNCACHED) <= nasti_master_out_none;
dsu_ena : if CFG_DSU_ENABLE generate
------------------------------------
--! @brief Debug Support Unit with access to the CSRs
--! @details Map address:
--! 0x80080000..0x8009ffff (128 KB total)
dsu0 : nasti_dsu generic map (
xindex => CFG_NASTI_SLAVE_DSU,
xaddr => 16#80080#,
xmask => 16#fffe0#,
htif_index => CFG_HTIF_SRC_DSU
) port map (
clk => wClkBus,
nrst => wNReset,
o_cfg => slv_cfg(CFG_NASTI_SLAVE_DSU),
i_axi => axisi,
o_axi => axiso(CFG_NASTI_SLAVE_DSU),
i_host => htifi_grant,
o_host => htifo(CFG_HTIF_SRC_DSU),
o_soft_reset => soft_rst
);
end generate;
dsu_dis : if not CFG_DSU_ENABLE generate
slv_cfg(CFG_NASTI_SLAVE_DSU) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_DSU) <= nasti_slave_out_none;
htifo(CFG_HTIF_SRC_DSU) <= host_out_none;
end generate;
------------------------------------
--! @brief BOOT ROM module isntance with the AXI4 interface.
--! @details Map address:
--! 0x00000000..0x00001fff (8 KB total)
boot0 : nasti_bootrom generic map (
memtech => CFG_MEMTECH,
xindex => CFG_NASTI_SLAVE_BOOTROM,
xaddr => 0,
xmask => 16#ffffe#,
sim_hexfile => CFG_SIM_BOOTROM_HEX
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_BOOTROM),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_BOOTROM)
);
------------------------------------
--! @brief Firmware Image ROM with the AXI4 interface.
--! @details Map address:
--! 0x00100000..0x0013ffff (256 KB total)
--! @warning Don't forget to change ROM_ADDR_WIDTH in rom implementation
img0 : nasti_romimage generic map (
memtech => CFG_MEMTECH,
xindex => CFG_NASTI_SLAVE_ROMIMAGE,
xaddr => 16#00100#,
xmask => 16#fffc0#,
sim_hexfile => CFG_SIM_FWIMAGE_HEX
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_ROMIMAGE),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_ROMIMAGE)
);
------------------------------------
--! Internal SRAM module instance with the AXI4 interface.
--! @details Map address:
--! 0x10000000..0x1007ffff (512 KB total)
sram0 : nasti_sram generic map (
memtech => CFG_MEMTECH,
xindex => CFG_NASTI_SLAVE_SRAM,
xaddr => 16#10000#,
xmask => 16#fff80#, -- 512 KB mask
abits => (10 + log2(512)), -- 512 KB address
init_file => CFG_SIM_FWIMAGE_HEX -- Used only for inferred
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_SRAM),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_SRAM)
);
------------------------------------
--! @brief Controller of the LEDs, DIPs and GPIO with the AXI4 interface.
--! @details Map address:
--! 0x80000000..0x80000fff (4 KB total)
gpio0 : nasti_gpio generic map (
xindex => CFG_NASTI_SLAVE_GPIO,
xaddr => 16#80000#,
xmask => 16#fffff#
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_GPIO),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_GPIO),
i_dip => ib_dip,
o_led => o_led
);
------------------------------------
uart1i.cts <= not i_uart1_ctsn;
uart1i.rd <= i_uart1_rd;
--! @brief UART Controller with the AXI4 interface.
--! @details Map address:
--! 0x80001000..0x80001fff (4 KB total)
uart1 : nasti_uart generic map (
xindex => CFG_NASTI_SLAVE_UART1,
xaddr => 16#80001#,
xmask => 16#FFFFF#,
fifosz => 16
) port map (
nrst => wNReset,
clk => wClkbus,
cfg => slv_cfg(CFG_NASTI_SLAVE_UART1),
i_uart => uart1i,
o_uart => uart1o,
i_axi => axisi,
o_axi => axiso(CFG_NASTI_SLAVE_UART1),
o_irq => irq_pins(CFG_IRQ_UART1)
);
o_uart1_td <= uart1o.td;
o_uart1_rtsn <= not uart1o.rts;
------------------------------------
--! @brief Interrupt controller with the AXI4 interface.
--! @details Map address:
--! 0x80002000..0x80002fff (4 KB total)
irq0 : nasti_irqctrl generic map (
xindex => CFG_NASTI_SLAVE_IRQCTRL,
xaddr => 16#80002#,
xmask => 16#FFFFF#,
htif_index => CFG_HTIF_SRC_IRQCTRL
) port map (
clk => wClkBus,
nrst => bus_nrst,
i_irqs => irq_pins,
o_cfg => slv_cfg(CFG_NASTI_SLAVE_IRQCTRL),
i_axi => axisi,
o_axi => axiso(CFG_NASTI_SLAVE_IRQCTRL),
i_host => htifi_grant,
o_host => htifo(CFG_HTIF_SRC_IRQCTRL)
);
------------------------------------
--! @brief GNSS Engine stub with the AXI4 interface.
--! @details Map address:
--! 0x80003000..0x80003fff (4 KB total)
geneng_ena : if CFG_GNSSLIB_ENABLE generate
gnss_i.nrst <= wNReset;
gnss_i.clk_bus <= wClkBus;
gnss_i.axi <= axisi;
gnss_i.clk_adc <= wClkAdc;
gnss_i.gps_I <= i_gps_I;
gnss_i.gps_Q <= i_gps_Q;
gnss_i.glo_I <= i_glo_I;
gnss_i.glo_Q <= i_glo_I;
gnss0 : gnssengine generic map (
tech => CFG_MEMTECH,
xindex => CFG_NASTI_SLAVE_ENGINE,
xaddr => 16#80003#,
xmask => 16#FFFFF#
) port map (
i => gnss_i,
o => gnss_o
);
axiso(CFG_NASTI_SLAVE_ENGINE) <= gnss_o.axi;
slv_cfg(CFG_NASTI_SLAVE_ENGINE) <= gnss_o.cfg;
irq_pins(CFG_IRQ_GNSSENGINE) <= gnss_o.ms_pulse;
end generate;
geneng_dis : if not CFG_GNSSLIB_ENABLE generate
axiso(CFG_NASTI_SLAVE_ENGINE) <= nasti_slave_out_none;
slv_cfg(CFG_NASTI_SLAVE_ENGINE) <= nasti_slave_config_none;
irq_pins(CFG_IRQ_GNSSENGINE) <= '0';
end generate;
--! @brief RF front-end controller with the AXI4 interface.
--! @details Map address:
--! 0x80004000..0x80004fff (4 KB total)
rf0 : axi_rfctrl generic map (
xindex => CFG_NASTI_SLAVE_RFCTRL,
xaddr => 16#80004#,
xmask => 16#fffff#
) port map (
nrst => wNReset,
clk => wClkBus,
o_cfg => slv_cfg(CFG_NASTI_SLAVE_RFCTRL),
i_axi => axisi,
o_axi => axiso(CFG_NASTI_SLAVE_RFCTRL),
i_gps_ld => i_gps_ld,
i_glo_ld => i_glo_ld,
outSCLK => o_max_sclk,
outSDATA => o_max_sdata,
outCSn => o_max_ncs,
inExtAntStat => i_antext_stat,
inExtAntDetect => i_antext_detect,
outExtAntEna => o_antext_ena,
outIntAntContr => o_antint_contr
);
--! @brief Timers with the AXI4 interface.
--! @details Map address:
--! 0x80005000..0x80005fff (4 KB total)
gptmr0 : nasti_gptimers generic map (
xindex => CFG_NASTI_SLAVE_GPTIMERS,
xaddr => 16#80005#,
xmask => 16#fffff#,
tmr_total => 2
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_GPTIMERS),
i_axi => axisi,
o_axi => axiso(CFG_NASTI_SLAVE_GPTIMERS),
o_irq => irq_pins(CFG_IRQ_GPTIMERS)
);
--! @brief GPS-CA Fast Search Engine with the AXI4 interface.
--! @details Map address:
--! 0x8000a000..0x8000afff (4 KB total)
fse0_ena : if CFG_GNSSLIB_ENABLE and CFG_GNSSLIB_FSEGPS_ENABLE = 1 generate
fse_i.nrst <= wNReset;
fse_i.clk_bus <= wClkBus;
fse_i.clk_fse <= wClkBus;
fse_i.axi <= axisi;
fse_i.clk_adc <= wClkAdc;
fse_i.I <= i_gps_I;
fse_i.Q <= i_gps_Q;
fse_i.ms_pulse <= gnss_o.ms_pulse;
fse_i.pps <= gnss_o.pps;
fse_i.test_mode <= '0';
fse0 : TopFSE generic map (
tech => CFG_MEMTECH,
xindex => CFG_NASTI_SLAVE_FSE_GPS,
xaddr => 16#8000a#,
xmask => 16#fffff#,
sys => GEN_SYSTEM_GPSCA
) port map (
i => fse_i,
o => fse_o
);
slv_cfg(CFG_NASTI_SLAVE_FSE_GPS) <= fse_o.cfg;
axiso(CFG_NASTI_SLAVE_FSE_GPS) <= fse_o.axi;
end generate;
--! FSE GPS disable
fse0_dis : if CFG_GNSSLIB_FSEGPS_ENABLE = 0 generate
slv_cfg(CFG_NASTI_SLAVE_FSE_GPS) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_FSE_GPS) <= nasti_slave_out_none;
end generate;
--! Gigabit clock phase rotator with buffers
clkrot90 : clkp90_tech generic map (
tech => CFG_FABTECH,
freq => 125000 -- KHz = 125 MHz
) port map (
i_rst => wReset,
i_clk => ib_gmiiclk,
o_clk => eth_i.gtx_clk,
o_clkp90 => eth_i.tx_clk_90,
o_clk2x => open, -- used in gbe 'io_ref'
o_lock => open
);
--! @brief Ethernet MAC with the AXI4 interface.
--! @details Map address:
--! 0x80040000..0x8007ffff (256 KB total)
--! EDCL IP: 192.168.1.51 = C0.A8.01.33
eth0_ena : if CFG_ETHERNET_ENABLE generate
eth_i.tx_clk <= i_etx_clk;
eth_i.rx_clk <= i_erx_clk;
eth_i.rxd <= i_erxd;
eth_i.rx_dv <= i_erx_dv;
eth_i.rx_er <= i_erx_er;
eth_i.rx_col <= i_erx_col;
eth_i.rx_crs <= i_erx_crs;
eth_i.mdint <= i_emdint;
mac0 : grethaxi generic map (
xslvindex => CFG_NASTI_SLAVE_ETHMAC,
xmstindex => CFG_NASTI_MASTER_ETHMAC,
xaddr => 16#80040#,
xmask => 16#FFFC0#,
xirq => CFG_IRQ_ETHMAC,
memtech => CFG_MEMTECH,
mdcscaler => 60, --! System Bus clock in MHz
enable_mdio => 1,
fifosize => 16,
nsync => 1,
edcl => 1,
edclbufsz => 16,
macaddrh => 16#20789#,
macaddrl => 16#123#,
ipaddrh => 16#C0A8#,
ipaddrl => 16#0033#,
phyrstadr => 7,
enable_mdint => 1,
maxsize => 1518
) port map (
rst => wNReset,
clk => wClkBus,
msti => aximi,
msto => aximo(CFG_NASTI_MASTER_ETHMAC),
mstcfg => mst_cfg(CFG_NASTI_MASTER_ETHMAC),
msto2 => open, -- EDCL separate access is disabled
mstcfg2 => open, -- EDCL separate access is disabled
slvi => axisi,
slvo => axiso(CFG_NASTI_SLAVE_ETHMAC),
slvcfg => slv_cfg(CFG_NASTI_SLAVE_ETHMAC),
ethi => eth_i,
etho => eth_o,
irq => irq_pins(CFG_IRQ_ETHMAC)
);
end generate;
--! Ethernet disabled
eth0_dis : if not CFG_ETHERNET_ENABLE generate
slv_cfg(CFG_NASTI_SLAVE_ETHMAC) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_ETHMAC) <= nasti_slave_out_none;
mst_cfg(CFG_NASTI_MASTER_ETHMAC) <= nasti_master_config_none;
aximo(CFG_NASTI_MASTER_ETHMAC) <= nasti_master_out_none;
irq_pins(CFG_IRQ_ETHMAC) <= '0';
eth_o <= eth_out_none;
end generate;
emdio_pad : iobuf_tech generic map(
CFG_PADTECH
) port map (
o => eth_i.mdio_i,
io => io_emdio,
i => eth_o.mdio_o,
t => eth_o.mdio_oe
);
o_egtx_clk <= eth_i.gtx_clk;--eth_i.tx_clk_90;
o_etxd <= eth_o.txd;
o_etx_en <= eth_o.tx_en;
o_etx_er <= eth_o.tx_er;
o_emdc <= eth_o.mdc;
o_erstn <= wNReset;
--! @brief Plug'n'Play controller of the current configuration with the
--! AXI4 interface.
--! @details Map address:
--! 0xfffff000..0xffffffff (4 KB total)
pnp0 : nasti_pnp generic map (
xindex => CFG_NASTI_SLAVE_PNP,
xaddr => 16#fffff#,
xmask => 16#fffff#,
tech => CFG_MEMTECH
) port map (
sys_clk => wClkBus,
adc_clk => wClkAdc,
nrst => wNReset,
mstcfg => mst_cfg,
slvcfg => slv_cfg,
cfg => slv_cfg(CFG_NASTI_SLAVE_PNP),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_PNP)
);
end arch_rocket_soc;
|
bsd-2-clause
|
13e44da43535f913a61f609d2613647f
| 0.580315 | 3.272045 | false | false | false | false |
hoangt/PoC
|
src/bus/stream/stream_DeMux.vhdl
| 2 | 6,302 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: A generic buffer module for the PoC.Stream protocol.
--
-- Description:
-- ------------------------------------
-- This module implements a generic buffer (FifO) for the PoC.Stream protocol.
-- It is generic in DATA_BITS and in META_BITS as well as in FifO depths for
-- data and meta information.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
entity Stream_DeMux is
generic (
portS : POSITIVE := 2;
DATA_BITS : POSITIVE := 8;
META_BITS : NATURAL := 8;
META_REV_BITS : NATURAL := 2
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- Control interface
DeMuxControl : in STD_LOGIC_VECTOR(portS - 1 downto 0);
-- IN Port
In_Valid : in STD_LOGIC;
In_Data : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
In_Meta : in STD_LOGIC_VECTOR(META_BITS - 1 downto 0);
In_Meta_rev : out STD_LOGIC_VECTOR(META_REV_BITS - 1 downto 0);
In_SOF : in STD_LOGIC;
In_EOF : in STD_LOGIC;
In_Ack : out STD_LOGIC;
-- OUT Ports
Out_Valid : out STD_LOGIC_VECTOR(portS - 1 downto 0);
Out_Data : out T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0);
Out_Meta : out T_SLM(portS - 1 downto 0, META_BITS - 1 downto 0);
Out_Meta_rev : in T_SLM(portS - 1 downto 0, META_REV_BITS - 1 downto 0);
Out_SOF : out STD_LOGIC_VECTOR(portS - 1 downto 0);
Out_EOF : out STD_LOGIC_VECTOR(portS - 1 downto 0);
Out_Ack : in STD_LOGIC_VECTOR(portS - 1 downto 0)
);
end;
architecture rtl of Stream_DeMux is
attribute KEEP : BOOLEAN;
attribute FSM_ENCODING : STRING;
subtype T_CHANNEL_INDEX is NATURAL range 0 to portS - 1;
type T_STATE is (ST_IDLE, ST_DATAFLOW, ST_DISCARD_FRAME);
signal State : T_STATE := ST_IDLE;
signal NextState : T_STATE;
signal Is_SOF : STD_LOGIC;
signal Is_EOF : STD_LOGIC;
signal In_Ack_i : STD_LOGIC;
signal Out_Valid_i : STD_LOGIC;
signal DiscardFrame : STD_LOGIC;
signal ChannelPointer_rst : STD_LOGIC;
signal ChannelPointer_en : STD_LOGIC;
signal ChannelPointer : STD_LOGIC_VECTOR(portS - 1 downto 0);
signal ChannelPointer_d : STD_LOGIC_VECTOR(portS - 1 downto 0) := (others => '0');
signal ChannelPointer_bin : UNSIGNED(log2ceilnz(portS) - 1 downto 0);
signal idx : T_CHANNEL_INDEX;
signal Out_Data_i : T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave)
signal Out_Meta_i : T_SLM(portS - 1 downto 0, META_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave)
begin
In_Ack_i <= slv_or(Out_Ack and ChannelPointer);
DiscardFrame <= slv_nor(DeMuxControl);
Is_SOF <= In_Valid and In_SOF;
Is_EOF <= In_Valid and In_EOF;
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
State <= ST_IDLE;
else
State <= NextState;
end if;
end if;
end process;
process(State, In_Ack_i, In_Valid, Is_SOF, Is_EOF, DiscardFrame, DeMuxControl, ChannelPointer_d)
begin
NextState <= State;
ChannelPointer_rst <= Is_EOF;
ChannelPointer_en <= '0';
ChannelPointer <= ChannelPointer_d;
In_Ack <= '0';
Out_Valid_i <= '0';
case State is
when ST_IDLE =>
ChannelPointer <= DeMuxControl;
if (Is_SOF = '1') then
if (DiscardFrame = '0') then
ChannelPointer_en <= '1';
In_Ack <= In_Ack_i;
Out_Valid_i <= '1';
NextState <= ST_DATAFLOW;
else
In_Ack <= '1';
NextState <= ST_DISCARD_FRAME;
end if;
end if;
when ST_DATAFLOW =>
In_Ack <= In_Ack_i;
Out_Valid_i <= In_Valid;
ChannelPointer <= ChannelPointer_d;
if (Is_EOF = '1') then
NextState <= ST_IDLE;
end if;
when ST_DISCARD_FRAME =>
In_Ack <= '1';
if (Is_EOF = '1') then
NextState <= ST_IDLE;
end if;
end case;
end process;
process(Clock)
begin
if rising_edge(Clock) then
if ((Reset or ChannelPointer_rst) = '1') then
ChannelPointer_d <= (others => '0');
else
if (ChannelPointer_en = '1') then
ChannelPointer_d <= DeMuxControl;
end if;
end if;
end if;
end process;
ChannelPointer_bin <= onehot2bin(ChannelPointer_d);
idx <= to_integer(ChannelPointer_bin);
In_Meta_rev <= get_row(Out_Meta_rev, idx);
genOutput : for i in 0 to portS - 1 generate
Out_Valid(i) <= Out_Valid_i and ChannelPointer(i);
assign_row(Out_Data_i, In_Data, i);
assign_row(Out_Meta_i, In_Meta, i);
Out_SOF(i) <= In_SOF;
Out_EOF(i) <= In_EOF;
end generate;
Out_Data <= Out_Data_i;
Out_Meta <= Out_Meta_i;
end architecture;
|
apache-2.0
|
faba838ce155e14227e84335e8501467
| 0.578388 | 3.121347 | false | false | false | false |
BogdanArdelean/FPWAM
|
hardware/src/hdl/FpwamPkg.vhd
| 1 | 9,581 |
library ieee;
library xil_defaultlib;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package FpwamPkg is
constant kWamAddressWidth : natural := 16;
constant kWamWordWidth : natural := 18;
constant kWamPdlAddressWidth : natural := 10;
constant kWamTrailAddressWidth : natural := 10;
constant kGPRAddressWidth : natural := 4;
constant kFunctorWidth : natural := 12;
constant kArityWidth : natural := kGPRAddressWidth;
constant kWamInstructionWidth : natural := 32;
constant kWamInstrMemWidth : natural := 10;
constant kWamHeapStart : std_logic_vector(kWamAddressWidth -1 downto 0) := (others=>'0');
constant kWamStackStart : std_logic_vector(kWamAddressWidth -1 downto 0) := std_logic_vector(to_unsigned(2**(kWamAddressWidth-1)+1, kWamAddressWidth));
-- Possible address inputs for memory (eg: MA_H_t => Memory Address from register H)
type mem_addr_input_t is (MA_H_t, MA_Hplus1_t, MA_deref_unit_t, MA_untag_deref_t, MA_bind_unit_1_t, MA_bind_unit_2_t,
MA_unify_unit_t, MA_stack_addr_t, MA_S_t, MA_addr_t, MA_Ep2orB_t, MA_newE_t, MA_newEp1_t,
MA_newEp2_t, MA_E_t, MA_Ep1_t, MA_newB_t, MA_newBNRi_t, MA_newBNRip1_t, MA_newBI_t, MA_newBIp1_t,
MA_B_t, MA_BI_t, MA_BIp1_t, MA_BNRI_t, MA_BNRIp1_t, MA_unwind_trail_t, MA_BImem_port1_t, MA_DFC_t);
-- Possible input sources for memory
type mem_port_input_t is ( MI_str_Hplus1_t, MI_constant_t, MI_GPR_t, MI_GPR2_t, MI_bind_unit_1_t, MI_bind_unit_2_t, MI_unify_unit_t,
MI_mem_port1_t, MI_mem_port2_t, MI_ref_H_t, MI_ref_addr_t, MI_E_t, MI_CP_t, MI_B_t, MI_TR_t, MI_NRAGRGS_t, MI_unwind_trail_t, MI_H_t, MI_dfc_t, MI_deref_t, MI_lis_Hplus1_t, MI_P_t);
-- Possible input sources for H register
type h_input_t is (HI_p1_t, HI_p2_t, HI_HB_t, HI_mem_port1_t, HI_mem_port2_t, HI_Hpconstant_t);
-- Possible input sources for S register
type s_input_t is (SI_untag_deref_p1_t, SI_p1_t, SI_untag_deref_t, SI_pconstant_t);
-- Possible input sources for P register
type p_input_t is (PI_pinstr_size_t, PI_p1_t, PI_CP_t, PI_instr_t, PI_mem_port1_t, PI_mem_port2_t, PI_PpI_t, PI_bmem_port1_t, PI_constant_t);
-- Possible input sources for E register
type e_input_t is (EI_newE_t, EI_mem_port1_t, EI_mem_port2_t);
-- Possible input sources for CP register
type cp_input_t is (CPI_P_t, CPI_mem_port1_t, CPI_mem_port2_t);
-- Possible input sources for B Register
type b_input_t is (BRI_newB_t, BRI_mem_port1_t, BRI_mem_port2_t);
-- Possible input sources for TR Register
type tr_input_t is (TRI_Trp1_t, TRI_mem_port1_t, TRI_mem_port2_t);
-- Possible input sources for HB Register
type hb_input_t is (HBI_H_t, HBI_mem_port1_t, HBI_mem_port2_t);
-- Possible input sources for NRARGS register
type nrargs_input_t is (NRARGSI_instr_t, NRARGSI_mem_port1_t, NRARGSI_mem_port2_t);
-- Possible input sources for General Purpose Registers
type GPR_input_t is (GPRI_ref_H_t, GPRI_str_H_t, GPRI_lis_H_t, GPRI_con_t, GPRI_mem_port1_t, GPRI_mem_port2_t, GPRI_ref_addr_t, GPRI_gpr2_t, GPRI_gpr1_t, GPRI_deref_t, GPRI_constant_t);
-- Possible input sources for General Purpose Registers address
type GPR_addr_input_t is (GPRA_instr_t, GPRA_I_t, GPRA_Ip1_t, GPRA_1_t);
-- Possible input sources for deref unit
type deref_input_t is (DI_GPR_t, DI_unify_unit_t, DI_EYnp2_t, DI_mem_port1_t);
-- Possible input sources for bind unit
type bind_input_t is (BI_deref_unit_t, BI_mem_port1_t, BI_unify_unit_t);
-- Possible input sources for trail unit
type trail_input_t is (TI_bind_output_t, TI_unwind_trail_t, TI_deref_t);
-- WAM execution modes
type wam_mode_t is (mode_write_t, mode_read_t);
-- Types of objects supported in WAM
type tag_t is (tag_str_t, tag_ref_t, tag_lis_t, tag_int_t);
-- Unify unit input
type unify_input_t is (UI_GPR_t, UI_mem_port1_t, UI_mem_port2_t);
-- Unify mem input
type unify_mem_sel_t is (sel_unify_t, sel_deref_t, sel_bind_t);
type instruction_t is (i_nop -- 000000
,i_put_structure_t -- 000001 put_structure p/n, Xm -> [INSTRNUM][Xm][p][n]
,i_put_variable_X_t -- 000010
,i_put_variable_Y_t -- 000011
,i_put_value_t -- 000100
,i_get_structure_t -- 000101
,i_get_variable_t -- 000110
,i_get_value_t -- 000111
,i_unify_variable_t -- 001000
,i_unify_value_t -- 001001
,i_call_t -- 001010
,i_proceed_t -- 001011
,i_allocate_t -- 001100
,i_deallocate_t -- 001101
,i_try_me_else_t -- 001110
,i_retry_me_else_t -- 001111
,i_trust_me_t -- 010000
,i_put_unsafe_value_t -- 010001
,i_put_list_t -- 010010
,i_put_constant_t -- 010011
,i_get_list_t -- 010100
,i_get_constant_t -- 010101
,i_unify_local_value_t -- 010110
,i_unify_constant_t -- 010111
,i_unify_void -- 011000
,i_try_t -- 011001
,i_retry_t -- 011010
,i_trust_t -- 011011
,i_execute_t -- 011100
,i_unify_structure_t -- 011101
,i_switch_on_term_t -- 011110
,i_fail_t -- 011111
,i_switch_on_int_str_t -- 100000
,i_unify_list_t -- 100001
);
constant kInstrDecodeWidth : integer := 6;
function fpwam_tag (word : std_logic_vector) return tag_t;
function fpwam_value (word : std_logic_vector) return std_logic_vector;
function fpwam_word (word : std_logic_vector; tag : tag_t) return std_logic_vector;
function fpwam_functor (word : std_logic_vector(kWamWordWidth -1 downto 0)) return std_logic_vector;
function fpwam_arity (word : std_logic_vector(kWamWordWidth -1 downto 0)) return std_logic_vector;
function fpwam_instr (word : std_logic_vector(31 downto 0)) return instruction_t;
function fpwam_instr_addr (word : std_logic_vector) return std_logic_vector;
function fpwam_instr_arity (word : std_logic_vector) return std_logic_vector;
function fpwam_var_on_stack (word : std_logic_vector) return boolean;
function fpwam_var_stack_addr(instr : std_logic_vector; E : std_logic_vector) return std_logic_vector;
function to_std_logic (bool : boolean) return std_logic;
end FpwamPkg;
package body FpwamPkg is
function fpwam_tag (word : std_logic_vector) return tag_t is
variable result : integer;
begin
result := to_integer(unsigned(word(kWamWordWidth -1 downto kWamWordWidth -2)));
return tag_t'val(result);
end function;
function fpwam_value (word: std_logic_vector) return std_logic_vector is
begin
return word(word'length - 3 downto 0);
end function;
function fpwam_word (word : std_logic_vector; tag : tag_t) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(tag_t'pos(tag),2)) & word;
end function;
function fpwam_functor (word : std_logic_vector(kWamWordWidth -1 downto 0)) return std_logic_vector is
begin
return word(word'length-1 downto word'length - kFunctorWidth+1);
end function;
function fpwam_arity (word : std_logic_vector(kWamWordWidth -1 downto 0)) return std_logic_vector is
begin
return word(kArityWidth-1 downto 0);
end function;
function fpwam_instr (word : std_logic_vector(31 downto 0)) return instruction_t is
variable result : integer;
begin
result := to_integer(unsigned(word(kWamInstructionWidth -1 downto kWamInstructionWidth - kInstrDecodeWidth)));
return instruction_t'val(result);
end function;
function fpwam_instr_addr (word : std_logic_vector) return std_logic_vector is
begin
return word(kWamInstrMemWidth + kGPRAddressWidth -1 downto kGPRAddressWidth);
end function;
function fpwam_instr_arity (word : std_logic_vector) return std_logic_vector is
begin
return word(kGPRAddressWidth -1 downto 0);
end function;
function fpwam_var_on_stack(word : std_logic_vector) return boolean is
begin
return word(22) = '1';
end function;
function fpwam_var_stack_addr(instr : std_logic_vector; E : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(kWamAddressWidth -1 downto 0);
begin
result := std_logic_vector(unsigned(instr(kGPRAddressWidth + kWamWordWidth - 1 downto kWamWordWidth)) + unsigned(E) + 2);
return result;
end function;
function to_std_logic(bool : boolean) return std_logic is
begin
if bool then
return('1');
else
return('0');
end if;
end function;
end package body;
|
apache-2.0
|
eb31dd319099a722265791eb692c3419
| 0.592005 | 3.357043 | false | false | false | false |
IAIK/ascon_hardware
|
caesar_hardware_api/HDL/AEAD/src_rtl_hs/CipherCore.vhd
| 1 | 2,944 |
-------------------------------------------------------------------------------
--! @file CipherCore.vhd
--! @brief Cipher core template module
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2016 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
entity CipherCore is
generic (
--! Reset behavior
G_ASYNC_RSTN : boolean := False; --! Async active low reset
--! Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data
G_KEY_SIZE : integer := 128; --! Key
G_TAG_SIZE : integer := 128; --! Tag
--! The number of bits required to hold block size expressed in
--! bytes = log2_ceil(G_DBLK_SIZE/8)
G_LBS_BYTES : integer := 4
);
port (
--! Global
clk : in std_logic;
rst : in std_logic;
--! PreProcessor (data)
key : in std_logic_vector(G_KEY_SIZE -1 downto 0);
bdi : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
--! PreProcessor (controls)
key_ready : out std_logic;
key_valid : in std_logic;
key_update : in std_logic;
decrypt : in std_logic;
bdi_ready : out std_logic;
bdi_valid : in std_logic;
bdi_type : in std_logic_vector(3 -1 downto 0);
bdi_partial : in std_logic;
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_size : in std_logic_vector(G_LBS_BYTES+1 -1 downto 0);
bdi_valid_bytes : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
--! PostProcessor
bdo : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_valid : out std_logic;
bdo_ready : in std_logic;
bdo_size : out std_logic_vector(G_LBS_BYTES+1 -1 downto 0);
msg_auth_done : out std_logic;
msg_auth_valid : out std_logic
);
end entity CipherCore;
architecture structure of CipherCore is
begin
end structure;
|
apache-2.0
|
4c57f030b96adac0df5435b97b49f88c
| 0.511897 | 4.052342 | false | false | false | false |
hoangt/PoC
|
tb/fifo/fifo_cc_got_tempput_tb.vhdl
| 2 | 5,862 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
--
-- Testbench: Testbench for a FIFO with Common Clock (cc) and Pipelined Interface
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
entity fifo_cc_got_tempput_tb is
end entity;
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.utils.all;
architecture tb of fifo_cc_got_tempput_tb is
-- component generics
constant D_BITS : positive := 8;
constant MIN_DEPTH : positive := 8;
constant ESTATE_WR_BITS : natural := 2;
constant FSTATE_RD_BITS : natural := 2;
constant ISPEC : string := "C C Cccccpppp pppp c ccc pp Cppppp ppp rp RpC";
constant OSPEC : string := "ggg gggggggg ggg G G";
-- Sequence Generator
constant GEN : bit_vector := "100110001";
constant ORG : std_logic_vector := "00000001";
-- Clock Control
signal rst : std_logic;
signal clk : std_logic := '0';
signal done : std_logic_vector(0 to 7) := (others => '0');
begin
clk <= not clk after 5 ns when done /= (done'range => '1') else '0';
genTests: for c in 0 to 7 generate
constant DATA_REG : boolean := c mod 2 > 0;
constant STATE_REG : boolean := c mod 4 > 1;
constant OUTPUT_REG : boolean := c mod 8 > 3;
signal put : std_logic;
signal putx : std_logic;
signal di : std_logic_vector(D_BITS-1 downto 0);
signal ful : std_logic;
signal commit : std_logic;
signal rollback : std_logic;
signal got : std_logic;
signal gotx : std_logic;
signal do : std_logic_vector(D_BITS-1 downto 0);
signal dox : std_logic_vector(D_BITS-1 downto 0);
signal vld : std_logic;
begin
putx <= put and not ful;
geni : entity PoC.comm_scramble
generic map (
GEN => GEN,
BITS => D_BITS
)
port map (
clk => clk,
set => rst,
din => ORG,
step => putx,
mask => di
);
process
begin
rst <= '1';
wait until rising_edge(clk);
rst <= '0';
for i in ISPEC'range loop
put <= '0';
commit <= '0';
rollback <= '0';
case ISPEC(i) is
when ' ' =>
wait until rising_edge(clk);
when 'p' =>
put <= '1';
wait until rising_edge(clk) and ful = '0';
when 'c' =>
commit <= '1';
wait until rising_edge(clk);
when 'C' =>
put <= '1';
commit <= '1';
wait until rising_edge(clk) and ful = '0';
when 'r' =>
rollback <= '1';
wait until rising_edge(clk);
when 'R' =>
put <= '1';
rollback <= '1';
wait until rising_edge(clk) and ful = '0';
when others =>
report "Illegal ISPEC." severity failure;
end case;
end loop;
put <= '0';
commit <= '0';
wait;
end process;
DUT : entity PoC.fifo_cc_got_tempput
generic map (
D_BITS => D_BITS,
MIN_DEPTH => MIN_DEPTH,
DATA_REG => DATA_REG,
STATE_REG => STATE_REG,
OUTPUT_REG => OUTPUT_REG,
ESTATE_WR_BITS => ESTATE_WR_BITS,
FSTATE_RD_BITS => FSTATE_RD_BITS
)
port map (
rst => rst,
clk => clk,
put => put,
din => di,
full => ful,
estate_wr => open,
commit => commit,
rollback => rollback,
got => got,
dout => do,
valid => vld,
fstate_rd => open
);
process
begin
for i in OSPEC'range loop
case OSPEC(i) is
when ' ' =>
got <= '0';
wait until rising_edge(clk);
when 'g' =>
got <= '1';
wait until rising_edge(clk) and vld = '1';
assert do = dox report "Test #"&integer'image(c)&": Output Mismatch." severity error;
when 'G' =>
got <= '1';
wait until rising_edge(clk) and vld = '1';
assert do /= dox report "Output Mismatch." severity error;
when others =>
report "Illegal ISPEC." severity failure;
end case;
end loop;
done(c) <= '1';
report "Test #"&integer'image(c)&" completed." severity note;
wait;
end process;
gotx <= got and vld;
geno : entity PoC.comm_scramble
generic map (
GEN => GEN,
BITS => D_BITS
)
port map (
clk => clk,
set => rst,
din => ORG,
step => gotx,
mask => dox
);
end generate;
end tb;
|
apache-2.0
|
3e7e03e462c8ae34d7a57c4fe9c26e37
| 0.4971 | 3.905396 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_emc_v3_0/a61d85ec/hdl/src/vhdl/pselect_f.vhd
| 4 | 8,765 |
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end imp;
|
gpl-3.0
|
014d3a7c2e7841c809088205cf9adb61
| 0.384826 | 5.858957 | false | false | false | false |
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/axi_interface.vhd
| 4 | 38,710 |
-------------------------------------------------------------------------------
-- axi_interface - entity / architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
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-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
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-- ** lead to death, personal injury or severe property or **
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-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: axi_interface.vhd
-- Version: v1.00a
-- Description: This module takes care of AXI protocol interface for AXI4
-- AXI4-Lite interfaces. This supports word access and INCR
-- burst only.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
--
-- AXI generics
-- C_S_AXI_PROTOCOL -- AXI protocol type
-- C_S_AXI_CTRL_BASEADDR -- Base address of the core
-- C_S_AXI_HIGHADDR -- Permits alias of address space
-- by making greater than xFFF
-- C_S_AXI_CTRL_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_CTRL_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
--
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System signals
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- IP2INTC_Irpt -- Device interrupt output to microprocessor
-- interrupt input or system interrupt controller.
-- AXI signals
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
--
-- IPIC signals
-- IP2Bus_Data -- IP to Bus data
-- IP2Bus_Error -- IP to Bus error
-- Bus2IP_Addr -- Bus to IP address
-- Bus2IP_Data -- Bus to IP data
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_Burst -- Bus to IP burst indicator
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity axi_interface is
generic (
-- -- System Parameter
C_FAMILY : string := "virtex6";
-- -- AXI Parameters
C_S_AXI_PROTOCOL : string := "AXI4";
C_S_AXI_ID_WIDTH : integer range 1 to 16 := 4;
C_S_AXI_ADDR_WIDTH : integer := 13;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32
);
port (
-- -- AXI Global System Signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- -- AXI Write Address Channel Signals
S_AXI_AWID : in std_logic_vector((C_S_AXI_ID_WIDTH-1) downto 0);
S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
-- -- AXI Write Channel Signals
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
-- -- AXI Write Response Channel Signals
S_AXI_BID : out std_logic_vector((C_S_AXI_ID_WIDTH-1) downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
-- -- AXI Read Address Channel Signals
S_AXI_ARID : in std_logic_vector((C_S_AXI_ID_WIDTH-1) downto 0);
S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
-- -- AXI Read Data Channel Signals
S_AXI_RID : out std_logic_vector((C_S_AXI_ID_WIDTH-1) downto 0);
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
IP2Bus_Data : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0 );
IP2Bus_Error : in std_logic;
Bus2IP_Addr : out std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_Data : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
Bus2IP_BE : out std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1)downto 0);
Bus2IP_Burst : out std_logic;
Bus2IP_RdCE : out std_logic;
Bus2IP_WrCE : out std_logic
);
end entity axi_interface;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture rtl of axi_interface is
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant ZEROES : std_logic_vector := X"00000000";
constant RST_ACTIVE : std_logic := '0';
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-----------------------------------------------------------------------------
signal bus2ip_addr_i : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal wid : std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
signal rid : std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
signal read_burst_cntr : std_logic_vector(7 downto 0);
signal bvalid : std_logic;
signal rvalid : std_logic;
signal read_req : std_logic;
signal write_req : std_logic;
signal awready_i : std_logic;
signal arready_i : std_logic;
signal arready_i1 : std_logic;
signal arready_i2 : std_logic;
signal s_axi_rlast_i : std_logic;
signal read_burst_length : std_logic_vector(7 downto 0);
signal rd_burst : std_logic;
signal rd_last : std_logic;
signal read_req_d1 : std_logic;
signal read_req_re : std_logic;
signal bus2ip_rdce_i : std_logic;
signal bus2ip_rdce_i_d1 : std_logic;
signal IP2Bus_Data_sampled: std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0 );
signal read_in_prog, write_in_prog : std_logic;
signal read_complete, write_complete : std_logic;
-----------------------------------------------------------------------------
-- Begin Architecture
-----------------------------------------------------------------------------
begin
-- AXI signal assignment
S_AXI_BRESP <= "00";
S_AXI_BVALID <= bvalid;
-- S_AXI_RDATA <= IP2Bus_Data;
--S_AXI_RVALID <= rvalid;
S_AXI_RRESP <= "00";
-- IPIC signal assignment
Bus2IP_Addr <= bus2ip_addr_i;
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_RdCE <= bus2ip_rdce_i;
Bus2IP_BE <= S_AXI_WSTRB;
Bus2IP_Burst <= '0';
AXI4_RDATA_GEN : if (C_S_AXI_PROTOCOL = "AXI4") generate
AXI_READ_OUTPUT_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
S_AXI_RDATA <= (others =>'0');
elsif S_AXI_RREADY = '1' then
S_AXI_RDATA <= IP2Bus_Data;
end if;
end if;
end process AXI_READ_OUTPUT_P;
end generate AXI4_RDATA_GEN;
AXI4LITE_RDATA_GEN : if (C_S_AXI_PROTOCOL = "AXI4LITE") generate
S_AXI_RDATA <= IP2Bus_Data_sampled;
end generate AXI4LITE_RDATA_GEN;
-- AWREADY is enabled only if valid write request and no read request
--awready_i <= (not write_req) and not (S_AXI_ARVALID or read_req or rvalid);
-- ARREADY is enabled only if valid read request and no current write request
--arready_i <= (not read_req) and not (write_req);
-----------------------------------------------------------------------------
-- Generate AXI4-MM interface if (C_S_AXI_PROTOCOL="AXI4")
-----------------------------------------------------------------------------
AXI4_MM_IF_GEN : if (C_S_AXI_PROTOCOL = "AXI4") generate
S_AXI_AWREADY <= awready_i;
S_AXI_WREADY <= write_req;
S_AXI_ARREADY <= arready_i;
Bus2IP_WrCE <= S_AXI_WVALID and write_req;
-- -----------------------------------------------------------------------
-- Process AXI_AWREADY_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
AXI_AWREADY_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
awready_i <='0';
elsif (S_AXI_AWVALID = '1' and awready_i = '1') then
awready_i <= '0';
else
awready_i <= (not write_req) and not (S_AXI_ARVALID or read_req or rvalid);
end if;
end if;
end process AXI_AWREADY_P;
-- -----------------------------------------------------------------------
-- Process AXI_ARREADY_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
AXI_ARREADY_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
arready_i <='0';
elsif (S_AXI_ARVALID = '1' and arready_i = '1') then
arready_i <= '0';
else
arready_i <= (not read_req) and not (S_AXI_AWVALID or write_req);
end if;
end if;
end process AXI_ARREADY_P;
-- -----------------------------------------------------------------------
-- Process AXI_READ_OUTPUT_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
--AXI_READ_OUTPUT_P: process (S_AXI_ACLK) is
--begin
-- if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
-- if (S_AXI_ARESETN=RST_ACTIVE) then
-- S_AXI_RDATA <= (others =>'0');
-- S_AXI_RVALID <='0';
-- elsif S_AXI_RREADY = '1' then
-- S_AXI_RDATA <= IP2Bus_Data;
-- S_AXI_RVALID <= rvalid;
-- end if;
-- end if;
--end process AXI_READ_OUTPUT_P;
AXI_READ_VALID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
S_AXI_RVALID <='0';
elsif S_AXI_RREADY = '1' then
S_AXI_RVALID <= rvalid;
end if;
end if;
end process AXI_READ_VALID_P;
AXI_READ_CE_DELAY_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
bus2ip_rdce_i_d1 <= '0';
else
bus2ip_rdce_i_d1 <= bus2ip_rdce_i;
end if;
end if;
end process AXI_READ_CE_DELAY_P;
AXI_READ_OUTPUT_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
IP2Bus_Data_sampled <= (others =>'0');
elsif bus2ip_rdce_i_d1 = '1' then
IP2Bus_Data_sampled <= IP2Bus_Data;
end if;
end if;
end process AXI_READ_OUTPUT_P;
-- AXI4 outputs
S_AXI_BID <= wid;
S_AXI_RID <= rid;
--S_AXI_RLAST <= s_axi_rlast_i and rvalid;
-- Read burst
rd_burst <= or_reduce(read_burst_length);
rd_last <= (s_axi_rlast_i and rd_burst) or (s_axi_rlast_i and S_AXI_RREADY);
s_axi_rlast_i <= '1' when read_burst_cntr = "00000000" else '0';
-- Read request on IPIC
bus2ip_rdce_i <= read_req_re or (read_req and S_AXI_RREADY);
-- AXI/IPIC Read request signal generation
read_req_re <= read_req and not read_req_d1;
-- -----------------------------------------------------------------------
-- Process AXI_READ_OUTPUT_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
AXI_READ_LAST_OUTPUT_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
S_AXI_RLAST <= '0';
elsif S_AXI_RREADY = '1' then
S_AXI_RLAST <= s_axi_rlast_i and rvalid;
end if;
end if;
end process AXI_READ_LAST_OUTPUT_P;
-- -----------------------------------------------------------------------
-- Process WRITE_REQUEST_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
WRITE_REQUEST_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
write_req <= '0';
elsif (S_AXI_AWVALID = '1' and awready_i = '1') then
write_req <= '1';
elsif (S_AXI_WVALID = '1' and S_AXI_WLAST = '1') then
write_req <= '0';
else
write_req <= write_req;
end if;
end if;
end process WRITE_REQUEST_P;
-- -----------------------------------------------------------------------
-- Process READ_REQUEST_P to generate read request
-- -----------------------------------------------------------------------
READ_REQUEST_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
read_req <= '0';
elsif (S_AXI_ARVALID = '1' and arready_i = '1') then
read_req <= '1';
elsif (s_axi_rlast_i = '1') then
read_req <= '0';
end if;
end if;
end process READ_REQUEST_P;
-- -----------------------------------------------------------------------
-- Process ADDR_GEN_P to generate bus2ip_addr for read/write
-- -----------------------------------------------------------------------
ADDR_GEN_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
bus2ip_addr_i <= (others=>'0');
elsif (S_AXI_ARVALID = '1' and arready_i = '1') then
bus2ip_addr_i <= S_AXI_ARADDR;
elsif (bus2ip_rdce_i='1' and rd_burst='1') then
bus2ip_addr_i <= bus2ip_addr_i + 4;
elsif (S_AXI_AWVALID = '1' and awready_i = '1') then
bus2ip_addr_i <= S_AXI_AWADDR;
elsif (S_AXI_WVALID = '1' and write_req='1') then
bus2ip_addr_i <= bus2ip_addr_i + 4;
end if;
end if;
end process ADDR_GEN_P;
-- -----------------------------------------------------------------------
-- Process WRITE_ID_P to generate Write response ID on AXI
-- -----------------------------------------------------------------------
WRITE_ID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
wid <= (others=>'0');
elsif (S_AXI_AWVALID = '1' and awready_i = '1') then
wid <= S_AXI_AWID;
end if;
end if;
end process WRITE_ID_P;
-- -----------------------------------------------------------------------
-- Process WRITE_BVALID_P to generate Write Response valid
-- -----------------------------------------------------------------------
WRITE_BVALID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
bvalid <= '0';
elsif (S_AXI_WLAST = '1' and write_req = '1' and S_AXI_WVALID = '1') then
bvalid <= '1';
elsif (S_AXI_BREADY = '1') then
bvalid <= '0';
end if;
end if;
end process WRITE_BVALID_P;
-- -----------------------------------------------------------------------
-- Process READ_ID_P to generate read ID
-- -----------------------------------------------------------------------
READ_ID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
rid <= (others=>'0');
elsif (S_AXI_ARVALID = '1' and arready_i = '1') then
rid <= S_AXI_ARID;
end if;
end if;
end process READ_ID_P;
-- -----------------------------------------------------------------------
-- Process READ_BURST_CNTR_P to generate rdlast signal after completion
-- of burst
-- -----------------------------------------------------------------------
READ_BURST_CNTR_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
read_burst_cntr <= (others=>'0');
elsif (S_AXI_ARVALID = '1' and arready_i = '1') then
read_burst_cntr <= S_AXI_ARLEN;
elsif (rvalid = '1' and S_AXI_RREADY='1') then
read_burst_cntr <= read_burst_cntr-'1';
end if;
end if;
end process READ_BURST_CNTR_P;
-- -----------------------------------------------------------------------
-- Process READ_BURST_LENGTH_P to latch the burst length for read xfer
-- -----------------------------------------------------------------------
READ_BURST_LENGTH_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
read_burst_length <= (others=>'0');
elsif (S_AXI_ARVALID = '1' and arready_i = '1') then
read_burst_length <= S_AXI_ARLEN;
end if;
end if;
end process READ_BURST_LENGTH_P;
-- -----------------------------------------------------------------------
-- Process READ_RVALID_P to generate Read valid
-- -----------------------------------------------------------------------
READ_RVALID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
rvalid <= '0';
elsif (s_axi_rlast_i = '1' and S_AXI_RREADY='1' and rd_burst='1') then
rvalid <= '0';
elsif (read_req = '1') then
rvalid <= '1';
elsif (s_axi_rlast_i = '1' and S_AXI_RREADY='1') then
rvalid <= '0';
end if;
end if;
end process READ_RVALID_P;
-- -----------------------------------------------------------------------
-- Process READ_REQUEST_REG_P to generate Read request on IPIC
-- -----------------------------------------------------------------------
READ_REQUEST_REG_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
read_req_d1 <= '0';
else
read_req_d1 <= read_req;
end if;
end if;
end process READ_REQUEST_REG_P;
--------------------------
end generate AXI4_MM_IF_GEN;
---------------------------
-----------------------------------------------------------------------------
-- Generate AXI4-Lite interface if (C_S_AXI_PROTOCOL="AXI4LITE")
-----------------------------------------------------------------------------
AXI4_LITE_IF_GEN : if (C_S_AXI_PROTOCOL = "AXI4LITE") generate
S_AXI_AWREADY <= awready_i;
S_AXI_WREADY <= awready_i;
S_AXI_ARREADY <= arready_i;
Bus2IP_WrCE <= S_AXI_WVALID and write_in_prog; --and write_req;
-- -----------------------------------------------------------------------
-- Process AXI_AWREADY_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
AXI_AWREADY_P1: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
write_in_prog <='0';
read_in_prog <='0';
elsif ((rvalid = '1' and S_AXI_RREADY = '1') or (bvalid = '1' and S_AXI_BREADY = '1')) then -- and write_complete = '1') then
-- elsif (read_complete = '1' or (bvalid = '1' and S_AXI_BREADY = '1')) then -- and write_complete = '1') then
write_in_prog <='0';
read_in_prog <='0';
elsif (S_AXI_ARVALID = '1' and write_in_prog = '0') then
read_in_prog <='1';
elsif ((S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') and read_in_prog = '0') then
write_in_prog <='1';
end if;
end if;
end process AXI_AWREADY_P1;
-- -----------------------------------------------------------------------
-- Process AXI_AWREADY_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
AXI_AWREADY_P2: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
awready_i <='0';
elsif (S_AXI_WVALID = '1' and write_in_prog = '1' and awready_i = '0') then
awready_i <= '1';
else
awready_i <= '0'; --(not write_req) and not (S_AXI_ARVALID or read_req or rvalid);
end if;
end if;
end process AXI_AWREADY_P2;
-- -----------------------------------------------------------------------
-- Process WRITE_BVALID_P to generate Write Response valid
-- -----------------------------------------------------------------------
WRITE_BVALID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
bvalid <= '0';
elsif (awready_i = '1') then
bvalid <= '1';
elsif (S_AXI_BREADY = '1') then
bvalid <= '0';
end if;
end if;
end process WRITE_BVALID_P;
WRITE_BVALID_P2: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
write_complete <= '0';
elsif (bvalid = '1' and S_AXI_BREADY = '1' and write_complete = '0') then
write_complete <= '1';
else
write_complete <= '0';
end if;
end if;
end process WRITE_BVALID_P2;
-- -----------------------------------------------------------------------
-- Process AXI_ARREADY_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
AXI_ARREADY_P1: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
arready_i1 <='0';
elsif (read_in_prog = '1') then -- and rvalid = '1') then --S_AXI_ARVALID = '1' and read_complete = '1' and arready_i = '0') then
arready_i1 <= '1';
else
arready_i1 <= '0';
end if;
end if;
end process AXI_ARREADY_P1;
AXI_ARREADY_P2: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
arready_i2 <='0';
else
arready_i2 <= arready_i1;
end if;
end if;
end process AXI_ARREADY_P2;
arready_i <= arready_i1 and (not arready_i2);
-- AXI_READ_VALID_P1: process (S_AXI_ACLK) is
-- begin
-- if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
-- if (S_AXI_ARESETN=RST_ACTIVE) then
-- S_AXI_RVALID <='0';
-- elsif S_AXI_RREADY = '1' then
S_AXI_RVALID <= rvalid;
-- end if;
-- end if;
-- end process AXI_READ_VALID_P1;
AXI_READ_CE_DELAY_P1: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
bus2ip_rdce_i_d1 <= '0';
else
bus2ip_rdce_i_d1 <= bus2ip_rdce_i;
end if;
end if;
end process AXI_READ_CE_DELAY_P1;
AXI_READ_OUTPUT_P1: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
IP2Bus_Data_sampled <= (others =>'0');
elsif bus2ip_rdce_i_d1 = '1' then
IP2Bus_Data_sampled <= IP2Bus_Data;
end if;
end if;
end process AXI_READ_OUTPUT_P1;
-- AXI4 outputs
--S_AXI_BID <= (others => '0');
--S_AXI_RID <= (others => '0');
S_AXI_RLAST <= rvalid;
S_AXI_BID <= wid;
S_AXI_RID <= rid;
wid <= (others => '0');
rid <= (others => '0');
-- -----------------------------------------------------------------------
-- Process WRITE_REQUEST_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
-- WRITE_REQUEST_P: process (S_AXI_ACLK) is
-- begin
-- if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
-- if (S_AXI_ARESETN=RST_ACTIVE) then
-- write_req <= '0';
-- elsif (S_AXI_AWVALID = '1' and awready_i = '1') then
-- write_req <= '1';
-- elsif (write_req = '1' and S_AXI_WVALID = '1') then
-- write_req <= '0';
-- else
-- write_req <= write_req;
-- end if;
-- end if;
-- end process WRITE_REQUEST_P;
-- -----------------------------------------------------------------------
-- Process READ_REQUEST_P to generate read request
-- -----------------------------------------------------------------------
READ_REQUEST_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then -- or read_in_prog = '0') then
read_req <= '0';
elsif (S_AXI_ARVALID = '1' and bus2ip_rdce_i_d1 = '0') then
read_req <= '1';
elsif (S_AXI_RREADY = '1') then
read_req <= '0';
end if;
end if;
end process READ_REQUEST_P;
-- -----------------------------------------------------------------------
-- Process ADDR_GEN_P to generate bus2ip_addr for read/write
-- -----------------------------------------------------------------------
ADDR_GEN_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
bus2ip_addr_i <= (others=>'0');
elsif (S_AXI_ARVALID = '1' and write_in_prog = '0') then --read_in_prog = '1') then
bus2ip_addr_i <= S_AXI_ARADDR;
elsif (S_AXI_AWVALID = '1' and read_in_prog = '0') then --write_in_prog = '1') then
bus2ip_addr_i <= S_AXI_AWADDR;
end if;
end if;
end process ADDR_GEN_P;
-- -----------------------------------------------------------------------
-- Process READ_RVALID_P to generate Read valid
-- -----------------------------------------------------------------------
READ_RVALID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
rvalid <= '0';
elsif (S_AXI_RREADY='1' and rvalid = '1') then
rvalid <= '0';
elsif (read_req = '1' and bus2ip_rdce_i_d1 = '1') then
rvalid <= '1';
end if;
end if;
end process READ_RVALID_P;
READ_RVALID_P1: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
read_complete <= '0';
elsif ((rvalid = '1' and S_AXI_RREADY = '1')) then --(arready_i = '1') then
read_complete <= '1';
else
read_complete <= '0';
end if;
end if;
end process READ_RVALID_P1;
-- -- -----------------------------------------------------------------------
-- -- Process WRITE_ID_P to generate Write response ID on AXI
-- -- -----------------------------------------------------------------------
-- WRITE_ID_P: process (S_AXI_ACLK) is
-- begin
-- if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
-- if (S_AXI_ARESETN=RST_ACTIVE) then
-- wid <= (others=>'0');
-- elsif (S_AXI_AWVALID = '1' and awready_i = '1') then
-- wid <= S_AXI_AWID;
-- end if;
-- end if;
-- end process WRITE_ID_P;
--
-- -- Process READ_ID_P to generate read ID
-- -- -----------------------------------------------------------------------
-- READ_ID_P: process (S_AXI_ACLK) is
-- begin
-- if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
-- if (S_AXI_ARESETN=RST_ACTIVE) then
-- rid <= (others=>'0');
-- elsif (S_AXI_ARVALID = '1' and arready_i = '1') then
-- rid <= S_AXI_ARID;
-- end if;
-- end if;
-- end process READ_ID_P;
-- Read request on IPIC
bus2ip_rdce_i <= read_in_prog; --read_req;
--------------------------
end generate AXI4_LITE_IF_GEN;
---------------------------
end architecture rtl;
--
|
gpl-3.0
|
d0af6f48147789ac6b152b69e1472406
| 0.415681 | 4.104114 | false | false | false | false |
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