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int64 1
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int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
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float64 1.51
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| autogenerated
bool 1
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classes | has_no_keywords
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class | has_few_assignments
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class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
Xero-Hige/LuGus-VHDL
|
TP3/addition/base_complementer/base_complementer.vhd
| 1 | 793 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity base_complementer is
generic(
TOTAL_BITS : natural := 16
);
port(
number_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
number_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end base_complementer;
architecture base_complementer_arq of base_complementer is
begin
process (number_in) is
variable negated_in : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
variable tmp_out : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
begin
negated_in := not number_in;
tmp_out := std_logic_vector(unsigned(negated_in) + 1);
number_out <= tmp_out;
end process;
end architecture;
|
gpl-3.0
|
d0d1295be869a7758143c194e4d3c887
| 0.638083 | 3.210526 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/Contador.vhd
| 2 | 1,016 |
library IEEE;
use IEEE.std_logic_1164.all;
entity contador is
port(
rst_c: in std_logic;
clk_c: in std_logic;
enable_c: in std_logic;
--Q: out std_logic_vector(1 downto 0);
q1_c: out std_logic;
q0_c: out std_logic
);
end;
architecture contador_func of contador is
component FFD is
port(
enable: in std_logic;
reset: in std_logic;
clk: in std_logic;
Q: out std_logic;
D: in std_logic
);
end component;
signal q0_c_aux,q1_c_aux,d0_c_aux,d1_c_aux:std_logic;
begin
ffd0: FFD port map( --nombres del FFD : enable,reset,clk,Q,D
clk => clk_c,
enable => enable_c,
reset => rst_c, --Siempre van a la izquierda los puertos de los componentes
D => d0_c_aux,
Q => q0_c_aux
);
q0_c <= q0_c_aux;
ffd1: FFD port map(
clk=> clk_c,
enable => enable_c,
reset => rst_c,
D => d1_c_aux,
Q => q1_c_aux
);
q1_c <= q1_c_aux;
d0_c_aux <= not(q0_c_aux);
d1_c_aux <= q1_c_aux xor q0_c_aux;
end architecture;
|
gpl-3.0
|
b7f905287cd1362a24c34e2ef1cb6e84
| 0.581693 | 2.368298 | false | false | false | false |
jgibbard/fir_filter
|
fir_filter_tb.vhd
| 1 | 3,995 |
---------------------------------------------------------------------------
-- Project : FIR Filter
-- Author : James Gibbard ([email protected])
-- Date : 2017-03-25
-- File : fir_filter_tb.vhd
---------------------------------------------------------------------------
-- Description :
---------------------------------------------------------------------------
-- Change Log
-- Version 0.0.1 : Initial version
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use STD.textio.all;
use ieee.std_logic_textio.all;
use work.signed_array_pkg.all;
entity fir_filter_tb is
end fir_filter_tb;
architecture testbench of fir_filter_tb is
constant coeficient_width : integer := 16;
constant data_width : integer := 16;
constant num_taps : integer := 15;
signal clk : std_logic;
signal rst : std_logic;
signal en_in : std_logic;
signal data_in : signed(data_width - 1 downto 0);
signal taps : signed_array_15 := (X"0001", X"0002", X"0003", X"0004", X"0005", X"0006",X"0007", X"0008", X"0009", X"000A", X"000B", X"000C", X"000D", X"000E", X"000F");
signal data_valid_in : std_logic;
signal data_out : signed(data_width - 1 downto 0);
signal data_valid_out : std_logic;
signal ready_out : std_logic;
signal scale_factor : unsigned(5 downto 0) := (others => '0');
signal counter : unsigned(3 downto 0);
file test_vector_file : text;
constant clk_period : time := 20 ns;
begin
uut : entity work.fir_filter
generic map (
data_in_width_g => data_width,
data_out_width_g => data_width,
num_taps_g => num_taps
)
port map (
clk => clk,
rst => rst,
en_in => en_in,
data_in => data_in,
taps_in => taps,
scale_factor_in => scale_factor,
data_valid_in => data_valid_in,
data_out => data_out,
data_valid_out => data_valid_out,
ready_out => ready_out
);
--Make a clock signal with a 50% duty cycle
clk_gen_p : process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
--Take module out of reset
enable_p : process
begin
rst <= '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
rst <= '0';
wait;
end process;
stimulus_p : process(clk)
variable row : line;
variable test_vector : integer := 0;
begin
file_open(test_vector_file, "test.txt", read_mode);
if rising_edge(clk) then
if rst = '1' then
data_in <= (others => '0');
data_valid_in <= '0';
counter <= (others => '0');
else
if counter = 15 then
--if ready_out = '1' then
if(not endfile(test_vector_file)) then
readline(test_vector_file,row);
end if;
read(row, test_vector);
data_in <= to_signed(test_vector, data_width);
data_valid_in <= '1';
else
data_valid_in <= '0';
data_in <= (others => '0');
end if;
if ready_out = '1' then
counter <= counter + 1;
end if;
end if;
end if;
end process;
end testbench;
|
unlicense
|
7362131ba805c822ba2d704102b07f41
| 0.418773 | 4.209694 | false | true | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/TP1-Contador/led_enabler_tb.vhd
| 1 | 1,057 |
library ieee;
use ieee.std_logic_1164.all;
entity led_enabler_tb is
end;
architecture led_enabler_tb_func of led_enabler_tb is
signal signal_in_a : std_logic:='0';
signal signal_in_b : std_logic:='0';
signal signal_in_c : std_logic:='0';
signal signal_in_d : std_logic:='0';
signal enabler_in : std_logic_vector (3 downto 0);
signal enabler_out : std_logic_vector(7 downto 0);
component led_enabler is
port(
enabler_input : in std_logic_vector(3 downto 0);
enabler_output : out std_logic_vector(7 downto 0)
);
end component;
begin
signal_in_a <= not signal_in_a after 10 ns;
signal_in_b <= not signal_in_b after 20 ns;
signal_in_c <= not signal_in_c after 40 ns;
signal_in_d <= not signal_in_d after 80 ns;
enabler_in(0) <= signal_in_a;
enabler_in(1) <= signal_in_b;
enabler_in(2) <= signal_in_c;
enabler_in(3) <= signal_in_d;
led_enablerMap: led_enabler
port map(
enabler_input => enabler_in,
enabler_output => enabler_out
);
end architecture;
|
gpl-3.0
|
019363287cc15ec584d584a0454b3b13
| 0.635762 | 2.689567 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/ram_generator_matrix.vhd
| 1 | 4,045 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: QDGoppa
-- Module Name: RAM Generator Matrix
-- Project Name: QDGoppa
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavior of a RAM Bank behavioral, where it can output
-- number_of_memories at once, with different address for each memory. Only used for tests.
--
-- The circuits parameters
--
-- number_of_memories :
--
-- Number of memories in the RAM Bank
--
-- ram_address_size :
-- Address size of the RAM bank used on the circuit.
--
-- ram_word_size :
-- The size of internal word on the RAM Bank.
--
-- file_ram_word_size :
-- The size of the word used in the file to be loaded on the RAM Bank.(ARCH: FILE_LOAD)
--
-- load_file_name :
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
-- The name of the file to be used to dump the memory.
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
entity ram_generator_matrix is
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (((ram_address_size)*(number_of_memories) - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end ram_generator_matrix;
architecture simple of ram_generator_matrix is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
for I in ramtype'range loop
memory_ram(I) <= rst_value;
end loop;
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))) <= data_in(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
for index in 0 to (number_of_memories - 1) loop
data_out(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index)))));
end loop;
end if;
end process;
end simple;
|
bsd-2-clause
|
4ecf6b15a346c3e0c4f44c19fd3bc87e
| 0.54314 | 3.624552 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/counter_rst_nbits.vhd
| 1 | 1,748 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_rst_n_bits
-- Module Name: Counter_rst_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Counter of size bits with reset signal, that only increments when ce equals to 1.
-- The reset is synchronous and the value loaded during reset is defined by reset_value.
--
-- The circuits parameters
--
-- size :
--
-- The size of the counter in bits.
--
-- increment_value :
--
-- The amount will be incremented each cycle.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_rst_nbits is
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end counter_rst_nbits;
architecture Behavioral of counter_rst_nbits is
signal internal_value : UNSIGNED((size - 1) downto 0);
begin
process(clk, ce, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= unsigned(rst_value);
elsif(ce = '1') then
internal_value <= internal_value + to_unsigned(increment_value, internal_value'Length);
else
null;
end if;
end if;
end process;
q <= std_logic_vector(internal_value);
end Behavioral;
|
bsd-2-clause
|
4508cb8c61641f3eee5f4e07aab27513
| 0.60984 | 3.427451 | false | false | false | false |
laurivosandi/hdl
|
arithmetic/src/goldschmidt_division.vhd
| 1 | 3,855 |
library ieee;
use ieee.STD_LOGIC_1164.all;
use std.textio.all;
entity goldschmidt_division is
port (
a : in std_logic_vector (15 downto 0); -- Dividend
b : in std_logic_vector (15 downto 0); -- Divisor
c : in std_logic_vector (2 downto 0); -- Iteration count
clk : in std_logic;
rst : in std_logic;
q : out std_logic_vector (15 downto 0) -- Quotinent
);
end goldschmidt_division;
architecture behavioral of goldschmidt_division is
-- Booth multiplier
component multiplier is
port (
a : in std_logic_vector (15 downto 0);
b : in std_logic_vector (15 downto 0);
m : out std_logic_vector (31 downto 0)
);
end component;
-- Carry lookahead adder
component cla is
generic (N : integer := 16);
port (
a : in std_logic_vector (N-1 downto 0);
b : in std_logic_vector (N-1 downto 0);
ci : in std_logic;
s : out std_logic_vector (N-1 downto 0);
co : out std_logic
);
end component;
-- Reciprocal approximator
component reciprocal is
port (
b : in std_logic_vector (15 downto 0);
r : out std_logic_vector (15 downto 0)
);
end component;
-- Counter register
signal counter : std_logic_vector(2 downto 0);
signal counter_decremented : std_logic_vector(2 downto 0);
-- Intermediate output signals
signal nop : std_logic_vector(31 downto 0);
signal dop : std_logic_vector(31 downto 0);
signal dos : std_logic_vector(15 downto 0);
signal don : std_logic_vector(15 downto 0);
-- Current iteration outputs
signal no : std_logic_vector(15 downto 0);
signal do : std_logic_vector(15 downto 0);
signal fo : std_logic_vector(15 downto 0);
-- Previous iteration registers
signal np : std_logic_vector(15 downto 0);
signal dp : std_logic_vector(15 downto 0);
signal fp : std_logic_vector(15 downto 0);
-- Initial reciprocal
signal ir : std_logic_vector(15 downto 0);
begin
-- Dump output process
dump_proc: process
file OUTPUT_FILE : text open write_mode is "dump.txt";
variable output_line: LINE;
begin
for i in 1 to 10 loop
wait until rising_edge(clk);
write(output_line,to_bitvector(no));
writeline(output_file,output_line);
end loop;
end process;
-- Registers for N, D and F
sync_process: process(clk, counter)
begin
if (rst = '1') then
counter <= c;
np <= a;
dp <= b;
fp <= ir;
elsif rising_edge(clk) then
counter <= counter_decremented;
np <= no;
dp <= do;
fp <= fo;
end if;
end process;
-- Have initial reciprocal always ready to go
initial_reciprocal: reciprocal port map(b=>b, r=>ir);
-- Decrement iteration counter
counter_decremented <=
"110" when counter = "111" else
"101" when counter = "110" else
"100" when counter = "101" else
"011" when counter = "100" else
"010" when counter = "011" else
"001" when counter = "010" else
"000";
-- Multiply input F and input N
n_stage: multiplier port map(a=>fp, b=>np, m=>nop);
-- Multiply input F and input D
d_stage: multiplier port map(a=>fp, b=>dp, m=>dop);
-- Round output N
no <= nop(23 downto 8);
-- Round output D
dos <= dop(23 downto 8);
-- Find two's complement of output D
don <= not dos;
-- Subtract D from 2
f_stage: cla port map(a=>"0000001000000000", b=>don, ci=>'1', s=>fo);
do <= dos;
-- Bind outputs
q <= no;
end behavioral;
|
mit
|
8d34ccaefbcdbdb7e1ea9aab5911a0e3
| 0.561349 | 3.851149 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/stage_polynomial_calc.vhd
| 1 | 3,067 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Stage_Polynomial_Calc
-- Module Name: Stage_Polynomial_Calc
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 3rd step in Goppa Code Decoding.
--
-- This circuit is the stage for pipeline_polynomial_calc. The pipeline is composed of
-- an arbitrary number of this stages.
--
-- For the computation this circuit applies the school book algorithm of powering x
-- and multiplying by the respective polynomial coefficient and adding into the accumulator.
-- This method is not appropriate for this computation, so in stage_polynomial_calc_v2
-- Horner scheme is applied to reduce circuits costs.
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- Dependencies:
-- VHDL-93
--
-- mult_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity stage_polynomial_calc is
Generic(gf_2_m : integer range 1 to 20 := 11);
Port (
value_x : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
value_x_pow : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
value_polynomial_coefficient : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
new_value_x_pow : out STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0)
);
end stage_polynomial_calc;
architecture Behavioral of stage_polynomial_calc is
component mult_gf_2_m
Generic(gf_2_m : integer range 1 to 20 := 11);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal mult_x_a : STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
signal mult_x_b : STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
signal mult_x_o : STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
signal mult_sigma_a : STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
signal mult_sigma_b : STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
signal mult_sigma_o : STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
signal sigma_i_1 : STD_LOGIC_VECTOR ((gf_2_m - 1) downto 0);
begin
mult_x : mult_gf_2_m
Generic Map (gf_2_m => gf_2_m)
Port Map (
a => mult_x_a,
b => mult_x_b,
o => mult_x_o
);
mult_sigma : mult_gf_2_m
Generic Map (gf_2_m => gf_2_m)
Port Map (
a => mult_sigma_a,
b => mult_sigma_b,
o => mult_sigma_o
);
mult_x_a <= value_x;
mult_x_b <= value_x_pow;
mult_sigma_a <= value_polynomial_coefficient;
mult_sigma_b <= value_x_pow;
sigma_i_1 <= mult_sigma_o;
new_value_x_pow <= mult_x_o;
new_value_acc <= sigma_i_1 xor value_acc;
end Behavioral;
|
bsd-2-clause
|
adac47c17a20cf26eba68cb82a0d021a
| 0.625367 | 2.915399 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-LuGus/TP2-Voltimetro/FFD_array.vhd
| 1 | 734 |
library IEEE;
use IEEE.std_logic_1164.all;
entity FFD_Array is
generic (
SIZE: natural := 12
);
port(
enable: in std_logic;
reset: in std_logic;
clk: in std_logic;
Q: out std_logic_vector(SIZE-1 downto 0);
D: in std_logic_vector(SIZE-1 downto 0)
);
end;
architecture FFD_Array_Funct of FFD_Array is
begin
--Q <= "001100110011";--'1' then (others => '1');
process(enable, clk, reset)
begin
for i in 0 to SIZE-1 loop
if reset = '1' then
Q(i) <= '0';
elsif rising_edge(clk) then
if enable = '1' then
Q(i) <= D(i);
end if; --No va else para considerar todos los casos porque asi deja el valor anterior de Q.
end if;
end loop;
end process;
end;
|
gpl-3.0
|
ba2f7ee3e40d39b07cb14c6d6d6b9eef
| 0.599455 | 2.801527 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/multiplication/number_splitter/number_splitter_tb.vhd
| 2 | 2,135 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity number_splitter_tb is
end entity;
architecture number_splitter_tb_arq of number_splitter_tb is
signal number_in: std_logic_vector(22 downto 0);
signal sign_out: std_logic;
signal exp_out: std_logic_vector(5 downto 0);
signal mant_out: std_logic_vector(15 downto 0);
component number_splitter is
generic(
TOTAL_BITS:natural := 23;
EXP_BITS:natural := 6);
port (
number_in: in std_logic_vector(TOTAL_BITS-1 downto 0);
sign_out: out std_logic;
exp_out: out std_logic_vector(EXP_BITS-1 downto 0);
mant_out: out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0)
);
end component;
for number_splitter_0: number_splitter use entity work.number_splitter;
begin
number_splitter_0: number_splitter port map(
number_in => number_in,
sign_out => sign_out,
exp_out => exp_out,
mant_out => mant_out
);
process
type pattern_type is record
n : std_logic_vector(22 downto 0); --input number
s : std_logic; --output sign
m : std_logic_vector(15 downto 0); --output mantisa
e : std_logic_vector(5 downto 0); --output exponent
end record;
-- The patterns to apply.
type pattern_array is array (natural range<>) of pattern_type;
constant patterns : pattern_array := (
("11111111111111111111111", '1', "1111111111111111", "111111"),
("00000000000000000000000", '0', "0000000000000000", "000000"),
("10101010101010101010101", '1', "0101010101010101", "010101")
);
begin
for i in patterns'range loop
-- Set the inputs.
number_in <= patterns(i).n;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert sign_out = patterns(i).s report "BAD SIGN: " & std_logic'image(sign_out) severity error;
assert mant_out = patterns(i).m report "BAD MANTISSA: " & integer'image(to_integer(unsigned(mant_out))) severity error;
assert exp_out = patterns(i).e report "BAD EXP: " & integer'image(to_integer(unsigned(exp_out))) severity error;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
23782c92d8674a4431daeb4791324ebc
| 0.67822 | 3.259542 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/sign_based_complementer/sign_based_complementer_tb.vhd
| 1 | 2,050 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sign_based_complementer_tb is
end entity;
architecture sign_based_complementer_arq of sign_based_complementer_tb is
signal sign_1_in : std_logic := '0';
signal sign_2_in : std_logic := '0';
signal man_in : std_logic_vector(15 downto 0);
signal man_out : std_logic_vector(15 downto 0);
component sign_based_complementer is
generic(
BITS : natural := 16
);
port(
sign_1_in : in std_logic;
sign_2_in : in std_logic;
man_in : in std_logic_vector(BITS - 1 downto 0);
man_out : out std_logic_vector(BITS -1 downto 0)
);
end component;
for sign_based_complementer_0 : sign_based_complementer use entity work.sign_based_complementer;
begin
sign_based_complementer_0 : sign_based_complementer
generic map(BITS => 16)
port map(
sign_1_in => sign_1_in,
sign_2_in => sign_2_in,
man_in => man_in,
man_out => man_out
);
process
type pattern_type is record
s1 : std_logic;
s2 : std_logic;
mi : std_logic_vector(15 downto 0);
mo : std_logic_vector(15 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
('0', '0', "0000000000000000", "0000000000000000"),
('0', '1', "0000000000000000", "0000000000000000"),
('1', '0', "0000000000000000", "0000000000000000"),
('1', '1', "0000000000000000", "0000000000000000"),
('0', '1', "0000000000000001", "1111111111111111"),
('1', '1', "0000000000000001", "0000000000000001"),
('1', '0', "0000000000000001", "1111111111111111")
);
begin
for i in patterns'range loop
-- Set the inputs.
sign_1_in <= patterns(i).s1;
sign_2_in <= patterns(i).s2;
man_in <= patterns(i).mi;
wait for 1 ns;
assert patterns(i).mo = man_out report "BAD COMPLEMENT, GOT: " & integer'image(to_integer(signed(man_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
0869bc73094cc0403fcc07c565563a2b
| 0.652683 | 2.997076 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/registry/registry.vhd
| 1 | 698 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity registry is
generic(TOTAL_BITS : integer := 32);
port(
enable: in std_logic := '0';
reset: in std_logic := '0';
clk: in std_logic := '0';
D: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
Q: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end;
architecture registry_arq of registry is
begin
process(clk, reset, enable, D)
begin
if reset = '1' then
Q <= (others => '0');
elsif rising_edge(clk) then
if enable = '1' then
Q <= D;
end if; --No va else para considerar todos los casos porque asi deja el valor anterior de Q.
end if;
end process;
end;
|
gpl-3.0
|
f2ded20277c1701d98c5465214eed29f
| 0.636103 | 2.803213 | false | false | false | false |
sakolkar/4BitSorter
|
Synopsis/sorter_tb.vhd
| 1 | 1,899 |
----------------------------------------------------------
-- EE453 Lab3 Tutorial - Sorter Testbench
-- Khaled Al-Amoodi
-- Modified by: Jiawei Wu, Satyen Akolkar
-- Test-Bench (sorter_tb)
----------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.ALL;
ENTITY sorter_tb IS
END sorter_tb;
ARCHITECTURE behavior OF sorter_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sorter_top
PORT(
padClk : IN std_logic;
padA, padB, padC, padD : IN std_logic_vector(3 downto 0);
padS1reg, padS2reg, padS3reg, padS4reg : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal A, B, C, D : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal S1reg, S2reg, S3reg, S4reg : std_logic_vector(3 downto 0);
-- Clock period definitions
constant Clk_period : time := 30 ns;
constant inc : integer := 1;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sorter_top PORT MAP (
padClk => Clk,
padA => A, padB => B, padC => C, padD => D,
padS1reg => S1reg, padS2reg => S2reg, padS3reg => S3reg, padS4reg => S4reg
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
A <= x"3";
B <= x"5";
C <= x"5";
D <= x"5";
wait for clk_period;
A <= x"A";
B <= x"F";
C <= x"5";
D <= x"5";
wait for clk_period;
A <= x"A";
B <= x"3";
C <= x"B";
D <= x"7";
wait for clk_period;
A <= x"1";
B <= x"2";
C <= x"3";
D <= x"4";
wait for clk_period;
A <= x"4";
B <= x"3";
C <= x"2";
D <= x"1";
wait for clk_period;
end process;
END;
|
apache-2.0
|
a63fb8d668ae41df514a2afaee0e1dd2
| 0.541338 | 2.764192 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/TP1-Contador/bcd_counter.vhd
| 1 | 934 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd_counter is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
counter_out: out std_logic_vector(3 downto 0);
carry_out: out std_logic
);
end;
architecture bcd_counter_arq of bcd_counter is
begin
--el comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(clk,rst)
variable count: integer range 0 to 10;
begin
if rst = '1' then
counter_out <= (others => '0');
carry_out <= '0';
count := 0;
elsif rising_edge(clk) then
if ena = '1' then
count:=count + 1;
if count = 9 then
carry_out <= '1';
elsif count = 10 then
count := 0;
carry_out <= '0';
else
carry_out <= '0';
end if;
end if;
end if;
counter_out <= std_logic_vector(to_unsigned(count,4)); end process;
end;
|
gpl-3.0
|
9418ad77fefb19181fe6ad0c355ec5dd
| 0.5803 | 2.830303 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-LuGus/TP2-Voltimetro/rom_manager.vhd
| 1 | 2,852 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rom_manager is
generic (
SCREEN_H:natural := 1080;
SCREEN_W:natural := 1920;
BITS:natural := 11
);
port (
pixel_x_v: in std_logic_vector(BITS-1 downto 0);
pixel_y_v: in std_logic_vector(BITS-1 downto 0);
to_mux_v: out std_logic_vector(2 downto 0);
char_x_v: out std_logic_vector(2 downto 0);
char_y_v: out std_logic_vector(2 downto 0)
);
end;
-- architecture rom_manager_arq of rom_manager is
-- --Se necesita calcular el rango de dibujo. Si se lo quiere centrado en la pantalla, sera un corrimiento de 4 bits a cada lado en y sobre la mitad de la pantalla y de 8*5/2 en x
-- constant middle_x: integer := SCREEN_W/2;
-- constant middle_y: integer := SCREEN_H/2;
-- constant x_offset: integer := 8*5/2;
-- constant min_x: integer := middle_x - x_offset;
-- constant max_x: integer := middle_x + x_offset;
-- constant min_y: integer := middle_y - 4;
-- constant max_y: integer := middle_y + 4;
-- begin
-- process(pixel_x_v,pixel_y_v)
-- variable pixel_x: integer := to_integer(unsigned(pixel_x_v));
-- variable pixel_y: integer := to_integer(unsigned(pixel_y_v));
-- variable local_x: integer;
-- variable char_x: integer;
-- variable char_y: integer;
-- variable char: integer;
-- begin
-- if (pixel_x > min_x) AND (pixel_x < max_x) AND (pixel_y > min_y) AND (pixel_y < min_y) then
-- local_x := pixel_x - min_x;
-- char := local_x/8;
-- char_x := local_x mod 8;
-- char_y := pixel_y mod 8;
-- char_x_v <= std_logic_vector(TO_UNSIGNED(char_x,3));
-- char_y_v <= std_logic_vector(TO_UNSIGNED(char_y,3));
-- to_mux_v <= std_logic_vector(TO_UNSIGNED(char,3));
-- end if;
-- end process;
architecture rom_manager_arq of rom_manager is
--Se necesita calcular el rango de dibujo. Si se lo quiere centrado en la pantalla, sera un corrimiento de 4 bits a cada lado en y sobre la mitad de la pantalla y de 8*5/2 en x
begin
process(pixel_x_v,pixel_y_v)
variable pixel_x: integer := 0; --to_integer(unsigned(pixel_x_v));
variable pixel_y: integer := 0; --t-o_integer(unsigned(pixel_y_v));
variable char_x: integer;
variable char_y: integer;
variable char: integer;
begin
pixel_x := to_integer(unsigned(pixel_x_v));
pixel_y := to_integer(unsigned(pixel_y_v));
char := pixel_x/8;
char_x := pixel_x mod 8;
char_y := pixel_y mod 8;
char_x_v <= std_logic_vector(TO_UNSIGNED(char_x,3));
char_y_v <= std_logic_vector(TO_UNSIGNED(char_y,3));
if (pixel_x >= 320) AND (pixel_x < 360) AND (pixel_y < 192) AND (pixel_y >= 184) then
to_mux_v <= std_logic_vector(TO_UNSIGNED(char,3));
else
to_mux_v <= "110";
end if;
end process;
end;
|
gpl-3.0
|
2f947c928bfd4d3ee5f4add40a5c8e5a
| 0.615358 | 2.79334 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/tp1/generic_enabler/gen_ena.vhd
| 1 | 806 |
library ieee;
use ieee.std_logic_1164.all;
entity generic_enabler is
generic(PERIOD:natural := 1000000 ); --1MHz
port(
clk: in std_logic;
rst: in std_logic;
ena_out: out std_logic
);
end;
architecture generic_enabler_arq of generic_enabler is
component generic_counter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end component;
begin
genericCounterMap: generic_counter generic map (32,PERIOD) --32 bits son suficientes para hasta 4 GHz
port map(
clk => clk,
rst => rst,
ena => '1',
carry_o => ena_out); --El count_dummy esta conectado siempre a tierra.
end;
|
gpl-3.0
|
c2b6d079760ca7097a6b476ee4e8aea5
| 0.637717 | 3.05303 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/arctg_lut/arctg_lut_tb.vhd
| 1 | 1,321 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity arctg_lut_tb is
end entity;
architecture arctg_lut_tb_arq of arctg_lut_tb is
signal step_index : integer := 0;
signal angle : std_logic_vector(31 downto 0) := (others => '0');
component arctg_lut is
generic(TOTAL_BITS: integer := 32);
port(
step_index: in integer := 0;
angle: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
for arctg_lut_0 : arctg_lut use entity work.arctg_lut;
begin
arctg_lut_0 : arctg_lut
generic map(TOTAL_BITS => 32)
port map(
step_index => step_index,
angle => angle
);
process
type pattern_type is record
i : integer;
a : std_logic_vector(31 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
(0,"00000000001011010000000000000000"),
(15,"00000000000000000000000001110010")
);
begin
for i in patterns'range loop
-- Set the inputs.
step_index <= patterns(i).i;
wait for 1 ns;
assert patterns(i).a = angle report "BAD ANGLE, GOT: " & integer'image(to_integer(unsigned(angle)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
e64676bfd630f1d065a1039507d52505
| 0.663891 | 3.072093 | false | false | false | false |
ruygargar/LCSE_lab
|
dma/dma_bus_controller.vhd
| 1 | 8,040 |
-------------------------------------------------------------------------------
-- Author: Aragonés Orellana, Silvia
-- García Garcia, Ruy
-- Project Name: PIC
-- Design Name: dma.vhd
-- Module Name: dma_bus_controller.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- La funcionalidad del Controlador de Bus es enmascarar las señales de entrada
-- y salida de los subsistemas Transmisor y Receptor del DMA, con el fin de
-- mantener tanto los Buses de Datos y Direcciones como las señales de control
-- conectadas entre la fuente y el destino correspondiente en función de las
-- señales de handshake entre uP/DMA y DMA/RS232.
-- A su vez, se encarga de mantener excitados los buses y las señales de
-- control (a una combinación de valores que no modifiquen el estado de la
-- memoria) durante las transiciones entre Receptor/Transmisor y el uP.
entity dma_bus_controller is
Port ( -- Señales procedentes del bus del uP.
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Databus : inout STD_LOGIC_VECTOR (7 downto 0);
Address : out STD_LOGIC_VECTOR (7 downto 0);
ChipSelect : out STD_LOGIC;
WriteEnable : out STD_LOGIC;
OutputEnable : out STD_LOGIC;
-- Señales de handshake entre uP y DMA.
Send : in STD_LOGIC;
Ready : out STD_LOGIC;
-- Señales de handshake entre RS232 y DMA.
DMA_RQ : out STD_LOGIC;
DMA_ACK : in STD_LOGIC;
RX_empty : in STD_LOGIC;
-- pragma synthesis off
BC_state_ns : out integer;
-- pragma synthesis on
-- Señales procedentes del Receptor para el control de los buses de
-- datos y direcciones, y las señales de control.
RX_Databus : in STD_LOGIC_VECTOR (7 downto 0);
RX_Address : in STD_LOGIC_VECTOR (7 downto 0);
RX_ChipSelect : in STD_LOGIC;
RX_WriteEnable : in STD_LOGIC;
-- Señales de control utilizadas por la máquina de estados del
-- Controlador de Bus para comunicarse con el Receptor.
RX_OutputEnable : in STD_LOGIC;
RX_start : out STD_LOGIC;
RX_end : in STD_LOGIC;
-- Señales procedentes del Transmisor.
TX_Databus : out STD_LOGIC_VECTOR (7 downto 0);
TX_Address : in STD_LOGIC_VECTOR (7 downto 0);
TX_ChipSelect : in STD_LOGIC;
TX_WriteEnable : in STD_LOGIC;
TX_OutputEnable : in STD_LOGIC;
-- Señales de control utilizadas por la máquina de estados del
-- Controlador de Bus para comunicarse con el Transmisor.
TX_start : out STD_LOGIC;
TX_ready : in STD_LOGIC;
TX_end : in STD_LOGIC
);
end dma_bus_controller;
architecture Behavioral of dma_bus_controller is
-- Definición de los posibles estados de la FSM del Controlador de Bus:
-- + Idle: Los buses de datos y direcciones, y las señales de control están
-- bajo el control del uP.
-- Las salidas del DMA se mantienen a alta impedancia.
-- + RX_wait_bus: Los buses de datos y direcciones, y las señales de control
-- están bajo el control del uP. El DMA avisa al uP de que hay datos a la
-- espera de ser recibidos.
-- Las salidas del DMA se mantienen a alta impedancia.
-- + RX_use_bus: El Controlador de Bus da el control de los buses de datos y
-- direcciones, y las señales de control, al Receptor.
-- Las salidas del DMA se correponden con las del Receptor.
-- + RX_free_bus: El Receptor ha terminado de utilizar los buses de datos y
-- direcciones, y las señales de control. El Controlador de Bus mantiene
-- excitadas dichas señales a la espera de que el uP vuelva a tomar su
-- control.
-- + TX_use_bus: El Controlador de Bus da el control de los buses de datos y
-- direcciones, y las señales de control, al Transmisor.
-- Las salidas del DMA se correponden con las del Transmisor.
-- + RX_free_bus: El Transmisor ha terminado de utilizar los buses de datos
-- y direcciones, y las señales de control. El Controlador de Bus
-- mantiene excitadas dichas señales a la espera de que el uP vuelva a
-- tomar su control.
type BusController_ST is (idle, RX_wait_bus, RX_use_bus , RX_free_bus,
TX_use_bus, TX_free_bus);
signal BC_now, BC_next : BusController_ST;
begin
-- Proceso secuencial de la máquina de estados del Controlador de Bus.
-- Dispone de una señal de Reset asíncrono activa a nivel bajo. Mientras que
-- esta señal se mantenga activa, la FSM se mantiene en el estado de 'Idle'.
process(Clk, Reset)
begin
if (Reset = '0') then
BC_now <= idle;
elsif Clk'event and Clk = '1' then
BC_now <= BC_next;
end if;
end process;
-- Proceso combinacional de la máquina de estados.
process(BC_now,
RX_empty, Send,
DMA_ACK, RX_end, TX_ready, TX_end, RX_Databus,
RX_Address, RX_ChipSelect, RX_WriteEnable, RX_OutputEnable,
TX_Address, TX_ChipSelect, TX_WriteEnable, TX_OutputEnable)
begin
-- Valores preasignados por defecto.
Databus <= (others => 'Z');
Address <= (others => 'Z');
ChipSelect <= 'Z';
WriteEnable <= 'Z';
OutputEnable <= 'Z';
DMA_RQ <= '0';
Ready <= '0';
RX_start <= '0';
TX_start <= '0';
case BC_now is
when idle =>
Ready <= '1';
-- Cuando el uP ordene envíar datos y el Transmisor del DMA este
-- listo:
if (Send = '1' and TX_ready = '1') then
Ready <= '0';
TX_start <= '1';
BC_next <= TX_use_bus;
-- Si no, si el DMA recibe la señal de que hay datos preparados
-- para leer desde el RS232...
elsif (RX_empty = '0') then
DMA_RQ <= '1';
BC_next <= RX_wait_bus;
else
BC_next <= idle;
end if;
when TX_use_bus =>
Address <= TX_Address;
ChipSelect <= TX_ChipSelect;
WriteEnable <= TX_WriteEnable;
OutputEnable <= TX_OutputEnable;
-- Si el Transmisor ha terminado de utilizar el bus...
if TX_end = '1' then
BC_next <= TX_free_bus;
else
BC_next <= TX_use_bus;
end if;
when TX_free_bus =>
Databus <= (others => '0');
Address <= (others => '0');
ChipSelect <= '0';
WriteEnable <= '0';
OutputEnable <= '0';
Ready <= '1';
-- Si el uP vuelve a tomar el control del bus en el siguiente
-- ciclo de reloj...
if Send = '0' then
BC_next <= idle;
else
BC_next <= TX_free_bus;
end if;
when RX_wait_bus =>
DMA_RQ <= '1';
Ready <= '1';
-- Si el uP cede el bus a partir del siguiente ciclo de reloj...
if DMA_ACK = '1' then
RX_start <= '1';
BC_next <= RX_use_bus;
-- Si no, y el uP ordene envíar datos y el Transmisor del DMA este
-- listo:
elsif (Send = '1' and TX_ready = '1') then
Ready <= '0';
TX_start <= '1';
BC_next <= TX_use_bus;
else
BC_next <= RX_wait_bus;
end if;
when RX_use_bus =>
Databus <= RX_Databus;
Address <= RX_Address;
ChipSelect <= RX_ChipSelect;
WriteEnable <= RX_WriteEnable;
OutputEnable <= RX_OutputEnable;
DMA_RQ <= '1';
-- Si el Receptor ha terminado de utilizar el bus...
if RX_end = '1' then
BC_next <= RX_free_bus;
else
BC_next <= RX_use_bus;
end if;
when RX_free_bus =>
Databus <= (others => '0');
Address <= (others => '0');
ChipSelect <= '0';
WriteEnable <= '0';
OutputEnable <= '0';
-- Si el uP vuelve a tomar el control del bus en el siguiente
-- ciclo de reloj...
if DMA_ACK = '0' then
BC_next <= idle;
else
BC_next <= RX_free_bus;
end if;
end case;
end process;
-- El bus de datos siempre estará conectado a la entrada del bus de datos
-- del subsistema receptor.
TX_Databus <= Databus;
-- pragma synthesis off
process(BC_now)
begin
case BC_now is
when idle => BC_state_ns <= 0;
when TX_use_bus => BC_state_ns <= 1;
when TX_free_bus => BC_state_ns <= 2;
when RX_wait_bus => BC_state_ns <= 3;
when RX_use_bus => BC_state_ns <= 4;
when RX_free_bus => BC_state_ns <= 5;
end case;
end process;
-- pragma synthesis on
end Behavioral;
|
gpl-3.0
|
28dcf1919d02d83718751eeae818a0d5
| 0.620398 | 3.310004 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/TP1-Contador/generic_enabler_tb.vhd
| 1 | 682 |
library ieee;
use ieee.std_logic_1164.all;
entity generic_enabler_tb is
end;
architecture generic_enabler_tb_func of generic_enabler_tb is
signal rst_in: std_logic:='1';
signal enable_out: std_logic:='0';
signal clk_in: std_logic:='0';
component generic_enabler is
generic(
PERIOD:natural := 1000000 --1MHz
);
port(
clk: in std_logic;
rst: in std_logic;
enabler_out: out std_logic
);
end component;
begin
clk_in <= not(clk_in) after 1 ns;
rst_in <= '0' after 10 ns;
generic_enablerMap: generic_enabler
generic map(6)
port map(
clk => clk_in,
rst => rst_in,
enabler_out => enable_out
);
end architecture;
|
gpl-3.0
|
5328f3be773114bbfcaa9f1cdc2591cb
| 0.63783 | 2.865546 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/addition/shift_register/shift_register.vhd
| 1 | 1,532 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity shift_register is
generic(REGISTRY_BITS : integer := 32;
STEPS : integer := 4);
port(
enable: in std_logic := '0';
reset: in std_logic := '0';
clk: in std_logic := '0';
D: in std_logic_vector(REGISTRY_BITS - 1 downto 0) := (others => '0');
Q: out std_logic_vector(REGISTRY_BITS - 1 downto 0) := (others => '0')
);
end;
architecture shift_register_arq of shift_register is
type inputs_array is array (natural range <>) of std_logic_vector(REGISTRY_BITS - 1 downto 0);
signal inputs : inputs_array(STEPS downto 0) := (others => (others => '0'));
signal enable_in : std_logic := '0';
signal reset_in : std_logic := '0';
signal clk_in : std_logic := '0';
signal master_q : std_logic_vector(REGISTRY_BITS - 1 downto 0) := (others => '0');
component registry is
generic(TOTAL_BITS : integer := 32);
port(
enable: in std_logic;
reset: in std_logic;
clk: in std_logic;
D: in std_logic_vector(TOTAL_BITS - 1 downto 0);
Q: out std_logic_vector(TOTAL_BITS - 1 downto 0)
);
end component;
begin
inputs(0) <= D;
all_registries: for i in 0 to (STEPS - 1) generate
reg : registry
generic map(TOTAL_BITS => REGISTRY_BITS)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => inputs(i),
Q => inputs(i+1)
);
end generate all_registries;
clk_in <= clk;
reset_in <= reset;
enable_in <= enable;
master_q <= inputs(STEPS);
Q <= master_q;
end;
|
gpl-3.0
|
de761eb49ba32f57a35d66e7b4de209d
| 0.619452 | 2.879699 | false | false | false | false |
ruygargar/LCSE_lab
|
rs232/rs232_tx.vhd
| 1 | 3,469 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:53:43 11/10/2013
-- Design Name:
-- Module Name: RS232_TX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RS232_TX is
port (
Clk : in std_logic;
Reset : in std_logic;
Start : in std_logic;
Data : in std_logic_vector(7 downto 0);
EOT : out std_logic;
TX : out std_logic);
end RS232_TX;
architecture Behavioral of RS232_TX is
type state is (idle, startbit, senddata, stopbit);
SIGNAL current_st, next_st: state;
SIGNAL copy_data: std_logic_vector (7 downto 0);
SIGNAL enable_copy, pw_sreset, dc_sreset, dc_enable: std_logic;
SIGNAL pulse_width: std_logic_vector (8 downto 0);
CONSTANT PEOC: std_logic_vector (8 downto 0) := "010101101";
SIGNAL data_count: std_logic_vector (2 downto 0);
BEGIN
PROCESS (clk, reset)
BEGIN
IF reset = '0' THEN
current_st <= idle;
ELSIF clk'event AND clk='1' THEN
current_st <= next_st;
END IF;
END PROCESS;
PROCESS (current_st, start, pulse_width, data_count)
BEGIN
enable_copy <= '0';
pw_sreset <= '0';
dc_sreset <= '0';
dc_enable <= '0';
EOT <= '0';
TX <= '1';
CASE current_st IS
WHEN idle =>
enable_copy <= '1';
EOT <= '1';
IF (start = '1') THEN
pw_sreset <= '1';
next_st <= startbit;
ELSE
next_st <= idle;
END IF;
WHEN startbit =>
TX <= '0';
IF (pulse_width = PEOC) THEN
pw_sreset <= '1';
dc_sreset <= '1';
next_st <= senddata;
ELSE
next_st <= startbit;
END IF;
WHEN senddata =>
TX <= copy_data(conv_integer(data_count));
IF (pulse_width = PEOC) THEN
dc_enable <= '1';
pw_sreset <= '1';
END IF;
IF (data_count = "111") AND (pulse_width = PEOC) THEN
pw_sreset <= '1';
next_st <= stopbit;
ELSE
next_st <= senddata;
END IF;
WHEN stopbit =>
TX <= '1';
IF (pulse_width = PEOC) THEN
next_st <= idle;
ELSE
next_st <= stopbit;
END IF;
END CASE;
END PROCESS;
PROCESS (clk, reset)
BEGIN
IF reset = '0' THEN
copy_data <= (others=>'0');
ELSIF clk'event AND clk = '1' THEN
IF enable_copy = '1' THEN
copy_data <= data;
END IF;
END IF;
END PROCESS;
PROCESS (clk, reset, pw_sreset)
BEGIN
IF reset = '0' THEN
pulse_width <= (others => '0');
ELSIF clk'event AND clk = '1' THEN
IF pw_sreset = '1' THEN
pulse_width <= (others => '0');
ELSE
pulse_width <= pulse_width + '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk, reset, dc_sreset)
BEGIN
IF reset = '0' THEN
data_count <= (others => '0');
ELSIF clk'event AND clk = '1' THEN
IF dc_sreset = '1' THEN
data_count <= (others => '0');
ELSIF dc_enable = '1' THEN
data_count <= data_count + '1';
END IF;
END IF;
END PROCESS;
end Behavioral;
|
gpl-3.0
|
d023c219b356f42eaf205a8d8ef0f191
| 0.571058 | 3.064488 | false | false | false | false |
rodrigoazs/-7-5-Reed-Solomon
|
code/counter.vhd
| 1 | 963 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity counter is
port(Clock: in std_logic;
Count5: out std_logic;
Count7: out std_logic);
end counter;
architecture Behavioral of counter is
signal temp: std_logic_vector(0 to 2) := "000";
begin process(Clock)
begin
if(Clock'event and Clock='0') then
if temp = "000" or temp = "111"
then
Count7 <= '1';
else
Count7 <= '0';
end if;
end if;
if(Clock'event and Clock='1') then
Count7 <= '0';
if temp="101" or temp="110" then
Count5 <= '1';
else
Count5 <= '0';
end if;
if temp="111" then
temp<="001";
else
temp <= temp + 1;
end if;
end if;
end process;
end Behavioral;
|
mit
|
4b90e89df9fb162b151445b468b604d2
| 0.616822 | 3.199336 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/syndrome_calculator_n.vhd
| 1 | 15,582 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Syndrome_Calculator_N
-- Module Name: Syndrome_Calculator_N
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st step in Goppa Code Decoding.
--
-- This circuit computes the syndrome from the ciphertext, support elements and
-- inverted evaluation of support elements into polynomial g, aka g(L)^(-1).
-- This circuit works by computing the syndrome of only the positions where the ciphertext
-- has value 1.
--
-- This is the second version with a variable number of computation units, but no pipeline.
-- A optimized version that computes the syndrome with a pipeline was made called
-- syndrome_calculator_n_pipe.
--
-- The circuits parameters
--
-- number_of_units :
--
-- The number of units that compute each syndrome at the same time.
-- This number must be 1 or greater.
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword or in this case the ciphertext. Both the codeword
-- and ciphertext has the same size.
--
-- size_codeword :
--
-- The number of bits necessary to hold the ciphertext/codeword.
-- This is ceil(log2(length_codeword)).
--
-- length_syndrome :
--
-- The size of the syndrome array. This parameter depends of the
-- Goppa code used.
--
-- size_syndrome :
--
-- The number of bits necessary to hold the array syndrome.
-- This is ceil(log2(length_syndrome)).
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- controller_syndrome_calculator_2 Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- shift_register_rst_nbits Rev 1.0
-- mult_gf_2_m Rev 1.0
-- adder_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity syndrome_calculator_n is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- length_syndrome : integer := 54;
-- size_syndrome : integer := 6
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- length_syndrome : integer := 100;
-- size_syndrome : integer := 7
-- QD-GOPPA [2528, 2144, 32, 12] --
number_of_units : integer := 16;
gf_2_m : integer range 1 to 20 := 12;
length_codeword : integer := 2528;
size_codeword : integer := 12;
length_syndrome : integer := 64;
size_syndrome : integer := 7
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 128;
-- size_syndrome : integer := 7
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 128;
-- size_syndrome : integer := 7
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_units : integer := 32;
-- gf_2_m : integer range 1 to 20 := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- length_syndrome : integer := 256;
-- size_syndrome : integer := 8
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_L : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR(0 downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_h : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_L : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0)
);
end syndrome_calculator_n;
architecture Behavioral of syndrome_calculator_n is
component controller_syndrome_calculator_2
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
almost_units_ready : in STD_LOGIC;
empty_units : in STD_LOGIC;
limit_ctr_codeword_q : in STD_LOGIC;
limit_ctr_syndrome_q : in STD_LOGIC;
reg_first_syndrome_q : in STD_LOGIC_VECTOR(0 downto 0);
reg_codeword_q : in STD_LOGIC_VECTOR(0 downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
control_units_ce : out STD_LOGIC;
control_units_rst : out STD_LOGIC;
int_reg_L_ce : out STD_LOGIC;
int_square_h : out STD_LOGIC;
int_reg_h_ce : out STD_LOGIC;
int_reg_h_rst : out STD_LOGIC;
int_sel_reg_h : out STD_LOGIC;
reg_syndrome_ce : out STD_LOGIC;
reg_syndrome_rst : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_first_syndrome_ce : out STD_LOGIC;
reg_first_syndrome_rst : out STD_LOGIC;
ctr_syndrome_ce : out STD_LOGIC;
ctr_syndrome_rst : out STD_LOGIC;
ctr_codeword_ce : out STD_LOGIC;
ctr_codeword_rst : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component shift_register_rst_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component mult_gf_2_m
Generic (gf_2_m : integer range 1 to 20 := 11);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component adder_gf_2_m
Generic(
gf_2_m : integer := 1;
number_of_elements : integer range 2 to integer'high := 2
);
Port(
a : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_elements) - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal reg_L_d : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal reg_L_ce : STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
signal reg_L_q : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal reg_h_d :STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal reg_h_ce : STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
signal reg_h_rst : STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
constant reg_h_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_h_q : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal sel_reg_h : STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
signal square_h : STD_LOGIC_VECTOR((number_of_units - 1) downto 0);
signal reg_syndrome_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_syndrome_ce : STD_LOGIC;
signal reg_syndrome_rst : STD_LOGIC;
constant reg_syndrome_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
signal reg_syndrome_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_codeword_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_codeword_ce : STD_LOGIC;
signal reg_codeword_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_first_syndrome_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_first_syndrome_ce : STD_LOGIC;
signal reg_first_syndrome_rst : STD_LOGIC;
constant reg_first_syndrome_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "1";
signal reg_first_syndrome_q : STD_LOGIC_VECTOR(0 downto 0);
signal mult_a : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal mult_b : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal mult_o : STD_LOGIC_VECTOR(((number_of_units)*gf_2_m - 1) downto 0);
signal adder_a : STD_LOGIC_VECTOR(((number_of_units+1)*gf_2_m - 1) downto 0);
signal adder_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_syndrome_ce : STD_LOGIC;
signal ctr_syndrome_rst : STD_LOGIC;
constant ctr_syndrome_rst_value : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0) := std_logic_vector(to_unsigned(0, size_syndrome));
signal ctr_syndrome_q : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal ctr_codeword_ce : STD_LOGIC;
signal ctr_codeword_rst : STD_LOGIC;
constant ctr_codeword_rst_value : STD_LOGIC_VECTOR((size_codeword - 1) downto 0) := std_logic_vector(to_unsigned(0, size_codeword));
signal ctr_codeword_q : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal control_units_ce : STD_LOGIC;
signal control_units_rst : STD_LOGIC;
constant control_units_rst_value0 : STD_LOGIC_VECTOR((number_of_units - 1) downto 0) := (others => '0');
constant control_units_rst_value1 : STD_LOGIC_VECTOR((number_of_units) downto (number_of_units)) := "1";
constant control_units_rst_value : STD_LOGIC_VECTOR((number_of_units) downto 0) := control_units_rst_value1 & control_units_rst_value0;
signal control_units_q : STD_LOGIC_VECTOR((number_of_units) downto 0);
signal control_units_data_out : STD_LOGIC;
signal int_reg_L_ce : STD_LOGIC;
signal int_square_h : STD_LOGIC;
signal int_reg_h_ce : STD_LOGIC;
signal int_reg_h_rst : STD_LOGIC;
signal int_sel_reg_h : STD_LOGIC;
signal almost_units_ready : STD_LOGIC;
signal empty_units : STD_LOGIC;
signal limit_ctr_codeword_q : STD_LOGIC;
signal limit_ctr_syndrome_q : STD_LOGIC;
begin
controller : controller_syndrome_calculator_2
Port Map(
clk => clk,
rst => rst,
almost_units_ready => almost_units_ready,
empty_units => empty_units,
limit_ctr_codeword_q => limit_ctr_codeword_q,
limit_ctr_syndrome_q => limit_ctr_syndrome_q,
reg_first_syndrome_q => reg_first_syndrome_q,
reg_codeword_q => reg_codeword_q,
syndrome_finalized => syndrome_finalized,
write_enable_new_syndrome => write_enable_new_syndrome,
control_units_ce => control_units_ce,
control_units_rst => control_units_rst,
int_reg_L_ce => int_reg_L_ce,
int_square_h => int_square_h,
int_reg_h_ce => int_reg_h_ce,
int_reg_h_rst => int_reg_h_rst,
int_sel_reg_h => int_sel_reg_h,
reg_syndrome_ce => reg_syndrome_ce,
reg_syndrome_rst => reg_syndrome_rst,
reg_codeword_ce => reg_codeword_ce,
reg_first_syndrome_ce => reg_first_syndrome_ce,
reg_first_syndrome_rst => reg_first_syndrome_rst,
ctr_syndrome_ce => ctr_syndrome_ce,
ctr_syndrome_rst => ctr_syndrome_rst,
ctr_codeword_ce => ctr_codeword_ce,
ctr_codeword_rst => ctr_codeword_rst
);
calculator_units : for I in 0 to (number_of_units - 1) generate
reg_L_I : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_L_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
clk => clk,
ce => reg_L_ce(I),
q => reg_L_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
reg_h_I : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_h_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
clk => clk,
ce => reg_h_ce(I),
rst => reg_h_rst(I),
rst_value => reg_h_rst_value,
q => reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
mult_I : mult_gf_2_m
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => mult_a(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
b => mult_b(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
o => mult_o(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
reg_L_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= value_L;
reg_h_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= mult_o(((I + 1)*gf_2_m - 1) downto I*gf_2_m) when sel_reg_h(I) = '1' else
value_h;
mult_a(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m) when square_h(I) = '1' else
reg_L_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m);
mult_b(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m);
reg_L_ce(I) <= int_reg_L_ce and control_units_q(I);
square_h(I) <= int_square_h and control_units_q(I);
reg_h_ce(I) <= int_reg_h_ce and (control_units_q(I) or (int_sel_reg_h and (not int_square_h)));
reg_h_rst(I) <= int_reg_h_rst and (control_units_q(I));
sel_reg_h(I) <= int_sel_reg_h;
end generate;
control_units : shift_register_rst_nbits
Generic Map(
size => number_of_units+1
)
Port Map(
data_in => control_units_data_out,
clk => clk,
ce => control_units_ce,
rst => control_units_rst,
rst_value => control_units_rst_value,
q => control_units_q,
data_out => control_units_data_out
);
adder : adder_gf_2_m
Generic Map(
gf_2_m => gf_2_m,
number_of_elements => number_of_units+1
)
Port Map(
a => adder_a,
o => adder_o
);
reg_syndrome : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_syndrome_d,
clk => clk,
ce => reg_syndrome_ce,
rst => reg_syndrome_rst,
rst_value => reg_syndrome_rst_value,
q => reg_syndrome_q
);
reg_codeword : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_codeword_d,
clk => clk,
ce => reg_codeword_ce,
q => reg_codeword_q
);
reg_first_syndrome : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_first_syndrome_d,
clk => clk,
ce => reg_first_syndrome_ce,
rst => reg_first_syndrome_rst,
rst_value => reg_first_syndrome_rst_value,
q => reg_first_syndrome_q
);
ctr_syndrome : counter_rst_nbits
Generic Map(
size => size_syndrome,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_syndrome_ce,
rst => ctr_syndrome_rst,
rst_value => ctr_syndrome_rst_value,
q => ctr_syndrome_q
);
ctr_codeword : counter_rst_nbits
Generic Map(
size => size_codeword,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_codeword_ce,
rst => ctr_codeword_rst,
rst_value => ctr_codeword_rst_value,
q => ctr_codeword_q
);
adder_a <= reg_h_q & reg_syndrome_q;
reg_syndrome_d <= value_syndrome;
reg_codeword_d <= value_codeword;
reg_first_syndrome_d <= "0";
new_value_syndrome <= adder_o;
address_h <= ctr_codeword_q;
address_L <= ctr_codeword_q;
address_codeword <= ctr_codeword_q;
address_syndrome <= std_logic_vector(to_unsigned(length_syndrome - 1, ctr_syndrome_q'length) - unsigned(ctr_syndrome_q));
almost_units_ready <= control_units_q(number_of_units - 1);
empty_units <= control_units_q(0);
limit_ctr_codeword_q <= '1' when (ctr_codeword_q = std_logic_vector(to_unsigned(length_codeword - 1, ctr_codeword_q'length))) else '0';
limit_ctr_syndrome_q <= '1' when (ctr_syndrome_q = std_logic_vector(to_unsigned(length_syndrome - 1, ctr_syndrome_q'length))) else '0';
end Behavioral;
|
bsd-2-clause
|
140c90caae335afed7a86545f4bbf1b2
| 0.647863 | 2.713216 | false | false | false | false |
ruygargar/LCSE_lab
|
dma/dma_tx.vhd
| 1 | 4,538 |
-------------------------------------------------------------------------------
-- Author: Aragonés Orellana, Silvia
-- García Garcia, Ruy
-- Project Name: PIC
-- Design Name: dma.vhd
-- Module Name: dma_tx.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dma_tx is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
-- Señales procedentes del bus del uP.
Databus : in STD_LOGIC_VECTOR (7 downto 0);
Address : out STD_LOGIC_VECTOR (7 downto 0);
ChipSelect : out STD_LOGIC;
WriteEnable : out STD_LOGIC;
OutputEnable : out STD_LOGIC;
-- Señales procedentes de la FSM del Controlador de Bus.
Start_TX : in STD_LOGIC;
Ready_TX : out STD_LOGIC;
End_TX : out STD_LOGIC;
-- Bus de datos y señales de handshake orientadas al transmisor del
-- RS232.
DataOut : out STD_LOGIC_VECTOR(7 downto 0);
Valid_DO : out STD_LOGIC;
Ack_DO : in STD_LOGIC);
end dma_tx;
architecture Behavioral of dma_tx is
-- Definición de los posibles estados de la FSM del Transmisor:
type Transmitter_ST is (idle, CPY_REG0, CPY_REG1, SND_REG0, SND_REG1);
signal TX_now, TX_next : Transmitter_ST;
-- Señales usadas para inferir los biestables necesarios para cada uno de
-- los registros de copia de los datos a envíar.
signal REG0, REG1 : std_logic_vector(7 downto 0);
-- Señal de enable de cada uno de los registros anteriores.
signal R0_enable, R1_enable : std_logic;
-- Tabla de direcciones:
-- El valor contenido en cada uno de los registros anteriores será recibido
-- desde su respectiva dirección de memoria.
constant R0_address : std_logic_vector(7 downto 0) := X"04";
constant R1_address : std_logic_vector(7 downto 0) := X"05";
begin
-- El Transmisor nunca modificará un valor de memoria. Únicamente lee los
-- datos necesarios de ella.
WriteEnable <= '0';
-- Proceso secuencial de la máquina de estados del Transmisor.
-- Dispone de una señal de Reset asíncrono activa a nivel bajo. Mientras que
-- esta señal se mantenga activa, la FSM se mantiene en el estado de 'Idle',
-- y los registros se inicializan a 0.
process(Clk, Reset)
begin
if (Reset = '0') then
TX_now <= idle;
REG0 <= X"00";
REG1 <= X"00";
elsif Clk'event and Clk = '1' then
TX_now <= TX_next;
if R0_enable = '1' then
REG0 <= Databus;
end if;
if R1_enable = '1' then
REG1 <= Databus;
end if;
end if;
end process;
-- Proceso combinacional de la máquina de estados.
process(TX_now, Start_TX, REG0, REG1, Ack_DO)
begin
-- Valores preasignados por defecto.
Address <= X"00";
ChipSelect <= '0';
OutputEnable <= '0';
Ready_TX <= '0';
End_TX <= '0';
DataOut <= X"00";
Valid_DO <= '1';
R0_enable <= '0';
R1_enable <= '0';
case TX_now is
when idle =>
Ready_TX <= '1';
-- Si el Controlador de Bus da permiso para iniciar una nueva
-- transmisión...
if Start_TX = '1' then
TX_next <= CPY_REG0;
else
TX_next <= idle;
end if;
when CPY_REG0 =>
Address <= R0_address;
ChipSelect <= '1';
OutputEnable <= '1';
R0_enable <= '1';
-- Las lecturas desde memoria se realizan en un único ciclo de
-- reloj. Por tanto en el siguiente flanco de reloj, R0 habrá
-- almacenado su dato, y se debe pedir a la memoria el siguiente
-- valor.
TX_next <= CPY_REG1;
when CPY_REG1 =>
Address <= R1_address;
ChipSelect <= '1';
OutputEnable <= '1';
R1_enable <= '1';
-- Las lecturas desde memoria se realizan en un único ciclo de
-- reloj. Por tanto en el siguiente flanco de reloj, R1 habrá
-- almacenado su dato, terminando así el uso de los buses del uP,
-- pudiendo devolver su control e iniciando la tranferencia con el
-- RS232.
End_TX <= '1';
TX_next <= SND_REG0;
when SND_REG0 =>
DataOut <= REG0;
Valid_DO <= '0';
-- Si el RS232 ha aceptado el dato...
if Ack_DO = '0' then
Valid_DO <= '1';
TX_next <= SND_REG1;
else
TX_next <= SND_REG0;
end if;
when SND_REG1 =>
DataOut <= REG1;
Valid_DO <= '0';
-- Si el RS232 ha aceptado el dato...
if Ack_DO = '0' then
Valid_DO <= '1';
TX_next <= idle;
else
TX_next <= SND_REG1;
end if;
end case;
end process;
end Behavioral;
|
gpl-3.0
|
4530eda963e46befbb9e62e27c2a6659
| 0.584619 | 3.229893 | false | false | false | false |
laurivosandi/hdl
|
zynq/src/ov7670_vga/ov7670_vga.vhd
| 1 | 3,353 |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Generate analog 640x480 VGA, double-doublescanned from 19200 bytes of RAM
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_vga is
port (
clk25 : in STD_LOGIC;
vga_red : out STD_LOGIC_VECTOR(4 downto 0);
vga_green : out STD_LOGIC_VECTOR(5 downto 0);
vga_blue : out STD_LOGIC_VECTOR(4 downto 0);
vga_hsync : out STD_LOGIC;
vga_vsync : out STD_LOGIC;
frame_addr : out STD_LOGIC_VECTOR(17 downto 0);
frame_pixel : in STD_LOGIC_VECTOR(11 downto 0)
);
end ov7670_vga;
architecture Behavioral of ov7670_vga is
-- Timing constants
constant hRez : natural := 640;
constant hStartSync : natural := 640+16;
constant hEndSync : natural := 640+16+96;
constant hMaxCount : natural := 800;
constant vRez : natural := 480;
constant vStartSync : natural := 480+10;
constant vEndSync : natural := 480+10+2;
constant vMaxCount : natural := 480+10+2+33;
constant hsync_active : std_logic := '0';
constant vsync_active : std_logic := '0';
signal hCounter : unsigned( 9 downto 0) := (others => '0');
signal vCounter : unsigned( 9 downto 0) := (others => '0');
signal address : unsigned(18 downto 0) := (others => '0');
signal blank : std_logic := '1';
begin
frame_addr <= std_logic_vector(address(18 downto 1));
process(clk25)
begin
if rising_edge(clk25) then
-- Count the lines and rows
if hCounter = hMaxCount-1 then
hCounter <= (others => '0');
if vCounter = vMaxCount-1 then
vCounter <= (others => '0');
else
vCounter <= vCounter+1;
end if;
else
hCounter <= hCounter+1;
end if;
if blank = '0' then
vga_red <= frame_pixel(11 downto 8) & "0";
vga_green <= frame_pixel( 7 downto 4) & "00";
vga_blue <= frame_pixel( 3 downto 0) & "0";
else
vga_red <= (others => '0');
vga_green <= (others => '0');
vga_blue <= (others => '0');
end if;
if vCounter >= vRez then
address <= (others => '0');
blank <= '1';
else
if hCounter < 640 then
blank <= '0';
address <= address+1;
else
blank <= '1';
end if;
end if;
-- Are we in the hSync pulse? (one has been added to include frame_buffer_latency)
if hCounter > hStartSync and hCounter <= hEndSync then
vga_hSync <= hsync_active;
else
vga_hSync <= not hsync_active;
end if;
-- Are we in the vSync pulse?
if vCounter >= vStartSync and vCounter < vEndSync then
vga_vSync <= vsync_active;
else
vga_vSync <= not vsync_active;
end if;
end if;
end process;
end Behavioral;
|
mit
|
45d92f751d27481ab6b8cce359400c90
| 0.489412 | 4.144623 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/controller_solving_key_equation_2.vhd
| 1 | 84,920 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Solving_Key_Equation_2
-- Module Name: Controller_Solving_Key_Equation_2
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 2nd step in Goppa Code Decoding.
--
-- This is a state machine circuit that controls solving_key_equation_2.
-- This state machine have 3 phases: first phase variable initialization,
-- second computation of polynomial sigma, third step writing the polynomial sigma
-- on a specific memory position.
--
-- This controls a pipeline circuit.
-- Another version each spends more area with two pipelines and two state machines
-- called solving_key_equation_4 was made.
--
-- Dependencies:
--
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_solving_key_equation_2 is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
FB_equal_zero : in STD_LOGIC;
i_equal_zero : in STD_LOGIC;
i_minus_j_less_than_zero : in STD_LOGIC;
degree_G_less_equal_final_degree : in STD_LOGIC;
degree_F_less_than_degree_G : in STD_LOGIC;
degree_B_equal_degree_C_plus_j : in STD_LOGIC;
degree_B_less_than_degree_C_plus_j : in STD_LOGIC;
reg_looking_degree_q : in STD_LOGIC_VECTOR(0 downto 0);
key_equation_found : out STD_LOGIC;
signal_inv : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
sel_base_mul : out STD_LOGIC;
reg_h_ce : out STD_LOGIC;
ctr_i_ce : out STD_LOGIC;
ctr_i_load : out STD_LOGIC;
ctr_i_rst : out STD_LOGIC;
sel_ctr_i_rst_value : out STD_LOGIC;
sel_ctr_i_d : out STD_LOGIC;
reg_j_ce : out STD_LOGIC;
reg_j_rst : out STD_LOGIC;
reg_FB_ce : out STD_LOGIC;
reg_FB_rst : out STD_LOGIC;
reg_new_value_FB_ce : out STD_LOGIC;
reg_new_value_FB_rst : out STD_LOGIC;
sel_reg_new_value_FB : out STD_LOGIC;
sel_load_new_value_FB : out STD_LOGIC;
reg_GC_ce : out STD_LOGIC;
reg_GC_rst : out STD_LOGIC;
reg_new_value_GC_ce : out STD_LOGIC;
reg_new_value_GC_rst : out STD_LOGIC;
sel_reg_new_value_GC : out STD_LOGIC;
ctr_degree_F_ce : out STD_LOGIC;
ctr_degree_F_load : out STD_LOGIC;
ctr_degree_F_rst : out STD_LOGIC;
reg_degree_G_ce : out STD_LOGIC;
reg_degree_G_rst : out STD_LOGIC;
ctr_degree_B_ce : out STD_LOGIC;
ctr_degree_B_load : out STD_LOGIC;
ctr_degree_B_rst : out STD_LOGIC;
sel_ctr_degree_B : out STD_LOGIC;
reg_degree_C_ce : out STD_LOGIC;
reg_degree_C_rst : out STD_LOGIC;
reg_looking_degree_d : out STD_LOGIC_VECTOR(0 downto 0);
reg_looking_degree_ce : out STD_LOGIC;
reg_swap_ce : out STD_LOGIC;
reg_swap_rst : out STD_LOGIC;
sel_address_FB : out STD_LOGIC;
sel_address_GC : out STD_LOGIC;
ctr_load_address_FB_ce : out STD_LOGIC;
ctr_load_address_FB_load : out STD_LOGIC;
ctr_load_address_FB_rst : out STD_LOGIC;
ctr_load_address_GC_ce : out STD_LOGIC;
ctr_load_address_GC_load : out STD_LOGIC;
ctr_load_address_GC_rst : out STD_LOGIC;
reg_bus_address_FB_ce : out STD_LOGIC;
reg_bus_address_GC_ce : out STD_LOGIC;
reg_calc_address_FB_ce : out STD_LOGIC;
reg_calc_address_GC_ce : out STD_LOGIC;
reg_store_address_FB_ce : out STD_LOGIC;
reg_store_address_GC_ce : out STD_LOGIC;
enable_external_swap : out STD_LOGIC
);
end controller_solving_key_equation_2;
architecture Behavioral of controller_solving_key_equation_2 is
type State is (reset, load_counter, load_counter_2, load_counter_3, load_first_inv, send_first_inv_store_G2t, load_F_store_G, last_store_G, prepare_store_B_C, prepare_store_B_C_2, store_B_C, last_store_B_C, swap_F_G_B_C, no_swap_F_G_B_C, prepare_load_j, load_j, load_first_G_first_F, load_h, prepare_load_F_G, load_store_F_G, prepare_degree_B, finalize_i, prepare_i, prepare_load_B_C, load_store_B_C, prepare_final_swap, preparel_swap_address, prepare_load_sigma, prepare_load_sigma_2, load_sigma, load_store_sigma, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process(actual_state, FB_equal_zero, i_equal_zero, i_minus_j_less_than_zero, degree_G_less_equal_final_degree, degree_F_less_than_degree_G, degree_B_equal_degree_C_plus_j, degree_B_less_than_degree_C_plus_j, reg_looking_degree_q)
begin
case (actual_state) is
when reset =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '1';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '1';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '1';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '1';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '1';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '1';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when load_counter =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '1';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '1';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '1';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
sel_address_FB <= '1';
sel_address_GC <= '1';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '1';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '1';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when load_counter_2 =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '1';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '1';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when load_counter_3 =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '1';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '1';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when load_first_inv =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "1";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
when send_first_inv_store_G2t =>
key_equation_found <= '0';
signal_inv <= '1';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '1';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
when load_F_store_G =>
if(i_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '1';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '1';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
elsif(reg_looking_degree_q(0) = '1' and FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
end if;
when last_store_G =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when prepare_store_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '1';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '1';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when prepare_store_B_C_2 =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '1';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '1';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
when store_B_C =>
if(i_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '1';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '1';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '1';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '1';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
end if;
when last_store_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when swap_F_G_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '1';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '1';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '1';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '1';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '1';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when no_swap_F_G_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when prepare_load_j =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_rst <= '0';
reg_j_ce <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '1';
sel_address_GC <= '1';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '1';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '1';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when load_j =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '1';
reg_j_ce <= '1';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '1';
sel_address_GC <= '1';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when load_first_G_first_F =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when load_h =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '1';
reg_h_ce <= '1';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "1";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when prepare_load_F_G =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
when load_store_F_G =>
if(i_minus_j_less_than_zero = '1') then
if(reg_looking_degree_q(0) = '1') then
if(FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
elsif(degree_F_less_than_degree_G = '1') then
key_equation_found <= '0';
signal_inv <= '1';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
end if;
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
end if;
else
if(reg_looking_degree_q(0) = '1') then
if(FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '1';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
elsif(degree_F_less_than_degree_G = '1') then
key_equation_found <= '0';
signal_inv <= '1';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
end if;
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
end if;
end if;
when prepare_degree_B =>
if(degree_B_equal_degree_C_plus_j = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "1";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '1';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '1';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
elsif(degree_B_less_than_degree_C_plus_j = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '1';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '1';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '1';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '1';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '1';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '1';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
end if;
when prepare_i =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '1';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_load_new_value_FB <= '0';
sel_reg_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when finalize_i =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when prepare_load_B_C =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
when load_store_B_C =>
if(i_minus_j_less_than_zero = '1') then
if(reg_looking_degree_q(0) = '1' and FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
end if;
elsif(reg_looking_degree_q(0) = '1' and FB_equal_zero = '1') then
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '1';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
else
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '1';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '1';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '1';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
end if;
when prepare_final_swap =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when preparel_swap_address =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '1';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '1';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when prepare_load_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when prepare_load_sigma_2 =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '1';
when load_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '1';
when load_store_sigma =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '1';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '1';
ctr_i_load <= '0';
ctr_i_rst <= '0';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '1';
reg_FB_rst <= '0';
reg_new_value_FB_ce <= '1';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '1';
reg_GC_rst <= '0';
reg_new_value_GC_ce <= '1';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '0';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '0';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '0';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '0';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '1';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '1';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '1';
reg_bus_address_GC_ce <= '1';
reg_calc_address_FB_ce <= '1';
reg_calc_address_GC_ce <= '1';
reg_store_address_FB_ce <= '1';
reg_store_address_GC_ce <= '1';
enable_external_swap <= '0';
when final =>
key_equation_found <= '1';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '1';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '0';
when others =>
key_equation_found <= '0';
signal_inv <= '0';
write_enable_FB <= '0';
write_enable_GC <= '0';
sel_base_mul <= '0';
reg_h_ce <= '0';
ctr_i_ce <= '0';
ctr_i_load <= '0';
ctr_i_rst <= '1';
sel_ctr_i_rst_value <= '0';
sel_ctr_i_d <= '0';
reg_j_ce <= '0';
reg_j_rst <= '0';
reg_FB_ce <= '0';
reg_FB_rst <= '1';
reg_new_value_FB_ce <= '0';
reg_new_value_FB_rst <= '0';
sel_reg_new_value_FB <= '0';
sel_load_new_value_FB <= '0';
reg_GC_ce <= '0';
reg_GC_rst <= '1';
reg_new_value_GC_ce <= '0';
reg_new_value_GC_rst <= '0';
sel_reg_new_value_GC <= '0';
ctr_degree_F_ce <= '0';
ctr_degree_F_load <= '0';
ctr_degree_F_rst <= '1';
reg_degree_G_ce <= '0';
reg_degree_G_rst <= '1';
ctr_degree_B_ce <= '0';
ctr_degree_B_load <= '0';
ctr_degree_B_rst <= '1';
sel_ctr_degree_B <= '0';
reg_degree_C_ce <= '0';
reg_degree_C_rst <= '1';
reg_looking_degree_d <= "0";
reg_looking_degree_ce <= '0';
reg_swap_ce <= '0';
reg_swap_rst <= '0';
sel_address_FB <= '0';
sel_address_GC <= '0';
ctr_load_address_FB_ce <= '0';
ctr_load_address_FB_load <= '0';
ctr_load_address_FB_rst <= '0';
ctr_load_address_GC_ce <= '0';
ctr_load_address_GC_load <= '0';
ctr_load_address_GC_rst <= '0';
reg_bus_address_FB_ce <= '0';
reg_bus_address_GC_ce <= '0';
reg_calc_address_FB_ce <= '0';
reg_calc_address_GC_ce <= '0';
reg_store_address_FB_ce <= '0';
reg_store_address_GC_ce <= '0';
enable_external_swap <= '0';
end case;
end process;
New_State : process(actual_state, FB_equal_zero, i_equal_zero, i_minus_j_less_than_zero, degree_G_less_equal_final_degree, degree_F_less_than_degree_G, degree_B_equal_degree_C_plus_j, degree_B_less_than_degree_C_plus_j, reg_looking_degree_q)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= load_counter_2;
when load_counter_2 =>
next_state <= load_counter_3;
when load_counter_3 =>
next_state <= load_first_inv;
when load_first_inv =>
next_state <= send_first_inv_store_G2t;
when send_first_inv_store_G2t =>
next_state <= load_F_store_G;
when load_F_store_G =>
if(i_equal_zero = '1') then
next_state <= last_store_G;
else
next_state <= load_F_store_G;
end if;
when last_store_G =>
next_state <= prepare_store_B_C;
when prepare_store_B_C =>
next_state <= prepare_store_B_C_2;
when prepare_store_B_C_2 =>
next_state <= store_B_C;
when store_B_C =>
if(i_equal_zero = '1') then
next_state <= last_store_B_C;
else
next_state <= store_B_C;
end if;
when last_store_B_C =>
next_state <= swap_F_G_B_C;
when swap_F_G_B_C =>
next_state <= prepare_load_j;
when no_swap_F_G_B_C =>
next_state <= prepare_load_j;
when prepare_load_j =>
next_state <= load_j;
when load_j =>
next_state <= load_first_G_first_F;
when load_first_G_first_F =>
next_state <= load_h;
when load_h =>
next_state <= prepare_load_F_G;
when prepare_load_F_G =>
next_state <= load_store_F_G;
when load_store_F_G =>
if(i_equal_zero = '1') then
next_state <= prepare_degree_B;
else
next_state <= load_store_F_G;
end if;
when prepare_degree_B =>
next_state <= prepare_i;
when prepare_i =>
next_state <= finalize_i;
when finalize_i =>
next_state <= prepare_load_B_C;
when prepare_load_B_C =>
next_state <= load_store_B_C;
when load_store_B_C =>
if(i_equal_zero = '1') then
if(degree_F_less_than_degree_G = '1') then
if(degree_G_less_equal_final_degree = '1') then
next_state <= prepare_final_swap;
else
next_state <= swap_F_G_B_C;
end if;
else
next_state <= no_swap_F_G_B_C;
end if;
else
next_state <= load_store_B_C;
end if;
when prepare_final_swap =>
next_state <= preparel_swap_address;
when preparel_swap_address =>
next_state <= prepare_load_sigma;
when prepare_load_sigma =>
next_state <= prepare_load_sigma_2;
when prepare_load_sigma_2 =>
next_state <= load_sigma;
when load_sigma =>
next_state <= load_store_sigma;
when load_store_sigma =>
if(i_equal_zero = '1') then
next_state <= final;
else
next_state <= load_store_sigma;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
331b5998a807573a5edddaa2ed6196ba
| 0.510339 | 2.287654 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-LuGus/TP2-Voltimetro/bcd_1_counter_tb.vhd
| 1 | 869 |
library ieee;
use ieee.std_logic_1164.all;
use work.utility.all;
entity bcd_1_counter_tb is
end;
architecture bcd_1_counter_tb_func of bcd_1_counter_tb is
signal rst_in: std_logic:='1';
signal clk_in: std_logic:='0';
signal ena_in: std_logic:='0';
signal counter_out: bcd_vector (2 downto 0);
component bcd_1_counter is
generic (
COUNTERS:natural := 5;
OUTPUT:natural := 3
);
port (
clk_in: in std_logic;
rst_in: in std_logic;
ena_in: in std_logic;
counter_out: out bcd_vector ( OUTPUT-1 downto 0)
);
end component;
begin
clk_in <= not(clk_in) after 1 ns;
rst_in <= '0' after 10 ns;
ena_in <= '1' after 20 ns;
bcd_1_counterMap: bcd_1_counter generic map(5,3)
port map(
clk_in => clk_in,
rst_in => rst_in,
ena_in => ena_in,
counter_out => counter_out
);
end architecture;
|
gpl-3.0
|
3d111d7ba25cc77a68624f0119db7967
| 0.614499 | 2.665644 | false | false | false | false |
pwuertz/digitizer2fw
|
sim/adc_program_tb.vhd
| 1 | 3,029 |
-------------------------------------------------------------------------------
-- ADS5403 ADC, serial programming test bench
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
entity adc_program_tb is
end adc_program_tb;
architecture adc_program_tb_arch of adc_program_tb is
signal ADC_SDENB, ADC_SDIO, ADC_SCLK: std_logic;
component adc_program
port (
-- application interface
clk_main: in std_logic;
start: in std_logic;
rd: in std_logic;
busy: out std_logic;
addr: in std_logic_vector(6 downto 0);
din: in std_logic_vector(15 downto 0);
dout: out std_logic_vector(15 downto 0);
-- adc interface
adc_sdenb: out std_logic;
adc_sdio: inout std_logic;
adc_sclk: out std_logic
);
end component;
signal adc_prog_start: std_logic := '0';
signal adc_prog_rd: std_logic := '0';
signal adc_prog_busy: std_logic;
signal adc_prog_addr: std_logic_vector(6 downto 0) := (others => '-');
signal adc_prog_din: std_logic_vector(15 downto 0) := (others => '-');
signal adc_prog_dout: std_logic_vector(15 downto 0) := (others => '-');
constant clk_period : time := 10 ns;
signal clk: std_logic;
begin
adc_program_inst: adc_program
port map (
clk_main => clk,
start => adc_prog_start,
rd => adc_prog_rd,
busy => adc_prog_busy,
addr => adc_prog_addr,
din => adc_prog_din,
dout => adc_prog_dout,
adc_sdenb => ADC_SDENB,
adc_sdio => ADC_SDIO,
adc_sclk => ADC_SCLK
);
clk_process: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stimulus: process
constant ADDRESS: std_logic_vector := "0100011";
constant WORD: std_logic_vector := "1100000011111111";
begin
ADC_SDIO <= 'Z';
adc_prog_start <= '0';
adc_prog_addr <= ADDRESS;
adc_prog_din <= WORD;
-- start read cycle
wait for clk_period/2;
wait for 10 * clk_period;
adc_prog_rd <= '1';
adc_prog_start <= '1';
wait for clk_period;
adc_prog_start <= '0';
-- wait until adc_prog stops driving SDIO and drive test signal
wait until ADC_SDIO = 'Z';
ADC_SDIO <= '0';
wait for 200 ns;
ADC_SDIO <= '1';
wait until adc_prog_busy = '0';
ADC_SDIO <= 'Z';
-- wait a bit
wait for 100 * clk_period;
-- start write cycle
adc_prog_rd <= '0';
adc_prog_start <= '1';
wait for clk_period;
adc_prog_start <= '0';
-- wait for finished
wait until adc_prog_busy = '0';
assert false report "Stimulus finished" severity note;
wait;
end process;
end adc_program_tb_arch;
|
gpl-3.0
|
acb7ba064f9502b8ad67e06dde877d7f
| 0.5786 | 3.500578 | false | false | false | false |
ruygargar/LCSE_lab
|
alu/alu.vhd
| 1 | 7,627 |
-------------------------------------------------------------------------------
-- Author: Aragonés Orellana, Silvia
-- García Garcia, Ruy
-- Project Name: PIC
-- Design Name: alu.vhd
-- Module Name: alu.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
use work.PIC_pkg.all;
entity alu is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
-- Código de microinstrucción decodificado en la Unidad de Control.
u_instruction : in alu_op;
-- Banderas de estado de la última operación.
FlagZ : out STD_LOGIC;
FlagC : out STD_LOGIC;
FlagN : out STD_LOGIC;
FlagE : out STD_LOGIC;
-- Índice orientado a accesos indexados a memoria.
Index : out STD_LOGIC_VECTOR (7 downto 0);
-- Bus de datos del sistema.
Databus : inout STD_LOGIC_VECTOR (7 downto 0));
end alu;
architecture rtl of alu is
-- Señales usadas para inferir los biestables necesarios para cada uno de
-- los registros existentes en la ALU.
signal A, B, ACC, IND : std_logic_vector(7 downto 0);
-- Señal de enable de cada uno de los registros anteriores.
signal A_enable, B_enable, ACC_enable, IND_enable : std_logic;
-- Señales auxiliares empleadas para llevar a cabo la multiplexación de las
-- señales de entrada a los registros.
signal a_in, b_in, acc_in, ind_in : std_logic_vector(7 downto 0);
-- Señales usadas para inferir los biestables necesarios para las banderas
-- de estado de la operación realizada en la ALU.
signal FlagZ_reg, FlagC_reg, FlagN_reg, FlagE_reg : std_logic;
-- Señales auxiliares empleadas para llevar a cabo la multiplexación de las
-- diferentes fuentes de estos biestables.
signal FlagZ_in, FlagC_in, FlagN_in, FlagE_in : std_logic;
-- Señales empleadas para la creación de un único sumador en la ALU (y uno
-- adicional para complementar números a complemento a 2).
-- Sum_out es el resultado de la suma, mientras que op0 y op1 son los
-- operandos. Éstas últimas señales multiplexan las entradas del sumador.
signal sum_out, op0, op1 : std_logic_vector(7 downto 0);
begin
-- Proceso secuencial para la síntesis de los registros de la ALU y sus
-- banderas.
-- Dispone de una señal de Reset asíncrono activa a nivel bajo, empleada
-- para inicializar los registros y banderas de la ALU a 0.
process(Clk, Reset)
begin
if Reset = '0' then
A <= X"00";
B <= X"00";
ACC <= X"00";
IND <= X"00";
FlagZ_reg <= '0';
FlagC_reg <= '0';
FlagN_reg <= '0';
FlagE_reg <= '0';
elsif Clk'event and Clk = '1' then
if A_enable = '1' then
A <= a_in;
else
A <= A;
end if;
if B_enable = '1' then
B <= b_in;
else
B <= B;
end if;
if ACC_enable = '1' then
ACC <= acc_in;
else
ACC <= ACC;
end if;
if IND_enable = '1' then
IND <= ind_in;
else
IND <= IND;
end if;
FlagZ_reg <= FlagZ_in;
FlagC_reg <= FlagC_in;
FlagN_reg <= FlagN_in;
FlagE_reg <= FlagE_in;
end if;
end process;
-- Proceso combinacional para la multiplexación de las entradas a cada uno
-- de los registros de la ALU, en función del código de operación recibido.
process(u_instruction, Databus, A, B, ACC, sum_out)
begin
a_in <= X"00";
b_in <= X"00";
acc_in <= X"00";
ind_in <= X"00";
a_enable <= '0';
b_enable <= '0';
acc_enable <= '0';
ind_enable <= '0';
Databus <= (others => 'Z');
case u_instruction is
when nop =>
when op_lda =>
a_in <= Databus;
a_enable <= '1';
when op_ldb =>
b_in <= Databus;
b_enable <= '1';
when op_ldacc =>
acc_in <= Databus;
acc_enable <= '1';
when op_ldid =>
ind_in <= Databus;
ind_enable <= '1';
when op_mvacc2id =>
ind_in <= ACC;
ind_enable <= '1';
when op_mvacc2a =>
a_in <= ACC;
a_enable <= '1';
when op_mvacc2b =>
b_in <= ACC;
b_enable <= '1';
when op_add =>
acc_in <= sum_out(7 downto 0);
acc_enable <= '1';
when op_sub =>
acc_in <=sum_out(7 downto 0);
acc_enable <= '1';
when op_shiftl =>
acc_in <= ACC(6 downto 0)&'0';
acc_enable <= '1';
when op_shiftr =>
acc_in <= '0'&ACC(7 downto 1);
acc_enable <= '1';
when op_and =>
for i in 7 downto 0 loop
acc_in(i) <= A(i) and B(i);
end loop;
acc_enable <= '1';
when op_or =>
for i in 7 downto 0 loop
acc_in(i) <= A(i) or B(i);
end loop;
acc_enable <= '1';
when op_xor =>
for i in 7 downto 0 loop
acc_in(i) <= A(i) xor B(i);
end loop;
acc_enable <= '1';
when op_ascii2bin =>
acc_in <= sum_out(7 downto 0);
acc_enable <= '1';
when op_bin2ascii =>
acc_in <= sum_out(7 downto 0);
acc_enable <= '1';
when op_oeacc =>
Databus <= ACC;
when others =>
end case;
end process;
-- Proceso combinacional para la multiplexación de las fuentes para cada una
-- de las banderas ALU, en función del código de operación recibido.
process(u_instruction, A, B, acc_in, sum_out, op0, op1)
begin
FlagZ_in <= '0';
FlagC_in <= '0';
FlagN_in <= '0';
FlagE_in <= '0';
case u_instruction is
when nop =>
when op_add =>
if acc_in = X"00" then
FlagZ_in <= '1';
end if;
if (sum_out(7) = '1' and op0(7) = '0' and op1(7) = '0') or
(sum_out(7) = '0' and op0(7) = '1' and op0(7) = '1') then
FlagC_in <= '1';
end if;
if op0(3) = '1' and op1(3) = '1' then
FlagN_in <= '1';
end if;
when op_sub =>
if acc_in = X"00" then
FlagZ_in <= '1';
end if;
if (sum_out(7) = '1' and op0(7) = '0' and op1(7) = '1') or
(sum_out(7) = '0' and op0(7) = '1' and op1(7) = '0') then
FlagC_in <= '1';
end if;
if op0(3) = '1' and op1(3) = '1' then
FlagN_in <= '1';
end if;
when op_and =>
if acc_in = X"00" then
FlagZ_in <= '1';
end if;
when op_or =>
if acc_in = X"00" then
FlagZ_in <= '1';
end if;
when op_xor =>
if acc_in = X"00" then
FlagZ_in <= '1';
end if;
when op_cmpe =>
if A = B then
FlagZ_in <= '1';
end if;
when op_cmpl =>
if unsigned(A) < unsigned(B) then
FlagZ_in <= '1';
end if;
when op_cmpg =>
if unsigned(A) > unsigned(B) then
FlagZ_in <= '1';
end if;
when op_ascii2bin =>
if acc_in < X"00" or acc_in > X"09" then
FlagE_in <= '1';
end if;
when op_bin2ascii =>
if acc_in < X"30" or acc_in > X"39" then
FlagE_in <= '1';
end if;
when others =>
end case;
end process;
-- Proceso combinacional para la multiplexación de las entradas al sumador,
-- en función del código de operación recibido.
process(u_instruction, A, B)
begin
case u_instruction is
when op_add =>
op0 <= A(7 downto 0);
op1 <= B(7 downto 0);
when op_sub =>
op0 <= A(7 downto 0);
op1 <= (not B(7 downto 0)) + X"01";
when op_ascii2bin =>
op0 <= A(7 downto 0);
op1 <= (not X"30") + X"01";
when op_bin2ascii =>
op0 <= A(7 downto 0);
op1 <= X"30";
when others =>
op0 <= (others => '0');
op1 <= (others => '0');
end case;
end process;
-- Creación del sumador.
sum_out <= op0 + op1;
-- Unión entre las salidas del registro Index y las banderas de la ALU, y
-- las salidas de la entidad.
Index <= IND;
FlagZ <= FlagZ_reg;
FlagC <= FlagC_reg;
FlagN <= FlagN_reg;
FlagE <= FlagE_reg;
end rtl;
|
gpl-3.0
|
9a3564ae760e86aa989f9bce2024f5f0
| 0.553822 | 2.806107 | false | false | false | false |
rodrigoazs/-7-5-Reed-Solomon
|
code/write_file.vhd
| 1 | 1,220 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity write_file is
port (clock: in std_logic;
message: in std_logic_vector(14 downto 0)
);
end write_file;
architecture behavioral of write_file is
signal counter_write: std_logic_vector(2 downto 0)
:= "000";
begin
process(clock)
file file_pointer : text;
variable line_content : string(1 to 15);
variable line_num : line;
variable i,j : integer := 0;
variable char : character:='0';
begin
if (clock'event and clock='1') then
counter_write <= counter_write + 1;
if(i = 0 and counter_write = "111") then
file_open(file_pointer,"write.txt",write_mode);
end if;
if (counter_write = "111") then
for j in 0 to 14 loop
if(message(j) = '0') then
line_content(15-j) := '0';
else
line_content(15-j) := '1';
end if;
end loop;
write(line_num,line_content);
writeline (file_pointer,line_num);
i := 1;
counter_write <= "001";
end if;
end if;
end process;
end behavioral;
|
mit
|
20cc61af17ca09f56f912a7d6ea57733
| 0.667213 | 3.104326 | false | false | false | false |
pwuertz/digitizer2fw
|
src/rtl/sample_average.vhd
| 1 | 3,309 |
-------------------------------------------------------------------------------
-- Moving average filter
--
-- n=0 "00" no averaging
-- n=1 "01" 2 samples
-- n=2 "10" 4 samples
-- n=3 "11" undefined
--
-- TODO: adapt to incoming signal length
-- TODO: carry correct overflow bits to result
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sampling_pkg.all;
entity sample_average is
port (
clk: in std_logic;
n: in std_logic_vector(1 downto 0);
samples_a_in: in adc_samples_t(0 to 1);
samples_a_out: out adc_samples_t(0 to 1)
);
end sample_average;
architecture sample_average_arch of sample_average is
type samples_t is array (integer range <>) of signed(ADC_SAMPLE_BITS-1 downto 0);
signal s0_samples: samples_t(0 to 4);
signal s1_samples: samples_t(0 to 3);
signal s2_samples: samples_t(0 to 1);
begin
stage0: process(clk)
begin
if rising_edge(clk) then
-- shift buffer
s0_samples(0 to 2) <= s0_samples(2 to 4);
-- add new samples
s0_samples(3) <= signed(samples_a_in(0).data);
s0_samples(4) <= signed(samples_a_in(1).data);
end if;
end process;
stage1: process(clk)
variable a2, a3: signed(ADC_SAMPLE_BITS downto 0);
begin
if rising_edge(clk) then
-- shift buffer
s1_samples(0 to 1) <= s1_samples(2 to 3);
-- calculate new averages
a2 := resize(s0_samples(2), ADC_SAMPLE_BITS+1) + resize(s0_samples(3), ADC_SAMPLE_BITS+1);
a3 := resize(s0_samples(3), ADC_SAMPLE_BITS+1) + resize(s0_samples(4), ADC_SAMPLE_BITS+1);
s1_samples(2) <= a2(ADC_SAMPLE_BITS downto 1);
s1_samples(3) <= a3(ADC_SAMPLE_BITS downto 1);
end if;
end process;
stage2: process(clk)
variable a0, a1: signed(ADC_SAMPLE_BITS downto 0);
begin
if rising_edge(clk) then
-- calculate new averages
a0 := resize(s1_samples(0), ADC_SAMPLE_BITS+1) + resize(s1_samples(2), ADC_SAMPLE_BITS+1);
a1 := resize(s1_samples(1), ADC_SAMPLE_BITS+1) + resize(s1_samples(3), ADC_SAMPLE_BITS+1);
s2_samples(0) <= a0(ADC_SAMPLE_BITS downto 1);
s2_samples(1) <= a1(ADC_SAMPLE_BITS downto 1);
end if;
end process;
output_selection: process(n, samples_a_in, s1_samples, s2_samples)
begin
samples_a_out(0).ovfl <= samples_a_in(0).ovfl;
samples_a_out(1).ovfl <= samples_a_in(1).ovfl;
case n is
when "00" =>
samples_a_out(0).data <= samples_a_in(0).data;
samples_a_out(1).data <= samples_a_in(1).data;
when "01" =>
samples_a_out(0).data <= signed(s1_samples(2));
samples_a_out(1).data <= signed(s1_samples(3));
when "10" =>
samples_a_out(0).data <= signed(s2_samples(0));
samples_a_out(1).data <= signed(s2_samples(1));
when others =>
samples_a_out(0).data <= (others => '-');
samples_a_out(1).data <= (others => '-');
end case;
end process;
end sample_average_arch;
|
gpl-3.0
|
55ada9cbaa818092dd166da2c7ec6cae
| 0.582527 | 3.168582 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/counter_load_nbits.vhd
| 1 | 1,779 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_load_n_bits
-- Module Name: Counter_load_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Counter of size bits with no reset signal, that only increments when ce equals to 1.
-- The counter has a synchronous load signal, which will register the value on input d,
-- when load is 1.
--
-- The circuits parameters
--
-- size :
--
-- The size of the counter in bits.
--
-- increment_value :
--
-- The amount will be incremented each cycle.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_load_nbits is
Generic (
size : integer;
increment_value : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end counter_load_nbits;
architecture Behavioral of counter_load_nbits is
signal internal_value : unsigned((size - 1) downto 0);
begin
process(clk, ce, load)
begin
if(clk'event and clk = '1')then
if(ce = '1') then
if(load = '1') then
internal_value <= unsigned(d);
else
internal_value <= internal_value + to_unsigned(increment_value, internal_value'Length);
end if;
else
null;
end if;
end if;
end process;
q <= std_logic_vector(internal_value);
end Behavioral;
|
bsd-2-clause
|
8ae443c381944454bdbb72831190d9fe
| 0.605396 | 3.408046 | false | false | false | false |
hitomi2500/wasca
|
fpga_firmware/wasca/synthesis/submodules/abus_avalon_sdram_bridge.vhd
| 2 | 54,999 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity abus_avalon_sdram_bridge is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(24 downto 0) := (others => '0'); -- abus.address
abus_data : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.data
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_interrupt : out std_logic := '1'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_interrupt_disable_out : out std_logic := '0'; -- .disableout
sdram_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
sdram_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_cas_n : out std_logic; -- .cas_n
sdram_cke : out std_logic; -- .cke
sdram_cs_n : out std_logic; -- .cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_dqm : out std_logic_vector(1 downto 0) := (others => '1'); -- .dqm
sdram_ras_n : out std_logic; -- .ras_n
sdram_we_n : out std_logic; -- .we_n
sdram_clk : out std_logic;
avalon_sdram_read : in std_logic := '0'; -- avalon_master.read
avalon_sdram_write : in std_logic := '0'; -- .write
avalon_sdram_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_sdram_address : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
avalon_sdram_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_sdram_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_sdram_readdatavalid : out std_logic := '0'; -- .readdatavalid
avalon_sdram_byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .readdata
avalon_regs_read : in std_logic := '0'; -- avalon_master.read
avalon_regs_write : in std_logic := '0'; -- .write
avalon_regs_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_regs_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_regs_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_regs_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_regs_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity abus_avalon_sdram_bridge;
architecture rtl of abus_avalon_sdram_bridge is
component sniff_fifo
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
end component;
--xilinx mode
--component sniff_fifo
-- PORT
-- (
-- clk : IN STD_LOGIC;
-- srst : IN STD_LOGIC;
-- din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-- wr_en : IN STD_LOGIC;
-- rd_en : IN STD_LOGIC;
-- dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
-- full : OUT STD_LOGIC;
-- empty : OUT STD_LOGIC;
-- data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
-- );
--end component;
signal abus_address_ms : std_logic_vector(24 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(24 downto 0) := (others => '0'); -- abus.address
signal abus_data_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_data_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched_prepatch : std_logic_vector(24 downto 0) := (others => '0'); -- abus.address prior to patching
signal abus_address_latched : std_logic_vector(24 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MAPPER_READ : std_logic_vector(63 downto 0) := (others => '1');
signal REG_MAPPER_WRITE : std_logic_vector(63 downto 0) := (others => '1');
--signal sdram_read : std_logic;
--signal sdram_write : std_logic;
-- avalon_waitrequest : in std_logic := '0'; -- .waitrequest
-- avalon_address : out std_logic_vector(27 downto 0); -- .address
-- avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
-- avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
-- avalon_readdatavalid : in std_logic
------------------- sdram signals ---------------
signal sdram_abus_pending : std_logic := '0'; --abus request is detected and should be parsed
signal sdram_abus_complete : std_logic := '0';
signal sdram_wait_counter : unsigned(3 downto 0) := (others => '0');
--refresh interval should be no bigger than 7.8us = 906 clock cycles
--to keep things simple, perfrorm autorefresh at 512 cycles
signal sdram_init_counter : unsigned(15 downto 0) := (others => '0');
signal sdram_autorefresh_counter : unsigned(9 downto 0) := (others => '1');
signal sdram_datain_latched : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_sdram_complete : std_logic := '0';
signal avalon_sdram_reset_pending : std_logic := '0';
signal avalon_sdram_read_pending : std_logic := '0';
signal avalon_sdram_read_pending_f1 : std_logic := '0';
signal avalon_sdram_write_pending : std_logic := '0';
signal avalon_sdram_pending_address : std_logic_vector(25 downto 0) := (others => '0');
signal avalon_sdram_pending_data : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_sdram_readdata_latched : std_logic_vector(15 downto 0) := (others => '0');
--signal avalon_regs_address_latched : std_logic_vector(7 downto 0) := (others => '0');
signal avalon_regs_readdatavalid_p1 : std_logic := '0';
signal counter_filter_control : std_logic_vector(7 downto 0) := (others => '0');
signal counter_reset : std_logic := '0';
signal counter_count_read : std_logic := '0';
signal counter_count_write : std_logic := '0';
signal counter_value : unsigned(31 downto 0) := (others => '0');
signal sniffer_filter_control : std_logic_vector(7 downto 0) := (others => '0');
signal sniffer_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal sniffer_data_in_p1 : std_logic_vector(15 downto 0) := (others => '0');
signal sniffer_data_out : std_logic_vector(15 downto 0) := (others => '0');
--signal sniffer_data_out_p1 : std_logic_vector(15 downto 0) := (others => '0');
signal sniffer_prefifo : std_logic_vector(15 downto 0) := (others => '0');
signal sniffer_prefifo_full : std_logic := '0';
--signal sniffer_data_write_p1 : std_logic := '0';
signal sniffer_data_write : std_logic := '0';
signal sniffer_data_ack : std_logic := '0';
signal sniffer_fifo_content_size : std_logic_vector(10 downto 0) := (others => '0');
signal sniffer_fifo_empty : std_logic := '0';
signal sniffer_fifo_full : std_logic := '0';
signal sniffer_last_active_block : std_logic_vector(15 downto 0) := (others => '1');
signal sniffer_pending_set : std_logic := '0';
signal sniffer_pending_reset : std_logic := '0';
signal sniffer_pending_flag : std_logic := '0';
signal sniffer_pending_block : std_logic_vector(15 downto 0) := (others => '0');
signal sniffer_pending_timeout : std_logic := '0';
signal sniffer_pending_timeout_counter : std_logic_vector(31 downto 0) := (others => '0');
signal mapper_write_enable : std_logic := '1';
signal mapper_read_enable : std_logic := '1';
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
TYPE sdram_mode_type IS (
SDRAM_INIT0,
SDRAM_INIT1,
SDRAM_INIT2,
SDRAM_INIT3,
SDRAM_INIT4,
SDRAM_INIT5,
SDRAM_IDLE,
SDRAM_AUTOREFRESH,
SDRAM_AUTOREFRESH2,
SDRAM_ABUS_ACTIVATE,
SDRAM_ABUS_READ_AND_PRECHARGE,
SDRAM_ABUS_WRITE_AND_PRECHARGE,
SDRAM_AVALON_ACTIVATE,
SDRAM_AVALON_READ_AND_PRECHARGE,
SDRAM_AVALON_WRITE_AND_PRECHARGE
);
SIGNAL sdram_mode : sdram_mode_type := SDRAM_INIT0;
begin
abus_direction <= abus_direction_internal;
--we won't be aserting interrupt and waitrequest. because we can. can we?
abus_interrupt <= '1';
abus_interrupt_disable_out <= '1'; --dasbling waitrequest & int outputs, so they're tristate
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_data_ms <= abus_data;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_data_buf <= abus_data_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it looks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
--abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_write_pulse <= abus_write_buf and not abus_write_ms;
--abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
abus_read_pulse <= abus_read_buf and not abus_read_ms;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
--abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_write_pulse_off <= abus_write_ms and not abus_write_buf;
--abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_read_pulse_off <= abus_read_ms and not abus_read_buf;
--abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_chipselect_pulse_off <= abus_chipselect_ms and not abus_chipselect_buf;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_cspulse = '1' then
abus_address_latched_prepatch <= abus_address;
end if;
end if;
end process;
--patching abus_address_latched : for RAM 1M mode A19 and A20 should be set to zero
--trying to do this asynchronously
abus_address_latched <= abus_address_latched_prepatch(24 downto 21)&"00"&abus_address_latched_prepatch(18 downto 0) when wasca_mode = MODE_RAM_1M and abus_address_latched_prepatch(24 downto 21) = "0010"
else abus_address_latched_prepatch;
--mapper write enable decode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_buf(0) = '0' then
mapper_write_enable <= REG_MAPPER_WRITE(to_integer(unsigned(abus_address_latched(24 downto 20))));
elsif abus_chipselect_buf(1) = '0' then
mapper_write_enable <= REG_MAPPER_WRITE(32+to_integer(unsigned(abus_address_latched(23 downto 20))));
elsif abus_chipselect_buf(2) = '0' then
mapper_write_enable <= REG_MAPPER_WRITE(48);
end if;
end if;
end process;
--mapper read enable decode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_buf(0) = '0' then
mapper_read_enable <= REG_MAPPER_READ(to_integer(unsigned(abus_address_latched(24 downto 20))));
elsif abus_chipselect_buf(1) = '0' then
mapper_read_enable <= REG_MAPPER_READ(32+to_integer(unsigned(abus_address_latched(23 downto 20))));
elsif abus_chipselect_buf(2) = '0' then
mapper_read_enable <= REG_MAPPER_READ(48);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
when DIR_READ =>
abus_direction_internal <= mapper_read_enable;--'1'; --active
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
end case;
end if;
end if;
end process;
--abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
-- '0';
--sync mux for abus read requests
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_BOOT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
when MODE_BOOT => abus_data_out <= sdram_datain_latched(7 downto 0) & sdram_datain_latched (15 downto 8) ;
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
elsif avalon_regs_write= '1' then
case avalon_regs_address(7 downto 0) is
when X"F4" =>
REG_MODE <= avalon_regs_writedata;
case (avalon_regs_writedata (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (avalon_regs_writedata (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (avalon_regs_writedata (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
when others =>
null;
end case;
end if;
end if;
end process;
abus_data_in <= abus_data_buf;
--working only if direction is 1
abus_data <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_regs_readdatavalid_p1 <= '0';
sniffer_data_ack <= '0';
if avalon_regs_read = '1' then
avalon_regs_readdatavalid_p1 <= '1';
case avalon_regs_address(7 downto 0) is
when X"C0" =>
avalon_regs_readdata <= REG_MAPPER_READ(15 downto 0);
when X"C2" =>
avalon_regs_readdata <= REG_MAPPER_READ(31 downto 16);
when X"C4" =>
avalon_regs_readdata <= REG_MAPPER_READ(47 downto 32);
when X"C6" =>
avalon_regs_readdata <= REG_MAPPER_READ(63 downto 48);
when X"C8" =>
avalon_regs_readdata <= REG_MAPPER_WRITE(15 downto 0);
when X"CA" =>
avalon_regs_readdata <= REG_MAPPER_WRITE(31 downto 16);
when X"CC" =>
avalon_regs_readdata <= REG_MAPPER_WRITE(47 downto 32);
when X"CE" =>
avalon_regs_readdata <= REG_MAPPER_WRITE(63 downto 48);
when X"D0" =>
avalon_regs_readdata <= std_logic_vector(counter_value(15 downto 0));
when X"D2" =>
avalon_regs_readdata <= std_logic_vector(counter_value(31 downto 16));
when X"D4" =>
avalon_regs_readdata(15 downto 8) <= X"00";
avalon_regs_readdata(7 downto 0) <= counter_filter_control;
--D6 is a reset, writeonly
--D8 to DE are reserved
when X"E0" =>
avalon_regs_readdata <= sniffer_data_out;
sniffer_data_ack <= '1';
--E2 to E6 are reserved
when X"E8" =>
avalon_regs_readdata(15 downto 8) <= X"00";
avalon_regs_readdata(7 downto 0) <= sniffer_filter_control;
when X"EA" =>
avalon_regs_readdata(15 downto 12) <= "0000";
avalon_regs_readdata(11) <= sniffer_fifo_full;
avalon_regs_readdata(10 downto 0) <= sniffer_fifo_content_size;
--EC to EE are reserved
when X"F0" =>
avalon_regs_readdata <= REG_PCNTR;
when X"F2" =>
avalon_regs_readdata <= REG_STATUS;
when X"F4" =>
avalon_regs_readdata <= REG_MODE;
when X"F6" =>
avalon_regs_readdata <= REG_HWVER;
when X"F8" =>
avalon_regs_readdata <= REG_SWVER;
when X"FA" =>
avalon_regs_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_regs_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
avalon_regs_readdatavalid <= avalon_regs_readdatavalid_p1 when rising_edge(clock);
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
counter_reset <= '0';
if avalon_regs_write= '1' then
case avalon_regs_address(7 downto 0) is
when X"C0" =>
REG_MAPPER_READ(15 downto 0) <= avalon_regs_writedata;
when X"C2" =>
REG_MAPPER_READ(31 downto 16) <= avalon_regs_writedata;
when X"C4" =>
REG_MAPPER_READ(47 downto 32) <= avalon_regs_writedata;
when X"C6" =>
REG_MAPPER_READ(63 downto 48) <= avalon_regs_writedata;
when X"C8" =>
REG_MAPPER_WRITE(15 downto 0) <= avalon_regs_writedata;
when X"CA" =>
REG_MAPPER_WRITE(31 downto 16) <= avalon_regs_writedata;
when X"CC" =>
REG_MAPPER_WRITE(47 downto 32) <= avalon_regs_writedata;
when X"CE" =>
REG_MAPPER_WRITE(63 downto 48) <= avalon_regs_writedata;
when X"D0" =>
null;
when X"D2" =>
null;
when X"D4" =>
counter_filter_control <= avalon_regs_writedata(7 downto 0);
when X"D6" =>
counter_reset <= '1';
--D8 to DE are reserved
when X"E0" =>
null;
--E2 to E6 are reserved
when X"E8" =>
sniffer_filter_control <= avalon_regs_writedata(7 downto 0);
when X"EA" =>
null;
--EC to EE are reserved
when X"F0" =>
REG_PCNTR <= avalon_regs_writedata;
when X"F2" =>
REG_STATUS <= avalon_regs_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_regs_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Avalon regs interface is only regs, so always ready to write.
avalon_regs_waitrequest <= '0';
---------------------- sdram avalon interface -------------------
--to talk to sdram interface, avalon requests are latched until sdram is ready to process them
process (clock)
begin
if rising_edge(clock) then
if avalon_sdram_reset_pending = '1' then
avalon_sdram_read_pending <= '0';
avalon_sdram_write_pending <= '0';
elsif avalon_sdram_read = '1' then
avalon_sdram_read_pending <= '1';
avalon_sdram_pending_address <= avalon_sdram_address;
elsif avalon_sdram_write = '1' then
avalon_sdram_write_pending <= '1';
avalon_sdram_pending_address <= avalon_sdram_address;
avalon_sdram_pending_data<= avalon_sdram_writedata;
end if;
end if;
end process;
avalon_sdram_read_pending_f1 <= avalon_sdram_read_pending when rising_edge(clock);
--avalon_sdram_readdatavalid <= avalon_sdram_complete and avalon_sdram_read_pending_f1;
avalon_sdram_readdata <= avalon_sdram_readdata_latched;
--avalon_sdram_readdata_latched should be set by sdram interface directly
------------------------------ SDRAM stuff ---------------------------------------
-- abus pending flag.
-- abus_anypulse might appear up to 3-4 times at transaction start, so we shouldn't issue ack until at least 3-4 cycles from the start
process (clock)
begin
if rising_edge(clock) then
if abus_cspulse2 = '1' then
sdram_abus_pending <= '1';
elsif sdram_abus_complete = '1' then
sdram_abus_pending <= '0';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
sdram_autorefresh_counter <= sdram_autorefresh_counter + 1;
case sdram_mode is
when SDRAM_INIT0 =>
--first stage init. cke off, dqm high, others Z
sdram_addr <= (others => 'Z');
sdram_ba <= "ZZ";
sdram_cas_n <= 'Z';
sdram_cke <= '0';
sdram_cs_n <= 'Z';
sdram_dq <= (others => 'Z');
sdram_ras_n <= 'Z';
sdram_we_n <= 'Z';
sdram_dqm <= "11";
sdram_init_counter <= sdram_init_counter + 1;
avalon_sdram_readdatavalid <= '0';
if sdram_init_counter(15) = '1' then
-- 282 us from the start elapsed, moving to next init
sdram_init_counter <= (others => '0');
sdram_mode <= SDRAM_INIT1;
end if;
when SDRAM_INIT1 =>
--another stage init. cke on, dqm high, set other pin
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_cke <= '1';
sdram_cs_n <= '0';
sdram_dq <= (others => 'Z');
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_dqm <= "11";
sdram_init_counter <= sdram_init_counter + 1;
if sdram_init_counter(10) = '1' then
-- some smaller time elapsed, moving to next init - issue "precharge all"
sdram_mode <= SDRAM_INIT2;
sdram_ras_n <= '0';
sdram_we_n <= '0';
sdram_addr(10) <= '1';
sdram_wait_counter <= to_unsigned(1,4);
end if;
when SDRAM_INIT2 =>
--move on with init
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_addr(10) <= '0';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "auto refresh"
sdram_mode <= SDRAM_INIT3;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_wait_counter <= to_unsigned(7,4);
end if;
when SDRAM_INIT3 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "auto refresh"
sdram_mode <= SDRAM_INIT4;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_wait_counter <= to_unsigned(7,4);
end if;
when SDRAM_INIT4 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- issue "mode register set command"
sdram_mode <= SDRAM_INIT5;
sdram_ras_n <= '0';
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_addr <= "0001000110000"; --write single, no testmode, cas 3, burst seq, burst len 1
sdram_wait_counter <= to_unsigned(10,4);
end if;
when SDRAM_INIT5 =>
--move on with init
sdram_ras_n <= '1';
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_addr <= (others => '0');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
-- init done, switching to working mode
sdram_mode <= SDRAM_IDLE;
end if;
when SDRAM_IDLE =>
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_cke <= '1';
sdram_cs_n <= '0';
sdram_dq <= (others => 'Z');
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_dqm <= "11";
sdram_abus_complete <= '0';
avalon_sdram_complete <= '0';
avalon_sdram_readdatavalid <= '0';
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '0';
-- in idle mode we should check if any of the events occured:
-- 1) abus transaction detected - priority 0
-- 2) avalon transaction detected - priority 1
-- 3) autorefresh counter exceeded threshold - priority 2
-- if none of these events occur, we keep staying in the idle mode
if sdram_abus_pending = '1' and sdram_abus_complete = '0' then
sdram_mode <= SDRAM_ABUS_ACTIVATE;
--something on abus, address should be stable already (is it???), so we activate row now
sdram_ras_n <= '0';
sdram_addr <= abus_address_latched(23 downto 11);
sdram_ba(0) <= abus_address_latched(24);
sdram_ba(1) <= abus_chipselect_buf(0); --if CS0 is active, it's 0, else it's 1
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
sdram_wait_counter <= to_unsigned(3,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
sdram_wait_counter <= to_unsigned(5,4); -- for writing we use a little longer activate delay, so that the data at the a-bus will become ready
end if;
elsif (avalon_sdram_read_pending = '1' or avalon_sdram_write_pending = '1') and avalon_sdram_complete = '0' then
sdram_mode <= SDRAM_AVALON_ACTIVATE;
--something on avalon, activating!
sdram_ras_n <= '0';
sdram_addr <= avalon_sdram_pending_address(23 downto 11);
sdram_ba <= avalon_sdram_pending_address(25 downto 24);
sdram_wait_counter <= to_unsigned(2,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
if avalon_sdram_read_pending = '1' then
sdram_dqm <= "00";
else
sdram_dqm(0) <= not avalon_sdram_byteenable(0);
sdram_dqm(1) <= not avalon_sdram_byteenable(1);
end if;
elsif sdram_autorefresh_counter(9) = '1' then --512 cycles
sdram_mode <= SDRAM_AUTOREFRESH;
--first stage of autorefresh issues "precharge all" command
sdram_ras_n <= '0';
sdram_we_n <= '0';
sdram_addr(10) <= '1';
sdram_autorefresh_counter <= (others => '0');
sdram_wait_counter <= to_unsigned(1,4); -- precharge all is fast
end if;
when SDRAM_AUTOREFRESH =>
sdram_ras_n <= '1';
sdram_we_n <= '1';
sdram_addr(10) <= '0';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
--switching to ABUS in case of ABUS request caught us between refresh stages
if sdram_abus_pending = '1' then
sdram_mode <= SDRAM_ABUS_ACTIVATE;
--something on abus, address should be stable already (is it???), so we activate row now
sdram_ras_n <= '0';
sdram_addr <= abus_address_latched(23 downto 11);
sdram_ba(0) <= abus_address_latched(24);
sdram_ba(1) <= abus_chipselect_buf(0); --if CS0 is active, it's 0, else it's 1
sdram_wait_counter <= to_unsigned(3,4); -- tRCD = 21ns min ; 3 cycles @ 116mhz = 25ns
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
end if;
else
-- second autorefresh stage - autorefresh command
sdram_cas_n <= '0';
sdram_ras_n <= '0';
sdram_wait_counter <= to_unsigned(7,4); --7 cut to 6 -- tRC = 63ns min ; 8 cycles @ 116mhz = 67ns
sdram_mode <= SDRAM_AUTOREFRESH2;
end if;
end if;
when SDRAM_AUTOREFRESH2 =>
--here we wait for autorefresh to end and move on to idle state
sdram_cas_n <= '1';
sdram_ras_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
end if;
when SDRAM_ABUS_ACTIVATE =>
--while waiting for row to be activated, we choose where to switch to - read or write
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_ras_n <= '1';
--we keep updating dqm in activate stage, because it could change after abus pending
if abus_write_buf = "11" then
sdram_dqm <= "00"; --it's a read
else
sdram_dqm(0) <= abus_write_buf(1); --it's a write
sdram_dqm(1) <= abus_write_buf(0); --it's a write
end if;
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
if my_little_transaction_dir = DIR_WRITE and mapper_write_enable = '1' then --if mapper write is not enabled, doing read instead
sdram_mode <= SDRAM_ABUS_WRITE_AND_PRECHARGE;
counter_count_write <= '1';
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_dq <= abus_data_in(7 downto 0)&abus_data_in(15 downto 8);
sdram_addr <= "001"&abus_address_latched(10 downto 1);
sdram_ba(0) <= abus_address_latched(24);
sdram_ba(1) <= abus_chipselect_buf(0); --if CS0 is active, it's 0, else it's 1
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
else --if my_little_transaction_dir = DIR_READ then
sdram_mode <= SDRAM_ABUS_READ_AND_PRECHARGE;
counter_count_read <= '1';
sdram_cas_n <= '0';
sdram_addr <= "001"&abus_address_latched(10 downto 1);
sdram_ba(0) <= abus_address_latched(24);
sdram_ba(1) <= abus_chipselect_buf(0); --if CS0 is active, it's 0, else it's 1
sdram_wait_counter <= to_unsigned(4,4); --5 cut to 4 -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
--else
-- this is an invalid transaction - either it's for CS2 or from an unmapped range
-- but the bank is already prepared, and we need to precharge it
-- we can issue a precharge command, but read&precharge command will have the same effect, so we use that one
end if;
end if;
when SDRAM_ABUS_READ_AND_PRECHARGE =>
--move on with reading, bus is a Z after idle
--data should be latched at 2nd or 3rd clock (cas=2 or cas=3)
counter_count_read <= '0';
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
sdram_datain_latched <= sdram_dq;
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
sdram_abus_complete <= '1';
sdram_dqm <= "11";
end if;
when SDRAM_ABUS_WRITE_AND_PRECHARGE =>
--move on with writing
counter_count_write <= '0';
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_dq <= (others => 'Z');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
sdram_abus_complete <= '1';
sdram_dqm <= "11";
end if;
when SDRAM_AVALON_ACTIVATE =>
--while waiting for row to be activated, we choose where to switch to - read or write
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_ras_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 0 then
if avalon_sdram_read_pending = '1' then
sdram_mode <= SDRAM_AVALON_READ_AND_PRECHARGE;
sdram_ba <= avalon_sdram_pending_address(25 downto 24);
sdram_cas_n <= '0';
sdram_addr <= "001"&avalon_sdram_pending_address(10 downto 1);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
else
sdram_mode <= SDRAM_AVALON_WRITE_AND_PRECHARGE;
sdram_cas_n <= '0';
sdram_we_n <= '0';
sdram_ba <= avalon_sdram_pending_address(25 downto 24);
sdram_dq <= avalon_sdram_pending_data;
sdram_addr <= "001"&avalon_sdram_pending_address(10 downto 1);
sdram_wait_counter <= to_unsigned(4,4); -- tRP = 21ns min ; 3 cycles @ 116mhz = 25ns
end if;
end if;
when SDRAM_AVALON_READ_AND_PRECHARGE =>
--move on with reading, bus is a Z after idle
--data should be latched at 2nd or 3rd clock (cas=2 or cas=3)
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
avalon_sdram_readdata_latched <= sdram_dq;
avalon_sdram_waitrequest <= '0';
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
avalon_sdram_complete <= '1';
sdram_dqm <= "11";
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '1';
avalon_sdram_readdatavalid <= '1';--'0';
end if;
when SDRAM_AVALON_WRITE_AND_PRECHARGE =>
--move on with writing
sdram_addr <= (others => '0');
sdram_ba <= "00";
sdram_cas_n <= '1';
sdram_we_n <= '1';
sdram_dq <= (others => 'Z');
sdram_wait_counter <= sdram_wait_counter - 1;
if sdram_wait_counter = 1 then
avalon_sdram_reset_pending <= '1';
avalon_sdram_waitrequest <= '0';
end if;
if sdram_wait_counter = 0 then
sdram_mode <= SDRAM_IDLE;
avalon_sdram_complete <= '1';
sdram_dqm <= "11";
avalon_sdram_waitrequest <= '1';
avalon_sdram_reset_pending <= '0';
end if;
end case;
end if;
end process;
sdram_clk <= clock;
------------------------------ A-bus transactions counter ---------------------------------------
-- counter filters transactions transferred over a-bus and counts them
-- for writes, 8-bit transactions are counted as 1 byte, 16-bit as 2 bytes
-- for reads, every access is counted as 2 bytes
-- filter control :
-- bit 0 - read
-- bit 1 - write
-- bit 2 - CS0
-- bit 3 - CS1
-- bit 4 - CS2
process (clock)
begin
if rising_edge(clock) then
if counter_reset = '1' then
counter_value <= (others =>'0');
elsif counter_count_write='1' and counter_filter_control(1) = '1' then
--write detected, checking state
if abus_chipselect_buf(0) = '0' and counter_filter_control(2) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
elsif abus_chipselect_buf(1) = '0' and counter_filter_control(3) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
elsif abus_chipselect_buf(2) = '0' and counter_filter_control(4) = '1' then
if abus_write_buf="00" then
counter_value <= counter_value + 2;
else
counter_value <= counter_value + 1;
end if;
end if;
elsif counter_count_read='1' and counter_filter_control(0) = '1' then
--read detected, checking state
if abus_chipselect_buf(0) = '0' and counter_filter_control(2) = '1' then
counter_value <= counter_value + 2;
elsif abus_chipselect_buf(1) = '0' and counter_filter_control(3) = '1' then
counter_value <= counter_value + 2;
elsif abus_chipselect_buf(2) = '0' and counter_filter_control(4) = '1' then
counter_value <= counter_value + 2;
end if;
end if;
end if;
end process;
------------------------------ A-bus sniffer ---------------------------------------
--fifo should be written in 2 cases
-- 1) write was done to a different block
-- 2) no write within 10 ms
process (clock)
begin
if rising_edge(clock) then
sniffer_pending_set <= '0';
if counter_count_write='1' and sniffer_filter_control(1) = '1' then
--write detected, checking state
if abus_chipselect_buf(0) = '0' and sniffer_filter_control(2) = '1' then
sniffer_pending_set <= '1';
elsif abus_chipselect_buf(1) = '0' and sniffer_filter_control(3) = '1' then
sniffer_pending_set <= '1';
elsif abus_chipselect_buf(2) = '0' and sniffer_filter_control(4) = '1' then
sniffer_pending_set <= '1';
end if;
elsif counter_count_read='1' and sniffer_filter_control(0) = '1' then
--read detected, checking state
if abus_chipselect_buf(0) = '0' and sniffer_filter_control(2) = '1' then
sniffer_pending_set <= '1';
elsif abus_chipselect_buf(1) = '0' and sniffer_filter_control(3) = '1' then
sniffer_pending_set <= '1';
elsif abus_chipselect_buf(2) = '0' and sniffer_filter_control(4) = '1' then
sniffer_pending_set <= '1';
end if;
end if;
end if;
end process;
--if an access passed thru filter, set the request as pending
process (clock)
begin
if rising_edge(clock) then
if sniffer_pending_set = '1' then
sniffer_pending_flag <= '1';
sniffer_pending_block <= abus_address_latched(24 downto 9);
elsif sniffer_pending_reset = '1' then
sniffer_pending_flag <= '0';
end if;
end if;
end process;
--if we have a pending request, and it's for a different block, fill prefifo
process (clock)
begin
if rising_edge(clock) then
sniffer_pending_reset <= '0';
if sniffer_pending_flag = '1' and sniffer_pending_block /= sniffer_last_active_block then
sniffer_last_active_block <= sniffer_pending_block;
sniffer_prefifo <= sniffer_pending_block;
sniffer_pending_reset <= '1';
end if;
end if;
end process;
--if we have a pending request, and it's for a different block, and prefifo is full, flush prefifo
--if we don't have eny requests, but the timeout fired, flush prefifo as well
process (clock)
begin
if rising_edge(clock) then
sniffer_data_write <= '0';
if sniffer_pending_flag = '1' and sniffer_pending_block /= sniffer_last_active_block then
sniffer_prefifo_full <= '1';
if sniffer_prefifo_full='1' then
sniffer_data_in <= sniffer_prefifo;
sniffer_data_write <= '1';
end if;
elsif sniffer_pending_timeout = '1' then
sniffer_data_write <= '1';
sniffer_data_in <= sniffer_prefifo;
sniffer_prefifo_full <= '0';
end if;
end if;
end process;
--timeout counter. resets when another pending is set
process (clock)
begin
if rising_edge(clock) then
if sniffer_pending_set = '1' then
sniffer_pending_timeout_counter <= (others => '0');
elsif sniffer_pending_timeout_counter < std_logic_vector(to_unsigned(134217728,32)) then
sniffer_pending_timeout_counter <= std_logic_vector(unsigned(sniffer_pending_timeout_counter) + 1);
end if;
end if;
end process;
--timeout comparator @ 10ms = 1160000
process (clock)
begin
if rising_edge(clock) then
sniffer_pending_timeout <= '0';
if sniffer_pending_timeout_counter = std_logic_vector(to_unsigned(1160000,32)) then
sniffer_pending_timeout <= '1';
end if;
end if;
end process;
--sniffer_data_in_p1(15 downto 0) <= sniffer_last_active_block when rising_edge(clock);
--sniffer_data_in <= sniffer_data_in_p1 when rising_edge(clock);
--sniffer_data_write <= sniffer_data_write_p1 when rising_edge(clock);
--sniffer_data_out_p1 <= sniffer_data_out when rising_edge(clock);
sniff_fifo_inst : sniff_fifo PORT MAP (
clock => clock,
data => sniffer_data_in,
rdreq => sniffer_data_ack,
wrreq => sniffer_data_write,
empty => sniffer_fifo_empty,
full => sniffer_fifo_full,
q => sniffer_data_out,
usedw => sniffer_fifo_content_size
);
-- --xilinx mode
-- sniff_fifo_inst : sniff_fifo PORT MAP (
-- clk => clock,
-- srst => '0',
-- din => sniffer_data_in,
-- rd_en => sniffer_data_ack,
-- wr_en => sniffer_data_write,
-- empty => sniffer_fifo_empty,
-- full => sniffer_fifo_full,
-- dout => sniffer_data_out,
-- data_count => sniffer_fifo_content_size
-- );
end architecture rtl; -- of sega_saturn_abus_slave
|
gpl-2.0
|
33892c9b933ae07807c158020fc332ab
| 0.557556 | 3.413755 | false | false | false | false |
OpticalMeasurementsSystems/2DImageProcessing
|
2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ip/image_processing_2d_design_proc_sys_reset_0_1/sim/image_processing_2d_design_proc_sys_reset_0_1.vhd
| 1 | 5,970 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_9;
USE proc_sys_reset_v5_0_9.proc_sys_reset;
ENTITY image_processing_2d_design_proc_sys_reset_0_1 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END image_processing_2d_design_proc_sys_reset_0_1;
ARCHITECTURE image_processing_2d_design_proc_sys_reset_0_1_arch OF image_processing_2d_design_proc_sys_reset_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF image_processing_2d_design_proc_sys_reset_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 16,
C_AUX_RST_WIDTH => 16,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END image_processing_2d_design_proc_sys_reset_0_1_arch;
|
gpl-2.0
|
abe6d8c43e72a1b16a7edf26b03e20ae
| 0.709548 | 3.57485 | false | false | false | false |
pwuertz/digitizer2fw
|
sim/tdc_sample_prep_tb.vhd
| 1 | 2,367 |
-------------------------------------------------------------------------------
-- TDC sample preparation test bench
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
use work.sampling_pkg.all;
use work.tdc_sample_prep_pkg.all;
entity tdc_sample_prep_tb is
end tdc_sample_prep_tb;
architecture tdc_sample_prep_tb_arch of tdc_sample_prep_tb is
constant CNT_BITS: natural := 8;
signal samples_d_in: din_samples_t( 0 to 3 ) := (others => (others => '0'));
signal samples_a_in: adc_samples_t( 0 to 1 ) := (others => (ovfl => '0', data => (others => '0')));
signal a_threshold: a_sample_t := (others => '0');
signal a_invert: std_logic := '0';
signal a_average: std_logic_vector( 1 downto 0 ) := (others => '0');
signal samples_d_out: din_samples_t( 0 to 3 );
signal samples_a_out: a_samples_t( 0 to 1 );
signal sample_cnt: unsigned(CNT_BITS-1 downto 0);
signal tdc_events: tdc_events_t;
constant clk_period : time := 4 ns;
signal clk: std_logic := '0';
begin
uut: tdc_sample_prep
generic map (CNT_BITS => CNT_BITS)
port map(
clk => clk,
samples_d_in => samples_d_in,
samples_a_in => samples_a_in,
a_threshold => a_threshold,
a_invert => a_invert,
a_average => a_average,
samples_d_out => samples_d_out,
samples_a_out => samples_a_out,
cnt => sample_cnt,
tdc_events => tdc_events
);
clk_process: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stimulus: process
begin
a_invert <= '1';
wait for 10*clk_period;
samples_d_in <= (others => (others => '1'));
wait for 5*clk_period;
samples_d_in <= (others => (others => '0'));
wait for 10*clk_period;
samples_a_in(0).data <= to_signed(-1000, ADC_SAMPLE_BITS);
samples_a_in(1).data <= to_signed(0, ADC_SAMPLE_BITS);
wait for clk_period;
samples_a_in <= (others => (ovfl => '0', data => (others => '0')));
wait;
end process;
end tdc_sample_prep_tb_arch;
|
gpl-3.0
|
e1bb76a98076603fb414d8ee0603864f
| 0.582418 | 3.175839 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/stage_polynomial_calc_v3.vhd
| 1 | 2,924 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Stage_Polynomial_Calc_v3
-- Module Name: Stage_Polynomial_Calc_v3
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st and 3rd step in Goppa Code Decoding.
--
-- This circuit is the stage for pipeline_polynomial_calc_v3. The pipeline is composed of
-- an arbitrary number of this stages.
--
-- For the computation this circuit applies the Horner scheme, where at each stage
-- an accumulator is multiplied by respective x and then added accumulated with coefficient.
-- In Horner scheme algorithm, it begin from the most significative coefficient until reaches
-- lesser significative coefficient.
--
-- It can also change the inner working to compute syndrome at each stage.
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- Dependencies:
-- VHDL-93
--
-- mult_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity stage_polynomial_calc_v3 is
Generic(gf_2_m : integer range 1 to 20 := 11);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial_coefficient : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC;
mode_polynomial_syndrome : in STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end stage_polynomial_calc_v3;
architecture Behavioral of stage_polynomial_calc_v3 is
component mult_gf_2_m
Generic(gf_2_m : integer range 1 to 20 := 11);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal mult_x_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_x_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_x_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_accumulated : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
begin
value_accumulated <= value_acc xor value_polynomial_coefficient;
mult_x : mult_gf_2_m
Generic Map (gf_2_m => gf_2_m)
Port Map (
a => mult_x_a,
b => mult_x_b,
o => mult_x_o
);
mult_x_a <= value_x;
mult_x_b <= value_acc when mode_polynomial_syndrome = '1' else
value_accumulated;
new_value_syndrome <= value_accumulated when value_codeword = '1' else
value_polynomial_coefficient;
new_value_acc <= mult_x_o;
end Behavioral;
|
bsd-2-clause
|
7d7b124b1383ae3238acb203c4fde306
| 0.647743 | 3.178261 | false | false | false | false |
ruygargar/LCSE_lab
|
rs232/rs232_rx.vhd
| 1 | 3,280 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:35:22 11/15/2013
-- Design Name:
-- Module Name: RS232_RX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RS232_RX is
port (
Clk : in std_logic;
Reset : in std_logic;
LineRD_in : in std_logic;
Valid_out : out std_logic;
Code_out : out std_logic;
Store_out : out std_logic
);
end RS232_RX;
architecture Behavioral of RS232_RX is
type state is (idle, startbit, rcvdata, endbit);
SIGNAL current_st, next_st: state;
CONSTANT PEOC: std_logic_vector (8 downto 0) := "010101101";
CONSTANT HPEOC : std_logic_vector (8 downto 0) := "001010110";
SIGNAL data_count: std_logic_vector (2 downto 0);
SIGNAL bit_counter: std_logic_vector (8 downto 0);
SIGNAL bc_sreset, dc_sreset, dc_enable: std_logic;
begin
Code_out <= LineRD_in;
PROCESS (clk, reset)
BEGIN
IF reset = '0' THEN
current_st <= idle;
ELSIF clk'event AND clk='1' THEN
current_st <= next_st;
END IF;
END PROCESS;
PROCESS (current_st, LineRD_in, bit_counter, data_count)
BEGIN
bc_sreset <= '0';
dc_sreset <= '0';
dc_enable <= '0';
Valid_out <= '0';
Store_out <= '0';
CASE current_st IS
WHEN idle =>
IF (LineRD_in = '0') THEN
bc_sreset <= '1';
next_st <= startbit;
ELSE
next_st <= idle;
END IF;
WHEN startbit =>
IF (bit_counter = HPEOC) THEN
bc_sreset <= '1';
dc_sreset <= '1';
next_st <= rcvdata;
ELSE
next_st <= startbit;
END IF;
WHEN rcvdata =>
IF (bit_counter = PEOC) THEN
dc_enable <= '1';
bc_sreset <= '1';
valid_out <= '1';
END IF;
IF (data_count = "111") AND (bit_counter = PEOC) THEN
bc_sreset <= '1';
next_st <= endbit;
ELSE
next_st <= rcvdata;
END IF;
WHEN endbit =>
IF (bit_counter = PEOC) THEN
IF (LineRD_in = '1') THEN
store_out <= '1';
END IF;
next_st <= idle;
ELSE
next_st <= endbit;
END IF;
END CASE;
END PROCESS;
PROCESS (clk, reset, bc_sreset)
BEGIN
IF reset = '0' THEN
bit_counter <= (others => '0');
ELSIF clk'event AND clk = '1' THEN
IF bc_sreset = '1' THEN
bit_counter <= (others => '0');
ELSE
bit_counter <= bit_counter + '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk, reset, dc_sreset)
BEGIN
IF reset = '0' THEN
data_count <= (others => '0');
ELSIF clk'event AND clk = '1' THEN
IF dc_sreset = '1' THEN
data_count <= (others => '0');
ELSIF dc_enable = '1' THEN
data_count <= data_count + '1';
END IF;
END IF;
END PROCESS;
end Behavioral;
|
gpl-3.0
|
6fb18088e253aa52577e0c8beb5cc57d
| 0.568293 | 3.074039 | false | false | false | false |
ruygargar/LCSE_lab
|
rs232/shift_register.vhd
| 1 | 1,399 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:33:27 11/15/2013
-- Design Name:
-- Module Name: ShiftRegister - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ShiftRegister is
Port ( Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
Enable : in STD_LOGIC;
D : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end ShiftRegister;
architecture Behavioral of ShiftRegister is
signal q_i : std_logic_vector (7 downto 0);
begin
PROCESS (clk, reset)
BEGIN
IF reset = '0' THEN
q_i <= "00000000";
ELSIF clk'event AND clk='1' THEN
IF enable = '1' THEN
q_i <= D & q_i(7 downto 1);
ELSE
q_i <= q_i;
END IF;
END IF;
END PROCESS;
Q <= q_i;
end Behavioral;
|
gpl-3.0
|
0dc21552ae76df80fc48c0757a53ff55
| 0.5604 | 3.760753 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/or_reduce.vhd
| 1 | 1,847 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 07/01/2013
-- Design Name: OR_Reduce
-- Module Name: OR_Reduce
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- OR reduction for any std_logic_vector
--
-- The circuits parameters
--
-- size_vector :
--
-- The size of the std_logic_vector to be reduced.
--
-- number_of_vectors :
--
-- The number of vector to be reduced in one vector of size size_vector.
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or_reduce is
Generic(
vector_size : integer := 1;
number_of_vectors : integer range 2 to integer'high := 2
);
Port(
a : in STD_LOGIC_VECTOR(((vector_size)*(number_of_vectors) - 1) downto 0);
o : out STD_LOGIC_VECTOR((vector_size - 1) downto 0)
);
end or_reduce;
architecture RTL of or_reduce is
signal b : STD_LOGIC_VECTOR(((vector_size)*(number_of_vectors - 1) - 1) downto 0);
begin
b((vector_size - 1) downto 0) <= a((vector_size - 1) downto 0) or a((2*vector_size - 1) downto (vector_size));
more_than_two : if number_of_vectors > 2 generate
reduction : for Index in 0 to (number_of_vectors - 3) generate
b(((vector_size)*(Index + 2) - 1) downto ((vector_size)*(Index + 1))) <= a(((vector_size)*(Index + 3) - 1) downto ((vector_size)*(Index + 2))) or b(((vector_size)*(Index + 1) - 1) downto ((vector_size)*(Index)));
end generate;
end generate;
o <= b(((vector_size)*(number_of_vectors - 1) - 1) downto ((vector_size)*(number_of_vectors - 2)));
end RTL;
|
bsd-2-clause
|
228b42d5fb5f3f96bc8d1ad6630cdb16
| 0.593936 | 3.346014 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/memory_matrix/memory_matrix_tb.vhd
| 1 | 3,769 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory_matrix_tb is
end entity;
architecture memory_matrix_tb_arq of memory_matrix_tb is
signal finished : boolean := false;
signal x_write: std_logic_vector(9 downto 0) := (others => '0');
signal y_write: std_logic_vector(9 downto 0) := (others => '0');
signal write_data: std_logic_vector(0 downto 0) := (others => '0');
signal write_enable: std_logic := '0';
signal clk: std_logic := '0';
signal enable: std_logic := '0';
signal reset: std_logic := '0';
signal x_read: std_logic_vector(9 downto 0) := (others => '0');
signal y_read: std_logic_vector(9 downto 0) := (others => '0');
signal read_data : std_logic_vector(0 downto 0) := (others => '0');
component memory_matrix is
generic(ROWS: integer := 350; COLUMNS: integer := 350; CLK_DELAY_COUNT: integer := 9);
port(
x_write: in std_logic_vector(9 downto 0) := (others => '0');
y_write: in std_logic_vector(9 downto 0) := (others => '0');
write_data: in std_logic_vector(0 downto 0) := (others => '0');
write_enable: in std_logic := '0';
clk: in std_logic := '0';
enable: in std_logic := '0';
reset: in std_logic := '0';
x_read: in std_logic_vector(9 downto 0) := (others => '0');
y_read: in std_logic_vector(9 downto 0) := (others => '0');
read_data : out std_logic_vector(0 downto 0) := (others => '0')
);
end component;
begin
memory_matrix_0 : memory_matrix
generic map(CLK_DELAY_COUNT => 9)
port map(
x_write => x_write,
y_write => y_write,
write_data => write_data,
write_enable => write_enable,
clk => clk,
enable => enable,
reset => reset,
x_read => x_read,
y_read => y_read,
read_data => read_data
);
process(clk)
begin
if(not finished) then
clk <= not(clk) after 1 ns;
end if;
end process;
process
type pattern_type is record
xin : std_logic_vector(9 downto 0);
yin : std_logic_vector(9 downto 0);
wd : std_logic_vector(0 downto 0);
wen : std_logic;
xo : std_logic_vector(9 downto 0);
yo : std_logic_vector(9 downto 0);
dot : std_logic_vector(0 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("0000000100",
"0000000100",
"1",
'1',
"0000000000",
"0000000000",
"0"),
("0000000011",
"0000000011",
"1",
'1',
"0000000000",
"0000000000",
"0"),
("0000000000",
"0000000000",
"0",
'0',
"0000000100",
"0000000100",
"1"),
("0000000000",
"0000000000",
"0",
'0',
"0000000011",
"0000000011",
"1"),
("0000000000",
"0000000000",
"0",
'0',
"0000000011",
"0000000011",
"1"),
("0000000000",
"0000000000",
"0",
'0',
"0000000011",
"0000000011",
"1")
);
begin
reset <= '0';
enable <= '1';
for i in patterns'range loop
-- Set the inputs.
x_write <= patterns(i).xin;
y_write <= patterns(i).yin;
write_data <= patterns(i).wd;
write_enable <= patterns(i).wen;
x_read <= patterns(i).xo;
y_read <= patterns(i).yo;
enable <= '1';
wait for 20 ns;
assert patterns(i).dot = read_data report "BAD SAVED VALUE, EXPECTED: " & std_logic'image(patterns(i).dot(0)) & " GOT: " & std_logic'image(read_data(0));
-- Check the outputs.
end loop;
reset <= '1';
wait for 20 ns;
assert read_data = "0" report "BAD SAVED VALUE, EXPECTED: " & std_logic'image('0') & " GOT: " & std_logic'image(read_data(0));
finished <= true;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
5da53f7fe71c22212994833d29f85601
| 0.572831 | 3.059253 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/contBCD/contbcd_tb.vhd
| 2 | 755 |
library ieee;
use ieee.std_logic_1164.all;
entity contBCD_tb is
end;
architecture contBCD_tb_func of contBCD_tb is
signal rst_in: std_logic:='1';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal n_out: std_logic_vector(3 downto 0);
signal c_out: std_logic:='0';
component contBCD is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
s: out std_logic_vector(3 downto 0);
co: out std_logic
);
end component;
begin
clk_in <= not(clk_in) after 20 ns;
rst_in <= '0' after 50 ns;
enable_in <= '1' after 60 ns;
contadorBCDMap: contBCD port map(
clk => clk_in,
rst => rst_in,
ena => enable_in,
s => n_out,
co => c_out
);
end architecture;
|
gpl-3.0
|
de63d437d1b4fc134a78f1ed045a09c2
| 0.606623 | 2.706093 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/multiplication/floating_point_multiplier/floating_point_multiplier_tb.vhd
| 1 | 1,994 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity floating_point_multiplier_tb is
end entity;
architecture floating_point_multiplier_tb_arq of floating_point_multiplier_tb is
signal number_1_in : std_logic_vector(22 downto 0) := (others => '0');
signal number_2_in : std_logic_vector(22 downto 0) := (others => '0');
signal result : std_logic_vector(22 downto 0) := (others => '0');
component floating_point_multiplier is
generic(
TOTAL_BITS : natural := 23;
EXP_BITS : natural := 6
);
port(
number1_in : in std_logic_vector(TOTAL_BITS - 1 downto 0);
number2_in : in std_logic_vector(TOTAL_BITS - 1 downto 0);
multiplication_result: out std_logic_vector(TOTAL_BITS - 1 downto 0)
);
end component;
for floating_point_multiplier_0 : floating_point_multiplier use entity work.floating_point_multiplier;
begin
floating_point_multiplier_0 : floating_point_multiplier
generic map(TOTAL_BITS => 23, EXP_BITS => 6)
port map(
number1_in => number_1_in,
number2_in => number_2_in,
multiplication_result => result
);
process
type pattern_type is record
n1 : std_logic_vector(22 downto 0);
n2 : std_logic_vector(22 downto 0);
r : std_logic_vector(22 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("11111101111111111111111","00111101010001110011001","11111101010001110011000"),
("11111101111111111111111","00111101010001110011001","11111101010001110011000")
);
begin
for i in patterns'range loop
-- Set the inputs.
number_1_in <= patterns(i).n1;
number_2_in <= patterns(i).n2;
wait for 1 ms;
assert patterns(i).r = result report "EXPECTED: " & integer'image(to_integer(unsigned(patterns(i).r))) & " GOT: " & integer'image(to_integer(unsigned(result)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
6afdceef20398e3f478c8e3dd75dca18
| 0.694584 | 3.175159 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/ram_double_file.vhd
| 1 | 4,468 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: RAM_Double
-- Module Name: RAM_Double_File
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavioral of a double memory RAM.
-- With this memory is possible to read and write at the same cycle.
-- Only used for tests.
--
-- The circuits parameters
--
-- ram_address_size :
--
-- Address size of the RAM used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word on the RAM.
--
-- file_ram_word_size :
--
-- The size of the word used in the file to be loaded on the RAM.(ARCH: FILE_LOAD)
--
-- load_file_name :
--
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
--
-- The name of the file to be used to dump the memory.(ARCH: FILE_LOAD)
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
architecture file_load of ram_double is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
pure function load_ram (ram_file_name : in string) return ramtype is
FILE ram_file : text is in ram_file_name;
variable line_n : line;
variable memory_ram : ramtype;
variable file_read_buffer : std_logic_vector((file_ram_word_size - 1) downto 0);
variable file_buffer_amount : integer;
variable ram_buffer_amount : integer;
begin
file_buffer_amount := file_ram_word_size;
for I in ramtype'range loop
ram_buffer_amount := 0;
if (not endfile(ram_file) or (file_buffer_amount /= file_ram_word_size)) then
while ram_buffer_amount /= ram_word_size loop
if file_buffer_amount = file_ram_word_size then
if (not endfile(ram_file)) then
readline (ram_file, line_n);
read (line_n, file_read_buffer);
else
file_read_buffer := (others => '0');
end if;
file_buffer_amount := 0;
end if;
memory_ram(I)(ram_buffer_amount) := file_read_buffer(file_buffer_amount);
ram_buffer_amount := ram_buffer_amount + 1;
file_buffer_amount := file_buffer_amount + 1;
end loop;
else
memory_ram(I) := (others => '0');
end if;
end loop;
return memory_ram;
end function;
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype := load_ram(load_file_name);
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
memory_ram <= load_ram(load_file_name);
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw_a = '1' then
memory_ram(to_integer(unsigned(address_a))) <= data_in_a;
end if;
data_out_a <= memory_ram(to_integer(unsigned(address_a)));
if rw_b = '1' then
memory_ram(to_integer(unsigned(address_b))) <= data_in_b;
end if;
data_out_b <= memory_ram(to_integer(unsigned(address_b)));
end if;
end process;
end file_load;
|
bsd-2-clause
|
b8ceb890dff4c655c92188dbdf66b837
| 0.506938 | 3.815542 | false | false | false | false |
laurivosandi/hdl
|
arithmetic/src/reciprocal.vhd
| 1 | 1,471 |
library ieee;
use ieee.std_logic_1164.all;
entity reciprocal is
port (
b : in std_logic_vector (15 downto 0);
r : out std_logic_vector (15 downto 0)
);
end reciprocal;
architecture behavioral of reciprocal is
begin
-- Note that this is not the most compact solution,
-- but it leaves room for experimentation.
r <= "1100000000000000" when b = "0000000000000000" else
"0110000000000000" when b(15 downto 1) = "000000000000000" else
"0011000000000000" when b(15 downto 2) = "00000000000000" else
"0001100000000000" when b(15 downto 3) = "0000000000000" else
"0000110000000000" when b(15 downto 4) = "000000000000" else
"0000011000000000" when b(15 downto 5) = "00000000000" else
"0000001100000000" when b(15 downto 6) = "0000000000" else
"0000000110000000" when b(15 downto 7) = "000000000" else
"0000000011000000" when b(15 downto 8) = "00000000" else
"0000000001100000" when b(15 downto 9) = "0000000" else
"0000000000110000" when b(15 downto 10) = "000000" else
"0000000000011000" when b(15 downto 11) = "00000" else
"0000000000001100" when b(15 downto 12) = "0000" else
"0000000000000110" when b(15 downto 13) = "000" else
"0000000000000011" when b(15 downto 14) = "00" else
"0000000000000001" when b(15) = '0' else
"0000000000000000";
end behavioral;
|
mit
|
143e3f4811ff93aa29519f9478a8c735
| 0.634262 | 4.052342 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-LuGus/TP2-Voltimetro/voltage_registry_enabler.vhd
| 1 | 1,037 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utility.all;
entity voltage_registry_enabler is
port (
clk_in: in std_logic;
rst_in: in std_logic;
ena_in: in std_logic;
out_1: out std_logic;
out_2: out std_logic
);
end;
architecture voltage_registry_enabler_arq of voltage_registry_enabler is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(clk_in,rst_in)
variable tmp_count: integer range 0 to 33099;
begin
if rst_in = '1' then
tmp_count := 0;
elsif rising_edge(clk_in) then
if ena_in = '1' then
tmp_count:=tmp_count + 1;
if tmp_count = 33000 then
out_1 <= '1';
out_2 <= '0';
elsif tmp_count = 33001 then
out_1 <= '0';
out_2 <= '1';
elsif tmp_count = 33002 then
tmp_count := 0;
out_1 <= '0';
out_2 <= '0';
else
out_1 <= '0';
out_2 <= '0';
end if;
end if;
end if;
end process;
end;
|
gpl-3.0
|
0ed06a57b22f171d78e40a2c963ba2d8
| 0.566056 | 2.825613 | false | false | false | false |
alainmarcel/Surelog
|
third_party/tests/ariane/fpga/src/apb_uart/src/uart_receiver.vhd
| 5 | 13,609 |
--
-- UART receiver
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.2
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART receiver
entity uart_receiver is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
RXCLK : in std_logic; -- Receiver clock (16x baudrate)
RXCLEAR : in std_logic; -- Reset receiver state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
SIN : in std_logic; -- Receiver input
PE : out std_logic; -- Parity error
FE : out std_logic; -- Framing error
BI : out std_logic; -- Break interrupt
DOUT : out std_logic_vector(7 downto 0); -- Output data
RXFINISHED : out std_logic -- Receiver operation finished
);
end uart_receiver;
architecture rtl of uart_receiver is
-- Majority voting logic
component slib_mv_filter is
generic (
WIDTH : natural := 4;
THRESHOLD : natural := 10
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
SAMPLE : in std_logic; -- Clock enable for sample process
CLEAR : in std_logic; -- Reset process
D : in std_logic; -- Signal input
Q : out std_logic -- Signal D was at least THRESHOLD samples high
);
end component;
component slib_input_filter is
generic (
SIZE : natural := 4 -- Filter counter size
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end component;
-- Counter
component slib_counter is
generic (
WIDTH : natural := 4 -- Counter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear counter register
LOAD : in std_logic; -- Load counter register
ENABLE : in std_logic; -- Enable count operation
DOWN : in std_logic; -- Count direction down
D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input
Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output
OVERFLOW : out std_logic -- Counter overflow
);
end component;
-- FSM
type state_type is (IDLE, START, DATA, PAR, STOP, MWAIT);
signal CState, NState : state_type;
-- Signals
signal iBaudCount : std_logic_vector(3 downto 0); -- Baud counter output
signal iBaudCountClear : std_logic; -- Baud counter clear
signal iBaudStep : std_logic; -- Next symbol pulse
signal iBaudStepD : std_logic; -- Next symbol pulse delayed by one clock
signal iFilterClear : std_logic; -- Reset input filter
signal iFSIN : std_logic; -- Filtered SIN
signal iFStopBit : std_logic; -- Filtered SIN for stop bit detection
signal iParity : std_logic; -- Data parity
signal iParityReceived : std_logic; -- Parity received
signal iDataCount : integer range 0 to 8; -- Data bit counter
signal iDataCountInit : std_logic; -- Initialize data bit counter to word length
signal iDataCountFinish : std_logic; -- Data bit counter finished
signal iRXFinished : std_logic; -- Word received, output data valid
signal iFE : std_logic; -- Internal frame error
signal iBI : std_logic; -- Internal break interrupt
signal iNoStopReceived : std_logic; -- No valid stop bit received
signal iDOUT : std_logic_vector(7 downto 0); -- Data output
begin
-- Baudrate counter: RXCLK/16
RX_BRC: slib_counter generic map (
WIDTH => 4
) port map (
CLK => CLK,
RST => RST,
CLEAR => iBaudCountClear,
LOAD => '0',
ENABLE => RXCLK,
DOWN => '0',
D => x"0",
Q => iBaudCount,
OVERFLOW => iBaudStep
);
-- Input filter
RX_MVF: slib_mv_filter generic map (
WIDTH => 4,
THRESHOLD => 10
) port map (
CLK => CLK,
RST => RST,
SAMPLE => RXCLK,
CLEAR => iFilterClear,
D => SIN,
Q => iFSIN
);
-- Input filter for the stop bit
RX_IFSB: slib_input_filter generic map (
SIZE => 4
) port map (
CLK => CLK,
RST => RST,
CE => RXCLK,
D => SIN,
Q => iFStopBit
);
-- iBaudStepD
RX_IFC: process (CLK, RST)
begin
if (RST = '1') then
iBaudStepD <= '0';
elsif (CLK'event and CLK = '1') then
iBaudStepD <= iBaudStep;
end if;
end process;
iFilterClear <= iBaudStepD or iBaudCountClear;
-- Parity generation
RX_PAR: process (iDOUT, EPS)
begin
iParity <= iDOUT(7) xor iDOUT(6) xor iDOUT(5) xor iDOUT(4) xor iDOUT(3) xor iDOUT(2) xor iDOUT(1) xor iDOUT(0) xor not EPS;
end process;
-- Data bit capture
RX_DATACOUNT: process (CLK, RST)
begin
if (RST = '1') then
iDataCount <= 0;
iDOUT <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iDataCountInit = '1') then
iDataCount <= 0;
iDOUT <= (others => '0');
else
if (iBaudStep = '1' and iDataCountFinish = '0') then
iDOUT(iDataCount) <= iFSIN;
iDataCount <= iDataCount + 1;
end if;
end if;
end if;
end process;
iDataCountFinish <= '1' when (WLS = "00" and iDataCount = 5) or
(WLS = "01" and iDataCount = 6) or
(WLS = "10" and iDataCount = 7) or
(WLS = "11" and iDataCount = 8) else '0';
-- FSM update process
RX_FSMUPDATE: process (CLK, RST)
begin
if (RST = '1') then
CState <= IDLE;
elsif (CLK'event and CLK = '1') then
CState <= NState;
end if;
end process;
-- RX FSM
RX_FSM: process (CState, SIN, iFSIN, iFStopBit, iBaudStep, iBaudCount, iDataCountFinish, PEN, WLS, STB)
begin
-- Defaults
NState <= IDLE;
iBaudCountClear <= '0';
iDataCountInit <= '0';
iRXFinished <= '0';
case CState is
when IDLE => if (SIN = '0') then -- Start detected
NState <= START;
end if;
iBaudCountClear <= '1';
iDataCountInit <= '1';
when START => iDataCountInit <= '1';
if (iBaudStep = '1') then -- Wait for start bit end
if (iFSIN = '0') then
NState <= DATA;
end if;
else
NState <= START;
end if;
when DATA => if (iDataCountFinish = '1') then -- Received all data bits
if (PEN = '1') then
NState <= PAR; -- Parity enabled
else
NState <= STOP; -- No parity
end if;
else
NState <= DATA;
end if;
when PAR => if (iBaudStep = '1') then -- Wait for parity bit
NState <= STOP;
else
NState <= PAR;
end if;
when STOP => if (iBaudCount(3) = '1') then -- Wait for stop bit
if (iFStopBit = '0') then -- No stop bit received
iRXFinished <= '1';
NState <= MWAIT;
else
iRXFinished <= '1';
NState <= IDLE; -- Stop bit end
end if;
else
NState <= STOP;
end if;
when MWAIT => if (SIN = '0') then -- Wait for mark
NState <= MWAIT;
end if;
when others => null;
end case;
end process;
-- Check parity
RX_PARCHECK: process (CLK, RST)
begin
if (RST = '1') then
PE <= '0';
iParityReceived <= '0';
elsif (CLK'event and CLK = '1') then
if (CState = PAR and iBaudStep = '1') then
iParityReceived <= iFSIN; -- Received parity bit
end if;
-- Check parity
if (PEN = '1') then -- Parity enabled
PE <= '0';
if (SP = '1') then -- Sticky parity
if ((EPS xor iParityReceived) = '0') then
PE <= '1'; -- Parity error
end if;
else
if (iParity /= iParityReceived) then
PE <= '1'; -- Parity error
end if;
end if;
else
PE <= '0'; -- Parity disabled
iParityReceived <= '0';
end if;
end if;
end process;
-- Framing error and break interrupt
iNoStopReceived <= '1' when iFStopBit = '0' and (CState = STOP) else '0';
iBI <= '1' when iDOUT = "00000000" and
iParityReceived = '0' and
iNoStopReceived = '1' else '0';
iFE <= '1' when iNoStopReceived = '1' else '0';
-- Output signals
DOUT <= iDOUT;
BI <= iBI;
FE <= iFE;
RXFINISHED <= iRXFinished;
end rtl;
|
apache-2.0
|
656e157c07aded78a0a52679257a6c85
| 0.396061 | 5.419753 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
VHDL/DDR2/DDR_CONTROL.vhd
| 1 | 16,690 |
--FPGA application for this system.
--copyright(c) 2014 dtysky
--This program is free software; you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation; either version 2 of the License, or
--(at your option) any later version.
--This program is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License along
--with this program; if not, write to the Free Software Foundation, Inc.,
--51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
------------------------------------------------------------------------
----The wr_num or rd_num must be less than x"0100"----
----It means Only 1 line would be read/write per operation----
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity DDR2_CONTROL is
generic
(
----------------------timing-------------------
constant tRPA:integer:=4; --PRC ALL Period
constant tMRD:integer:=2; --LM Cycle
constant tRFC:integer:=25; --RF to BA/RF
constant tRP:integer:=3; --PRC ONE Period
constant tWR:integer:=3; --Write Recovery
constant tRCD:integer:=3; --BA TO WR/RD
constant tXSRD:integer:=200; --EXT SRF TO OTHER
constant AL:integer:=2;
constant CL:integer:=3;
constant BL:integer:=4;
constant BLC:integer:=2; ---BL/2
constant WL:integer:=4; ----AL+CL-1
constant RL:integer:=5; ----AL+CL
constant SETUP:integer:=35000;
-----------------------CMD---------------------
constant CMD_INIT:std_logic_vector(4 downto 0):="01000";
constant CMD_LM:std_logic_vector(4 downto 0):="10000";
constant CMD_RF:std_logic_vector(4 downto 0):="10001";
constant CMD_SRF_IN:std_logic_vector(4 downto 0):="00001";
constant CMD_SRF_OUT:std_logic_vector(4 downto 0):="10111";
constant CMD_PRC:std_logic_vector(4 downto 0):="10010";
constant CMD_BA:std_logic_vector(4 downto 0):="10011";
constant CMD_WR:std_logic_vector(4 downto 0):="10100";
constant CMD_RD:std_logic_vector(4 downto 0):="10101";
constant CMD_NOP:std_logic_vector(4 downto 0):="10111";
----------PD FAST,WR=2,CL=3,BT SE,BL=4------------
----------------MR with DLL RESET-----------------
constant MR1:std_logic_vector(12 downto 0):="0010100110010";
---------------MR without DLL RESET---------------
constant MR2:std_logic_vector(12 downto 0):="0010000110010";
--RDQS/DQS# OFF,OCD/DLL ON,ODS FULL,RTT=50,AL=2---
---------------EMR with OCD default---------------
constant EMR_0:std_logic_vector(12 downto 0):="0011111010100";
-----------------EMR with OCD exit----------------
constant EMR_1:std_logic_vector(12 downto 0):="0010001010100";
---------------------default----------------------
constant EMR2:std_logic_vector(12 downto 0):="0000000000000";
constant EMR3:std_logic_vector(12 downto 0):="0000000000000"
);
port
(
pll_lock:in std_logic;
clk_control_p,clk_out_p,clk_out_n:in std_logic;
clk_data:in std_logic;
clk,n_clk:out std_logic;
cke,n_cs,n_ras,n_cas,n_we:out std_logic:='1';
udm,ldm:out std_logic:='0';
udqs_in,ldqs_in:in std_logic:='1';
udqs_out,ldqs_out:out std_logic:='1';
dqs_en:out std_logic:='0';
odt:out std_logic:='0';
bank:out std_logic_vector(2 downto 0):="000";
addr:out std_logic_vector(12 downto 0):="0000000000000";
ram_data_in:in std_logic_vector(15 downto 0):=x"0000";
ram_data_out:out std_logic_vector(15 downto 0):=x"0000";
ram_data_en:out std_logic:='0';
ram_reset:in std_logic:='0';
wr_rqu,rd_rqu:in std_logic:='0';
wr_ready,rd_ready:out std_logic:='0';
wr_end,rd_end:out std_logic:='0';
udm_in,ldm_in:in std_logic:='0';
write_num:in std_logic_vector(15 downto 0);
read_num:in std_logic_vector(15 downto 0);
data_other_in:in std_logic_vector(15 downto 0);
data_other_out:out std_logic_vector(15 downto 0);
bank_other:in std_logic_vector(2 downto 0);
addr_other_row:in std_logic_vector(12 downto 0);
addr_other_col:in std_logic_vector(9 downto 0)
);
end entity;
architecture ddr2_con of DDR2_CONTROL is
---------------------clock-----------------------
signal clk_self,clk_out:std_logic;
----------cke,n_cs,n_ras,n_cas,n_we--------------
signal cmd:std_logic_vector(4 downto 0):=CMD_INIT;
--------------------flags------------------------
type states is (start,wr,rd,prc,srf,arf,reset);
--attribute states_encoding:string;
--attribute states_encoding of states:type is "000 001 010 011 100 101 110";
signal state:states:=start;
-------------------addr buffer-------------------
signal addr_row:std_logic_vector(12 downto 0):="1111111111111";
signal addr_other_row_s:std_logic_vector(12 downto 0);
signal addr_col:std_logic_vector(9 downto 0);
signal bank_s:std_logic_vector(2 downto 0);
--------------------others-----------------------
signal wr_start,rd_start:std_logic:='0';
signal wr_ready_s,rd_ready_s:std_logic:='0';
signal rd_ready_s_1,rd_ready_s_2:std_logic:='0';
signal wr_rqu_s,rd_rqu_s:std_logic;
signal udqs_last,udqs_last_last:std_logic:='0';
signal write_num_s,read_num_s:std_logic_vector(15 downto 0);
signal dqs_en_s:std_logic:='0';
begin
clk<=clk_out_p;
n_clk<=clk_out_n;
cke<=cmd(4);
n_cs<=cmd(3);
n_ras<=cmd(2);
n_cas<=cmd(1);
n_we<=cmd(0);
rd_ready_s<=rd_ready_s_1 or rd_ready_s_2;
wr_ready<=wr_ready_s;
rd_ready<=rd_ready_s;
CONTROL:process(clk_control_p,pll_lock)
variable con_init:integer range 0 to 65535:=0;
variable con_srf:integer range 0 to 255:=0;
variable con_arf:integer range 0 to 31:=0;
variable con_prc:integer range 0 to 7:=0;
variable con_write:integer range 0 to 15:=0;
variable con_write_trans:integer range 0 to 3:=0;
variable con_write_total:integer range 0 to 65536;
variable con_read:integer range 0 to 63:=0;
variable con_read_trans:integer range 0 to 3:=0;
variable con_read_total:integer range 0 to 65536:=0;
variable con_reset:integer range 0 to 31:=0;
begin
if clk_control_p'event and clk_control_p='1' and pll_lock='1' then
if ram_reset='1' then
state<=reset;
else
case state is
---------------------INIT---------------------
when start=>
con_init:=con_init+1;
case con_init is
when 10 =>
odt<='0';
when SETUP=>
cmd<=CMD_NOP;
when SETUP+100=>
cmd<=CMD_PRC;
addr(10)<='1';
when SETUP+100+1=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+1=>
cmd<=CMD_LM;
bank<="010";
addr<=EMR2;
when SETUP+100+tRPA+2=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+2=>
cmd<=CMD_LM;
bank<="011";
addr<=EMR3;
when SETUP+100+tRPA+tMRD+3=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+3=>
cmd<=CMD_LM;
bank<="001";
addr<=EMR_0;
when SETUP+100+tRPA+tMRD+tMRD+4=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+4=>
cmd<=CMD_LM;
bank<="000";
addr<=MR1;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+5=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+5=>
cmd<=CMD_PRC;
addr(10)<='1';
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+6=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+6=>
cmd<=CMD_RF;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+7=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+7=>
cmd<=CMD_RF;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+8=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+8=>
cmd<=CMD_LM;
bank<="000";
addr<=MR2;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+9=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+tMRD+9=>
cmd<=CMD_LM;
bank<="001";
addr<=EMR_0;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+tMRD+10=>
cmd<=CMD_NOP;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+tMRD+tMRD+10=>
cmd<=CMD_LM;
bank<="001";
addr<=EMR_1;
when SETUP+100+tRPA+tMRD+tMRD+tMRD+tMRD+tRPA+tRFC+tRFC+tMRD+tMRD+11=>
cmd<=CMD_NOP;
when SETUP+1000=>
state<=srf;
con_init:=0;
when others=>
con_init:=con_init;
end case;
------------------AUTO REFRESH----------------
when arf=>
if dqs_en_s='0' then
wr_end<='0';
rd_end<='0';
case con_arf is
when 0 =>
con_arf:=con_arf+1;
cmd<=CMD_RF;
when 1=>
cmd<=CMD_NOP;
con_arf:=con_arf+1;
when 1+tRFC=>
con_arf:=0;
if wr_rqu_s='1' then
udm<=udm_in;
ldm<=ldm_in;
bank_s<=bank_other;
addr_row<=addr_other_row;
addr_col<=addr_other_col;
write_num_s<=write_num;
state<=wr;
elsif rd_rqu_s='1' then
udm<=udm_in;
ldm<=ldm_in;
bank_s<=bank_other;
addr_row<=addr_other_row;
addr_col<=addr_other_col;
read_num_s<=read_num;
state<=rd;
else
state<=arf;
end if;
when others=>
con_arf:=con_arf+1;
end case;
elsif wr_ready_s='1' then
case con_write is
when WL =>---WL?未定
wr_end<='1';
wr_ready_s<='0';
dqs_en_s<='0';
dqs_en<='0';
ram_data_en<='0';
con_write:=0;
when others=>
con_write:=con_write+1;
end case;
elsif rd_ready_s='1' then
case con_read is
when RL =>---RL?未定
rd_end<='1';
rd_ready_s_1<='0';
dqs_en_s<='0';
dqs_en<='0';
ram_data_en<='0';
con_read:=0;
when others=>
con_read:=con_read+1;
end case;
else
state<=reset;
end if;
------------------SELF REFRESH----------------
when srf=>
case con_srf is
when 0 =>
cmd<=CMD_SRF_IN;
con_srf:=con_srf+1;
when 1 =>
if wr_rqu_s='1' then
cmd<=CMD_SRF_OUT;
con_srf:=con_srf+1;
elsif rd_rqu_s='1' then
cmd<=CMD_SRF_OUT;
con_srf:=con_srf+1;
else
con_srf:=con_srf;
end if;
when 1+tXSRD =>
if wr_rqu_s='1' or rd_rqu_s='1' then
udm<=udm_in;
ldm<=ldm_in;
wr_end<='0';
rd_end<='0';
bank_s<=bank_other;
addr_row<=addr_other_row;
addr_col<=addr_other_col;
write_num_s<=write_num;
state<=prc;
con_srf:=0;
else
state<=reset;
end if;
when others =>
con_srf:=con_srf+1;
end case;
-------------------PRECHARGE------------------
when prc=>
case con_prc is
when 0 =>
bank<=bank_s;
addr<=addr_row;
con_prc:=con_prc+1;
when 1 =>
cmd<=CMD_PRC;
con_prc:=con_prc+1;
when 2 =>
cmd<=CMD_NOP;
con_prc:=con_prc+1;
when 1+tRP =>
con_prc:=0;
state<=arf;
when others=>
con_prc:=con_prc+1;
end case;
---------------------WRITE--------------------
when wr=>
if dqs_en_s='0' then
case con_write is
when 1 =>
cmd<=CMD_BA;
ram_data_en<='1';
bank<=bank_s;
addr<=addr_row;
con_write_total:=1;
con_write:=con_write+1;
when 2 =>
cmd<=CMD_NOP;
con_write:=con_write+1;
when 2+tRCD =>
cmd<=CMD_WR;
addr(9 downto 0)<=addr_col;
addr(12 downto 10)<="000";
con_write:=con_write+1;
when 3+tRCD =>
cmd<=CMD_NOP;
wr_start<='1';
addr_col<=addr_col+BL;
con_write:=con_write+1;
when 3+tRCD+WL-2 =>
dqs_en<='1';
--wr_ready_s<='1';
con_write:=con_write+1;
when 3+tRCD+WL-1 =>
dqs_en_s<='1';
wr_ready_s<='1';
con_write:=0;
when others =>
con_write:=con_write+1;
end case;
else
state<=state;
end if;
if wr_start='1' then
case con_write_trans is
when BLC-1 =>
cmd<=CMD_NOP;
addr_col<=addr_col+BL;
con_write_trans:=0;
con_write_total:=con_write_total+1;
if con_write_total=conv_integer(write_num_s) then
-- dqs_en_s<='0';
-- ram_data_en<='0';
wr_start<='0';
state<=prc;
else
wr_start<=wr_start;
end if;
when 0 =>
cmd<=CMD_WR;
addr(9 downto 0)<=addr_col;
addr(12 downto 10)<="000";
con_write_trans:=con_write_trans+1;
when others =>
con_write_trans:=con_write_trans+1;
end case;
else
state<=state;
end if;
---------------------READ---------------------
when rd=>
if rd_ready_s_2='1' then
rd_ready_s_1<='1';
else
rd_ready_s_1<=rd_ready_s_1;
end if;
if dqs_en_s='0' then
case con_read is
when 1 =>
cmd<=CMD_BA;
ram_data_en<='0';
bank<=bank_s;
addr<=addr_row;
con_read:=con_read+1;
when 2 =>
cmd<=CMD_NOP;
con_read:=con_read+1;
when 2+tRCD =>
cmd<=CMD_RD;
addr(9 downto 0)<=addr_col;
addr(12 downto 10)<="000";
con_read:=con_read+1;
when 3+tRCD =>
cmd<=CMD_NOP;
rd_start<='1';
addr_col<=addr_col+BL;
con_read:=con_read+1;
when 3+tRCD+RL-2 =>
con_read:=con_read+1;
when 3+tRCD+RL-1 =>
dqs_en_s<='1';
con_read:=0;
when others =>
con_read:=con_read+1;
end case;
else
state<=state;
end if;
if rd_start='1' then
case con_read_trans is
when BLC-1 =>
addr_col<=addr_col+BL;
cmd<=CMD_NOP;
if con_read_total=conv_integer(read_num_s) then
rd_start<='0';
con_read_total:=0;
state<=prc;
else
rd_start<=rd_start;
end if;
con_read_trans:=0;
when 0 =>
cmd<=CMD_RD;
addr(9 downto 0)<=addr_col;
addr(12 downto 10)<="000";
con_read_total:=con_read_total+1;
con_read_trans:=con_read_trans+1;
--when 1 =>
--cmd<=CMD_NOP;
--con_read_total:=con_read_total+1;
when others =>
state<=reset;
end case;
else
state<=state;
end if;
---------------------RESET--------------------
when reset=>
con_arf:=0;
con_prc:=0;
con_read:=0;
con_read_total:=0;
con_read_trans:=0;
con_srf:=0;
con_write:=0;
con_write_total:=0;
con_write_trans:=0;
wr_ready_s<='0';
rd_ready_s_1<='0';
rd_start<='0';
dqs_en_s<='0';
dqs_en<='0';
ram_data_en<='0';
cmd<=CMD_NOP;
case con_reset is
when 20 =>
state<=prc;
con_reset:=0;
when others =>
con_reset:=con_reset+1;
end case;
--------------------OTHERS--------------------
when others=>
state<=reset;
end case;
wr_rqu_s<=wr_rqu;
rd_rqu_s<=rd_rqu;
end if;
end if;
end process;
--------------------dqs/dq-write---------------------
with dqs_en_s select
udqs_out<=
clk_control_p when '1',
'0' when others;
with dqs_en_s select
ldqs_out<=
clk_control_p when '1',
'0' when others;
ram_data_out<=data_other_in;
--------------------dqs/dq-read----------------------
data_other_out<=ram_data_in;
DQS_FLAG:process(clk_data,pll_lock)
begin
if clk_data'event and clk_data='1' and pll_lock='1' then
if state=rd then
if udqs_last='0' and udqs_last_last/='0' then
rd_ready_s_2<='1';
else
rd_ready_s_2<=rd_ready_s_2;
end if;
elsif rd_ready_s_1='0' then
rd_ready_s_2<='0';
else
rd_ready_s_2<=rd_ready_s_2;
end if;
udqs_last<=udqs_in;
udqs_last_last<=udqs_last;
end if;
end process;
end ddr2_con;
|
gpl-2.0
|
01bfe01a7612574dfabee184d207d14a
| 0.517264 | 3.005766 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/mceliece_qd_goppa_decrypt_v2.vhd
| 1 | 26,241 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: McEliece_QD-Goppa_Decrypt_v2
-- Module Name: McEliece_QD-Goppa_Decrypt_v2
-- Project Name: McEliece Goppa Decryption
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit implements McEliece decryption algorithm for binary Goppa codes.
-- The circuit is divided into 3 phases : Syndrome computation, Solving Key Equation and
-- Finding Roots.
-- Each circuits waits for the next one to begin computation. All circuits share some
-- input and output memories, therefore is not possible to make a pipeline of this 3 phases.
-- First circuit, polynomial_syndrome_computing_n, computes the syndrome from the ciphertext
-- and private keys, support L and polynomial g(x) (In this case g(L)^-1).
-- Second circuit, solving_key_equation_4, computes polynomial sigma through
-- the syndrome computed by first circuit.
-- Third circuit, polynomial_syndrome_computing_n, find the roots of polynomial sigma
-- and correct respective errors in the ciphertext and obtains plaintext array.
-- Inversion circuit, inv_gf_2_m_pipeline, is only used during solving_key_equation_4.
-- This circuit was made outside of solving_key_equation_4 so it can be used by other circuits.
--
-- The circuits parameters
--
-- number_of_polynomial_evaluator_syndrome_pipelines :
--
-- The number of pipelines in polynomial_syndrome_computing_n circuit.
-- This number can be 1 or greater.
--
-- polynomial_evaluator_syndrome_pipeline_size :
--
-- This is the number of stages on polynomial_syndrome_computing_n circuit.
-- This number can be 2 or greater.
--
-- polynomial_evaluator_syndrome_size_pipeline_size :
--
-- The number of bits necessary to hold the number of stages on the pipeline.
-- This is ceil(log2(polynomial_evaluator_syndrome_pipeline_size))
--
-- gf_2_m :
--
-- The size of the finite field extension used in this circuit.
-- This values depends of the Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword in this Goppa code.
-- This values depends of the Goppa code used.
--
-- size_codeword :
--
-- The number of bits necessary to store an array of codeword lengths.
-- This is ceil(log2(length_codeword))
--
-- number_of_errors :
--
-- The number of errors the Goppa code is able to decode.
-- This values depends of the Goppa code used.
--
-- size_number_of_errors :
--
-- The number of bits necessary to store an array of number of errors + 1 length.
-- This is ceil(log2(number_of_errors+1))
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- polynomial_syndrome_computing_n Rev 1.0
-- solving_key_equation_4 Rev 1.0
-- inv_gf_2_m_pipeline Rev 1.0
-- register_rst_nbits Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mceliece_qd_goppa_decrypt_v2 is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 27;
-- size_number_of_errors : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 50;
-- size_number_of_errors : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 18;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3307;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 66;
-- size_number_of_errors : integer := 7;
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 32;
-- size_number_of_errors : integer := 6
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [7296, 5632, 128, 13] --
number_of_polynomial_evaluator_syndrome_pipelines : integer := 2;
polynomial_evaluator_syndrome_pipeline_size : integer := 18;
polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
gf_2_m : integer range 1 to 20 := 13;
length_codeword : integer := 7296;
size_codeword : integer := 13;
number_of_errors : integer := 128;
size_number_of_errors : integer := 8
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_L : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
value_G : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_B : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma_evaluated : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
syndrome_generation_finalized : out STD_LOGIC;
key_equation_finalized : out STD_LOGIC;
decryption_finalized : out STD_LOGIC;
address_value_h : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_L : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_codeword : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_G : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_B : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_G : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_B : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_sigma : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_error : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_G : out STD_LOGIC;
write_enable_new_value_B : out STD_LOGIC;
write_enable_new_value_sigma : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_new_value_error : out STD_LOGIC;
write_enable_new_value_sigma_evaluated : out STD_LOGIC;
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_G : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_B : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_error : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0)
);
end mceliece_qd_goppa_decrypt_v2;
architecture Behavioral of mceliece_qd_goppa_decrypt_v2 is
component polynomial_syndrome_computing_n
Generic (
number_of_pipelines : integer := 1;
pipeline_size : integer := 2;
size_pipeline_size : integer := 2;
gf_2_m : integer range 1 to 20 := 13;
number_of_errors : integer := 128;
size_number_of_errors : integer := 8;
number_of_support_elements: integer := 7296;
size_number_of_support_elements : integer := 13
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_message : in STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_h : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
computation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
address_value_error : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_value_error : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR(((gf_2_m) - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_error : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0)
);
end component;
component solving_key_equation_4
Generic(
gf_2_m : integer range 1 to 20;
final_degree : integer;
size_final_degree : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_F : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_G : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_B : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_C : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_F : out STD_LOGIC;
write_enable_G : out STD_LOGIC;
write_enable_B : out STD_LOGIC;
write_enable_C : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_F : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_B : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_G : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_C : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_value_F : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_G : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_B : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_C : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_F : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_G : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_B : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_C : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end component;
component inv_gf_2_m_pipeline
Generic(gf_2_m : integer range 1 to 20 := 13);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
flag : in STD_LOGIC;
clk : in STD_LOGIC;
oflag : out STD_LOGIC;
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component register_rst_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
signal polynomial_evaluator_syndrome_value_x : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_value_polynomial : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal polynomial_evaluator_syndrome_value_message : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal polynomial_evaluator_syndrome_value_h : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_mode_polynomial_syndrome : STD_LOGIC;
signal polynomial_evaluator_syndrome_rst : STD_LOGIC;
signal polynomial_evaluator_syndrome_computation_finalized : STD_LOGIC;
signal polynomial_evaluator_syndrome_address_value_polynomial : STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
signal polynomial_evaluator_syndrome_address_value_x : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_value_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_value_message : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_new_value_message : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_new_value_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_address_new_value_syndrome : STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
signal polynomial_evaluator_syndrome_address_value_error : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_syndrome_write_enable_new_value_acc : STD_LOGIC;
signal polynomial_evaluator_syndrome_write_enable_new_value_syndrome : STD_LOGIC;
signal polynomial_evaluator_syndrome_write_enable_new_value_message : STD_LOGIC;
signal polynomial_evaluator_syndrome_write_enable_value_error : STD_LOGIC;
signal polynomial_evaluator_syndrome_new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal polynomial_evaluator_syndrome_new_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal polynomial_evaluator_syndrome_new_value_message : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal polynomial_evaluator_syndrome_value_error : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal syndrome_finalized : STD_LOGIC;
signal solving_key_equation_rst : STD_LOGIC;
signal solving_key_equation_value_F : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_C : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_key_equation_found : STD_LOGIC;
signal solving_key_equation_write_enable_F : STD_LOGIC;
signal solving_key_equation_write_enable_G : STD_LOGIC;
signal solving_key_equation_write_enable_B : STD_LOGIC;
signal solving_key_equation_write_enable_C : STD_LOGIC;
signal solving_key_equation_new_value_F : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_C : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_address_value_F : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_C : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_F : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_C : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal inv_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal inv_flag : STD_LOGIC;
signal inv_oflag : STD_LOGIC;
signal inv_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
begin
polynomial_evaluator_syndrome : polynomial_syndrome_computing_n
Generic Map(
number_of_pipelines => number_of_polynomial_evaluator_syndrome_pipelines,
pipeline_size => polynomial_evaluator_syndrome_pipeline_size,
size_pipeline_size => polynomial_evaluator_syndrome_size_pipeline_size,
gf_2_m => gf_2_m,
number_of_errors => number_of_errors,
size_number_of_errors => size_number_of_errors,
number_of_support_elements => length_codeword,
size_number_of_support_elements => size_codeword
)
Port Map(
value_x => polynomial_evaluator_syndrome_value_x,
value_acc => polynomial_evaluator_syndrome_value_acc,
value_polynomial => polynomial_evaluator_syndrome_value_polynomial,
value_message => polynomial_evaluator_syndrome_value_message,
value_h => polynomial_evaluator_syndrome_value_h,
mode_polynomial_syndrome => polynomial_evaluator_syndrome_mode_polynomial_syndrome,
clk => clk,
rst => polynomial_evaluator_syndrome_rst,
computation_finalized => polynomial_evaluator_syndrome_computation_finalized,
address_value_polynomial => polynomial_evaluator_syndrome_address_value_polynomial,
address_value_x => polynomial_evaluator_syndrome_address_value_x,
address_value_acc => polynomial_evaluator_syndrome_address_value_acc,
address_value_message => polynomial_evaluator_syndrome_address_value_message,
address_new_value_message => polynomial_evaluator_syndrome_address_new_value_message,
address_new_value_acc => polynomial_evaluator_syndrome_address_new_value_acc,
address_new_value_syndrome => polynomial_evaluator_syndrome_address_new_value_syndrome,
address_value_error => polynomial_evaluator_syndrome_address_value_error,
write_enable_new_value_acc => polynomial_evaluator_syndrome_write_enable_new_value_acc,
write_enable_new_value_syndrome => polynomial_evaluator_syndrome_write_enable_new_value_syndrome,
write_enable_new_value_message => polynomial_evaluator_syndrome_write_enable_new_value_message,
write_enable_value_error => polynomial_evaluator_syndrome_write_enable_value_error,
new_value_syndrome => polynomial_evaluator_syndrome_new_value_syndrome,
new_value_acc => polynomial_evaluator_syndrome_new_value_acc,
new_value_message => polynomial_evaluator_syndrome_new_value_message,
value_error => polynomial_evaluator_syndrome_value_error
);
solving_key_equation : solving_key_equation_4
Generic Map(
gf_2_m => gf_2_m,
final_degree => number_of_errors,
size_final_degree => size_number_of_errors
)
Port Map(
clk => clk,
rst => solving_key_equation_rst,
ready_inv => inv_oflag,
value_F => solving_key_equation_value_F,
value_G => solving_key_equation_value_G,
value_B => solving_key_equation_value_B,
value_C => solving_key_equation_value_C,
value_inv => inv_o,
signal_inv => inv_flag,
key_equation_found => solving_key_equation_key_equation_found,
write_enable_F => solving_key_equation_write_enable_F,
write_enable_G => solving_key_equation_write_enable_G,
write_enable_B => solving_key_equation_write_enable_B,
write_enable_C => solving_key_equation_write_enable_C,
new_value_inv => inv_a,
new_value_F => solving_key_equation_new_value_F,
new_value_B => solving_key_equation_new_value_B,
new_value_G => solving_key_equation_new_value_G,
new_value_C => solving_key_equation_new_value_C,
address_value_F => solving_key_equation_address_value_F,
address_value_G => solving_key_equation_address_value_G,
address_value_B => solving_key_equation_address_value_B,
address_value_C => solving_key_equation_address_value_C,
address_new_value_F => solving_key_equation_address_new_value_F,
address_new_value_G => solving_key_equation_address_new_value_G,
address_new_value_B => solving_key_equation_address_new_value_B,
address_new_value_C => solving_key_equation_address_new_value_C
);
inverter : inv_gf_2_m_pipeline
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => inv_a,
flag => inv_flag,
clk => clk,
oflag => inv_oflag,
o => inv_o
);
reg_syndrome_finalized : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => "1",
clk => clk,
ce => polynomial_evaluator_syndrome_computation_finalized,
rst => rst,
rst_value => "0",
q(0) => syndrome_finalized
);
polynomial_evaluator_syndrome_value_x <= value_L;
polynomial_evaluator_syndrome_value_acc <= value_sigma_evaluated;
polynomial_evaluator_syndrome_value_polynomial <= value_sigma;
polynomial_evaluator_syndrome_value_message <= value_codeword;
polynomial_evaluator_syndrome_value_h <= value_h;
polynomial_evaluator_syndrome_mode_polynomial_syndrome <= not syndrome_finalized;
polynomial_evaluator_syndrome_rst <= ( (rst) or (syndrome_finalized and (not solving_key_equation_key_equation_found)));
solving_key_equation_rst <= not syndrome_finalized;
solving_key_equation_value_F <= value_syndrome;
solving_key_equation_value_G <= value_G;
solving_key_equation_value_B <= value_B;
solving_key_equation_value_C <= value_sigma;
syndrome_generation_finalized <= syndrome_finalized or polynomial_evaluator_syndrome_computation_finalized;
key_equation_finalized <= solving_key_equation_key_equation_found;
decryption_finalized <= polynomial_evaluator_syndrome_computation_finalized and solving_key_equation_key_equation_found;
address_value_h <= polynomial_evaluator_syndrome_address_value_acc;
address_value_L <= polynomial_evaluator_syndrome_address_value_x;
address_value_syndrome <= solving_key_equation_address_value_F when syndrome_finalized = '1' else
"0" & polynomial_evaluator_syndrome_address_new_value_syndrome;
address_value_codeword <= polynomial_evaluator_syndrome_address_value_message;
address_value_G <= solving_key_equation_address_value_G;
address_value_B <= solving_key_equation_address_value_B;
address_value_sigma <= "00" & polynomial_evaluator_syndrome_address_value_polynomial when solving_key_equation_key_equation_found = '1' else
solving_key_equation_address_value_C;
address_value_sigma_evaluated <= polynomial_evaluator_syndrome_address_value_acc;
new_value_syndrome <= solving_key_equation_new_value_F when syndrome_finalized = '1' else
polynomial_evaluator_syndrome_new_value_syndrome;
new_value_G <= solving_key_equation_new_value_G;
new_value_B <= solving_key_equation_new_value_B;
new_value_sigma <= solving_key_equation_new_value_C;
new_value_message <= polynomial_evaluator_syndrome_new_value_message;
new_value_error <= polynomial_evaluator_syndrome_value_error;
new_value_sigma_evaluated <= polynomial_evaluator_syndrome_new_value_acc;
write_enable_new_value_syndrome <= solving_key_equation_write_enable_F when syndrome_finalized = '1' else
polynomial_evaluator_syndrome_write_enable_new_value_syndrome;
write_enable_new_value_G <= solving_key_equation_write_enable_G;
write_enable_new_value_B <= solving_key_equation_write_enable_B;
write_enable_new_value_sigma <= solving_key_equation_write_enable_C;
write_enable_new_value_message <= polynomial_evaluator_syndrome_write_enable_new_value_message;
write_enable_new_value_error <= polynomial_evaluator_syndrome_write_enable_value_error;
write_enable_new_value_sigma_evaluated <= polynomial_evaluator_syndrome_write_enable_new_value_acc;
address_new_value_syndrome <= solving_key_equation_address_new_value_F when syndrome_finalized = '1' else
"0" & polynomial_evaluator_syndrome_address_new_value_syndrome;
address_new_value_G <= solving_key_equation_address_new_value_G;
address_new_value_B <= solving_key_equation_address_new_value_B;
address_new_value_sigma <= solving_key_equation_address_new_value_C;
address_new_value_message <= polynomial_evaluator_syndrome_address_new_value_message;
address_new_value_error <= polynomial_evaluator_syndrome_address_value_error;
address_new_value_sigma_evaluated <= polynomial_evaluator_syndrome_address_new_value_acc;
end Behavioral;
|
bsd-2-clause
|
1112afa45fc12b77ad325bd7defc388b
| 0.721314 | 3.15018 | false | false | false | false |
ruygargar/LCSE_lab
|
ram/spr.vhd
| 1 | 11,333 |
-------------------------------------------------------------------------------
-- Author: Aragonés Orellana, Silvia
-- García Garcia, Ruy
-- Project Name: PIC
-- Design Name: ram.vhd
-- Module Name: spr.vhd
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
entity spr is
PORT (
Clk : in std_logic;
Reset : in std_logic;
WriteEnable : in std_logic;
OutputEnable : in std_logic;
Address : in std_logic_vector(5 downto 0);
Databus : inout std_logic_vector(7 downto 0) := (others => 'Z');
Switches : out std_logic_vector(7 downto 0);
Temp_L : out std_logic_vector(6 downto 0);
Temp_H : out std_logic_vector(6 downto 0)
);
end spr;
architecture Behavioral of spr is
-- Señales usadas para inferir los biestables necesarios para cada uno de
-- los registros de función específica.
-- Cada señal tiene la longitud necesaria para almacenar únicamente
-- información útil, despreciando los bits de la palabra que no son
-- utilizados.
signal DMA_RX_BUFFER_MSB_REG : std_logic_vector (7 downto 0);
signal DMA_RX_BUFFER_MID_REG : std_logic_vector (7 downto 0);
signal DMA_RX_BUFFER_LSB_REG : std_logic_vector (7 downto 0);
signal NEW_INST_REG : std_logic_vector (7 downto 0);
signal DMA_TX_BUFFER_MSB_REG : std_logic_vector (7 downto 0);
signal DMA_TX_BUFFER_LSB_REG : std_logic_vector (7 downto 0);
signal SWITCH_0_REG : std_logic;
signal SWITCH_1_REG : std_logic;
signal SWITCH_2_REG : std_logic;
signal SWITCH_3_REG : std_logic;
signal SWITCH_4_REG : std_logic;
signal SWITCH_5_REG : std_logic;
signal SWITCH_6_REG : std_logic;
signal SWITCH_7_REG : std_logic;
signal LEVER_0_REG : std_logic_vector (3 downto 0);
signal LEVER_1_REG : std_logic_vector (3 downto 0);
signal LEVER_2_REG : std_logic_vector (3 downto 0);
signal LEVER_3_REG : std_logic_vector (3 downto 0);
signal LEVER_4_REG : std_logic_vector (3 downto 0);
signal LEVER_5_REG : std_logic_vector (3 downto 0);
signal LEVER_6_REG : std_logic_vector (3 downto 0);
signal LEVER_7_REG : std_logic_vector (3 downto 0);
signal LEVER_8_REG : std_logic_vector (3 downto 0);
signal LEVER_9_REG : std_logic_vector (3 downto 0);
signal T_STAT_REG : std_logic_vector (7 downto 0);
begin
-- Proceso secuencial utilizado para la actualización del valor almacenado
-- en los registros.
-- Únicamente cuando la señal de control WriteEnable esté activada,
-- almacenará el valor del bus de datos en el registro cuya dirección
-- esté seleccionada en el bus de direcciones.
-- Dispone de una señal de reset asíncrona, activa a nivel bajo, para
-- inicializar el valor de los biestables.
process (Clk, Reset)
begin
if Reset = '0' then
DMA_RX_BUFFER_MSB_REG <= X"00";
DMA_RX_BUFFER_MID_REG <= X"00";
DMA_RX_BUFFER_LSB_REG <= X"00";
NEW_INST_REG <= X"00";
DMA_TX_BUFFER_MSB_REG <= X"00";
DMA_TX_BUFFER_LSB_REG <= X"00";
SWITCH_0_REG <= '0';
SWITCH_1_REG <= '0';
SWITCH_2_REG <= '0';
SWITCH_3_REG <= '0';
SWITCH_4_REG <= '0';
SWITCH_5_REG <= '0';
SWITCH_6_REG <= '0';
SWITCH_7_REG <= '0';
LEVER_0_REG <= X"0";
LEVER_1_REG <= X"0";
LEVER_2_REG <= X"0";
LEVER_3_REG <= X"0";
LEVER_4_REG <= X"0";
LEVER_5_REG <= X"0";
LEVER_6_REG <= X"0";
LEVER_7_REG <= X"0";
LEVER_8_REG <= X"0";
LEVER_9_REG <= X"0";
T_STAT_REG <= X"20";
elsif Clk'event and Clk = '1' then
if WriteEnable = '1' then
case Address is
when DMA_RX_BUFFER_MSB(5 downto 0) =>
DMA_RX_BUFFER_MSB_REG <= Databus;
when DMA_RX_BUFFER_MID(5 downto 0) =>
DMA_RX_BUFFER_MID_REG <= Databus;
when DMA_RX_BUFFER_LSB(5 downto 0) =>
DMA_RX_BUFFER_LSB_REG <= Databus;
when NEW_INST(5 downto 0) =>
NEW_INST_REG <= Databus;
when DMA_TX_BUFFER_MSB(5 downto 0) =>
DMA_TX_BUFFER_MSB_REG <= Databus;
when DMA_TX_BUFFER_LSB(5 downto 0) =>
DMA_TX_BUFFER_LSB_REG <= Databus;
when SWITCH_BASE(5 downto 0) =>
SWITCH_0_REG <= Databus(0);
when (SWITCH_BASE(5 downto 0)+"000001") =>
SWITCH_1_REG <= Databus(0);
when (SWITCH_BASE(5 downto 0)+"000010") =>
SWITCH_2_REG <= Databus(0);
when (SWITCH_BASE(5 downto 0)+"000011") =>
SWITCH_3_REG <= Databus(0);
when (SWITCH_BASE(5 downto 0)+"000100") =>
SWITCH_4_REG <= Databus(0);
when (SWITCH_BASE(5 downto 0)+"000101") =>
SWITCH_5_REG <= Databus(0);
when (SWITCH_BASE(5 downto 0)+"000110") =>
SWITCH_6_REG <= Databus(0);
when (SWITCH_BASE(5 downto 0)+"000111") =>
SWITCH_7_REG <= Databus(0);
when LEVER_BASE(5 downto 0) =>
LEVER_0_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"000001") =>
LEVER_1_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"000010") =>
LEVER_2_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"000011") =>
LEVER_3_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"000100") =>
LEVER_4_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"000101") =>
LEVER_5_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"000110") =>
LEVER_6_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"000111") =>
LEVER_7_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"001000") =>
LEVER_8_REG <= Databus(3 downto 0);
when (LEVER_BASE(5 downto 0)+"001001") =>
LEVER_9_REG <= Databus(3 downto 0);
when T_STAT(5 downto 0) =>
T_STAT_REG <= Databus;
when others =>
end case;
end if;
end if;
end process;
-- Proceso combinacional que multiplexa la salida de los registros hacia el
-- bus de datos en función de la dirección indicada en el bus de
-- direcciones.
-- La salida al bus de datos se mantendrá a alta impedancia siempre que la
-- señal de control OutputEnable este desactivada.
process (OutputEnable, Address,
DMA_RX_BUFFER_MSB_REG, DMA_RX_BUFFER_MID_REG,
DMA_RX_BUFFER_LSB_REG, NEW_INST_REG,
DMA_TX_BUFFER_MSB_REG, DMA_TX_BUFFER_LSB_REG,
SWITCH_0_REG, SWITCH_1_REG, SWITCH_2_REG, SWITCH_3_REG,
SWITCH_4_REG, SWITCH_5_REG, SWITCH_6_REG, SWITCH_7_REG,
LEVER_0_REG, LEVER_1_REG, LEVER_2_REG, LEVER_3_REG, LEVER_4_REG,
LEVER_5_REG, LEVER_6_REG, LEVER_7_REG, LEVER_8_REG, LEVER_9_REG,
T_STAT_REG)
begin
if OutputEnable = '1' then
case Address is
when DMA_RX_BUFFER_MSB(5 downto 0) =>
Databus <= DMA_RX_BUFFER_MSB_REG;
when DMA_RX_BUFFER_MID(5 downto 0) =>
Databus <= DMA_RX_BUFFER_MID_REG;
when DMA_RX_BUFFER_LSB(5 downto 0) =>
Databus <= DMA_RX_BUFFER_LSB_REG;
when NEW_INST(5 downto 0) =>
Databus <= NEW_INST_REG;
when DMA_TX_BUFFER_MSB(5 downto 0) =>
Databus <= DMA_TX_BUFFER_MSB_REG;
when DMA_TX_BUFFER_LSB(5 downto 0) =>
Databus <= DMA_TX_BUFFER_LSB_REG;
when SWITCH_BASE(5 downto 0) =>
Databus <= "0000000"&SWITCH_0_REG;
when (SWITCH_BASE(5 downto 0)+"000001") =>
Databus <= "0000000"&SWITCH_1_REG;
when (SWITCH_BASE(5 downto 0)+"000010") =>
Databus <= "0000000"&SWITCH_2_REG;
when (SWITCH_BASE(5 downto 0)+"000011") =>
Databus <= "0000000"&SWITCH_3_REG;
when (SWITCH_BASE(5 downto 0)+"000100") =>
Databus <= "0000000"&SWITCH_4_REG;
when (SWITCH_BASE(5 downto 0)+"000101") =>
Databus <= "0000000"&SWITCH_5_REG;
when (SWITCH_BASE(5 downto 0)+"000110") =>
Databus <= "0000000"&SWITCH_6_REG;
when (SWITCH_BASE(5 downto 0)+"000111") =>
Databus <= "0000000"&SWITCH_7_REG;
when LEVER_BASE(5 downto 0) =>
Databus <= "0000"&LEVER_0_REG;
when (LEVER_BASE(5 downto 0)+"000001") =>
Databus <= "0000"&LEVER_1_REG;
when (LEVER_BASE(5 downto 0)+"000010") =>
Databus <= "0000"&LEVER_2_REG;
when (LEVER_BASE(5 downto 0)+"000011") =>
Databus <= "0000"&LEVER_3_REG;
when (LEVER_BASE(5 downto 0)+"000100") =>
Databus <= "0000"&LEVER_4_REG;
when (LEVER_BASE(5 downto 0)+"000101") =>
Databus <= "0000"&LEVER_5_REG;
when (LEVER_BASE(5 downto 0)+"000110") =>
Databus <= "0000"&LEVER_6_REG;
when (LEVER_BASE(5 downto 0)+"000111") =>
Databus <= "0000"&LEVER_7_REG;
when (LEVER_BASE(5 downto 0)+"001000") =>
Databus <= "0000"&LEVER_8_REG;
when (LEVER_BASE(5 downto 0)+"001001") =>
Databus <= "0000"&LEVER_9_REG;
when T_STAT(5 downto 0) =>
Databus <= T_STAT_REG;
when others =>
Databus <= (others => '0');
end case;
else
Databus <= (others => 'Z');
end if;
end process;
-- Concatenación de las señales de salida de todos los registros de
-- "Switch" para la creación del bus de salida "Switches".
Switches <= SWITCH_7_REG&SWITCH_6_REG&SWITCH_5_REG&SWITCH_4_REG&
SWITCH_3_REG&SWITCH_2_REG&SWITCH_1_REG&SWITCH_0_REG;
-- Lógica necesaria para transformar el valor almacenado en el registro de
-- temperatura (binario) a su representación en dos dígitos sobre un display
-- alfanumérico (7 segmentos).
-- Los 4 bits superiores del registro se utilizarán para representar el
-- dígito correspondiente a decenas. Los 4 bits inferiores, para el de las
-- unidades.
with T_STAT_REG(7 downto 4) select
Temp_H <=
"0000110" when "0001", -- 1
"1011011" when "0010", -- 2
"1001111" when "0011", -- 3
"1100110" when "0100", -- 4
"1101101" when "0101", -- 5
"1111101" when "0110", -- 6
"0000111" when "0111", -- 7
"1111111" when "1000", -- 8
"1101111" when "1001", -- 9
"1110111" when "1010", -- A
"1111100" when "1011", -- B
"0111001" when "1100", -- C
"1011110" when "1101", -- D
"1111001" when "1110", -- E
"1110001" when "1111", -- F
"0111111" when others; -- 0
with T_STAT_REG(3 downto 0) select
Temp_L <=
"0000110" when "0001", -- 1
"1011011" when "0010", -- 2
"1001111" when "0011", -- 3
"1100110" when "0100", -- 4
"1101101" when "0101", -- 5
"1111101" when "0110", -- 6
"0000111" when "0111", -- 7
"1111111" when "1000", -- 8
"1101111" when "1001", -- 9
"1110111" when "1010", -- A
"1111100" when "1011", -- B
"0111001" when "1100", -- C
"1011110" when "1101", -- D
"1111001" when "1110", -- E
"1110001" when "1111", -- F
"0111111" when others; -- 0
end Behavioral;
|
gpl-3.0
|
30f23f8e6f3f925b8c2c618738fc7ea7
| 0.559781 | 3.052249 | false | false | false | false |
pwuertz/digitizer2fw
|
src/rtl/digital_edge_detect.vhd
| 1 | 2,007 |
-------------------------------------------------------------------------------
-- Detect rising/falling edges in digital input samples
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sampling_pkg.all;
entity digital_edge_detect is
port (
clk: in std_logic;
samples_d: in din_samples_t(0 to 3);
rising_d: out din_samples_t(0 to 3);
falling_d: out din_samples_t(0 to 3)
);
end digital_edge_detect;
architecture digital_edge_detect_arch of digital_edge_detect is
signal samples_d_buffered: din_samples_t(0 to 4) := (others => (others => '0'));
begin
buffer_signal: process(clk)
begin
if rising_edge(clk) then
samples_d_buffered(0) <= samples_d_buffered(4);
samples_d_buffered(1 to 4) <= samples_d;
end if;
end process;
find_rising_edges: process(clk)
begin
if rising_edge(clk) then
for I in 0 to 3 loop
for CH in samples_d_buffered(I)'low to samples_d_buffered(I)'high loop
if samples_d_buffered(I)(CH) = '0' and samples_d_buffered(I+1)(CH) = '1' then
rising_d(I)(CH) <= '1';
else
rising_d(I)(CH) <= '0';
end if;
end loop;
end loop;
end if;
end process;
find_falling_edges: process(clk)
begin
if rising_edge(clk) then
for I in 0 to 3 loop
for CH in samples_d_buffered(I)'low to samples_d_buffered(I)'high loop
if samples_d_buffered(I)(CH) = '1' and samples_d_buffered(I+1)(CH) = '0' then
falling_d(I)(CH) <= '1';
else
falling_d(I)(CH) <= '0';
end if;
end loop;
end loop;
end if;
end process;
end digital_edge_detect_arch;
|
gpl-3.0
|
97b2769566cdaf4e1d368a5ee31cbaed
| 0.562313 | 3.500873 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/ram_multiple_access.vhd
| 1 | 4,310 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: RAM_multiple_access
-- Module Name: RAM_multiple_access
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavioral of multiple memory RAM that shares the same content.
-- It is useful when you want to access more than one location at the same time, and
-- the locations for each access can be anywhere in the memory, where in banks in most
-- time is one address after another.
-- It can be seen as one single with multiple I/O operating at the same time.
--
-- The circuits parameters
--
-- number_of_memories :
--
-- The total number of memories or the total number of I/O's applied.
--
-- ram_address_size :
--
-- Address size of the RAM used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word of the RAM.
--
-- file_ram_word_size :
--
-- The size of the word used in the file to be loaded on the RAM.(ARCH: FILE_LOAD)
--
-- load_file_name :
--
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
--
-- The name of the file to be used to dump the memory.(ARCH: FILE_LOAD)
--
-- Dependencies:
-- VHDL-93
--
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
entity ram_multiple_access is
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR(((ram_word_size)*(number_of_memories) - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR(((ram_address_size)*(number_of_memories) - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR(((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end ram_multiple_access;
architecture simple of ram_multiple_access is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
for I in ramtype'range loop
memory_ram(I) <= rst_value;
end loop;
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))) <= data_in(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
for index in 0 to (number_of_memories - 1) loop
data_out(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index)))));
end loop;
end if;
end process;
end simple;
|
bsd-2-clause
|
aae87b7956ced00238ddbc246a662663
| 0.553364 | 3.624895 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/cordic/cordic_tb.vhd
| 1 | 2,701 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cordic_tb is
end entity;
architecture cordic_tb_arq of cordic_tb is
signal x_in: std_logic_vector(31 downto 0) := (others => '0');
signal y_in: std_logic_vector(31 downto 0) := (others => '0');
signal angle : std_logic_vector(31 downto 0) := (others => '0');
signal x_out : std_logic_vector(31 downto 0) := (others => '0');
signal y_out : std_logic_vector(31 downto 0) := (others => '0');
component cordic is
generic(TOTAL_BITS: integer := 32; STEPS: integer := 16);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
angle: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
for cordic_0 : cordic use entity work.cordic;
begin
cordic_0 : cordic
port map(
x_in => x_in,
y_in => y_in,
angle => angle,
x_out => x_out,
y_out => y_out
);
process
type pattern_type is record
xi : std_logic_vector(31 downto 0);
yi : std_logic_vector(31 downto 0);
a : std_logic_vector(31 downto 0);
xo : std_logic_vector(31 downto 0);
yo : std_logic_vector(31 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000"),
("00000000000000010000000000000000",
"00000000000000010000000000000000",
"00000000001011010000000000000000",
"00000000000000000000000000000000",
"00000000000000010110101000001010"),
("00000000000000010000000000000000",
"00000000000000010000000000000000",
"00000000010110100000000000000000",
"11111111111111110000000000000001",
"00000000000000001111111111111100")
);
begin
for i in patterns'range loop
-- Set the inputs.
x_in <= patterns(i).xi;
y_in <= patterns(i).yi;
angle <= patterns(i).a;
wait for 1 ns;
assert patterns(i).xo = x_out report "BAD X, EXPECTED: " & integer'image(to_integer(signed(patterns(i).xo))) & " GOT: " & integer'image(to_integer(signed(x_out)));
assert patterns(i).yo = y_out report "BAD Y, GOT: " & integer'image(to_integer(signed(y_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
76d9227147d7d9a3455dae2b2b4c0ecc
| 0.661237 | 3.393216 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-LuGus/TP2-Voltimetro/bcd_multiplexer.vhd
| 1 | 1,301 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd_multiplexer is
port(
bcd0_input : in std_logic_vector(3 downto 0);
bcd1_input : in std_logic_vector(3 downto 0);
bcd2_input : in std_logic_vector(3 downto 0);
bcd3_input : in std_logic_vector(3 downto 0);
bcd4_input : in std_logic_vector(3 downto 0);
bcd5_input : in std_logic_vector(3 downto 0);
mux_selector : in std_logic_vector (2 downto 0);
mux_output : out std_logic_vector (5 downto 0)
);
end bcd_multiplexer;
architecture bcd_multiplexer_arq of bcd_multiplexer is
begin
process (mux_selector,bcd0_input,bcd1_input,bcd2_input,bcd3_input,bcd4_input,bcd5_input) is
begin
case mux_selector is
when "000" => mux_output <= "00"&bcd0_input;
when "001" => mux_output <= "00"&bcd1_input;
when "010" => mux_output <= "00"&bcd2_input;
when "011" => mux_output <= "00"&bcd3_input;
when "100" => mux_output <= "00"&bcd4_input;
--when "101" => mux_output <= "00"&bcd5_input;
when others => mux_output <= "00"&bcd5_input;
end case;
end process;
end bcd_multiplexer_arq;
|
gpl-3.0
|
14b08f16f370432a9f2d94f735ba7830
| 0.568793 | 3.212346 | false | false | false | false |
andrecp/myhdl_simple_uart
|
generated_files/baudrate_gen.vhd
| 1 | 2,442 |
-----------------------------------------------------------------------------
-- Title :
-- Project :
-----------------------------------------------------------------------------
-- File : baudrate_gen.vhd
-- Author :
-- Company :
-- Created : Thu Aug 21 10:54:44 2014
-- Last update : Thu Aug 21 10:54:44 2014
-- Target Device : Cyclone V
-- Standard : VHDL'93
------------------------------------------------------------------------------
-- Description :
------------------------------------------------------------------------------
-- Generated with MyHDL Version 0.8
------------------------------------------------------------------------------
-- Copyright : (c) 2014
------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
------------------------------------------------------------------------------
-- Libraries and use clauses
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity baudrate_gen is
port (
sysclk: in std_logic;
reset_n: in std_logic;
half_baud_rate_tick_o: out std_logic;
baud_rate_tick_o: out std_logic
);
end entity baudrate_gen;
-- Serial
-- This module implements a baudrate generator
--
-- Ports:
-- -----
-- sysclk: sysclk input
-- reset_n: reset input
-- baud_rate_i: the baut rate to generate
-- baud_rate_tick_o: the baud rate enable
-- -----
architecture MyHDL of baudrate_gen is
constant half_baud_const: integer := 434;
constant baud_rate_i: integer := 868;
signal baud_gen_count_reg: unsigned(9 downto 0);
begin
BAUDRATE_GEN_SEQUENTIAL_PROCESS: process (sysclk, reset_n) is
begin
if (reset_n = '0') then
baud_gen_count_reg <= to_unsigned(0, 10);
baud_rate_tick_o <= '0';
half_baud_rate_tick_o <= '0';
elsif rising_edge(sysclk) then
baud_gen_count_reg <= (baud_gen_count_reg + 1);
baud_rate_tick_o <= '0';
half_baud_rate_tick_o <= '0';
if (baud_gen_count_reg = baud_rate_i) then
baud_gen_count_reg <= to_unsigned(0, 10);
baud_rate_tick_o <= '1';
half_baud_rate_tick_o <= '1';
end if;
if (baud_gen_count_reg = half_baud_const) then
half_baud_rate_tick_o <= '1';
end if;
end if;
end process BAUDRATE_GEN_SEQUENTIAL_PROCESS;
end architecture MyHDL;
|
mit
|
d38c022a92670cd02e4b5bd9a2158faa
| 0.47502 | 3.996727 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
VHDL/TD_DISPLAYER.vhd
| 1 | 16,188 |
--FPGA application for this system.
--copyright(c) 2014 dtysky
--This program is free software; you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation; either version 2 of the License, or
--(at your option) any later version.
--This program is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License along
--with this program; if not, write to the Free Software Foundation, Inc.,
--51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
------------------------------------------------------------------------
--RAM模块输入为USB模块和LED模块的或
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
----------------clk_ledm 待替换-----------
------------------命名规则-----------------
---- uwr: usb with ram
---- lwr: ram with led
---- lwb: bluetooth with led
entity TD_DISPLAYER is
port
(
inclk:in std_logic;
------------DDR2------------
ddr2_clk,ddr2_n_clk:out std_logic;
cke,n_cs,n_ras,n_cas,n_we:out std_logic:='0';
udm,ldm:out std_logic:='0';
udm_2,ldm_2:out std_logic:='0';
udqs,ldqs:inout std_logic:='1';
udqs_2,ldqs_2:inout std_logic:='1';
odt:out std_logic:='1';
ddr2_bank:out std_logic_vector(2 downto 0);
ddr2_addr:out std_logic_vector(12 downto 0);
ddr2_data:inout std_logic_vector(31 downto 0):=x"00000000";
------------USB--------------
usb_full,usb_empty:in std_logic;
usb_clk:out std_logic;
sloe,slrd,pktend:out std_logic:='0';
slwr:out std_logic:='0';
pc_rqu:in std_logic;
usb_in:in std_logic;
usb_fifoadr:out std_logic_vector(1 downto 0);
usb_data:inout std_logic_vector(15 downto 0);
-------------LED--------------
sensor:in std_logic;
data_buffer_a:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_b:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_c:out std_logic_vector(39 downto 0):=x"0000000000";
en_row_a:out std_logic:='0';
en_row_b:out std_logic:='0';
en_row_c:out std_logic_vector(1 downto 0):="00"; --------分割为两个管脚，分配同一信号
en_col_a_1,en_col_a_2,en_col_a_3:out std_logic:='0';
en_col_b_1,en_col_b_2,en_col_b_3:out std_logic:='0';
en_col_c_1,en_col_c_2,en_col_c_3:out std_logic:='0';
-----------BLUETOOTH-----------
bluetooth_rqu:in std_logic:='0';
bluetooth_ack:out std_logic:='0';
bluetooth_reset:out std_logic:='0';
bluetooth_data:inout std_logic_vector(3 downto 0):=x"0";
test:in std_logic
);
end entity;
architecture displayer of TD_DISPLAYER is
component PLL1 is
port
(
inclk0:in std_logic;
c0,c1,c2,c3:out std_logic;
locked:out std_logic
);
end component;
component PLL2 is
port
(
inclk0:in std_logic;
c0,c1,c2,c3,c4:out std_logic;
locked:out std_logic
);
end component;
component PLL3 is
port
(
inclk0:in std_logic;
c0:out std_logic;
locked:out std_logic
);
end component;
component DDR2_CONTROL is
port
(
pll_lock:in std_logic;
clk_control_p,clk_out_p,clk_out_n:in std_logic;
clk_data:in std_logic;
clk,n_clk:out std_logic;
cke,n_cs,n_ras,n_cas,n_we:out std_logic:='1';
udm,ldm:out std_logic:='0';
udqs_in,ldqs_in:in std_logic:='1';
udqs_out,ldqs_out:out std_logic:='1';
dqs_en:out std_logic:='0';
odt:out std_logic:='1';
bank:out std_logic_vector(2 downto 0);
addr:out std_logic_vector(12 downto 0);
ram_data_in:in std_logic_vector(15 downto 0):=x"0000";
ram_data_out:out std_logic_vector(15 downto 0):=x"0000";
ram_data_en:out std_logic:='0';
ram_reset:in std_logic:='0';
wr_rqu,rd_rqu:in std_logic:='0';
wr_ready,rd_ready:out std_logic:='0';
wr_end,rd_end:out std_logic:='1';
udm_in,ldm_in:in std_logic:='0';
write_num:in std_logic_vector(15 downto 0);
read_num:in std_logic_vector(15 downto 0);
data_other_in:in std_logic_vector(15 downto 0);
data_other_out:out std_logic_vector(15 downto 0);
bank_other:in std_logic_vector(2 downto 0);
addr_other_row:in std_logic_vector(12 downto 0);
addr_other_col:in std_logic_vector(9 downto 0)
);
end component;
component USB_RAM_BUFFER is
port
(
clk_usb_lock,clk_ram_lock:in std_logic;
clk_usb_p,clk_usb_o_p:in std_logic;
clk_ram_p:in std_logic;
usb_clk:out std_logic;
usb_full,usb_empty:in std_logic;
sloe,slrd,pktend:out std_logic:='0';
slwr:out std_logic:='0';
fifoadr:out std_logic_vector(1 downto 0);
pc_rqu:in std_logic;
usb_in:in std_logic;
usb_data_in:in std_logic_vector(15 downto 0);
usb_data_out:out std_logic_vector(15 downto 0);
usb_data_en:out std_logic:='0';
ram_dm:out std_logic_vector(3 downto 0);
w_rqu,r_rqu:out std_logic;
w_ready,r_ready:in std_logic;
w_end,r_end:in std_logic;
w_num,r_num:out std_logic_vector(15 downto 0);
ram_bank:out std_logic_vector(2 downto 0);
ram_addr_row:out std_logic_vector(12 downto 0);
ram_addr_col:out std_logic_vector(9 downto 0);
ram_data_in:in std_logic_vector(15 downto 0);
ram_data_out:out std_logic_vector(15 downto 0);
ram_reset:out std_logic:='0';
usb_end:out std_logic:='0'
);
end component;
component LED is
port
(
clk_control:in std_logic;
clk_data_p:in std_logic;
sensor:in std_logic;
data_buffer_a:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_b:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_c:out std_logic_vector(39 downto 0):=x"0000000000";
en_row_a:out std_logic:='0';
en_row_b:out std_logic:='0';
en_row_c:out std_logic_vector(1 downto 0):="00"; --------分割为两个管脚，分配同一信号
en_col_a_1,en_col_a_2,en_col_a_3:out std_logic:='0';
en_col_b_1,en_col_b_2,en_col_b_3:out std_logic:='0';
en_col_c_1,en_col_c_2,en_col_c_3:out std_logic:='0';
blue_rqu:in std_logic:='0';
blue_end:out std_logic:='0';
blue_data:in std_logic_vector(7 downto 0):=x"00";
ram_data:in std_logic_vector(15 downto 0);
r_rqu:out std_logic;
r_ready:in std_logic;
ram_reset:out std_logic;
r_end:in std_logic;
r_num:out std_logic_vector(7 downto 0);
ram_dm:out std_logic_vector(3 downto 0);
ram_bank:out std_logic_vector(2 downto 0);
ram_addr_row:out std_logic_vector(12 downto 0);
ram_addr_col:out std_logic_vector(9 downto 0)
);
end component;
component BLUETOOTH_CONTROL is
port
(
clk_self,pll_lock:in std_logic;
bluetooth_rqu:in std_logic:='0';
bluetooth_ack:out std_logic:='0';
bluetooth_reset:out std_logic:='0';
bluetooth_data:inout std_logic_vector(3 downto 0):=x"0";
in_rqu:out std_logic:='0';
in_end:in std_logic:='0';
data_in:out std_logic_vector(7 downto 0)
--error:std_logic
);
end component;
-----------------------clock--------------------------
signal inclk_pll2,inclk_pll3:std_logic;
signal clk_40m_p,clk_40m_p1:std_logic;
signal clk_160m_p,clk_160m_p1,clk_160m_n1:std_logic;
signal clk_320m_p,clk_320m_n,clk_stpii:std_logic;
signal pll1_lock,pll2_lock,pll3_lock:std_logic:='0';
------------------------ram----------------------------
signal data_from_ram_1,data_from_ram_2:std_logic_vector(15 downto 0);
signal dm_s:std_logic_vector(3 downto 0);
signal rd_rqu_s,rd_ready_s,rd_end_s:std_logic;
signal rd_num_s:std_logic_vector(15 downto 0);
signal ram_bank_s:std_logic_vector(2 downto 0);
signal ram_addr_row_s:std_logic_vector(12 downto 0);
signal ram_addr_col_s:std_logic_vector(9 downto 0);
signal ram_data_in,ram_data_out:std_logic_vector(31 downto 0);
signal ram_data_en:std_logic:='0';
signal udqs_in,ldqs_in:std_logic:='1';
signal udqs_out,ldqs_out:std_logic:='1';
signal dqs_en:std_logic:='0';
signal udqs_in_2,ldqs_in_2:std_logic:='1';
signal udqs_out_2,ldqs_out_2:std_logic:='1';
signal dqs_en_2:std_logic:='0';
------------------------usb----------------------------
signal usb_data_in,usb_data_out:std_logic_vector(15 downto 0);
signal usb_data_en:std_logic:='0';
---------------------usb with ram----------------------
signal uwr_wr_rqu,uwr_rd_rqu:std_logic;
signal uwr_wr_ready,uwr_rd_ready:std_logic;
signal uwr_wr_end,uwr_rd_end:std_logic;
signal uwr_dm:std_logic_vector(3 downto 0);
signal uwr_wr_num,uwr_rd_num:std_logic_vector(15 downto 0);
signal uwr_bank:std_logic_vector(2 downto 0);
signal uwr_addr_row:std_logic_vector(12 downto 0);
signal uwr_addr_col:std_logic_vector(9 downto 0);
signal uwr_data_toram,uwr_data_tousb:std_logic_vector(15 downto 0);
signal ram_reset_s1,ram_reset_s2,ram_reset_s:std_logic;
signal usb_end_s,usb_end_last:std_logic;
---------------------led with ram----------------------
signal lwr_rd_rqu:std_logic;
signal lwr_rd_ready:std_logic;
signal lwr_rd_end:std_logic;
signal lwr_dm:std_logic_vector(3 downto 0);
signal lwr_rd_num:std_logic_vector(7 downto 0);
signal lwr_bank:std_logic_vector(2 downto 0);
signal lwr_addr_row:std_logic_vector(12 downto 0);
signal lwr_addr_col:std_logic_vector(9 downto 0);
signal lwr_data_ram:std_logic_vector(15 downto 0);
-------------------led with bluetooth-------------------
signal lwb_in_rqu:std_logic;
signal lwb_in_end:std_logic;
signal lwb_in_data:std_logic_vector(7 downto 0);
begin
PLL_1:PLL1
port map
(
inclk0=>inclk,
c0=>clk_40m_p,c1=>clk_40m_p1,c2=>inclk_pll2,c3=>inclk_pll3,
locked=>pll1_lock
);
PLL_2:PLL2
port map
(
inclk0=>inclk_pll2,
c0=>clk_160m_p,c1=>clk_160m_p1,c2=>clk_160m_n1,c3=>clk_320m_p,c4=>clk_320m_n,
locked=>pll2_lock
);
PLL_3:PLL3
port map
(
inclk0=>inclk_pll3,
c0=>clk_stpii,
locked=>pll3_lock
);
DDR2_1:DDR2_CONTROL
port map
(
pll_lock=>pll2_lock,
clk_control_p=>clk_160m_p,clk_out_p=>clk_160m_p1,clk_out_n=>clk_160m_n1,
clk_data=>clk_320m_p,
clk=>ddr2_clk,n_clk=>ddr2_n_clk,
cke=>cke,n_cs=>n_cs,n_ras=>n_ras,n_cas=>n_cas,n_we=>n_we,
udm=>udm,ldm=>ldm,
udqs_in=>udqs_in,ldqs_in=>ldqs_in,
udqs_out=>udqs_out,ldqs_out=>ldqs_out,
dqs_en=>dqs_en,
odt=>odt,
bank=>ddr2_bank,addr=>ddr2_addr,
ram_data_in=>ram_data_in(15 downto 0),
ram_data_out=>ram_data_out(15 downto 0),
ram_data_en=>ram_data_en,
ram_reset=>ram_reset_s,
wr_rqu=>uwr_wr_rqu,rd_rqu=>rd_rqu_s,
wr_ready=>uwr_wr_ready,rd_ready=>rd_ready_s,
wr_end=>uwr_wr_end,rd_end=>rd_end_s,
udm_in=>dm_s(1),ldm_in=>dm_s(0),
write_num=>uwr_wr_num,read_num=>rd_num_s,
bank_other=>ram_bank_s,
addr_other_row=>ram_addr_row_s,
addr_other_col=>ram_addr_col_s,
data_other_in=>uwr_data_toram,
data_other_out=>data_from_ram_1
);
DDR2_2:DDR2_CONTROL
port map
(
pll_lock=>pll2_lock,
clk_control_p=>clk_160m_p,clk_out_p=>clk_160m_p1,clk_out_n=>clk_160m_n1,
clk_data=>clk_320m_p,
-- clk=>ddr2_clk,n_clk=>ddr2_n_clk,
-- cke=>cke,n_cs=>n_cs,n_ras=>n_ras,n_cas=>n_cas,n_we=>n_we,
udm=>udm_2,ldm=>ldm_2,
udqs_in=>udqs_in_2,ldqs_in=>ldqs_in_2,
udqs_out=>udqs_out_2,ldqs_out=>ldqs_out_2,
dqs_en=>dqs_en_2,
-- odt=>odt,
-- bank=>ddr2_bank,addr=>ddr2_addr,
ram_data_in=>ram_data_in(31 downto 16),
ram_data_out=>ram_data_out(31 downto 16),
ram_reset=>ram_reset_s,
wr_rqu=>uwr_wr_rqu,rd_rqu=>rd_rqu_s,
-- wr_ready=>uwr_wr_ready,rd_ready=>uwr_rd_ready,
-- wr_end=>uwr_wr_end,rd_end=>uwr_rd_end,
write_num=>uwr_wr_num,read_num=>rd_num_s,
udm_in=>dm_s(3),ldm_in=>dm_s(2),
bank_other=>ram_bank_s,
addr_other_row=>ram_addr_row_s,
addr_other_col=>ram_addr_col_s,
data_other_in=>uwr_data_toram,
data_other_out=>data_from_ram_2
);
USB:USB_RAM_BUFFER
port map
(
clk_usb_lock=>pll1_lock,clk_ram_lock=>pll2_lock,
clk_usb_p=>clk_40m_p,clk_usb_o_p=>clk_40m_p1,
clk_ram_p=>clk_320m_p,
usb_clk=>usb_clk,
usb_full=>usb_full,usb_empty=>usb_empty,
sloe=>sloe,slrd=>slrd,slwr=>slwr,pktend=>pktend,
fifoadr=>usb_fifoadr,
usb_data_in=>usb_data_in,
usb_data_out=>usb_data_out,
usb_data_en=>usb_data_en,
pc_rqu=>pc_rqu,
usb_in=>usb_in,
w_rqu=>uwr_wr_rqu,r_rqu=>uwr_rd_rqu,
w_ready=>uwr_wr_ready,r_ready=>uwr_rd_ready,
w_end=>uwr_wr_end,r_end=>uwr_rd_end,
ram_dm=>uwr_dm,
w_num=>uwr_wr_num,r_num=>uwr_rd_num,
ram_bank=>uwr_bank,
ram_addr_row=>uwr_addr_row,
ram_addr_col=>uwr_addr_col,
ram_data_in=>uwr_data_tousb,
ram_data_out=>uwr_data_toram,
ram_reset=>ram_reset_s1,
usb_end=>usb_end_s
);
LED_CONTROL:LED
port map
(
clk_control=>clk_40m_p,
clk_data_p=>clk_320m_p,
sensor=>sensor,
data_buffer_a=>data_buffer_a,
data_buffer_b=>data_buffer_b,
data_buffer_c=>data_buffer_c,
en_row_a=>en_row_a,
en_row_b=>en_row_b,
en_row_c=>en_row_c,
en_col_a_1=>en_col_a_1,en_col_a_2=>en_col_a_2,en_col_a_3=>en_col_a_3,
en_col_b_1=>en_col_b_1,en_col_b_2=>en_col_b_2,en_col_b_3=>en_col_b_3,
en_col_c_1=>en_col_c_1,en_col_c_2=>en_col_c_2,en_col_c_3=>en_col_c_3,
blue_rqu=>lwb_in_rqu,
blue_end=>lwb_in_end,
blue_data=>lwb_in_data,
r_rqu=>lwr_rd_rqu,
r_ready=>lwr_rd_ready,
r_end=>lwr_rd_end,
r_num=>lwr_rd_num,
ram_reset=>ram_reset_s2,
ram_dm=>lwr_dm,
ram_bank=>lwr_bank,
ram_addr_row=>lwr_addr_row,
ram_addr_col=>lwr_addr_col,
ram_data=>lwr_data_ram
);
BLUETOOTH:BLUETOOTH_CONTROL
port map
(
clk_self=>clk_40m_p,pll_lock=>pll1_lock,
bluetooth_rqu=>bluetooth_rqu,
bluetooth_ack=>bluetooth_ack,
bluetooth_reset=>bluetooth_reset,
bluetooth_data=>bluetooth_data,
in_rqu=>lwb_in_rqu,
in_end=>lwb_in_end,
data_in=>lwb_in_data
);
RAM:process(clk_320m_p,pll2_lock)
begin
if clk_320m_p'event and clk_320m_p='1' and pll2_lock='1' then
-- case usb_data_en is
--
-- when '0' =>
-- usb_data<="ZZZZZZZZZZZZZZZZ";
-- usb_data_in<=usb_data;
--
-- when others =>
-- usb_data<=usb_data_out;
--
-- end case;
-- case dm_s is
--
-- when "0011" =>
-- uwr_data_tousb<=data_from_ram_2;
-- lwr_data_ram<=data_from_ram_2;
-- when "1100" =>
-- uwr_data_tousb<=data_from_ram_1;
-- lwr_data_ram<=data_from_ram_1;
-- when others =>
-- null;
--
-- end case;
case usb_end_last is
when '0' =>
dm_s<=uwr_dm;
ram_bank_s<=uwr_bank;
ram_addr_row_s<=uwr_addr_row;
ram_addr_col_s<=uwr_addr_col;
rd_rqu_s<=uwr_rd_rqu;
rd_num_s<=uwr_rd_num;
ram_reset_s<=ram_reset_s1;
when others =>
dm_s<=lwr_dm;
ram_bank_s<=lwr_bank;
ram_addr_row_s<=lwr_addr_row;
ram_addr_col_s<=lwr_addr_col;
rd_rqu_s<=lwr_rd_rqu;
rd_num_s(15 downto 8)<=x"00";
rd_num_s(7 downto 0)<=lwr_rd_num;
ram_reset_s<=ram_reset_s2;
end case;
usb_end_last<=usb_end_s;
-- if ram_data_out(15 downto 0)=x"0010" then
-- ram_data_out(15 downto 0)<=x"0000";
-- else
-- ram_data_out(15 downto 0)<=ram_data_out(15 downto 0)+1;
-- end if;
-- ram_data_out(31 downto 16)<=ram_data_out(15 downto 0);
end if;
end process;
with dm_s select
uwr_data_tousb<=data_from_ram_2 when "0011",
data_from_ram_1 when others;
with dm_s select
lwr_data_ram<=data_from_ram_2 when "0011",
data_from_ram_1 when others;
with usb_data_en select
usb_data <= usb_data_out when '1',
"ZZZZZZZZZZZZZZZZ" when others;
usb_data_in<=usb_data;
with dqs_en select
udqs <= udqs_out when '1',
'Z' when others;
udqs_in<=udqs;
with dqs_en select
ldqs <= ldqs_out when '1',
'Z' when others;
ldqs_in<=ldqs;
with dqs_en_2 select
udqs_2 <= udqs_out_2 when '1',
'Z' when others;
udqs_in_2<=udqs_2;
with dqs_en_2 select
ldqs_2 <= ldqs_out_2 when '1',
'Z' when others;
ldqs_in_2<=ldqs_2;
with ram_data_en select
ddr2_data <= ram_data_out when '1',
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" when others;
ram_data_in<=ddr2_data;
uwr_rd_ready<=rd_ready_s;
uwr_rd_end<=rd_end_s;
lwr_rd_ready<=rd_ready_s;
lwr_rd_end<=rd_end_s;
end displayer;
|
gpl-2.0
|
c4da052874cfbe4d8cdd604a16b3ae43
| 0.625388 | 2.423795 | false | false | false | false |
KenKeeley/My68k-system
|
CircuitBoards/MainBoard/SupportCPLD/IACK.vhd
| 1 | 3,023 |
----------------------------------------------------------------------------------------------------
--
-- FileName: IACK.vhd
-- Description: Interrupt Acknowledge.
--
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY work;
ENTITY IntAcknowledge IS
PORT
(
nReset : IN STD_LOGIC; -- Reset
nAS : IN STD_LOGIC; -- Address Strobe
Function_In : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- System Function
Address_In : IN STD_LOGIC_VECTOR (23 DOWNTO 0); -- Address Bus
IRQ_ATA : IN STD_LOGIC; -- ATA IRQ
IRQ_K : IN STD_LOGIC; -- Keyboard IRQ
IRQ_M : IN STD_LOGIC; -- Mouse IRQ
Data_Out : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- Data Out
nDSACK0 : OUT STD_LOGIC; -- Data Transfer Acknowledge 0
nIRQ4 : OUT STD_LOGIC; -- IRQ4
nIRQ6 : OUT STD_LOGIC; -- IRQ6
nIACK_DUART : OUT STD_LOGIC; -- DUART IACK
nIACK_OUT : OUT STD_LOGIC -- Expansion IACK
);
END IntAcknowledge;
ARCHITECTURE Behavioral OF IntAcknowledge IS
BEGIN
PROCESS(nReset, nAS)
BEGIN
IF (nReset = '0' OR nAS = '1') THEN
Data_Out <= "ZZZZZZZZ";
nDSACK0 <= 'Z';
nIACK_DUART <= '1';
nIACK_OUT <= '1';
ELSIF FALLING_EDGE(nAS) THEN
IF (Function_In = "111") THEN
-- Network Interrupt Acknowledge Vector 170.
IF Address_In = X"000002" THEN
Data_Out <= X"AA";
nDSACK0 <= '0';
-- ATA Interrupt Acknowledge Vector 187.
ELSIF Address_In = X"000004" AND IRQ_ATA = '1' THEN
Data_Out <= X"BB";
nDSACK0 <= '0';
-- DUART Interrupt Acknowledge.
ELSIF Address_In = X"000005" THEN
nIACK_DUART <= '0';
-- Keyboard Interrupt Acknowledge Vector 204.
ELSIF Address_In = X"000006" AND IRQ_K = '1' THEN
Data_Out <= X"CC";
nDSACK0 <= '0';
-- Mouse Interrupt Acknowledge Vector 221.
ELSIF Address_In = X"000006" AND IRQ_M = '1' THEN
Data_Out <= X"DD";
nDSACK0 <= '0';
-- expansion Interrupt Acknowledge.
ELSIF Address_In < X"000008" THEN
nIACK_OUT <= '0';
END IF;
END IF;
END IF;
END PROCESS;
-- Generate Interrupt 4 request.
nIRQ4 <= NOT IRQ_ATA;
-- Generate Interrupt 6 requests.
nIRQ6 <= NOT (IRQ_K OR IRQ_M);
END Behavioral;
|
gpl-3.0
|
3c02bc35d725d59e8d65c06fdb40e7fd
| 0.427721 | 4.806041 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/gen_multiplexer/gen_multiplexer.vhd
| 1 | 889 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gen_multiplexer is
generic(
PORT_SIZE: natural := 1;
PORT_QUANT: natural := 2); --Port quantity, la cantidad de puertos de entrada
port (
data_in: in
data_out: out std_logic_vector(PORT_SIZE-1 downto 0);
);
end;
architecture contBCD_arq of contBCD is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(clk,rst)
variable count: integer range 0 to 10;
begin
if rst = '1' then
s <= (others => '0');
co <= '0';
elsif rising_edge(clk) then
if ena = '1' then
count:=count + 1;
if count = 9 then
co <= '1';
elsif count = 10 then
count := 0;
co <= '0';
else
co <= '0';
end if;
end if;
end if;
s <= std_logic_vector(TO_UNSIGNED(count,4));
end process;
end;
|
gpl-3.0
|
00596ca1023eb3b5810c18c6f978a318
| 0.592801 | 3.003378 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
VHDL/USB/FIFO_TO_OTHER.vhd
| 2 | 8,043 |
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo_mixed_widths
-- ============================================================
-- File Name: FIFO_TO_OTHER.vhd
-- Megafunction Name(s):
-- dcfifo_mixed_widths
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY FIFO_TO_OTHER IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rdusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END FIFO_TO_OTHER;
ARCHITECTURE SYN OF fifo_to_other IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT dcfifo_mixed_widths
GENERIC (
add_usedw_msb_bit : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
lpm_widthu_r : NATURAL;
lpm_width_r : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(15 DOWNTO 0);
wrusedw <= sub_wire1(9 DOWNTO 0);
rdusedw <= sub_wire2(8 DOWNTO 0);
dcfifo_mixed_widths_component : dcfifo_mixed_widths
GENERIC MAP (
add_usedw_msb_bit => "ON",
intended_device_family => "Cyclone II",
lpm_hint => "MAXIMIZE_SPEED=5,MAXIMUM_DEPTH=512",
lpm_numwords => 512,
lpm_showahead => "OFF",
lpm_type => "dcfifo_mixed_widths",
lpm_width => 8,
lpm_widthu => 10,
lpm_widthu_r => 9,
lpm_width_r => 16,
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 5
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
q => sub_wire0,
wrusedw => sub_wire1,
rdusedw => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "512"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "1"
-- Retrieval info: PRIVATE: output_width NUMERIC "16"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_USEDW_MSB_BIT STRING "ON"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,,MAXIMUM_DEPTH=512"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9"
-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-- Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
-- Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_OTHER.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_OTHER.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_OTHER.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_OTHER.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_TO_OTHER_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
db7be72fefc5f5dc8716989d03da2cd9
| 0.669278 | 3.448971 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/genericCounter/generic_counter.vhd
| 3 | 993 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity genericCounter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end;
architecture genericCounter_arq of genericCounter is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(clk,rst)
variable tmp_count: integer range 0 to MAX_COUNT+1;
begin
if rst = '1' then
count <= (others => '0');
carry_o <= '0';
elsif rising_edge(clk) then
if ena = '1' then
tmp_count:=tmp_count + 1;
if tmp_count = MAX_COUNT then
carry_o <= '1';
elsif tmp_count = MAX_COUNT+1 then
tmp_count := 0;
carry_o <= '0';
else
carry_o <= '0';
end if;
end if;
end if;
count <= std_logic_vector(TO_UNSIGNED(tmp_count,BITS));
end process;
end;
|
gpl-3.0
|
1ba0e1c232c92ea30bab18f7c3307a9f
| 0.612286 | 2.920588 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/finite_field/mult_gf_2_m.vhd
| 1 | 7,176 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Multiplier_GF_2_M
-- Module Name: Multiplier_GF_2_M
-- Project Name: GF_2_M Arithmetic
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The multiplier for GF(2^m) arithmetic.
-- This circuit works through a pure combinatorial strategy.
-- This circuit generates all partial products and them XOR them altogether.
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit.
--
-- Dependencies:
-- VHDL-93
--
-- product_generator_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mult_gf_2_m is
Generic(gf_2_m : integer range 1 to 20);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end mult_gf_2_m;
architecture Behavioral of mult_gf_2_m is
component product_generator_gf_2_m
Generic(
value : integer;
m : integer range 2 to 20
);
Port (
a : in STD_LOGIC_VECTOR ((m - 1) downto 0);
o : out STD_LOGIC_VECTOR ((m - 1) downto 0)
);
end component;
type vector is array(integer range <>) of std_logic_vector((gf_2_m - 1) downto 0);
signal a_mult : vector(0 to (gf_2_m - 1));
signal b_mult : vector(0 to (gf_2_m - 1));
signal a_product_b : vector(0 to (gf_2_m - 1));
--for all : product_generator_gf_2_m use entity work.product_generator_gf_2_m(Software_POLYNOMIAL);
begin
x : for I in 0 to (gf_2_m - 1) generate
PGx : entity work.product_generator_gf_2_m(Software_POLYNOMIAL)
Generic Map(
value => I,
m => gf_2_m)
Port Map(
a => a,
o => a_mult(I)
);
b_mult(I) <= (others => b(I));
a_product_b(I) <= a_mult(I) and b_mult(I);
end generate;
GF_2_1 : if gf_2_m = 1 generate
o <= a and b;
end generate;
GF_2_2 : if gf_2_m = 2 generate
o <= a_product_b(1) xor a_product_b(0);
end generate;
GF_2_3 : if gf_2_m = 3 generate
o <= a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_4 : if gf_2_m = 4 generate
o <= a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_5 : if gf_2_m = 5 generate
o <= a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_6 : if gf_2_m = 6 generate
o <= a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_7 : if gf_2_m = 7 generate
o <= a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_8 : if gf_2_m = 8 generate
o <= a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_9 : if gf_2_m = 9 generate
o <= a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_10 : if gf_2_m = 10 generate
o <= a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_11 : if gf_2_m = 11 generate
o <= a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_12 : if gf_2_m = 12 generate
o <= a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_13 : if gf_2_m = 13 generate
o <= a_product_b(12) xor a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_14 : if gf_2_m = 14 generate
o <= a_product_b(13) xor a_product_b(12) xor a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_15 : if gf_2_m = 15 generate
o <= a_product_b(14) xor a_product_b(13) xor a_product_b(12) xor a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_16 : if gf_2_m = 16 generate
o <= a_product_b(15) xor a_product_b(14) xor a_product_b(13) xor a_product_b(12) xor a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_17 : if gf_2_m = 17 generate
o <= a_product_b(16) xor a_product_b(15) xor a_product_b(14) xor a_product_b(13) xor a_product_b(12) xor a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_18 : if gf_2_m = 18 generate
o <= a_product_b(17) xor a_product_b(16) xor a_product_b(15) xor a_product_b(14) xor a_product_b(13) xor a_product_b(12) xor a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_19 : if gf_2_m = 19 generate
o <= a_product_b(18) xor a_product_b(17) xor a_product_b(16) xor a_product_b(15) xor a_product_b(14) xor a_product_b(13) xor a_product_b(12) xor a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_20 : if gf_2_m = 20 generate
o <= a_product_b(19) xor a_product_b(18) xor a_product_b(17) xor a_product_b(16) xor a_product_b(15) xor a_product_b(14) xor a_product_b(13) xor a_product_b(12) xor a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
end Behavioral;
|
bsd-2-clause
|
dda68aacc393e8d746fa5eea5f7a51cb
| 0.641862 | 2.320828 | false | false | false | false |
laurivosandi/hdl
|
arithmetic/src/moving_average_filter_improved.vhd
| 1 | 2,503 |
library ieee;
use ieee.std_logic_1164.all;
entity moving_average_filter is
Port ( sin : in std_logic_vector (10 downto 0);
clk : in std_logic;
sout : out std_logic_vector (10 downto 0);
rst : in std_logic);
end moving_average_filter;
architecture behavioral of moving_average_filter is
-- Registers
type tregisters is array (0 to 15) of std_logic_vector(14 downto 0);
signal registers : tregisters;
signal sum : std_logic_vector(14 downto 0);
-- Wires
signal addition : std_logic_vector(14 downto 0);
signal addition_carries : std_logic_vector(14 downto 0);
signal subtraction : std_logic_vector(14 downto 0);
signal subtraction_carries : std_logic_vector(14 downto 0);
signal first : std_logic_vector(14 downto 0);
signal last : std_logic_vector(14 downto 0);
component carry_lookahead_adder is
Port ( a : in std_logic_vector (14 downto 0);
b : in std_logic_vector (14 downto 0);
ci : in std_logic;
s : out std_logic_vector (14 downto 0);
co : out std_logic);
end component;
begin
process (sin, clk)
begin
if rst = '1' then
-- Reset register
for i in 0 to 15 loop
registers(i) <= "000000000000000";
end loop;
sum <= "000000000000000";
elsif rising_edge(clk) then
-- Shift operands
for i in 15 downto 1 loop
registers(i) <= registers(i-1);
end loop;
-- Store first operand
registers(0) <= first;
-- Store sumious value
sum <= subtraction;
end if;
end process;
-- Sign extension
sign_extension_loop: for i in 14 downto 11 generate
first(i) <= sin(10);
end generate;
-- Connect lower 11-bits
input_loop: for i in 10 downto 0 generate
first(i) <= sin(i);
end generate;
-- Last operand
last <= not (registers(15));
-- Add first operand
addition_stage: carry_lookahead_adder port map(a=>first, b=>sum, ci=>'0', s=>addition);
-- Subtract last operand
subtraction_stage: carry_lookahead_adder port map(a=>addition, b=>last, ci=>'1', s=>subtraction);
-- Write output
division_loop: for i in 10 downto 0 generate
sout(i) <= subtraction(i+4);
end generate;
end Behavioral;
|
mit
|
3b61b8c700493b87b520c755c45294d0
| 0.568518 | 4.037097 | false | false | false | false |
rodrigoazs/-7-5-Reed-Solomon
|
code/symbol_power_decoder.vhd
| 1 | 819 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity SymbolPowerDecoder is
Port ( n1 : in std_logic_vector(2 downto 0);
n1c : out std_logic_vector(2 downto 0));
end SymbolPowerDecoder;
architecture Behavioral of SymbolPowerDecoder is
begin
process ( n1 )
begin
case n1 is
when "000"=> n1c <="100" ;
when "001"=> n1c <="010" ;
when "010"=> n1c <="001" ;
when "011"=> n1c <="110" ;
when "100"=> n1c <="011" ;
when "101"=> n1c <="111" ;
when "110"=> n1c <="101" ;
when others=> n1c <="---" ;
end case ;
end process ;
end Behavioral;
|
mit
|
bdc423813133934c30f37efe1967ce8e
| 0.637363 | 3.011029 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/Contador_vector_tb.vhd
| 2 | 842 |
library IEEE;
use IEEE.std_logic_1164.all;
entity contador_vector_tb is
end;
architecture contador_sim of contador_vector_tb is
signal rst_in: std_logic:='1';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal Q_out: std_logic_vector(1 downto 0);
component contador_vector is
port(
rst_c: in std_logic;
clk_c: in std_logic;
enable_c: in std_logic;
Q: out std_logic_vector(1 downto 0)
);
end component;
begin
clk_in <= not clk_in after 20 ns;
enable_in <= '1' after 100 ns;
--enable_in <= not(enable_in)) after 100 ns; //Para probar que funciona el enable
rst_in <= '0' after 50 ns;
ContadorMap: contador_vector port map(
clk_c => clk_in,
rst_c => rst_in,
enable_c => enable_in,
Q => Q_out
);
end architecture;
|
gpl-3.0
|
591153324e8502dc4d5f3c701b5a5531
| 0.610451 | 2.87372 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/memory_writer/memory_writer.vhd
| 1 | 10,809 |
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--This component receives the real value of the tip of the vector. Then, for every bit value, it checks if it should be painted or not according to the real value.
entity memory_writer is
generic(ROWS : integer := 350; COLUMNS : integer := 350; BITS : integer := 32);
port(
clk : in std_logic := '0';
enable : in std_logic := '0';
rst : in std_logic := '0';
pixel_x : out std_logic_vector(9 downto 0) := (others => '0');
pixel_y : out std_logic_vector(9 downto 0) := (others => '0');
pixel_on : out std_logic_vector(0 downto 0) := (others => '0')
);
end entity;
architecture memory_writer_arq of memory_writer is
constant AXIS_X_BIT : std_logic_vector(9 downto 0) := std_logic_vector(shift_right(to_unsigned(COLUMNS,10),1));
constant AXIS_Y_BIT : std_logic_vector(9 downto 0) := std_logic_vector(shift_right(to_unsigned(ROWS,10),1));
constant ONE : unsigned(BITS - 1 downto 0) := "00000000000000010000000000000000"; --1.0
constant PIXEL_COEF : std_logic_vector(BITS - 1 downto 0) := "00000000101011110000000000000000"; --350/2 to account for the displacement by 1
constant MAX_POSITION : integer := 177;
constant ROTATION_ANGLE : signed(31 downto 0) := "00000000000000001011010000000000"; --0.703125 degrees
--constant ROTATION_ANGLE : signed(31 downto 0) := "00000000000000000000000000000000";
signal clk_signal : std_logic := '0';
--Signals to memory
signal x_read_address_to_memory : std_logic_vector(9 downto 0) := (others => '0');
--Signals from memory
signal memory_read_x : std_logic_vector(15 downto 0) := (others => '0');
--Signals to preprocessor
signal preprocessor_x_input : std_logic_vector(BITS-1 downto 0) := (others => '0');
signal preprocessor_y_input : std_logic_vector(BITS-1 downto 0) := (others => '0');
signal preprocessor_angle_input : std_logic_vector(BITS-1 downto 0) := (others => '0');
--Signals to cordic
signal preprocessor_x_output_to_cordic : std_logic_vector(BITS - 1 downto 0) := (others => '0');
signal preprocessor_y_output_to_cordic : std_logic_vector(BITS - 1 downto 0) := (others => '0');
signal preprocessor_angle_output_to_cordic : std_logic_vector(BITS - 1 downto 0) := (others => '0');
--Output signals
signal output_x_from_cordic : std_logic_vector(BITS - 1 downto 0 ) := (others => '0');
signal output_y_from_cordic : std_logic_vector(BITS - 1 downto 0 ) := (others => '0');
--Mapped values
signal decimal_x : std_logic_vector(31 downto 0) := (others => '0');
signal decimal_y : std_logic_vector(31 downto 0) := (others => '0');
signal mapped_x : std_logic_vector(63 downto 0) := (others => '0');
signal mapped_y : std_logic_vector(63 downto 0) := (others => '0');
component cordic is
generic(TOTAL_BITS: integer := 32; STEPS: integer := 16);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
angle: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
component preprocessor is
generic(TOTAL_BITS: integer := 32);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
angle_in : in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
angle_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
component multiplier is
port(
op_1_in: in std_logic_vector(31 downto 0) := (others => '0');
op_2_in: in std_logic_vector(31 downto 0) := (others => '0');
result_out: out std_logic_vector(63 downto 0) := (others => '0')
);
end component;
begin
clk_signal <= clk;
preprocessor_0 : preprocessor
port map(
x_in => preprocessor_x_input,
y_in => preprocessor_y_input,
angle_in => preprocessor_angle_input,
x_out => preprocessor_x_output_to_cordic,
y_out => preprocessor_y_output_to_cordic,
angle_out => preprocessor_angle_output_to_cordic
);
cordic_0 : cordic
port map(
x_in => preprocessor_x_output_to_cordic,
y_in => preprocessor_y_output_to_cordic,
angle => preprocessor_angle_output_to_cordic,
x_out => output_x_from_cordic,
y_out => output_y_from_cordic
);
multiplier_0 : multiplier
port map(
op_1_in => decimal_x,
op_2_in => PIXEL_COEF,
result_out => mapped_x
);
multiplier_1 : multiplier
port map(
op_1_in => decimal_y,
op_2_in => PIXEL_COEF,
result_out => mapped_y
);
x_values_ram: RAMB16_S18_S18
generic map(WRITE_MODE_B => "READ_FIRST",
INIT_00 => X"176715F1147A1304118D10170EA00D2A0BB30A3D08C6075005D9046302EC0176",
INIT_01 => X"2ECF2D592BE22A6C28F5277F26082492231B21A5202E1EB81D411BCB1A5418DE",
INIT_02 => X"463744C1434A41D4405D3EE73D703BFA3A83390D3796362034A9333331BC3046",
INIT_03 => X"5D9F5C285AB2593B57C5564E54D8536251EB50754EFE4D884C114A9B492447AE",
INIT_04 => X"75077390721A70A36F2D6DB66C406AC9695367DC666664EF63796202608C5F15",
INIT_05 => X"8C6F8AF88982880B8695851E83A8823180BB7F447DCE7C577AE1796A77F4767D",
INIT_06 => X"A3D7A260A0EA9F739DFD9C869B109999982396AC953693BF924990D28F5C8DE5",
INIT_07 => X"BB3EB9C8B851B6DBB564B3EEB277B101AF8AAE14AC9DAB27A9B1A83AA6C4A54D",
INIT_08 => X"D2A6D130CFB9CE43CCCCCB56C9DFC869C6F2C57CC405C28FC118BFA2BE2BBCB5",
INIT_09 => X"EA0EE898E721E5ABE434E2BEE147DFD1DE5ADCE4DB6DD9F7D880D70AD593D41D",
INIT_0a => X"FFFFFFFFFE89FD13FB9CFA26F8AFF739F5C2F44CF2D5F15FEFE8EE72ECFBEB85"
)
port map (
DOA => open,
DOB => memory_read_x,
ADDRA => (others => '0'),
ADDRB => x_read_address_to_memory,
DIPA => (others => '0'),
DIPB => (others => '0'),
CLKA => '0',
CLKB => clk_signal,
DIA => (others => '0'),
DIB => (others => '0'),
ENA => '0',
ENB => enable,
SSRA => '0',
SSRB => '0',
WEA => '0',
WEB => '0'
);
--y_values_ram: RAMB16_S18_S18
-- generic map(WRITE_MODE_B => "READ_FIRST")
-- port map (
-- DOA => open,
-- DOB => memory_read_y,
-- ADDRA => open,
-- ADDRB => y_read_address_to_memory,
-- DIPA => (others => '0'),
-- DIPB => (others => '0'),
-- CLKA => clk_signal,
-- CLKB => clk_signal,
-- DIA => y_input_to_memory,
-- DIB => (others => '0'),
-- ENA => enable,
-- ENB => enable,
-- SSRA => '0',
-- SSRB => '0',
-- WEA => enable,
-- WEB => '0'
-- );
preprocessor_x_input <= ("0000000000000000" & memory_read_x);
preprocessor_y_input <= (others => '0');
process(clk, rst)
variable moved_x : unsigned(BITS - 1 downto 0) := (others => '0');
variable moved_y : unsigned(BITS - 1 downto 0) := (others => '0');
variable extended_moved_x_bit : std_logic_vector(BITS * 2 - 1 downto 0) := (others => '0');
variable extended_moved_y_bit_unsigned : unsigned(BITS * 2 - 1 downto 0) := (others => '0');
variable truncated_extended_moved_y_bit_unsigned : unsigned(9 downto 0) := (others => '0');
variable inverted_y_bit : unsigned(9 downto 0) := (others => '0');
variable extended_moved_y_bit : std_logic_vector(BITS * 2 - 1 downto 0) := (others => '0');
variable moved_x_bit : std_logic_vector(9 downto 0) := (others => '0');
variable moved_y_bit : std_logic_vector(9 downto 0) := (others => '0');
variable point_position : integer := 0;
variable erasing_x : integer := 0;
variable erasing_y : integer := 0;
variable should_erase : std_logic := '0';
variable done_writing : std_logic := '0';
variable accumulated_angle : signed(BITS - 1 downto 0) := (others => '0');
begin
if(rising_edge(clk)) then
--If rst is 1 we should either erase previous values or start writing the new ones
if(rst = '1') then
if(should_erase = '1') then
erasing_x := erasing_x + 1;
if(erasing_x = COLUMNS) then
erasing_x := 0;
erasing_y := erasing_y + 1;
end if;
if(erasing_y = ROWS) then
should_erase := '0';
end if;
report "ERASING: " & integer'image(erasing_x) & ":" & integer'image(erasing_y);
pixel_x <= std_logic_vector(to_unsigned(erasing_x, 10));
pixel_y <= std_logic_vector(to_unsigned(erasing_y, 10));
pixel_on <= (others => '0');
point_position := 0;
x_read_address_to_memory <= std_logic_vector(to_unsigned(point_position,10));
else --We should start writing the next values
if(point_position >= 0 and point_position < MAX_POSITION) then
point_position := point_position + 1;
--Compute address to set to memory
x_read_address_to_memory <= std_logic_vector(to_unsigned(point_position,10));
--To give time to the cordic to process the data, we shall draw the previous point and in the end set the next point to be processed
moved_x := unsigned(output_x_from_cordic) + ONE; --Move the x value to the right so that all it's posible locations are a positive number
moved_y := unsigned(output_y_from_cordic) + ONE; --Move the y value up so that all it's possible locations are a positive number
decimal_x <= std_logic_vector(moved_x);
extended_moved_x_bit := mapped_x; --Compute the pixel location
moved_x_bit := extended_moved_x_bit(32 + 9 downto 32); --Truncate to integer value
decimal_y <= std_logic_vector(moved_y);
extended_moved_y_bit_unsigned := unsigned(mapped_y); --Compute the pixel location
truncated_extended_moved_y_bit_unsigned := extended_moved_y_bit_unsigned(32 + 9 downto 32); --Truncate to integer value
inverted_y_bit := ROWS - truncated_extended_moved_y_bit_unsigned;
moved_y_bit := std_logic_vector(inverted_y_bit);
report "WRITTING: " & integer'image(point_position);
pixel_x <= moved_x_bit;
pixel_y <= moved_y_bit;
pixel_on <= "1";
else
report "DONE WRITTING -> WAITING_TO_ERASE";
pixel_on <= "0";
erasing_x := 0;
erasing_y := 0;
end if;
end if;
else
report "VIDEO ON, DONT MODIFY MEMORY";
if(should_erase = '0') then
accumulated_angle := accumulated_angle + ROTATION_ANGLE;
preprocessor_angle_input <= std_logic_vector(accumulated_angle);
end if;
should_erase := '1';
erasing_x := 0;
erasing_y := 0;
end if;
end if;
end process;
end memory_writer_arq;
|
gpl-3.0
|
9504de41259ac622313363a0b925e8d3
| 0.634379 | 2.981793 | false | false | false | false |
zeruniverse/Multiple-cycle_CPU
|
ISE project/ipcore_dir/mcmem.vhd
| 1 | 5,885 |
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file mcmem.vhd when simulating
-- the core, mcmem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY mcmem IS
port (
a: in std_logic_vector(5 downto 0);
d: in std_logic_vector(31 downto 0);
clk: in std_logic;
we: in std_logic;
spo: out std_logic_vector(31 downto 0));
END mcmem;
ARCHITECTURE mcmem_a OF mcmem IS
-- synthesis translate_off
component wrapped_mcmem
port (
a: in std_logic_vector(5 downto 0);
d: in std_logic_vector(31 downto 0);
clk: in std_logic;
we: in std_logic;
spo: out std_logic_vector(31 downto 0));
end component;
-- Configuration specification
for all : wrapped_mcmem use entity XilinxCoreLib.dist_mem_gen_v5_1(behavioral)
generic map(
c_has_clk => 1,
c_has_qdpo_clk => 0,
c_has_qdpo_ce => 0,
c_parser_type => 1,
c_has_d => 1,
c_has_spo => 1,
c_read_mif => 1,
c_has_qspo => 0,
c_width => 32,
c_reg_a_d_inputs => 0,
c_has_we => 1,
c_pipeline_stages => 0,
c_has_qdpo_rst => 0,
c_reg_dpra_input => 0,
c_qualify_we => 0,
c_family => "spartan3",
c_sync_enable => 1,
c_depth => 64,
c_has_qspo_srst => 0,
c_has_qdpo_srst => 0,
c_has_dpra => 0,
c_qce_joined => 0,
c_mem_type => 1,
c_has_i_ce => 0,
c_has_dpo => 0,
c_mem_init_file => "mcmem.mif",
c_default_data => "0",
c_has_spra => 0,
c_has_qspo_ce => 0,
c_addr_width => 6,
c_has_qspo_rst => 0,
c_has_qdpo => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_mcmem
port map (
a => a,
d => d,
clk => clk,
we => we,
spo => spo);
-- synthesis translate_on
END mcmem_a;
|
gpl-3.0
|
574c1b412c42f5f1d968b8e69c28753f
| 0.514528 | 4.305048 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/multiplication/biaser/biaser_tb.vhd
| 1 | 1,535 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity biaser_tb is
end entity;
architecture biaser_tb_arq of biaser_tb is
signal operation : std_logic := '0';
signal exp_in: std_logic_vector(2 downto 0) := (others => '0');
signal exp_out: std_logic_vector(2 downto 0) := (others => '0');
component biaser is
generic(
EXP_BITS: natural := 6
);
port (
operation : in std_logic;
exp_in: in std_logic_vector(EXP_BITS - 1 downto 0);
exp_out : out std_logic_vector(EXP_BITS - 1 downto 0)
);
end component;
for biaser_0: biaser use entity work.biaser;
begin
biaser_0: biaser
generic map(EXP_BITS => 3)
port map(
operation => operation,
exp_in => exp_in,
exp_out => exp_out
);
process
type pattern_type is record
o : std_logic;
ei : std_logic_vector(2 downto 0);
eo : std_logic_vector(2 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range<>) of pattern_type;
constant patterns : pattern_array := (
('1',"000","101"),
('1',"001","110"),
('0',"000","011")
);
begin
for i in patterns'range loop
-- Set the inputs.
operation <= patterns(i).o;
exp_in <= patterns(i).ei;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert exp_out = patterns(i).eo report "BAD EXPONENT: " & integer'image(to_integer(unsigned(exp_out))) severity error;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
9c0d63cb854d98b65a246982832b6f52
| 0.62671 | 3.05169 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/controller_find_correct_errors_n.vhd
| 1 | 4,819 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Find_Correct_Errors_N
-- Module Name: Controller_Find_Correct_Errors_N
-- Project Name: 3rd Step - Find and Correct Errors
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 3rd step in Goppa Code Decoding.
--
-- This circuit is the state machine controller for find_correct_errors_n.
-- This circuit loads all messages synchronized along side polynomial evaluator circuit.
-- The states of this circuit is to load values and when a signal of last evaluation
-- rises the values of the message are written.
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_find_correct_errors_n is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable_correction : in STD_LOGIC;
evaluation_finalized : in STD_LOGIC;
reg_value_evaluated_ce : out STD_LOGIC;
reg_address_store_new_value_message_ce : out STD_LOGIC;
reg_address_store_new_value_message_rst : out STD_LOGIC;
reg_write_enable_new_value_message_ce : out STD_LOGIC;
reg_write_enable_new_value_message_rst : out STD_LOGIC;
correction_finalized : out STD_LOGIC
);
end controller_find_correct_errors_n;
architecture Behavioral of controller_find_correct_errors_n is
type State is (reset, load_counter, load_x_write_x, load_message_x_write_message_x, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, enable_correction, evaluation_finalized)
begin
case (actual_state) is
when reset =>
reg_value_evaluated_ce <= '0';
reg_address_store_new_value_message_ce <= '0';
reg_address_store_new_value_message_rst <= '1';
reg_write_enable_new_value_message_ce <= '0';
reg_write_enable_new_value_message_rst <= '1';
correction_finalized <= '0';
when load_counter =>
reg_value_evaluated_ce <= '0';
reg_address_store_new_value_message_ce <= '0';
reg_address_store_new_value_message_rst <= '1';
reg_write_enable_new_value_message_ce <= '0';
reg_write_enable_new_value_message_rst <= '1';
correction_finalized <= '0';
when load_x_write_x =>
if(enable_correction = '1') then
reg_value_evaluated_ce <= '1';
reg_address_store_new_value_message_ce <= '1';
reg_address_store_new_value_message_rst <= '0';
reg_write_enable_new_value_message_ce <= '1';
reg_write_enable_new_value_message_rst <= '0';
correction_finalized <= '0';
else
reg_value_evaluated_ce <= '0';
reg_address_store_new_value_message_ce <= '0';
reg_address_store_new_value_message_rst <= '0';
reg_write_enable_new_value_message_ce <= '0';
reg_write_enable_new_value_message_rst <= '0';
correction_finalized <= '0';
end if;
when load_message_x_write_message_x =>
reg_value_evaluated_ce <= '1';
reg_address_store_new_value_message_ce <= '1';
reg_address_store_new_value_message_rst <= '0';
reg_write_enable_new_value_message_ce <= '1';
reg_write_enable_new_value_message_rst <= '0';
correction_finalized <= '0';
when final =>
reg_value_evaluated_ce <= '0';
reg_address_store_new_value_message_ce <= '0';
reg_address_store_new_value_message_rst <= '0';
reg_write_enable_new_value_message_ce <= '0';
reg_write_enable_new_value_message_rst <= '0';
correction_finalized <= '1';
when others =>
reg_value_evaluated_ce <= '0';
reg_address_store_new_value_message_ce <= '0';
reg_address_store_new_value_message_rst <= '0';
reg_write_enable_new_value_message_ce <= '0';
reg_write_enable_new_value_message_rst <= '0';
correction_finalized <= '0';
end case;
end process;
NewState: process (actual_state, enable_correction, evaluation_finalized)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= load_x_write_x;
when load_x_write_x =>
if(enable_correction = '1') then
next_state <= load_message_x_write_message_x;
else
next_state <= load_x_write_x;
end if;
when load_message_x_write_message_x =>
if(evaluation_finalized = '1') then
next_state <= final;
else
next_state <= load_message_x_write_message_x;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
e1a463e6197c2d784e69036b510c7bb9
| 0.64889 | 3.063573 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP3/multiplication/rounder/rounder_tb.vhd
| 1 | 2,263 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rounder_tb is
end entity;
architecture rounder_tb_arq of rounder_tb is
signal man_in: std_logic_vector(7 downto 0) := (others => '0');
signal exp_in: std_logic_vector(2 downto 0) := (others => '0');
signal man_out: std_logic_vector(5 downto 0) := (others => '0');
signal exp_out: std_logic_vector(2 downto 0) := (others => '0');
signal exponent_addition_cout: std_logic := '0';
component rounder is
generic(
TOTAL_BITS:natural := 23;
EXP_BITS: natural := 6
);
port (
exponent_addition_cout: in std_logic;
man_in: in std_logic_vector(TOTAL_BITS - EXP_BITS downto 0);
exp_in: in std_logic_vector(EXP_BITS - 1 downto 0);
man_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_out : out std_logic_vector(EXP_BITS - 1 downto 0)
);
end component;
for rounder_0: rounder use entity work.rounder;
begin
rounder_0: rounder
generic map(TOTAL_BITS => 10, EXP_BITS => 3)
port map(
exponent_addition_cout => exponent_addition_cout,
man_in => man_in,
exp_in => exp_in,
man_out => man_out,
exp_out => exp_out
);
process
type pattern_type is record
mi : std_logic_vector(7 downto 0);
ei : std_logic_vector(2 downto 0);
mo : std_logic_vector(5 downto 0);
ec : std_logic;
eo : std_logic_vector(2 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range<>) of pattern_type;
constant patterns : pattern_array := (
("00000000","000","000000",'0',"000"),
("11111111","000","000000",'0',"000"),
("10000001","110","000000",'0',"100")
);
begin
for i in patterns'range loop
-- Set the inputs.
man_in <= patterns(i).mi;
exp_in <= patterns(i).ei;
exponent_addition_cout <= patterns(i).ec;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert man_out = patterns(i).mo report "BAD MANTISSA: " & integer'image(to_integer(unsigned(man_out))) severity error;
assert exp_out = patterns(i).eo report "BAD EXPONENT: " & integer'image(to_integer(unsigned(exp_out))) severity error;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
0bbbbea2c978436c0248f00ab4aa115d
| 0.638533 | 3.062246 | false | false | false | false |
KenKeeley/My68k-system
|
CircuitBoards/MainBoard/SupportCPLD/Support.vhd
| 1 | 8,765 |
----------------------------------------------------------------------------------------------------
--
-- FileName: Support.vhd
-- Description: MainBoard Support CPLD Top Level.
--
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY Support IS
PORT
(
nReset : IN STD_LOGIC; -- Reset
Clk : IN STD_LOGIC; -- Clock
nAS : IN STD_LOGIC; -- Address Strobe
nWR : IN STD_LOGIC; -- Write Strobe
nHigh_Address : IN STD_LOGIC; -- Upper Address Range
Function_In : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- System Function
Address_In : IN STD_LOGIC_VECTOR (23 DOWNTO 0); -- Address Bus
DTACK_ATA : IN STD_LOGIC; -- ATA Data Acknowledge
DTACK_NET : IN STD_LOGIC; -- Network Data Acknowledge
IRQ_ATA : IN STD_LOGIC; -- ATA IRQ
IRQ_K : IN STD_LOGIC; -- Keyboard IRQ
IRQ_M : IN STD_LOGIC; -- Mouse IRQ
CPU_Clock : OUT STD_LOGIC; -- CPU Clock
PS2_Clock : OUT STD_LOGIC; -- PS2 Clock
nCS_FPU : OUT STD_LOGIC; -- FPU Chip Select
nCS_ATA : OUT STD_LOGIC; -- ATA Buffer Chip Select
nCS_ATA0 : OUT STD_LOGIC; -- ATA Chip Select 0
nCS_ATA1 : OUT STD_LOGIC; -- ATA Chip Select 1
nCS_RTC : BUFFER STD_LOGIC; -- RTC Chip Select
AS_RTC : OUT STD_LOGIC; -- RTC AS Select
DS_RTC : OUT STD_LOGIC; -- RTC DS Select
nCS_PS2 : BUFFER STD_LOGIC; -- PS2 Chip Select
nCS_ID1 : OUT STD_LOGIC; -- Hardware ID 1
nCS_ID2 : OUT STD_LOGIC; -- Hardware ID 2
nPS_OFF : BUFFER STD_LOGIC; -- Power Off
nCS_DUART : OUT STD_LOGIC; -- DUART Chip Select
nCS_NET : OUT STD_LOGIC; -- Network Chip Select
nCS_SRAM : BUFFER STD_LOGIC; -- SRAM Chip Select
nCS_ROM : BUFFER STD_LOGIC; -- ROM Chip Select
nDSACK0 : OUT STD_LOGIC; -- Data Transfer Acknowledge 0
nDSACK1 : OUT STD_LOGIC; -- Data Transfer Acknowledge 1
nRD : OUT STD_LOGIC; -- Read Strobe
Data_Out : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- Data Out
nIRQ4 : OUT STD_LOGIC; -- IRQ4
nIRQ6 : OUT STD_LOGIC; -- IRQ6
nIACK_DUART : OUT STD_LOGIC; -- DUART IACK
nIACK_OUT : OUT STD_LOGIC; -- Expansion IACK
nBERR : OUT STD_LOGIC -- Bus Error
);
END Support;
ARCHITECTURE Behavioral OF Support IS
-- Component Declaration for the 'Divide by 5' block.
COMPONENT Clock_Div_5
PORT(nReset : IN STD_LOGIC;
ClkIn : IN STD_LOGIC;
ClkOut : OUT STD_LOGIC
);
END COMPONENT;
-- Component Declaration for the 'Divide by 2' block.
COMPONENT Clock_Div_2
PORT(nReset : IN STD_LOGIC;
ClkIn : IN STD_LOGIC;
ClkOut : OUT STD_LOGIC
);
END COMPONENT;
-- Component Declaration for the Address_Decoder
COMPONENT Address_Decoder
PORT (
nReset : IN STD_LOGIC;
nAS : IN STD_LOGIC;
nHigh_Address : IN STD_LOGIC;
Function_In : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
Address_In : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
nCS_FPU : OUT STD_LOGIC;
nCS_ATA : OUT STD_LOGIC;
nCS_ATA0 : OUT STD_LOGIC;
nCS_ATA1 : OUT STD_LOGIC;
nCS_RTC : BUFFER STD_LOGIC;
AS_RTC : OUT STD_LOGIC;
DS_RTC : OUT STD_LOGIC;
nCS_PS2 : BUFFER STD_LOGIC;
nCS_ID1 : OUT STD_LOGIC;
nCS_ID2 : OUT STD_LOGIC;
nPS_OFF : BUFFER STD_LOGIC;
nCS_DUART : OUT STD_LOGIC;
nCS_NET : OUT STD_LOGIC;
nCS_SRAM : BUFFER STD_LOGIC;
nCS_ROM : BUFFER STD_LOGIC
);
END COMPONENT;
-- Component Declaration for the DTACK
COMPONENT DTACK
PORT (
nReset : IN STD_LOGIC;
ClkIn : IN STD_LOGIC;
nAS : IN STD_LOGIC;
nCS_RTC : IN STD_LOGIC;
nCS_PS2 : IN STD_LOGIC;
nPS_OFF : IN STD_LOGIC;
nCS_SRAM : IN STD_LOGIC;
nCS_ROM : IN STD_LOGIC;
nDSACK0 : OUT STD_LOGIC;
nBERR : OUT STD_LOGIC
);
END COMPONENT;
-- Component Declaration for the IntAcknowledge
COMPONENT IntAcknowledge
PORT (
nReset : IN STD_LOGIC; -- Reset
nAS : IN STD_LOGIC; -- Address Strobe
Function_In : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- System Function
Address_In : IN STD_LOGIC_VECTOR (23 DOWNTO 0); -- Address Bus
IRQ_ATA : IN STD_LOGIC; -- ATA IRQ
IRQ_K : IN STD_LOGIC; -- Keyboard IRQ
IRQ_M : IN STD_LOGIC; -- Mouse IRQ
Data_Out : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- Data Out
nDSACK0 : OUT STD_LOGIC; -- Data Transfer Acknowledge 0
nIRQ4 : OUT STD_LOGIC; -- IRQ4
nIRQ6 : OUT STD_LOGIC; -- IRQ6
nIACK_DUART : OUT STD_LOGIC; -- DUART IACK
nIACK_OUT : OUT STD_LOGIC -- Expansion IACK
);
END COMPONENT;
BEGIN
-- Instantiate the CPU Clock
Clock_CPU : Clock_Div_2 PORT MAP(
nReset => nReset,
ClkIn => Clk,
ClkOut => CPU_Clock
);
-- Instantiate the PS2 Clock
Clock_PS2 : Clock_Div_5 PORT MAP(
nReset => nReset,
ClkIn => Clk,
ClkOut => PS2_Clock
);
-- Instantiate the Chip Select Decoder
Chip_Selects : Address_Decoder PORT MAP (
nReset => nReset,
nAS => nAS,
nHigh_Address => nHigh_Address,
Function_In => Function_In,
Address_In => Address_In,
nCS_FPU => nCS_FPU,
nCS_ATA => nCS_ATA,
nCS_ATA0 => nCS_ATA0,
nCS_ATA1 => nCS_ATA1,
nCS_RTC => nCS_RTC,
AS_RTC => AS_RTC,
DS_RTC => DS_RTC,
nCS_PS2 => nCS_PS2,
nCS_ID1 => nCS_ID1,
nCS_ID2 => nCS_ID2,
nPS_OFF => nPS_OFF,
nCS_DUART => nCS_DUART,
nCS_NET => nCS_NET,
nCS_SRAM => nCS_SRAM,
nCS_ROM => nCS_ROM
);
-- Instantiate the DTACK
DTACK_Timer : DTACK PORT MAP (
nReset => nReset,
ClkIn => Clk,
nAS => nAS,
nCS_RTC => nCS_RTC,
nCS_PS2 => nCS_PS2,
nPS_OFF => nPS_OFF,
nCS_SRAM => nCS_SRAM,
nCS_ROM => nCS_ROM,
nDSACK0 => nDSACK0,
nBERR => nBERR
);
-- Instantiate the IntAcknowledge
Int_Acknowledge : IntAcknowledge PORT MAP (
nReset => nReset,
nAS => nAS,
Function_In => Function_In,
Address_In => Address_In,
IRQ_ATA => IRQ_ATA,
IRQ_K => IRQ_K,
IRQ_M => IRQ_M,
Data_Out => Data_Out,
nDSACK0 => nDSACK0,
nIRQ4 => nIRQ4,
nIRQ6 => nIRQ6,
nIACK_DUART => nIACK_DUART,
nIACK_OUT => nIACK_OUT
);
-- Generate Read Strobe.
nRD <= NOT nWR;
-- Generate ATA and Network DTACK.
nDSACK1 <= NOT ( DTACK_ATA OR DTACK_NET );
END Behavioral;
|
gpl-3.0
|
9b2ba08646e671debb7304696205bb09
| 0.422362 | 4.7404 | false | false | false | false |
KenKeeley/My68k-system
|
CircuitBoards/MainBoard/DRAMControllerCPLD/Decoder.vhd
| 1 | 5,606 |
----------------------------------------------------------------------------------------------------
--
-- FileName: Decoder.vhd
-- Description: MainBoard DRAM Controller CPLD Decoder.
--
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY Decoder IS
PORT
(
nReset : IN STD_LOGIC; -- Reset
nAS : IN STD_LOGIC; -- CPU Address signal
nSIZ0 : IN STD_LOGIC; -- CPU SIZ 0 signal
nSIZ1 : IN STD_LOGIC; -- CPU SIZ 1 signal
nPreCharge : IN STD_LOGIC; -- Flag to show when in PreCharge
Func : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- CPU Function Signals
Address : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- Address Bus
nCS_ROM : IN STD_LOGIC; -- ROM Chip Select
nBank : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- DRAM Bank to Address
nByte : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); -- Byte/s Selected
nCS_DRAM : BUFFER STD_LOGIC; -- DRAM Chip Select
nPage_Hit : OUT STD_LOGIC -- Request is in Same Page
);
END Decoder;
ARCHITECTURE Behavioral OF Decoder IS
-- Internal Signals
SIGNAL PreRow : STD_LOGIC_VECTOR(17 DOWNTO 0);
BEGIN
-- Record Previous Address
Previous_Address: PROCESS (nAS, nReset, nPreCharge)
BEGIN
IF (nReset = '0' OR nPreCharge = '0') THEN
PreRow <= "111111111111111111";
ELSIF RISING_EDGE(nAS) THEN
PreRow(17 DOWNTO 11) <= Address(31 DOWNTO 25);
PreRow(10 DOWNTO 0) <= Address(23 DOWNTO 13);
END IF;
END PROCESS;
-- Detect a Page Hit
Page_Hit: PROCESS (Address, PreRow, nReset)
BEGIN
IF (nReset = '0') THEN
nPage_Hit <= '1';
ELSIF PreRow(17 DOWNTO 11) = Address(31 DOWNTO 25) AND PreRow(10 DOWNTO 0) = Address(23 DOWNTO 13) THEN
nPage_Hit <= '0';
ELSE
nPage_Hit <= '1';
END IF;
END PROCESS;
-- DRAM Select
nCS_DRAM <= '0' WHEN (Address(31) = '0' AND Address(30) = '0' AND Address(29) = '0' AND nAS = '0' AND nCS_ROM = '1' AND Func = "01") ELSE
'0' WHEN (Address(31) = '0' AND Address(30) = '0' AND Address(29) = '0' AND nAS = '0' AND nCS_ROM = '1' AND Func = "10") ELSE
'1';
-- Bank Selection
nBank <= "11111110" WHEN Address(28) = '0' AND Address(27) = '0' AND Address(26) = '0' AND nCS_DRAM = '0' ELSE
"11111101" WHEN Address(28) = '0' AND Address(27) = '0' AND Address(26) = '1' AND nCS_DRAM = '0' ELSE
"11111011" WHEN Address(28) = '0' AND Address(27) = '1' AND Address(26) = '0' AND nCS_DRAM = '0' ELSE
"11110111" WHEN Address(28) = '0' AND Address(27) = '1' AND Address(26) = '1' AND nCS_DRAM = '0' ELSE
"11101111" WHEN Address(28) = '1' AND Address(27) = '0' AND Address(26) = '0' AND nCS_DRAM = '0' ELSE
"11011111" WHEN Address(28) = '1' AND Address(27) = '0' AND Address(26) = '1' AND nCS_DRAM = '0' ELSE
"10111111" WHEN Address(28) = '1' AND Address(27) = '1' AND Address(26) = '0' AND nCS_DRAM = '0' ELSE
"01111111" WHEN Address(28) = '1' AND Address(27) = '1' AND Address(26) = '1' AND nCS_DRAM = '0' ELSE
"11111111";
-- Byte Selection
nByte <= "0111" WHEN nSIZ1 = '0' AND nSIZ0 = '1' AND Address(1) = '0' AND Address(0) = '0' AND nCS_DRAM = '0' ELSE
"1011" WHEN nSIZ1 = '0' AND nSIZ0 = '1' AND Address(1) = '0' AND Address(0) = '1' AND nCS_DRAM = '0' ELSE
"1101" WHEN nSIZ1 = '0' AND nSIZ0 = '1' AND Address(1) = '1' AND Address(0) = '0' AND nCS_DRAM = '0' ELSE
"1110" WHEN nSIZ1 = '0' AND nSIZ0 = '1' AND Address(1) = '1' AND Address(0) = '1' AND nCS_DRAM = '0' ELSE
"0011" WHEN nSIZ1 = '1' AND nSIZ0 = '0' AND Address(1) = '0' AND Address(0) = '0' AND nCS_DRAM = '0' ELSE
"1001" WHEN nSIZ1 = '1' AND nSIZ0 = '0' AND Address(1) = '0' AND Address(0) = '1' AND nCS_DRAM = '0' ELSE
"1100" WHEN nSIZ1 = '1' AND nSIZ0 = '0' AND Address(1) = '1' AND Address(0) = '0' AND nCS_DRAM = '0' ELSE
"1110" WHEN nSIZ1 = '1' AND nSIZ0 = '0' AND Address(1) = '1' AND Address(0) = '1' AND nCS_DRAM = '0' ELSE
"0001" WHEN nSIZ1 = '1' AND nSIZ0 = '1' AND Address(1) = '0' AND Address(0) = '0' AND nCS_DRAM = '0' ELSE
"1000" WHEN nSIZ1 = '1' AND nSIZ0 = '1' AND Address(1) = '0' AND Address(0) = '1' AND nCS_DRAM = '0' ELSE
"1100" WHEN nSIZ1 = '1' AND nSIZ0 = '1' AND Address(1) = '1' AND Address(0) = '0' AND nCS_DRAM = '0' ELSE
"1110" WHEN nSIZ1 = '1' AND nSIZ0 = '1' AND Address(1) = '1' AND Address(0) = '1' AND nCS_DRAM = '0' ELSE
"0000" WHEN nSIZ1 = '0' AND nSIZ0 = '0' AND Address(1) = '0' AND Address(0) = '0' AND nCS_DRAM = '0' ELSE
"1000" WHEN nSIZ1 = '0' AND nSIZ0 = '0' AND Address(1) = '0' AND Address(0) = '1' AND nCS_DRAM = '0' ELSE
"1100" WHEN nSIZ1 = '0' AND nSIZ0 = '0' AND Address(1) = '1' AND Address(0) = '0' AND nCS_DRAM = '0' ELSE
"1110" WHEN nSIZ1 = '0' AND nSIZ0 = '0' AND Address(1) = '1' AND Address(0) = '1' AND nCS_DRAM = '0' ELSE
"1111";
END Behavioral;
|
gpl-3.0
|
8c8c194d5ef2aaf689572eac18cf366d
| 0.495719 | 3.383223 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/tp1/led_display_controller/led_display_controller.vhd
| 1 | 1,571 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity led_display_controller is
port (
clk_in: in std_logic;
bcd0: in std_logic_vector(3 downto 0);
bcd1: in std_logic_vector(3 downto 0);
bcd2: in std_logic_vector(3 downto 0);
bcd3: in std_logic_vector(3 downto 0);
a0: out std_logic;
a1: out std_logic;
a2: out std_logic;
a3: out std_logic;
a: out std_logic;
b: out std_logic;
c: out std_logic;
d: out std_logic;
e: out std_logic;
f: out std_logic;
g: out std_logic;
dp: out std_logic
);
end;
architecture led_display_controller_arq of led_display_controller is
signal counter_enabler: std_logic:= '1';
signal counter_output: std_logic_vector(1 downto 0);
component generic_counter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end component;
component generic_enabler is
generic(PERIOD:natural := 1000000 );
port(
clk: in std_logic;
rst: in std_logic;
ena_out: out std_logic
);
end component;
begin
genericCounterMap: generic_counter generic map (2,4)
port map(
clk => clk_in,
rst => '0',
ena => counter_enabler,
count => counter_output
);
generic_enabler_map: generic_enabler generic map (100000)
port map(
clk => clk_in,
rst => '0',
ena_out => counter_enabler
);
end;
|
gpl-3.0
|
03c042a7101791e2658e53dc2b89f30a
| 0.612349 | 3.193089 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/tp1/anode_selector.vhd
| 1 | 677 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY anode_sel IS
PORT(
sel_in : IN std_logic_vector(1 DOWNTO 0);
sel_out : OUT std_logic_vector(3 DOWNTO 0));
END anode_sel;
ARCHITECTURE anode_sel_arq OF anode_sel IS
BEGIN
PROCESS (sel_in) IS
BEGIN
CASE sel_in IS
WHEN "00" => sel_out <= b"0001";
WHEN "01" => sel_out <= b"0010";
WHEN "10" => sel_out <= b"0100";
WHEN "11" => sel_out <= b"1000";
WHEN OTHERS => sel_out <= (others => '0');
END CASE;
END PROCESS;
END anode_sel_arq;
|
gpl-3.0
|
a269f28535d3431b75e534ccd5afd442
| 0.496307 | 3.489691 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/codeword_generator_n_m_v2.vhd
| 1 | 19,558 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Codeword_Generator_n_m_v2
-- Module Name: Codeword_Generator_n_m_v2
-- Project Name: McEliece QD-Goppa Encoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The first and only step in QD-Goppa Code encoding.
-- This circuit transforms an k-bit message into a valid n-bit codeword.
-- The transformation is an multiplication of a message of k-bits by the
-- Generator matrix G. The Generator matrix is composed of Identity Matrix and
-- another matrix A. For this reason the first k bits of the codeword are equal
-- to the message, only the last n-k bits are computed. This circuit works only
-- only for QD-Goppa codes, where matrix A is composed of dyadic matrices and
-- can be stored only by the first row of each dyadic matrix.
-- Matrix A is supposed to be stored with a word with the same size as dyadic matrix rows.
-- Also, each dyadic matrix row followed by each one, in a row-wise pattern.
--
-- This circuit process n+m bits at time, each time is 1 cycle.
-- n and m are represented as number_of_multipliers_per_acc and number_of_accs parameters.
-- This circuit is efficient however it process in two steps:
-- First it copies k bits.
-- Second compute the last n-k bits.
-- To decrease response time, both operations are done in parallel in version n_m_v3.
--
-- The circuits parameters
--
-- number_of_multipliers_per_acc :
--
-- The number of matrix rows and message values calculate at once in one or more accumulators.
-- On this implementation this value, must be the same of number_of_accs,
-- because of copy message. When copying message message values loaded must be same stored in codeword.
--
-- number_of_accs :
--
-- The number of matrix columns and codeword values calculate at once.
-- On this implementation this value, must be the same of number_of_multipliers_per_acc,
-- because of copy message. When copying message message values loaded must be same stored in codeword.
--
-- length_message :
--
-- Length in bits of message size and also part of matrix size.
--
-- size_message :
--
-- The number of bits necessary to store the message. The ceil(log2(lenght_message))
--
-- length_codeword :
--
-- Length in bits of codeword size and also part of matrix size.
--
-- size_codeword :
--
-- The number of bits necessary to store the codeword. The ceil(log2(legth_codeword))
--
-- size_dyadic_matrix :
--
-- The number of bits necessary to store one row of the dyadic matrix.
-- It is also the ceil(log2(number of errors in the code))
--
-- number_dyadic_matrices :
--
-- The number of dyadic matrices present in matrix A.
--
-- size_number_dyadic_matrices :
--
-- The number of bits necessary to store the number of dyadic matrices.
-- The ceil(log2(number_dyadic_matrices))
--
-- Dependencies:
--
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- controller_codeword_generator_2 Rev 1.0
-- adder_gf_2_m Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_rst_set_nbits Rev 1.0
--
-- Revision:
-- Revision 1.00 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity codeword_generator_n_m_v2 is
Generic(
-- QD-GOPPA [2528, 2144, 32, 12] --
number_of_multipliers_per_acc : integer := 4;
number_of_accs : integer := 4;
length_message : integer := 2144;
size_message : integer := 12;
length_codeword : integer := 2528;
size_codeword : integer := 12;
size_dyadic_matrix : integer := 5;
number_dyadic_matrices : integer := 804;
size_number_dyadic_matrices : integer := 10
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_multipliers_per_acc : integer := 1;
-- number_of_accs : integer := 1;
-- length_message : integer := 2048;
-- size_message : integer := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 384;
-- size_number_dyadic_matrices : integer := 9
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_multipliers_per_acc : integer := 1;
-- number_of_accs : integer := 1;
-- length_message : integer := 2560;
-- size_message : integer := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 480;
-- size_number_dyadic_matrices : integer := 9
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_multipliers_per_acc : integer := 128;
-- number_of_accs : integer := 128;
-- length_message : integer := 5632;
-- size_message : integer := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- size_dyadic_matrix : integer := 7;
-- number_dyadic_matrices : integer := 572;
-- size_number_dyadic_matrices : integer := 10
);
Port(
codeword : in STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
matrix : in STD_LOGIC_VECTOR((2**size_dyadic_matrix - 1) downto 0);
message : in STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
new_codeword : out STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
write_enable_new_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC;
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_message : out STD_LOGIC_VECTOR((size_message - 1) downto 0);
address_matrix : out STD_LOGIC_VECTOR((size_dyadic_matrix + size_number_dyadic_matrices - 1) downto 0)
);
end codeword_generator_n_m_v2;
architecture RTL of codeword_generator_n_m_v2 is
component controller_codeword_generator_2
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_ctr_dyadic_column_q : in STD_LOGIC;
limit_ctr_dyadic_row_q : in STD_LOGIC;
limit_ctr_address_message_q : in STD_LOGIC;
limit_ctr_address_codeword_q : in STD_LOGIC;
zero_ctr_address_message_q : in STD_LOGIC;
write_enable_new_codeword : out STD_LOGIC;
external_matrix_ce : out STD_LOGIC;
message_added_to_codeword : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_codeword_rst : out STD_LOGIC;
reg_message_ce : out STD_LOGIC;
reg_matrix_ce : out STD_LOGIC;
ctr_dyadic_column_ce : out STD_LOGIC;
ctr_dyadic_column_rst : out STD_LOGIC;
ctr_dyadic_row_ce : out STD_LOGIC;
ctr_dyadic_row_rst : out STD_LOGIC;
ctr_dyadic_matrices_ce : out STD_LOGIC;
ctr_dyadic_matrices_rst : out STD_LOGIC;
ctr_address_base_message_ce : out STD_LOGIC;
ctr_address_base_message_rst : out STD_LOGIC;
ctr_address_base_codeword_ce : out STD_LOGIC;
ctr_address_base_codeword_rst : out STD_LOGIC;
ctr_address_base_codeword_set : out STD_LOGIC;
internal_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_set_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
set : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
set_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component adder_gf_2_m
Generic(
gf_2_m : integer := 1;
number_of_elements : integer range 2 to integer'high := 2
);
Port(
a : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_elements) - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal reg_codeword_d : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal reg_codeword_ce : STD_LOGIC;
signal reg_codeword_rst : STD_LOGIC;
constant reg_codeword_rst_value : STD_LOGIC_VECTOR := "0";
signal reg_codeword_q : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal reg_message_d : STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
signal reg_message_ce : STD_LOGIC;
signal reg_message_q : STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
signal reg_matrix_d : STD_LOGIC_VECTOR((number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
signal reg_matrix_ce : STD_LOGIC;
signal reg_matrix_q : STD_LOGIC_VECTOR((number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
signal external_matrix_d : STD_LOGIC_VECTOR((2**size_dyadic_matrix - 1) downto 0);
signal external_matrix_ce : STD_LOGIC;
signal external_matrix_q : STD_LOGIC_VECTOR((2**size_dyadic_matrix - 1) downto 0);
signal ctr_dyadic_column_ce : STD_LOGIC;
signal ctr_dyadic_column_rst : STD_LOGIC;
constant ctr_dyadic_column_rst_value : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_dyadic_column_q : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0);
signal limit_ctr_dyadic_column_q : STD_LOGIC;
signal ctr_dyadic_row_ce : STD_LOGIC;
signal ctr_dyadic_row_rst : STD_LOGIC;
constant ctr_dyadic_row_rst_value : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_dyadic_row_q : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0);
signal limit_ctr_dyadic_row_q : STD_LOGIC;
signal ctr_dyadic_matrices_ce : STD_LOGIC;
signal ctr_dyadic_matrices_rst : STD_LOGIC;
constant ctr_dyadic_matrices_rst_value : STD_LOGIC_VECTOR((size_number_dyadic_matrices - 1) downto 0) := (others => '0');
signal ctr_dyadic_matrices_q : STD_LOGIC_VECTOR((size_number_dyadic_matrices - 1) downto 0);
signal ctr_address_base_message_ce : STD_LOGIC;
signal ctr_address_base_message_rst : STD_LOGIC;
constant ctr_address_base_message_rst_value : STD_LOGIC_VECTOR((size_message - size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_address_base_message_q : STD_LOGIC_VECTOR((size_message - size_dyadic_matrix - 1) downto 0);
signal limit_ctr_address_message_q : STD_LOGIC;
signal zero_ctr_address_message_q : STD_LOGIC;
signal ctr_address_base_codeword_ce : STD_LOGIC;
signal ctr_address_base_codeword_rst : STD_LOGIC;
signal ctr_address_base_codeword_set : STD_LOGIC;
constant ctr_address_base_codeword_rst_value : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0) := (others => '0');
constant ctr_address_base_codeword_set_value : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0) := std_logic_vector(to_unsigned(length_message/2**size_dyadic_matrix, size_codeword - size_dyadic_matrix));
signal ctr_address_base_codeword_q : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0);
signal limit_ctr_address_codeword_q : STD_LOGIC;
signal internal_address_codeword : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal internal_address_message : STD_LOGIC_VECTOR((size_message - 1) downto 0);
signal internal_address_matrix : STD_LOGIC_VECTOR(((size_dyadic_matrix + size_number_dyadic_matrices) - 1) downto 0);
signal internal_codeword : STD_LOGIC;
signal internal_new_codeword : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal message_added_to_codeword : STD_LOGIC;
signal partial_product : STD_LOGIC_VECTOR((number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
signal accumulated_values : STD_LOGIC_VECTOR((number_of_accs*(number_of_multipliers_per_acc+1) - 1) downto 0);
signal dyadic_matrix_address : STD_LOGIC_VECTOR(((size_dyadic_matrix)*number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
begin
controller : controller_codeword_generator_2
Port Map(
clk => clk,
rst => rst,
limit_ctr_dyadic_column_q => limit_ctr_dyadic_column_q,
limit_ctr_dyadic_row_q => limit_ctr_dyadic_row_q,
limit_ctr_address_message_q => limit_ctr_address_message_q,
limit_ctr_address_codeword_q => limit_ctr_address_codeword_q,
zero_ctr_address_message_q => zero_ctr_address_message_q,
write_enable_new_codeword => write_enable_new_codeword,
external_matrix_ce => external_matrix_ce,
message_added_to_codeword => message_added_to_codeword ,
reg_codeword_ce => reg_codeword_ce,
reg_codeword_rst => reg_codeword_rst,
reg_message_ce => reg_message_ce,
reg_matrix_ce => reg_matrix_ce,
ctr_dyadic_column_ce => ctr_dyadic_column_ce,
ctr_dyadic_column_rst => ctr_dyadic_column_rst,
ctr_dyadic_row_ce => ctr_dyadic_row_ce,
ctr_dyadic_row_rst => ctr_dyadic_row_rst,
ctr_dyadic_matrices_ce => ctr_dyadic_matrices_ce,
ctr_dyadic_matrices_rst => ctr_dyadic_matrices_rst,
ctr_address_base_message_ce => ctr_address_base_message_ce,
ctr_address_base_message_rst => ctr_address_base_message_rst,
ctr_address_base_codeword_ce => ctr_address_base_codeword_ce,
ctr_address_base_codeword_rst => ctr_address_base_codeword_rst,
ctr_address_base_codeword_set => ctr_address_base_codeword_set,
internal_codeword => internal_codeword,
codeword_finalized => codeword_finalized
);
cod_accumulators : for I in 0 to (number_of_accs - 1) generate
cod_multipliers : for J in 0 to (number_of_multipliers_per_acc - 1) generate
reg_matrix_I_J : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_matrix_d((I*number_of_multipliers_per_acc + J) downto (I*number_of_multipliers_per_acc + J)),
clk => clk,
ce => reg_matrix_ce,
q => reg_matrix_q((I*number_of_multipliers_per_acc + J) downto (I*number_of_multipliers_per_acc + J))
);
dyadic_matrix_address(((I*number_of_multipliers_per_acc + J + 1)*(size_dyadic_matrix) - 1) downto ((I*number_of_multipliers_per_acc + J)*(size_dyadic_matrix))) <= ((std_logic_vector(unsigned(ctr_dyadic_column_q)+to_unsigned(I, ctr_dyadic_column_q'length))) xor (std_logic_vector(unsigned(ctr_dyadic_row_q)+to_unsigned(J, ctr_dyadic_row_q'length)-number_of_multipliers_per_acc)));
reg_matrix_d(I*number_of_multipliers_per_acc + J) <= external_matrix_q(to_integer(unsigned(dyadic_matrix_address(((I*number_of_multipliers_per_acc + J + 1)*(size_dyadic_matrix) - 1) downto ((I*number_of_multipliers_per_acc + J)*(size_dyadic_matrix))))));
partial_product((I*number_of_multipliers_per_acc + J)) <= reg_message_q(J) and reg_matrix_q((I*number_of_multipliers_per_acc + J));
end generate;
end generate;
accumulators : for I in 0 to (number_of_accs - 1) generate
adder_I : adder_gf_2_m
Generic Map(
gf_2_m => 1,
number_of_elements => number_of_multipliers_per_acc+1
)
Port Map(
a => accumulated_values(((I + 1)*(number_of_multipliers_per_acc+1) - 1) downto I*(number_of_multipliers_per_acc+1)),
o => internal_new_codeword(I downto I)
);
reg_acc_I : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_codeword_d(I downto I),
clk => clk,
ce => reg_codeword_ce,
rst => reg_codeword_rst,
rst_value => reg_codeword_rst_value,
q => reg_codeword_q(I downto I)
);
accumulated_values(((I + 1)*(number_of_multipliers_per_acc+1) - 1) downto I*(number_of_multipliers_per_acc+1)) <= partial_product(((I + 1)*number_of_multipliers_per_acc - 1) downto I*number_of_multipliers_per_acc) & reg_codeword_q(I downto I);
end generate;
multipliers : for I in 0 to (number_of_multipliers_per_acc - 1) generate
reg_vector_I : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_message_d(I downto I),
clk => clk,
ce => reg_message_ce,
q => reg_message_q(I downto I)
);
end generate;
external_matrix : register_nbits
Generic Map(
size => 2**size_dyadic_matrix
)
Port Map(
d => external_matrix_d,
clk => clk,
ce => external_matrix_ce,
q => external_matrix_q
);
ctr_dyadic_column : counter_rst_nbits
Generic Map(
size => size_dyadic_matrix,
increment_value => number_of_accs
)
Port Map(
clk => clk,
ce => ctr_dyadic_column_ce,
rst => ctr_dyadic_column_rst,
rst_value => ctr_dyadic_column_rst_value,
q => ctr_dyadic_column_q
);
ctr_dyadic_row : counter_rst_nbits
Generic Map(
size => size_dyadic_matrix,
increment_value => number_of_multipliers_per_acc
)
Port Map(
clk => clk,
ce => ctr_dyadic_row_ce,
rst => ctr_dyadic_row_rst,
rst_value => ctr_dyadic_row_rst_value,
q => ctr_dyadic_row_q
);
ctr_dyadic_matrices : counter_rst_nbits
Generic Map(
size => size_number_dyadic_matrices,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_dyadic_matrices_ce,
rst => ctr_dyadic_matrices_rst,
rst_value => ctr_dyadic_matrices_rst_value,
q => ctr_dyadic_matrices_q
);
ctr_address_base_vector : counter_rst_nbits
Generic Map(
size => size_message - size_dyadic_matrix,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_address_base_message_ce,
rst => ctr_address_base_message_rst,
rst_value => ctr_address_base_message_rst_value,
q => ctr_address_base_message_q
);
ctr_address_base_acc : counter_rst_set_nbits
Generic Map(
size => size_codeword - size_dyadic_matrix,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_address_base_codeword_ce,
set => ctr_address_base_codeword_set,
rst => ctr_address_base_codeword_rst,
set_value => ctr_address_base_codeword_set_value,
rst_value => ctr_address_base_codeword_rst_value,
q => ctr_address_base_codeword_q
);
external_matrix_d <= matrix;
new_codeword <= reg_message_q xor reg_codeword_q when message_added_to_codeword = '1' else
internal_new_codeword;
reg_codeword_d <= internal_new_codeword when internal_codeword = '1' else
codeword;
reg_message_d <= message;
internal_address_message <= ctr_address_base_message_q & ctr_dyadic_row_q;
internal_address_codeword <= ctr_address_base_codeword_q & ctr_dyadic_column_q;
internal_address_matrix((size_number_dyadic_matrices + size_dyadic_matrix - 1) downto size_dyadic_matrix) <= ctr_dyadic_matrices_q;
internal_address_matrix((size_dyadic_matrix - 1) downto 0) <= (others => '0');
address_codeword <= internal_address_codeword;
address_message <= internal_address_message;
address_matrix <= internal_address_matrix;
limit_ctr_dyadic_column_q <= '1' when ctr_dyadic_column_q = std_logic_vector(to_unsigned(2**size_dyadic_matrix - number_of_accs, ctr_dyadic_column_q'length)) else '0';
limit_ctr_dyadic_row_q <= '1' when ctr_dyadic_row_q = std_logic_vector(to_unsigned(2**size_dyadic_matrix - number_of_multipliers_per_acc, ctr_dyadic_row_q'length)) else '0';
limit_ctr_address_message_q <= '1' when internal_address_message((size_message - 1) downto 0) = std_logic_vector(to_unsigned(length_message - number_of_multipliers_per_acc, size_message)) else '0';
limit_ctr_address_codeword_q <= '1' when internal_address_codeword((size_codeword - 1) downto 0) = std_logic_vector(to_unsigned(length_codeword - number_of_accs, size_codeword)) else '0';
zero_ctr_address_message_q <= '1' when internal_address_message((size_message - 1) downto 0) = std_logic_vector(to_unsigned(0, size_message)) else '0';
end RTL;
|
bsd-2-clause
|
cb80f1625c1c6baacc937d0dd8c40e4b
| 0.691226 | 3.00661 | false | false | false | false |
rodrigoazs/-7-5-Reed-Solomon
|
code/reedsolomon.vhd
| 1 | 5,367 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity ReedSolomon is
end ReedSolomon;
architecture Behavioral of ReedSolomon is
component ReedSolomonEncoder is
Port ( Clock : in std_logic;
Count7 : in std_logic;
Qs0 : in std_logic_vector(2 downto 0);
Qp : out std_logic_vector(2 downto 0));
end component;
component ReedSolomonDecoder is
Port ( Clock : in std_logic;
Count7 : in std_logic;
Qs0: in std_logic_vector(2 downto 0);
Dsyn1: out std_logic_vector(2 downto 0);
Dsyn2: out std_logic_vector(2 downto 0));
end component;
component counter is
Port( Clock: in std_logic;
Count5: out std_logic;
Count7: out std_logic);
end component;
component mux6 is
Port (y1: in std_logic_vector(2 downto 0);
y0: in std_logic_vector(2 downto 0);
s: in std_logic;
f: out std_logic_vector(2 downto 0));
end component ;
component flipflop is
Port ( D: in std_logic_vector(2 downto 0);
Clock: in std_logic;
Reset: in std_logic;
Q: out std_logic_vector(2 downto 0));
end component ;
component ErrorGenerator is
Port ( Clock : in std_logic;
Qout: out std_logic_vector(2 downto 0));
end component;
component ErrorGuessing is
Port ( Syndrome: in std_logic_vector(5 downto 0);
Error : out std_logic_vector(20 downto 0));
end component;
component read_file is
Port (Clock: in std_logic;
Qout: out std_logic_vector(2 downto 0));
end component;
component write_file is
Port (Clock: in std_logic;
Message: in std_logic_vector(14 downto 0));
end component;
component write_error is
Port (Clock: in std_logic;
Message: in std_logic_vector(14 downto 0));
end component;
signal Qp: std_logic_vector(2 downto 0);
signal Count5: std_logic;
signal Count7: std_logic;
signal out_mux1: std_logic_vector(2 downto 0);
signal ErrorGenerated: std_logic_vector(2 downto 0);
signal out2: std_logic_vector(2 downto 0);
signal unusual: std_logic;
signal Qs0 : std_logic_vector(2 downto 0);
signal Db0 : std_logic_vector(2 downto 0);
signal Db1 : std_logic_vector(2 downto 0);
signal Db2 : std_logic_vector(2 downto 0);
signal Db3 : std_logic_vector(2 downto 0);
signal Db4 : std_logic_vector(2 downto 0);
signal Db5 : std_logic_vector(2 downto 0);
signal Db6 : std_logic_vector(2 downto 0);
signal Qb0 : std_logic_vector(2 downto 0);
signal Qb1 : std_logic_vector(2 downto 0);
signal Qb2 : std_logic_vector(2 downto 0);
signal Qb3 : std_logic_vector(2 downto 0);
signal Qb4 : std_logic_vector(2 downto 0);
signal Qb5 : std_logic_vector(2 downto 0);
signal Qb6 : std_logic_vector(2 downto 0);
signal Din : std_logic_vector(2 downto 0);
signal Syn1 : std_logic_vector(2 downto 0);
signal Syn2 : std_logic_vector(2 downto 0);
signal Syndrome : std_logic_vector(5 downto 0);
signal Error : std_logic_vector(20 downto 0);
signal Message: std_logic_vector(14 downto 0);
signal MessageError: std_logic_vector(14 downto 0);
signal Clock: std_logic;
begin
readdata: read_file Port map (Clock, Qs0);
muxCount: mux6 Port map (Qp, Qs0, Count5, Din);
RDE: ReedSolomonEncoder Port map (Clock, Count7, Din, Qp);
muxa: mux6 Port map (Qp, Din, Count5, out_mux1);
RndGen: ErrorGenerator Port map (Clock, ErrorGenerated);
out2(0) <= out_mux1(0) xor ErrorGenerated(0);
out2(1) <= out_mux1(1) xor ErrorGenerated(1);
out2(2) <= out_mux1(2) xor ErrorGenerated(2);
Db6 <= out2;
ffbuffer0 : flipflop Port map (Db0,Clock,'0',Qb0);
ffbuffer1 : flipflop Port map (Db1,Clock,'0',Qb1);
ffbuffer2 : flipflop Port map (Db2,Clock,'0',Qb2);
ffbuffer3 : flipflop Port map (Db3,Clock,'0',Qb3);
ffbuffer4 : flipflop Port map (Db4,Clock,'0',Qb4);
ffbuffer5 : flipflop Port map (Db5,Clock,'0',Qb5);
ffbuffer6 : flipflop Port map (Db6,Clock,'0',Qb6);
RDD: ReedSolomonDecoder Port map (Clock, Count7, out2,
Syn1, Syn2);
Syndrome(0) <= Syn2(0);
Syndrome(1) <= Syn2(1);
Syndrome(2) <= Syn2(2);
Syndrome(3) <= Syn1(0);
Syndrome(4) <= Syn1(1);
Syndrome(5) <= Syn1(2);
ErrorGuess: ErrorGuessing Port map (Syndrome, Error);
MessageError(0) <= Db0(0);
MessageError(1) <= Db0(1);
MessageError(2) <= Db0(2);
MessageError(3) <= Db1(0);
MessageError(4) <= Db1(1);
MessageError(5) <= Db1(2);
MessageError(6) <= Db2(0);
MessageError(7) <= Db2(1);
MessageError(8) <= Db2(2);
MessageError(9) <= Db3(0);
MessageError(10) <= Db3(1);
MessageError(11) <= Db3(2);
MessageError(12) <= Db4(0);
MessageError(13) <= Db4(1);
MessageError(14) <= Db4(2);
Message(0) <= Db0(0) xor Error(0);
Message(1) <= Db0(1) xor Error(1);
Message(2) <= Db0(2) xor Error(2);
Message(3) <= Db1(0) xor Error(3);
Message(4) <= Db1(1) xor Error(4);
Message(5) <= Db1(2) xor Error(5);
Message(6) <= Db2(0) xor Error(6);
Message(7) <= Db2(1) xor Error(7);
Message(8) <= Db2(2) xor Error(8);
Message(9) <= Db3(0) xor Error(9);
Message(10) <= Db3(1) xor Error(10);
Message(11) <= Db3(2) xor Error(11);
Message(12) <= Db4(0) xor Error(12);
Message(13) <= Db4(1) xor Error(13);
Message(14) <= Db4(2) xor Error(14);
Db0 <= Qb1;
Db1 <= Qb2;
Db2 <= Qb3;
Db3 <= Qb4;
Db4 <= Qb5;
Db5 <= Qb6;
count1: counter Port map (Clock, Count5, Count7);
writedata: write_file Port map (Clock, Message);
writeerror: write_error Port map (Clock, MessageError);
end Behavioral;
|
mit
|
97b4177bb338ec5b8bba8f3ba6a66390
| 0.694615 | 2.789501 | false | false | false | false |
rajvinjamuri/ECE385_VHDL
|
reg_unit.vhd
| 1 | 2,775 |
---------------------------------------------------------------------------
-- reg_unit.vhd --
-- Raj Vinjamuri --
-- 3-13 --
-- --
-- Purpose/Description: --
-- combines the registers to be used as simply as we desire the I/O --
-- --
-- based on register unit given by UIUC --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
-- --
-- --
-- Updates: --
-- --
-- >3.10: Made components lower case --
-- >changed A and B to SR and PR respectively --
-- >fixed 7 downto 0 to 10 downto 0 --
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg_unit is
Port ( Clk : in std_logic;
ClrSR, ClrPR : in std_logic;
D_In : in std_logic_vector(10 downto 0);
SR_In : in std_logic;
Ld_SR : in std_logic;
Ld_PR : in std_logic;
Shift_En : in std_logic;
SR_out : out std_logic;
PR_out : out std_logic;
SR : out std_logic_vector(10 downto 0);
PR : out std_logic_vector(10 downto 0));
end reg_unit;
architecture Behavioral of reg_unit is
component reg_11 is
Port ( Clk, Reset, Shift_In, Load, Shift_En : in std_logic;
D : in std_logic_vector(10 downto 0);
Shift_Out : out std_logic;
Data_Out : out std_logic_vector(10 downto 0));
end component reg_11;
signal shift_line : std_logic;
begin --connecting both registers so one feeds the other
scan_reg: reg_11
port map( Clk => Clk,
Reset => ClrSR,
D => D_In,
Shift_In => SR_in,
Load => Ld_SR,
Shift_En => Shift_En,
Shift_Out => shift_line,
Data_Out => SR);
prev_reg: reg_11
port map( Clk => Clk,
Reset => ClrPR,
D => D_In,
Shift_In => shift_line,
Load => Ld_PR,
Shift_En => Shift_En,
Shift_Out => PR_out,
Data_Out => PR);
end Behavioral;
|
mit
|
07adb17b95bdc0f0d47bff4ff68ec508
| 0.375135 | 4.609635 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
VHDL/LED/LED.vhd
| 1 | 26,850 |
--A program for testing.
--copyright(c) 2014 dtysky
--This program is free software; you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation; either version 2 of the License, or
--(at your option) any later version.
--This program is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License along
--with this program; if not, write to the Free Software Foundation, Inc.,
--51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
------------------------------------------------------------------------
--实现方案：
--由于FIFO输入和输出只能为偶数倍关系，输入又必为32或16bits，所以最后将其调整：
--设立三类FIFO，其中后两类为普通的图片双缓存，第一类为转换
--写入时就按16bits写入！（为了满足要求，由于每一个模块总数据为120*38=4560=285*16），充分利用DM（数据掩码），将RAM作为先后两个RAM对待！
--写入时，一次写入856个16bits数据，丢掉最后一个
--读出时，按照16bits读出！顺序写入一个第一类FIFO
--读出时，每张图片总突发次数为214（最后一个16bits扔掉）
--第一类FIFO为16bits输入，16bits输出；二三类FIFO为80bits输入，40bis输出
--第一类FIFO和二三类之间插入一个80bits信号做缓存（80=16*5=80*1）
--经计算，每10us需更新一次图片，用此方法，保证FIFO数据流跑到240M（DDR2数据流速度），一次更新只需不到2us，满足要求
--所有输出到RAM的信号初值为0
--再锁定尚待加入
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity LED is
generic
(
constant r20_con:integer:=2047; ------------20r/s时每一度间隔计数（clk_control下）
constant opic_con:integer:=1023; ------------刷一张图片一遍计数
constant unlock_con:integer:=4095 ------------解锁计数
);
port
(
clk_control:in std_logic;
clk_data_p:in std_logic;
sensor:in std_logic;
data_buffer_a:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_b:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_c:out std_logic_vector(39 downto 0):=x"0000000000";
en_row_a:out std_logic:='0';
en_row_b:out std_logic:='0';
en_row_c:out std_logic_vector(1 downto 0):="00"; --------分割为两个管脚，分配同一信号
en_col_a_1,en_col_a_2,en_col_a_3:out std_logic:='0';
en_col_b_1,en_col_b_2,en_col_b_3:out std_logic:='0';
en_col_c_1,en_col_c_2,en_col_c_3:out std_logic:='0';
blue_rqu:in std_logic:='0';
blue_end:out std_logic:='0';
blue_data:in std_logic_vector(7 downto 0):=x"00";
ram_data:in std_logic_vector(15 downto 0);
r_rqu:out std_logic;
r_ready:in std_logic;
r_end:in std_logic;
r_num:out std_logic_vector(7 downto 0);
ram_reset:out std_logic:='0';
ram_dm:out std_logic_vector(3 downto 0);
ram_bank:out std_logic_vector(2 downto 0);
ram_addr_row:out std_logic_vector(12 downto 0);
ram_addr_col:out std_logic_vector(9 downto 0)
);
end entity;
architecture ledx of LED is
component FIFO_LED_TRANS is
port
(
aclr:in std_logic;
data:in std_logic_vector(15 downto 0);
rdclk:in std_logic;
rdreq:in std_logic;
wrclk:in std_logic;
wrreq:in std_logic;
q:out std_logic_vector(15 downto 0);
wrusedw:out std_logic_vector(10 downto 0);
rdusedw:out std_logic_vector(10 downto 0)
);
end component;
component FIFO_LED_PIC is
port
(
aclr:in std_logic;
data:in std_logic_vector(79 downto 0);
rdclk:in std_logic;
rdreq:in std_logic;
wrclk:in std_logic;
wrreq:in std_logic;
q:out std_logic_vector(39 downto 0);
rdusedw:out std_logic_vector(7 downto 0);
wrusedw:out std_logic_vector(6 downto 0)
);
end component;
----------------转换缓存----------------
signal fifo_buffer:std_logic_vector(79 downto 0);
----------------fifo例化----------------
--signal data_trans_in:std_logic_vector(15 downto 0);
signal data_trans_out:std_logic_vector(15 downto 0);
signal fifo_trans_write,fifo_trans_read:std_logic:='0';
signal fifo_trans_aclr:std_logic:='0';
signal data_pic_in_a_1:std_logic_vector(79 downto 0);
signal data_pic_out_a_1:std_logic_vector(39 downto 0);
signal clk_pic_out_a_1:std_logic:='0';
signal fifo_pic_write_a_1,fifo_pic_read_a_1:std_logic:='0';
signal fifo_pic_aclr_a_1:std_logic:='0';
signal data_pic_in_a_2:std_logic_vector(79 downto 0);
signal data_pic_out_a_2:std_logic_vector(39 downto 0);
signal clk_pic_out_a_2:std_logic:='0';
signal fifo_pic_write_a_2,fifo_pic_read_a_2:std_logic:='0';
signal fifo_pic_aclr_a_2:std_logic:='0';
signal data_pic_in_a_3:std_logic_vector(79 downto 0);
signal data_pic_out_a_3:std_logic_vector(39 downto 0);
signal clk_pic_out_a_3:std_logic:='0';
signal fifo_pic_write_a_3,fifo_pic_read_a_3:std_logic:='0';
signal fifo_pic_aclr_a_3:std_logic:='0';
signal data_pic_in_b_1:std_logic_vector(79 downto 0);
signal data_pic_out_b_1:std_logic_vector(39 downto 0);
signal clk_pic_out_b_1:std_logic:='0';
signal fifo_pic_write_b_1,fifo_pic_read_b_1:std_logic:='0';
signal fifo_pic_aclr_b_1:std_logic:='0';
signal data_pic_in_b_2:std_logic_vector(79 downto 0);
signal data_pic_out_b_2:std_logic_vector(39 downto 0);
signal clk_pic_out_b_2:std_logic:='0';
signal fifo_pic_write_b_2,fifo_pic_read_b_2:std_logic:='0';
signal fifo_pic_aclr_b_2:std_logic:='0';
signal data_pic_in_b_3:std_logic_vector(79 downto 0);
signal data_pic_out_b_3:std_logic_vector(39 downto 0);
signal clk_pic_out_b_3:std_logic:='0';
signal fifo_pic_write_b_3,fifo_pic_read_b_3:std_logic:='0';
signal fifo_pic_aclr_b_3:std_logic:='0';
--------------fifo已写/可读数据-----------
signal fifo_trans_num:std_logic_vector(10 downto 0);
signal fifo_trans_num_buffer:std_logic_vector(10 downto 0);
signal fifo_pic_num_w_a_1:std_logic_vector(6 downto 0);
signal fifo_pic_num_r_a_1:std_logic_vector(7 downto 0);
signal fifo_pic_num_w_a_2:std_logic_vector(6 downto 0);
signal fifo_pic_num_w_a_3:std_logic_vector(6 downto 0);
signal fifo_pic_num_w_a_1_buffer:std_logic_vector(6 downto 0);
signal fifo_pic_num_w_a_2_buffer:std_logic_vector(6 downto 0);
signal fifo_pic_num_w_a_3_buffer:std_logic_vector(6 downto 0);
signal fifo_pic_num_w_b_1:std_logic_vector(6 downto 0);
signal fifo_pic_num_w_b_2:std_logic_vector(6 downto 0);
signal fifo_pic_num_w_b_3:std_logic_vector(6 downto 0);
signal fifo_pic_num_w_b_1_buffer:std_logic_vector(6 downto 0);
signal fifo_pic_num_w_b_2_buffer:std_logic_vector(6 downto 0);
signal fifo_pic_num_w_b_3_buffer:std_logic_vector(6 downto 0);
-------------------ram-------------------
signal ram_bank_s:std_logic_vector(2 downto 0):="000";
signal ram_addr_row_s:std_logic_vector(12 downto 0):="0000000000000";
signal ram_addr_col_s:std_logic_vector(9 downto 0):="0000000000";
signal r_rqu_s,r_ready_s:std_logic:='0';
------------------状态标志----------------
type states_t is (trans_in,trans_a,trans_b);
signal trans_state:states_t:=trans_in;
type states_c is (free,control_work);
signal control_state:states_c:=free;
type states_l is (lock,unlock);
signal lock_state:states_l:=lock;
signal control_begin:std_logic:='0';
signal fifo_choice:std_logic:='0';
signal sensor_last:std_logic:='0';
------------------图片第几张--------------
signal pic_num:std_logic_vector(12 downto 0):="0000000000001"; ----从1开始
signal pic_num_last:std_logic_vector(12 downto 0):="0000000000001";
signal pic_dm:std_logic_vector(3 downto 0):="0011";
signal pic_bank:std_logic_vector(2 downto 0):="000";
signal pic_addr_row:std_logic_vector(12 downto 0):="0000000000000";
-------------------图片行-----------------
signal pic_row_ab:bit_vector(37 downto 0):="01111111111111111111111111111111111111";
signal pic_row_c_h:bit_vector(37 downto 0):="01111111111111111111111111111111111111";
signal pic_row_c_l:bit_vector(37 downto 0):="11111111111111111101111111111111111111";
signal pic_no:std_logic_vector(7 downto 0):=x"00";
-------------------蓝牙------------------
signal blue_rqu_s:std_logic;
begin
r_rqu<=r_rqu_s;
--pic_row_abc_n<=pic_row_abc;
FIFO_TRANS:FIFO_LED_TRANS
port map
(
aclr=>fifo_trans_aclr,
data=>ram_data,q=>data_trans_out,
wrclk=>clk_data_p,rdclk=>clk_data_p,
wrreq=>fifo_trans_write,rdreq=>fifo_trans_read,
wrusedw=>fifo_trans_num
);
FIFO_PIC_A_1:FIFO_LED_PIC
port map
(
aclr=>fifo_pic_aclr_a_1,
data=>data_pic_in_a_1,q=>data_pic_out_a_1,
wrclk=>clk_data_p,rdclk=>clk_pic_out_a_1,
wrreq=>fifo_pic_write_a_1,rdreq=>fifo_pic_read_a_1,
wrusedw=>fifo_pic_num_w_a_1,rdusedw=>fifo_pic_num_r_a_1
);
FIFO_PIC_A_2:FIFO_LED_PIC
port map
(
aclr=>fifo_pic_aclr_a_2,
data=>data_pic_in_a_2,q=>data_pic_out_a_2,
wrclk=>clk_data_p,rdclk=>clk_pic_out_a_2,
wrreq=>fifo_pic_write_a_2,rdreq=>fifo_pic_read_a_2,
wrusedw=>fifo_pic_num_w_a_2
);
FIFO_PIC_A_3:FIFO_LED_PIC
port map
(
aclr=>fifo_pic_aclr_a_3,
data=>data_pic_in_a_3,q=>data_pic_out_a_3,
wrclk=>clk_data_p,rdclk=>clk_pic_out_a_3,
wrreq=>fifo_pic_write_a_3,rdreq=>fifo_pic_read_a_3,
wrusedw=>fifo_pic_num_w_a_3
);
FIFO_PIC_B_1:FIFO_LED_PIC
port map
(
aclr=>fifo_pic_aclr_b_1,
data=>data_pic_in_b_1,q=>data_pic_out_b_1,
wrclk=>clk_data_p,rdclk=>clk_pic_out_b_1,
wrreq=>fifo_pic_write_b_1,rdreq=>fifo_pic_read_b_1,
wrusedw=>fifo_pic_num_w_b_1
);
FIFO_PIC_B_2:FIFO_LED_PIC
port map
(
aclr=>fifo_pic_aclr_b_2,
data=>data_pic_in_b_2,q=>data_pic_out_b_2,
wrclk=>clk_data_p,rdclk=>clk_pic_out_b_2,
wrreq=>fifo_pic_write_b_2,rdreq=>fifo_pic_read_b_2,
wrusedw=>fifo_pic_num_w_b_2
);
FIFO_PIC_B_3:FIFO_LED_PIC
port map
(
aclr=>fifo_pic_aclr_b_3,
data=>data_pic_in_b_3,q=>data_pic_out_b_3,
wrclk=>clk_data_p,rdclk=>clk_pic_out_b_3,
wrreq=>fifo_pic_write_b_3,rdreq=>fifo_pic_read_b_3,
wrusedw=>fifo_pic_num_w_b_3
);
TRANS:process(clk_data_p)
variable con_unlock:integer range 0 to unlock_con+1:=0;
variable con_trans_in:integer range 0 to 3:=0;
variable con_trans_a:integer range 0 to 15:=0;
variable con_trans_b:integer range 0 to 15:=0;
variable con_timeout:integer range 0 to 127:=0;
begin
if clk_data_p'event and clk_data_p='1' then
case lock_state is
---------------LOCK------------------
when lock =>
if sensor_last='0' and sensor='1' then
if con_unlock>unlock_con then
lock_state<=unlock;
con_unlock:=0;
else
lock_state<=lock;
end if;
else
if con_unlock>unlock_con then
con_unlock:=con_unlock;
else
con_unlock:=con_unlock+1;
end if;
end if;
----------------RELOAD---------------
when others =>
pic_num_last<=pic_num;
if pic_num_last=pic_num then
control_begin<=control_begin;
else
control_begin<='0';
end if;
if sensor_last='0' and sensor='1' then
fifo_trans_aclr<='1';
con_trans_in:=0;
con_trans_a:=0;
con_trans_b:=0;
con_unlock:=0;
pic_addr_row(12 downto 9)<=pic_no(3 downto 0);
pic_bank<=pic_no(6 downto 4);
if pic_no(7)='1' then
pic_dm<="0011";
else
pic_dm<="1100";
end if;
trans_state<=trans_in;
else
case trans_state is
----------------TRANS_IN-----------------
when trans_in =>
case con_trans_in is
when 0 =>
r_num<=x"D6"; ----214次突发
ram_dm<=pic_dm; ----一张三维图的所有切片必在一个bank内，由于是静态三维图，故不用切换bank，更不用切换RAM
ram_bank_s<=pic_bank;
ram_addr_row_s<=pic_addr_row+pic_num-1;
ram_addr_col_s<="0000000000";
con_timeout:=0;
ram_reset<='0';
con_trans_in:=1;
when 1 =>
ram_bank<=ram_bank_s;
ram_addr_row<=ram_addr_row_s;
ram_addr_col<=ram_addr_col_s;
if fifo_trans_num_buffer="0000000000" then
fifo_trans_aclr<='0';
r_rqu_s<='1';
con_trans_in:=2;
else
fifo_trans_aclr<='1';
r_rqu_s<='0';
con_trans_in:=1;
end if;
when 2 =>
case r_ready_s is
when '1' =>
fifo_trans_write<='1';
con_timeout:=0;
when others =>
if con_timeout=80 then
r_rqu_s<='0';
ram_reset<='1';
con_timeout:=0;
else
con_timeout:=con_timeout+1;
end if;
if fifo_trans_num_buffer="01101011000" then ----是否提前一个周期待定
con_trans_in:=3;
else
con_trans_in:=2;
end if;
end case;
if fifo_trans_num_buffer="01101011000" then
fifo_trans_write<='0';
r_rqu_s<='0';
else
r_rqu_s<='1';
end if;
when others =>
if fifo_pic_num_w_a_1_buffer="0000000" and fifo_pic_num_w_b_1_buffer="0000000" then
trans_state<=trans_a;
con_trans_in:=0;
elsif fifo_pic_num_w_a_1_buffer="0000000" then
trans_state<=trans_a;
con_trans_in:=0;
elsif fifo_pic_num_w_b_1_buffer="0000000" then
trans_state<=trans_b;
con_trans_in:=0;
else
trans_state<=trans_in;
con_trans_in:=2;
end if;
end case;
----------------TRANS_A-----------------
when trans_a => ----------从FIFO_TRANS读五个，然后塞入第一个FIFO，满后第二个，满后第三个
case con_trans_a is
when 0 =>
fifo_trans_read<='1';
con_trans_a:=con_trans_a+1;
when 1 =>
fifo_buffer(79 downto 64)<=data_trans_out;
con_trans_a:=con_trans_a+1;
when 2 =>
fifo_buffer(63 downto 48)<=data_trans_out;
con_trans_a:=con_trans_a+1;
when 3 =>
fifo_buffer(47 downto 32)<=data_trans_out;
con_trans_a:=con_trans_a+1;
when 4 =>
fifo_buffer(31 downto 16)<=data_trans_out;
con_trans_a:=con_trans_a+1;
when 5 =>
fifo_buffer(15 downto 0)<=data_trans_out;
fifo_trans_read<='0';
con_trans_a:=con_trans_a+1;
when 6 =>
if fifo_pic_num_w_a_1_buffer<"0111001" then
data_pic_in_a_1<=fifo_buffer;
fifo_pic_write_a_1<='1';
elsif fifo_pic_num_w_a_2_buffer<"0111001" then
data_pic_in_a_2<=fifo_buffer;
fifo_pic_write_a_2<='1';
elsif fifo_pic_num_w_a_3_buffer<"0111001" then
data_pic_in_a_3<=fifo_buffer;
fifo_pic_write_a_3<='1';
else
con_trans_a:=con_trans_a;
end if;
con_trans_a:=con_trans_a+1;
when others =>
fifo_pic_write_a_1<='0';
fifo_pic_write_a_2<='0';
fifo_pic_write_a_3<='0';
con_trans_a:=0;
if fifo_trans_num_buffer="00000000001" then
if fifo_pic_num_w_b_1_buffer="0000000" then
control_begin<='1';
else
control_begin<='0';
end if;
fifo_trans_aclr<='1';
trans_state<=trans_in;
else
trans_state<=trans_a;
end if;
end case;
----------------TRANS_B-----------------
when trans_b => ----------从FIFO_TRANS读五个，然后塞入第一个FIFO，满后第二个，满后第三个
case con_trans_b is
when 0 =>
fifo_trans_read<='1';
con_trans_b:=con_trans_b+1;
when 1 =>
fifo_buffer(79 downto 64)<=data_trans_out;
con_trans_b:=con_trans_b+1;
when 2 =>
fifo_buffer(63 downto 48)<=data_trans_out;
con_trans_b:=con_trans_b+1;
when 3 =>
fifo_buffer(47 downto 32)<=data_trans_out;
con_trans_b:=con_trans_b+1;
when 4 =>
fifo_buffer(31 downto 16)<=data_trans_out;
con_trans_b:=con_trans_b+1;
when 5 =>
fifo_buffer(15 downto 0)<=data_trans_out;
fifo_trans_read<='0';
con_trans_b:=con_trans_b+1;
when 6 =>
if fifo_pic_num_w_b_1_buffer<"0111001" then
data_pic_in_b_1<=fifo_buffer;
fifo_pic_write_b_1<='1';
elsif fifo_pic_num_w_b_2_buffer<"0111001" then
data_pic_in_b_2<=fifo_buffer;
fifo_pic_write_b_2<='1';
elsif fifo_pic_num_w_b_3_buffer<"0111001" then
data_pic_in_b_3<=fifo_buffer;
fifo_pic_write_b_3<='1';
else
con_trans_b:=con_trans_b;
end if;
con_trans_b:=con_trans_b+1;
when others =>
fifo_pic_write_b_1<='0';
fifo_pic_write_b_2<='0';
fifo_pic_write_b_3<='0';
con_trans_b:=0;
if fifo_trans_num_buffer="00000000001" then
fifo_trans_aclr<='1';
trans_state<=trans_in;
else
trans_state<=trans_b;
end if;
end case;
end case;
end if;
end case;
r_ready_s<=r_ready;
sensor_last<=sensor;
fifo_trans_num_buffer<=fifo_trans_num;
fifo_pic_num_w_a_1_buffer<=fifo_pic_num_w_a_1;
fifo_pic_num_w_a_2_buffer<=fifo_pic_num_w_a_2;
fifo_pic_num_w_a_3_buffer<=fifo_pic_num_w_a_3;
fifo_pic_num_w_b_1_buffer<=fifo_pic_num_w_b_1;
fifo_pic_num_w_b_2_buffer<=fifo_pic_num_w_b_2;
fifo_pic_num_w_b_3_buffer<=fifo_pic_num_w_b_3;
end if;
end process;
CONTROL:process(clk_control)
variable con_step:integer range 0 to r20_con:=0;
variable con_control_work:integer range 0 to 15:=0;
begin
if clk_control'event and clk_control='1' then
blue_rqu_s<=blue_rqu;
case blue_rqu_s is
when '1' =>
pic_no<=blue_data;
blue_end<='1';
when others =>
blue_end<='0';
end case;
case lock_state is
---------------LOCK------------------
when lock =>
control_state<=control_state;
--------------CHIOCE-----------------
when others =>
if sensor_last='0' and sensor='1' then
con_step:=0;
con_control_work:=0;
fifo_pic_aclr_a_1<='1';
fifo_pic_aclr_a_2<='1';
fifo_pic_aclr_a_3<='1';
fifo_pic_aclr_b_1<='1';
fifo_pic_aclr_b_2<='1';
fifo_pic_aclr_b_3<='1';
control_state<=free;
else
case con_step is
when opic_con =>
con_step:=0;
con_control_work:=0;
fifo_pic_aclr_a_1<='1';
fifo_pic_aclr_a_2<='1';
fifo_pic_aclr_a_3<='1';
fifo_pic_aclr_b_1<='1';
fifo_pic_aclr_b_2<='1';
fifo_pic_aclr_b_3<='1';
if pic_num="0001000000000" then
pic_num<="0000000000001";
control_state<=free;
else
pic_num<=pic_num+1;
end if;
when others =>
con_step:=con_step+1;
case control_state is
---------------IDLE------------------
when free =>
fifo_pic_aclr_a_1<='0';
fifo_pic_aclr_a_2<='0';
fifo_pic_aclr_a_3<='0';
fifo_pic_aclr_b_1<='0';
fifo_pic_aclr_b_2<='0';
fifo_pic_aclr_b_3<='0';
if control_begin='1' then
control_state<=control_work;
else
control_state<=control_state;
end if;
---------------WORK------------------
when control_work =>
case con_control_work is
when 0 =>
if fifo_pic_num_r_a_1>0 then
fifo_choice<='0';
fifo_pic_read_a_1<='1';
fifo_pic_read_a_2<='1';
fifo_pic_read_a_3<='1';
else
fifo_choice<='1';
fifo_pic_read_b_1<='1';
fifo_pic_read_b_2<='1';
fifo_pic_read_b_3<='1';
end if;
data_buffer_a<=x"0000000000";
data_buffer_b<=x"0000000000";
data_buffer_c<=x"0000000000";
when 1 =>
en_row_a<='1';
con_control_work:=con_control_work+1;
when 2 =>
if fifo_choice='0' then
clk_pic_out_a_1<='1';
clk_pic_out_a_2<='1';
clk_pic_out_a_3<='1';
else
clk_pic_out_b_1<='1';
clk_pic_out_b_2<='1';
clk_pic_out_b_3<='1';
end if;
en_row_b<='1';
en_row_c<="11";
con_control_work:=con_control_work+1;
when 3 =>
en_row_a<='0';
en_row_b<='0';
en_row_c<="00";
if fifo_choice='0' then
clk_pic_out_a_1<='0';
clk_pic_out_a_2<='0';
clk_pic_out_a_3<='0';
else
clk_pic_out_b_1<='0';
clk_pic_out_b_2<='0';
clk_pic_out_b_3<='0';
end if;
con_control_work:=con_control_work+1;
when 4 =>
if fifo_choice='0' then
data_buffer_a<=data_pic_out_a_1;
data_buffer_b<=data_pic_out_a_2;
data_buffer_c<=data_pic_out_a_3;
else
data_buffer_a<=data_pic_out_b_1;
data_buffer_b<=data_pic_out_b_2;
data_buffer_c<=data_pic_out_b_3;
end if;
con_control_work:=con_control_work+1;
when 5 =>
if fifo_choice='0' then
clk_pic_out_a_1<='1';
clk_pic_out_a_2<='1';
clk_pic_out_a_3<='1';
else
clk_pic_out_b_1<='1';
clk_pic_out_b_2<='1';
clk_pic_out_b_3<='1';
end if;
en_col_a_1<='1';
en_col_b_1<='1';
en_col_c_1<='1';
con_control_work:=con_control_work+1;
when 6 =>
if fifo_choice='0' then
clk_pic_out_a_1<='0';
clk_pic_out_a_2<='0';
clk_pic_out_a_3<='0';
else
clk_pic_out_b_1<='0';
clk_pic_out_b_2<='0';
clk_pic_out_b_3<='0';
end if;
if fifo_choice='0' then
data_buffer_a<=data_pic_out_a_1;
data_buffer_b<=data_pic_out_a_2;
data_buffer_c<=data_pic_out_a_3;
else
data_buffer_a<=data_pic_out_b_1;
data_buffer_b<=data_pic_out_b_2;
data_buffer_c<=data_pic_out_b_3;
end if;
con_control_work:=con_control_work+1;
when 7 =>
if fifo_choice='0' then
clk_pic_out_a_1<='1';
clk_pic_out_a_2<='1';
clk_pic_out_a_3<='1';
else
clk_pic_out_b_1<='1';
clk_pic_out_b_2<='1';
clk_pic_out_b_3<='1';
end if;
en_col_a_2<='1';
en_col_b_2<='1';
en_col_c_2<='1';
con_control_work:=con_control_work+1;
when 8 =>
if fifo_choice='0' then
clk_pic_out_a_1<='0';
clk_pic_out_a_2<='0';
clk_pic_out_a_3<='0';
else
clk_pic_out_b_1<='0';
clk_pic_out_b_2<='0';
clk_pic_out_b_3<='0';
end if;
if fifo_choice='0' then
data_buffer_a<=data_pic_out_a_1;
data_buffer_b<=data_pic_out_a_2;
data_buffer_c<=data_pic_out_a_3;
else
data_buffer_a<=data_pic_out_b_1;
data_buffer_b<=data_pic_out_b_2;
data_buffer_c<=data_pic_out_b_3;
end if;
con_control_work:=con_control_work+1;
when 9 =>
en_col_a_3<='1';
en_col_b_3<='1';
en_col_c_3<='1';
con_control_work:=con_control_work+1;
when 10 =>
en_col_a_1<='0';
en_col_b_1<='0';
en_col_c_1<='0';
en_col_a_2<='0';
en_col_b_2<='0';
en_col_c_2<='0';
en_col_a_3<='0';
en_col_b_3<='0';
en_col_c_3<='0';
con_control_work:=con_control_work+1;
when 11 =>
data_buffer_b(39 downto 2)<=to_stdlogicvector(pic_row_ab);
if pic_row_c_h(37)='0' then
data_buffer_c(19 downto 1)<="0111111111111111111";
elsif pic_row_c_h(18)='0' then
data_buffer_c(19 downto 1)<="1111111111111111111";
else
data_buffer_c(19 downto 1)<=to_stdlogicvector(pic_row_c_h(18 downto 0));
end if;
if pic_row_c_l(0)='0' then
data_buffer_c(38 downto 20)<="1111111111111111110";
else
data_buffer_c(38 downto 20)<=to_stdlogicvector(pic_row_c_l(37 downto 19));
end if;
con_control_work:=con_control_work+1;
when 12 =>
en_row_a<='1';
con_control_work:=con_control_work+1;
when 13 =>
en_row_b<='1';
en_row_c<="11";
con_control_work:=con_control_work+1;
when 14 =>
en_col_a_1<='0';
en_col_b_1<='0';
en_col_c_1<='0';
en_col_a_2<='0';
en_col_b_2<='0';
en_col_c_2<='0';
en_col_a_3<='0';
en_col_b_3<='0';
en_col_c_3<='0';
en_row_a<='0';
en_row_b<='0';
en_row_c<="00";
con_control_work:=con_control_work+1;
when 15 =>
pic_row_ab<=pic_row_ab rol 1;
pic_row_c_h<=pic_row_c_h rol 1;
pic_row_c_l<=pic_row_c_l ror 1;
con_control_work:=0;
when others =>
con_control_work:=con_control_work+1;
end case;
when others =>
control_state<=control_work;
end case;
end case;
end if;
end case;
end if;
end process;
end ledx;
|
gpl-2.0
|
099b273ab084bdc6c7e50245ef1dbb1b
| 0.523331 | 2.722642 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/util/shift_register_nbits.vhd
| 1 | 1,469 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Shift_Register_n_bits
-- Module Name: Shift_Register_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Shift Register of size bits with no reset signal, that only registers
-- when ce equals to 1.
--
-- The circuits parameters
--
-- size :
--
-- The size of the shift register in bits.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shift_register_nbits is
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0);
data_out : out STD_LOGIC
);
end shift_register_nbits;
architecture Behavioral of shift_register_nbits is
signal internal_value : STD_LOGIC_VECTOR((size - 1) downto 0);
begin
process(clk, ce)
begin
if(clk'event and clk = '1')then
if(ce = '1') then
internal_value <= internal_value((size - 2) downto 0) & data_in;
else
null;
end if;
end if;
end process;
data_out <= internal_value(size - 1);
q <= internal_value;
end Behavioral;
|
bsd-2-clause
|
877e2fcd1b814b45cd23670a2f9baf00
| 0.589517 | 3.408353 | false | false | false | false |
dtysky/3D_Displayer_Controller
|
VHDL_PLANB/LED/LED.vhd
| 1 | 6,276 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity LED is
generic
(
constant cpd:integer:=2047 ------------count per one degree（inclk下）
);
port
(
inclk:in std_logic;
rst:in std_logic;
data_buffer_a:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_b:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_c:out std_logic_vector(39 downto 0):=x"0000000000";
en_row_a:out std_logic:='0';
en_row_b:out std_logic:='0';
en_row_c:out std_logic_vector(1 downto 0):="00"; --------分割为两个管脚，分配同一信号
en_col_a_1,en_col_a_2,en_col_a_3:out std_logic:='0';
en_col_b_1,en_col_b_2,en_col_b_3:out std_logic:='0';
en_col_c_1,en_col_c_2,en_col_c_3:out std_logic:='0';
control_begin:in std_logic:='0';
fifo_change:out std_logic:='0';
fifo_en_r:out std_logic;
fifo_data_1:in std_logic_vector(127 downto 0);
fifo_data_2:in std_logic_vector(127 downto 0);
fifo_data_3:in std_logic_vector(127 downto 0)
);
end entity;
architecture RTL of LED is
------------------State----------------
type states_c is (free,control_work);
signal control_state:states_c:=free;
signal fifo_change_s:std_logic:='0';
--------------Row of frame-------------
signal frame_row_ab:bit_vector(37 downto 0):="01111111111111111111111111111111111111";
signal frame_row_c_h:bit_vector(37 downto 0):="01111111111111111111111111111111111111";
signal frame_row_c_l:bit_vector(37 downto 0):="11111111111111111101111111111111111111";
procedure frame_change(
variable con_step:inout integer;
signal fifo_change:inout std_logic;
signal control_state:inout states_c
) is
begin
if con_step=cpd then
fifo_change<=not fifo_change;
control_state<=free;
con_step:=0;
else
con_step:=con_step+1;
end if;
end frame_change;
begin
fifo_change<=fifo_change_s;
MAIN:process(inclk,rst)
variable con_step:integer range 0 to cpd:=0;
variable con_control_work:integer range 0 to 63:=0;
variable con_total:integer range 0 to 63:=0;
begin
if rst='1' then
control_state<=free;
con_control_work:=0;
con_step:=0;
con_total:=0;
elsif rising_edge(inclk) then
case control_state is
---------------IDLE------------------
when free =>
con_control_work:=0;
con_step:=0;
con_total:=0;
if control_begin='1' then
control_state<=control_work;
else
control_state<=control_state;
end if;
---------------WORK------------------
when control_work =>
----------change a frame----------
frame_change(con_step,fifo_change_s,control_state);
if con_control_work=50 then
if con_total=37 then
null;
else
con_control_work:=0;
con_total:=con_total+1;
end if;
else
con_control_work:=con_control_work+1;
end if;
case con_control_work is
when 0 =>
data_buffer_a<=x"0000000000";
data_buffer_b<=x"0000000000";
data_buffer_c<=x"0000000000";
when 1 =>
en_col_a_1<='0';
en_col_b_1<='0';
en_col_c_1<='0';
en_col_a_2<='0';
en_col_b_2<='0';
en_col_c_2<='0';
en_col_a_3<='0';
en_col_b_3<='0';
en_col_c_3<='0';
when 2=>
en_col_a_1<='1';
en_col_b_1<='1';
en_col_c_1<='1';
when 3 =>
en_col_a_2<='1';
en_col_b_2<='1';
en_col_c_2<='1';
when 4 =>
en_col_a_3<='1';
en_col_b_3<='1';
en_col_c_3<='1';
when 5 =>
data_buffer_a<=x"FFFFFFFFFF";
when 6 =>
en_row_a<='0';
en_row_b<='0';
when 7 =>
en_row_a<='1';
en_row_b<='1';
when 8 =>
data_buffer_c<=x"FFFFFFFFFF";
when 9 =>
en_row_c<="00";
when 10 =>
en_row_c<="11";
when 11 =>
data_buffer_a<=x"0000000000";
data_buffer_c<=x"0000000000";
when 12 =>
fifo_en_r<='1';
when 13=>
fifo_en_r<='0';
when 14 =>
data_buffer_a(39 downto 2)<=to_stdlogicvector(frame_row_ab);
when 15 =>
en_row_a<='0';
en_row_b<='0';
when 16=>
en_row_a<='1';
en_row_b<='1';
when 17 =>
if frame_row_c_h(37)='0' then
data_buffer_c(19 downto 1)<="0111111111111111111";
elsif frame_row_c_h(18)='0' then
data_buffer_c(19 downto 1)<="1111111111111111111";
else
data_buffer_c(19 downto 1)<=to_stdlogicvector(frame_row_c_h(18 downto 0));
end if;
if frame_row_c_l(0)='0' then
data_buffer_c(38 downto 20)<="1111111111111111110";
else
data_buffer_c(38 downto 20)<=to_stdlogicvector(frame_row_c_l(37 downto 19));
end if;
when 18 =>
en_row_c<="00";
when 19 =>
en_row_c<="11";
when 20 =>
data_buffer_a<=fifo_data_1(119 downto 80);
when 21=>
data_buffer_b<=fifo_data_2(119 downto 80);
when 22 =>
data_buffer_c<=fifo_data_3(119 downto 80);
when 23=>
en_col_a_1<='0';
en_col_b_1<='0';
en_col_c_1<='0';
when 24 =>
en_col_a_1<='1';
en_col_b_1<='1';
en_col_c_1<='1';
when 25 =>
data_buffer_a<=fifo_data_1(79 downto 40);
when 26 =>
data_buffer_b<=fifo_data_2(79 downto 40);
when 27 =>
data_buffer_c<=fifo_data_3(79 downto 40);
when 28 =>
en_col_a_2<='0';
en_col_b_2<='0';
en_col_c_2<='0';
when 29 =>
en_col_a_2<='1';
en_col_b_2<='1';
en_col_c_2<='1';
when 30 =>
data_buffer_a<=fifo_data_1(39 downto 0);
when 31 =>
data_buffer_b<=fifo_data_2(39 downto 0);
when 32 =>
data_buffer_c<=fifo_data_3(39 downto 0);
when 33 =>
en_col_a_3<='0';
en_col_b_3<='0';
en_col_c_3<='0';
when 34 =>
en_col_a_3<='1';
en_col_b_3<='1';
en_col_c_3<='1';
when 35 =>
frame_row_ab<=frame_row_ab rol 1;
frame_row_c_h<=frame_row_c_h rol 1;
frame_row_c_l<=frame_row_c_l ror 1;
when others =>
null;
end case;
when others =>
control_state<=control_work;
end case;
end if;
end process;
end RTL;
|
gpl-2.0
|
883754863ab290ce170a55ce948328e4
| 0.536367 | 2.728147 | false | false | false | false |
pwuertz/digitizer2fw
|
src/rtl/adc_program.vhd
| 1 | 5,789 |
-------------------------------------------------------------------------------
-- ADS5403 ADC, serial programming
--
-- TODO: Read operation currently shifts in bits at falling edges
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity adc_program is
port (
-- application interface
clk_main: in std_logic;
start: in std_logic;
rd: in std_logic;
busy: out std_logic;
addr: in std_logic_vector(6 downto 0);
din: in std_logic_vector(15 downto 0);
dout: out std_logic_vector(15 downto 0);
-- adc interface
adc_sdenb: out std_logic;
adc_sdio: inout std_logic;
adc_sclk: out std_logic
);
end adc_program;
architecture adc_program_arch of adc_program is
-- state machine
type output_state_t is (s_output, s_deselect, s_done);
constant nbits: integer := 24;
constant nbits_addr: integer := 8;
type state_t is record
output_state: output_state_t;
rd: boolean;
clk_count: unsigned(3 downto 0);
bit_count: integer range 0 to nbits-1;
shift_reg: std_logic_vector(nbits-1 downto 0);
end record;
constant default_state: state_t := (
output_state => s_done,
rd => false,
clk_count => (others => '0'),
bit_count => 0,
shift_reg => (others => '0')
);
signal state: state_t := default_state;
signal next_state: state_t;
signal shift_bit: std_logic;
-- registered iob outputs
signal iob_adc_sdenb: std_logic := '1';
signal iob_adc_sdout: std_logic := '0';
signal iob_adc_sdin, iob_adc_sdin_from_iobuf: std_logic := '0';
signal iob_adc_sdhz: std_logic := '1';
signal iob_adc_sclk: std_logic := '0';
signal next_iob_adc_sdenb: std_logic;
signal next_iob_adc_sdout: std_logic;
signal next_iob_adc_sdhz: std_logic;
signal next_iob_adc_sclk: std_logic;
attribute IOB: string;
attribute IOB of iob_adc_sdenb: signal is "true";
attribute IOB of iob_adc_sdout: signal is "true";
attribute IOB of iob_adc_sdin: signal is "true";
attribute IOB of iob_adc_sdhz: signal is "true";
attribute IOB of iob_adc_sclk: signal is "true";
begin
busy <= '0' when state.output_state = s_done else '1';
dout <= state.shift_reg(15 downto 0);
adc_sdenb <= iob_adc_sdenb;
adc_sclk <= iob_adc_sclk;
adc_sdio_inst: IOBUF
generic map (DRIVE => 12, IOSTANDARD => "DEFAULT", SLEW => "SLOW")
port map (
I => iob_adc_sdout,
IO => adc_sdio,
O => iob_adc_sdin_from_iobuf,
T => iob_adc_sdhz
);
-- register in and outputs
sync_proc: process(clk_main)
begin
if rising_edge(clk_main) then
if (start = '1') then
state <= default_state;
state.output_state <= s_output;
state.rd <= (rd = '1');
state.shift_reg <= rd & addr & din;
else
state <= next_state;
iob_adc_sclk <= next_iob_adc_sclk;
iob_adc_sdenb <= next_iob_adc_sdenb;
iob_adc_sdout <= next_iob_adc_sdout;
iob_adc_sdin <= iob_adc_sdin_from_iobuf;
iob_adc_sdhz <= next_iob_adc_sdhz;
end if;
end if;
end process;
-- combinatorial logic / state transitions
comb_proc: process(state, iob_adc_sdin)
variable sclk_falling, sclk_rising: boolean;
type phase_t is (READ_PHASE, WRITE_PHASE);
variable phase: phase_t;
begin
-- default: keep state, deselect DAC
next_state <= state;
next_iob_adc_sdenb <= '1';
next_iob_adc_sdout <= '0';
next_iob_adc_sdhz <= '0';
next_iob_adc_sclk <= '0';
-- increment clock divide counter
if state.output_state /= s_done then
next_state.clk_count <= state.clk_count + 1;
end if;
sclk_rising := (state.clk_count = "0111");
sclk_falling := (state.clk_count = "1111");
-- determine if data is read or written
if state.rd and state.bit_count > (8-1) then
phase := READ_PHASE;
else
phase := WRITE_PHASE;
end if;
-- state machine
case state.output_state is
when s_output =>
-- control tristate iob
case phase is
when READ_PHASE => next_iob_adc_sdhz <= '1';
when WRITE_PHASE => next_iob_adc_sdhz <= '0';
end case;
-- generate clock signal from counter and output MSB of shift reg
next_iob_adc_sdenb <= '0';
next_iob_adc_sclk <= state.clk_count(state.clk_count'high);
next_iob_adc_sdout <= state.shift_reg(state.shift_reg'high);
-- for writing, shift bit out on falling edge
-- for reading, shift bit in on rising edge
if ((phase = WRITE_PHASE) and sclk_falling) or ((phase = READ_PHASE) and sclk_rising) then
next_state.shift_reg <= state.shift_reg(state.shift_reg'high-1 downto 0) & iob_adc_sdin;
next_state.bit_count <= state.bit_count + 1;
-- go to deselect state when all bits are written/read
if state.bit_count = (nbits-1) then
next_state.output_state <= s_deselect;
end if;
end if;
when s_deselect =>
-- wait one cycle in deselect
next_iob_adc_sdenb <= '1';
if sclk_falling then
next_state.output_state <= s_done;
end if;
when others =>
null;
end case;
end process;
end adc_program_arch;
|
gpl-3.0
|
f6410949a0bd8d11f709ce5199448116
| 0.576192 | 3.633396 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/UART/transmit.vhd
| 1 | 1,843 |
-----------------------------------------------
-- Transmit State Machine --
-----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity transmit is
generic (
NDBits : natural := 8
);
port (
CLK : in std_logic;
RST : in std_logic;
Tx : out std_logic;
Din : in std_logic_vector (NDBits-1 downto 0);
TxBusy : out std_logic;
TopTx : in std_logic;
StartTx : in std_logic
);
end;
architecture arch of transmit is
signal Tx_Reg : std_logic_vector (NDBits downto 0);
type State_Type is (Idle, Load_Tx, Shift_Tx, Stop_Tx);
signal TxFsm : State_Type;
signal RegDin : std_logic_vector (NDBits-1 downto 0);
signal TxBitCnt : natural range 0 to 15;
begin
TX <= Tx_Reg(0);
Tx_FSM: process (RST, CLK)
begin
if RST='1' then
Tx_Reg <= (others => '1');
TxBitCnt <= 0;
TxFSM <= idle;
TxBusy <= '0';
RegDin <= (others=>'0');
elsif rising_edge(CLK) then
TxBusy <= '1'; -- except when explicitly '0'
case TxFSM is
when Idle =>
if StartTx='1' then
-- latch the input data immediately.
RegDin <= Din;
TxBusy <= '1';
TxFSM <= Load_Tx;
else
TxBusy <= '0';
end if;
when Load_Tx =>
if TopTx='1' then
TxFSM <= Shift_Tx;
TxBitCnt <= (NDBits + 1); -- start + data
Tx_reg <= RegDin & '0';
end if;
when Shift_Tx =>
if TopTx='1' then
TxBitCnt <= TxBitCnt - 1;
Tx_reg <= '1' & Tx_reg (Tx_reg'high downto 1);
if TxBitCnt=1 then
TxFSM <= Stop_Tx;
end if;
end if;
when Stop_Tx =>
if TopTx='1' then
TxFSM <= Idle;
end if;
when others =>
TxFSM <= Idle;
end case;
end if;
end process;
end architecture;
|
gpl-3.0
|
c24364c210b276695ad4f0c0a0f02eda
| 0.517092 | 3.308797 | false | false | false | false |
pwuertz/digitizer2fw
|
src/rtl/maxfinder_base.vhd
| 1 | 11,945 |
-------------------------------------------------------------------------------
-- Maximum finder, base module
--
-- Finds maxima between two samples by checking for zero crossing of finite
-- differences.
--
-- The window length N_WINDOW_LENGTH defines the number of incoming samples per
-- clock cycle, each sample being a signed number with a size of N_SAMPLE_BITS.
-- It is possible to search for multiple maxima per window by splitting the
-- initial window length into N_OUTPUTS segments.
--
-- | sample0 sample1 sample2 sample3 | sample4 sample5 sample6 sample7 |
-- | maximum find 0 | maximum find 1 |
--
-- 'samples': N_WINDOW_LENGTH signed samples of N_SAMPLE_BITS, first sample at 0
-- 'threshold': Signed number of N_SAMPLE_BITS bits
-- 'max_found': N_OUTPUTS bits of '1' if a maximum was found in the n'th search
-- segment, else '0'
-- 'max_pos': N_OUTPUTS unsigned values of N_POS_BITS, specifying the position
-- left of a valid maximum within the n'th segment
-- (value for first segment at 0)
-- 'max_adiff0/1': N_OUTPUTS unsigned values of N_SAMPLE_BITS, specifying the
-- absolute values of the finite differences left and right of
-- a maximum within the n'th segment
-- (values for first segment at 0)
-- 'max_sample0/1': N_OUTPUTS signed values of N_SAMPLE_BITS, specifying the
-- original sample values left and right of
-- a maximum within the n'th segment
-- (values for first segment at 0)
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.maxfinder_pkg.all;
entity maxfinder_base is
generic(
N_WINDOW_LENGTH: natural;
N_OUTPUTS: natural := 1;
N_SAMPLE_BITS: natural := 12;
SYNC_STAGE1: boolean := FALSE;
SYNC_STAGE2: boolean := FALSE;
SYNC_STAGE3: boolean := TRUE
);
port (
clk: in std_logic;
samples: in std_logic_vector(N_WINDOW_LENGTH*N_SAMPLE_BITS-1 downto 0);
threshold: in std_logic_vector(N_SAMPLE_BITS-1 downto 0);
max_found: out std_logic_vector(N_OUTPUTS-1 downto 0);
max_pos: out std_logic_vector(N_OUTPUTS*log2ceil(N_WINDOW_LENGTH/N_OUTPUTS)-1 downto 0);
max_adiff0: out std_logic_vector(N_OUTPUTS*N_SAMPLE_BITS-1 downto 0);
max_adiff1: out std_logic_vector(N_OUTPUTS*N_SAMPLE_BITS-1 downto 0);
max_sample0: out std_logic_vector(N_OUTPUTS*N_SAMPLE_BITS-1 downto 0);
max_sample1: out std_logic_vector(N_OUTPUTS*N_SAMPLE_BITS-1 downto 0)
);
end maxfinder_base;
architecture maxfinder_base_arch of maxfinder_base is
constant N_POS_PER_OUTPUT: natural := N_WINDOW_LENGTH / N_OUTPUTS;
constant N_POS_BITS: natural := log2ceil(N_WINDOW_LENGTH/N_OUTPUTS);
type samples_t is array(natural range <>) of signed(N_SAMPLE_BITS-1 downto 0);
type samples_diff_t is array(natural range <>) of signed(N_SAMPLE_BITS+1-1 downto 0);
type samples_adiff_t is array(natural range <>) of unsigned(N_SAMPLE_BITS-1 downto 0);
type pos_arr_t is array(natural range <>) of unsigned(N_POS_BITS-1 downto 0);
-- stage0
signal s0_samples_in: samples_t(0 to N_WINDOW_LENGTH+4-1) := (others => (others => '0'));
-- stage1
signal s1_samples_in: samples_t(0 to N_WINDOW_LENGTH+1-1) := (others => (others => '0'));
signal s1_samples_diff: samples_diff_t(0 to N_WINDOW_LENGTH+2-1) := (others => (others => '0'));
signal s1_above_threshold: std_logic_vector(N_WINDOW_LENGTH-1 downto 0) := (others => '0');
procedure stage1(signal s0_samples_in: in samples_t;
signal threshold: in std_logic_vector;
signal s1_samples_in: out samples_t;
signal s1_samples_diff: out samples_diff_t;
signal s1_above_threshold: out std_logic_vector) is
begin
-- calculate finite differences
for i in 0 to N_WINDOW_LENGTH+2-1 loop
s1_samples_diff(i) <= resize(s0_samples_in(i+2), N_SAMPLE_BITS+1) - resize(s0_samples_in(i), N_SAMPLE_BITS+1);
end loop;
-- check if samples are above threshold
for i in 0 to N_WINDOW_LENGTH-1 loop
if s0_samples_in(i+2) > signed(threshold) then
s1_above_threshold(i) <= '1';
else
s1_above_threshold(i) <= '0';
end if;
end loop;
-- forward samples_in to next stage
s1_samples_in <= s0_samples_in(2 to s0_samples_in'high-1);
end stage1;
-- stage2
signal s2_samples_in: samples_t(0 to N_WINDOW_LENGTH+1-1);
signal s2_samples_diff: samples_diff_t(0 to N_WINDOW_LENGTH+1-1) := (others => (others => '0'));
signal s2_max_criterion: std_logic_vector(N_WINDOW_LENGTH-1 downto 0) := (others => '0');
procedure stage2(signal s1_samples_in: in samples_t;
signal s1_samples_diff: in samples_diff_t;
signal s1_above_threshold: in std_logic_vector;
signal s2_samples_diff: out samples_diff_t;
signal s2_samples_in: out samples_t;
signal s2_max_criterion: out std_logic_vector) is
variable s_left, s_center, s_right, s_valid, s_max: boolean;
begin
-- check criterion for maximum between i and i+1
for i in 0 to N_WINDOW_LENGTH-1 loop
s_left := s1_samples_diff(i+0) >= 0;
s_center := s1_samples_diff(i+1) >= 0;
s_right := s1_samples_diff(i+2) < 0;
s_valid := s1_above_threshold(i) = '1';
s_max := s_left and s_center and s_right and s_valid;
if s_max then
s2_max_criterion(i) <= '1';
else
s2_max_criterion(i) <= '0';
end if;
end loop;
-- forward samples_diff to next stage
s2_samples_diff <= s1_samples_diff(1 to s1_samples_diff'high);
-- forward samples_in to next stage
s2_samples_in <= s1_samples_in;
end stage2;
-- stage3
signal s3_found: std_logic_vector(N_OUTPUTS-1 downto 0);
signal s3_pos: pos_arr_t(N_OUTPUTS-1 downto 0);
signal s3_adiff0: samples_adiff_t(N_OUTPUTS-1 downto 0);
signal s3_adiff1: samples_adiff_t(N_OUTPUTS-1 downto 0);
signal s3_sample0: samples_t(N_OUTPUTS-1 downto 0);
signal s3_sample1: samples_t(N_OUTPUTS-1 downto 0);
procedure stage3(signal s2_samples_diff: in samples_diff_t;
signal s2_samples_in: in samples_t;
signal s2_max_criterion: in std_logic_vector;
signal s3_found: out std_logic_vector;
signal s3_pos: out pos_arr_t;
signal s3_adiff0: out samples_adiff_t;
signal s3_adiff1: out samples_adiff_t;
signal s3_sample0: out samples_t;
signal s3_sample1: out samples_t) is
variable i: natural;
variable diff1_positive: signed(N_SAMPLE_BITS downto 0);
begin
-- for each output..
for i_o in 0 to N_OUTPUTS-1 loop
-- default to not valid / don't care
s3_found(i_o) <= '0';
s3_pos(i_o) <= (others => '-');
s3_adiff0(i_o) <= (others => '-');
s3_adiff1(i_o) <= (others => '-');
s3_sample0(i_o) <= (others => '-');
s3_sample1(i_o) <= (others => '-');
-- check all positions within output for maxima
-- store the last one that is valid
for i_p in 0 to N_POS_PER_OUTPUT-1 loop
i := i_o*N_POS_PER_OUTPUT + i_p;
if s2_max_criterion(i) = '1' then
s3_found(i_o) <= '1';
s3_pos(i_o) <= to_unsigned(i_p, N_POS_BITS);
s3_adiff0(i_o) <= unsigned(s2_samples_diff(i)(N_SAMPLE_BITS-1 downto 0));
diff1_positive := -s2_samples_diff(i+1);
s3_adiff1(i_o) <= unsigned(diff1_positive(N_SAMPLE_BITS-1 downto 0));
s3_sample0(i_o) <= s2_samples_in(i);
s3_sample1(i_o) <= s2_samples_in(i+1);
end if;
end loop;
end loop;
end stage3;
begin
-------------------------------------------------------------------------------
stage0: process(clk)
begin
if rising_edge(clk) then
-- shift buffer
s0_samples_in(0 to 3) <= s0_samples_in(s0_samples_in'high-3 to s0_samples_in'high);
-- add new samples at the end
for i in 0 to N_WINDOW_LENGTH-1 loop
s0_samples_in(4+i) <= signed(samples((i+1)*N_SAMPLE_BITS-1 downto i*N_SAMPLE_BITS));
end loop;
end if;
end process;
-------------------------------------------------------------------------------
GEN_SYNC_STAGE1: if SYNC_STAGE1 generate
process(clk)
begin
if rising_edge(clk) then
stage1(s0_samples_in, threshold,
s1_samples_in, s1_samples_diff, s1_above_threshold);
end if;
end process;
end generate GEN_SYNC_STAGE1;
GEN_ASYNC_STAGE1: if not SYNC_STAGE1 generate
process(s0_samples_in, threshold, s1_samples_in, s1_samples_diff, s1_above_threshold)
begin
stage1(s0_samples_in, threshold,
s1_samples_in, s1_samples_diff, s1_above_threshold);
end process;
end generate GEN_ASYNC_STAGE1;
-------------------------------------------------------------------------------
GEN_SYNC_STAGE2: if SYNC_STAGE2 generate
process(clk)
begin
if rising_edge(clk) then
stage2(s1_samples_in, s1_samples_diff, s1_above_threshold,
s2_samples_diff, s2_samples_in, s2_max_criterion);
end if;
end process;
end generate GEN_SYNC_STAGE2;
GEN_ASYNC_STAGE2: if not SYNC_STAGE2 generate
process(s1_samples_in, s1_samples_diff, s1_above_threshold, s2_samples_diff, s2_samples_in, s2_max_criterion)
begin
stage2(s1_samples_in, s1_samples_diff, s1_above_threshold,
s2_samples_diff, s2_samples_in, s2_max_criterion);
end process;
end generate GEN_ASYNC_STAGE2;
-------------------------------------------------------------------------------
GEN_SYNC_STAGE3: if SYNC_STAGE3 generate
process(clk)
begin
if rising_edge(clk) then
stage3(s2_samples_diff, s2_samples_in, s2_max_criterion,
s3_found, s3_pos, s3_adiff0, s3_adiff1, s3_sample0, s3_sample1);
end if;
end process;
end generate GEN_SYNC_STAGE3;
GEN_ASYNC_STAGE3: if not SYNC_STAGE3 generate
process(s2_samples_diff, s2_samples_in, s2_max_criterion)
begin
stage3(s2_samples_diff, s2_samples_in, s2_max_criterion,
s3_found, s3_pos, s3_adiff0, s3_adiff1, s3_sample0, s3_sample1);
end process;
end generate GEN_ASYNC_STAGE3;
-------------------------------------------------------------------------------
map_s3_to_out: process(s3_found, s3_pos, s3_adiff0, s3_adiff1, s3_sample0, s3_sample1)
begin
for i_o in 0 to N_OUTPUTS-1 loop
-- register the output segment within final output vector
max_found(i_o) <= s3_found(i_o);
max_pos((i_o+1)*N_POS_BITS-1 downto i_o*N_POS_BITS) <= std_logic_vector(s3_pos(i_o));
max_adiff0((i_o+1)*N_SAMPLE_BITS-1 downto i_o*N_SAMPLE_BITS) <= std_logic_vector(s3_adiff0(i_o));
max_adiff1((i_o+1)*N_SAMPLE_BITS-1 downto i_o*N_SAMPLE_BITS) <= std_logic_vector(s3_adiff1(i_o));
max_sample0((i_o+1)*N_SAMPLE_BITS-1 downto i_o*N_SAMPLE_BITS) <= std_logic_vector(s3_sample0(i_o));
max_sample1((i_o+1)*N_SAMPLE_BITS-1 downto i_o*N_SAMPLE_BITS) <= std_logic_vector(s3_sample1(i_o));
end loop;
end process;
end maxfinder_base_arch;
|
gpl-3.0
|
7ac488567678d30ffb25c198f7da6dc0
| 0.581547 | 3.320545 | false | false | false | false |
rajvinjamuri/ECE385_VHDL
|
reg_11.vhd
| 1 | 2,105 |
---------------------------------------------------------------------------
-- reg_11.vhd --
-- Raj Vinjamuri --
-- 3-13 --
-- --
-- Purpose/Description: --
-- an 11-bit register unit with parallel-load and serial-in/out --
-- --
-- based on 4-bit register given by UIUC --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
-- --
-- --
-- Updates: --
-- --
-- >3.10: added appropriate number of zeros to 'reset' --
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg_11 is
Port ( Shift_In, Load, Shift_En, Clk, Reset : in std_logic;
D : in std_logic_vector(10 downto 0);
Shift_Out : out std_logic;
Data_Out : out std_logic_vector(10 downto 0)); --added range
end reg_11;
architecture Behavioral of reg_11 is
signal reg_value: std_logic_vector(10 downto 0);
begin
operate_reg: process(Load, Shift_En, Clk, Shift_In, Reset)
begin
if (rising_edge(Clk)) then
if (Shift_En = '1')then
reg_value <= Shift_In & reg_value (10 downto 1);
-- operator "&" concatenates two bit-fields
elsif (Load = '1') then
reg_value <= D;
elsif (Reset = '1') then
reg_value <= "00000000000";
else
reg_value <= reg_value;
end if;
end if;
end process;
Data_Out <= reg_value;
Shift_Out <=reg_value(0);
end Behavioral;
|
mit
|
b9bce6b114b652f60a3cd71f55ed43dc
| 0.380998 | 4.827982 | false | false | false | false |
Ricky-Gong/LegoCar
|
DE0-Nano/PWM/pwm_gen.vhd
| 4 | 4,352 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--!needs an input as level counter from the avalon reg to form the pwm it decides the duty cycle
--!needs an period counter number it decides the frequency
--!for dead zone, the level counter should has upper lower limit
--!flow of control: set the duty cycle 1 and 2, set the period of pwm, then
--enable the module by asserting the saw_en signal to high and keep it
entity pwm_gen is
-- generic (
-- G_WIDTH : integer:= 32;
-- G_reset_polarity : std_logic := '1' -- active high reset
-- );
port(
csi_I_clk: in std_logic;
csi_I_rst: in std_logic;
--!interface to Avalon
avs_address: in std_logic_vector(2 downto 0);
avs_write: in std_logic;
avs_I_cs: in std_logic;
avs_I_wr_data: in std_logic_vector(31 downto 0);
coe_O_pwm1: out std_logic;
coe_O_pwm2: out std_logic
-- I_saw_en : in std_logic;
-- I_period: in std_logic_vector(G_WIDTH-1 downto 0);
-- I_duty1: in std_logic_vector(G_WIDTH-1 downto 0);
-- I_duty2: in std_logic_vector(G_WIDTH-1 downto 0)
);
end pwm_gen;
architecture A_rtl of pwm_gen is
signal S_saw_cnt : unsigned(31 downto 0); --!saw wave gen counter
signal S_period : unsigned(31 downto 0) ; --!period of signal
signal S_duty1,S_duty2 : unsigned(31 downto 0) ; --!duty cycle
signal S_phase1,S_phase2: unsigned(31 downto 0);--!phase register
signal S_saw_en1,S_saw_en2 : std_logic ; --! enable signal for generation
begin -- A_rtl
--!triangle waveform gen
process(csi_I_clk,csi_I_rst,S_saw_cnt,S_saw_en1,S_saw_en2)
begin
if rising_edge(csi_I_clk) then
if csi_I_rst='0' then
S_saw_cnt<=(others=>'0');
else
if S_saw_en1='1' or S_saw_en2='1' then
if S_saw_cnt=S_period then
S_saw_cnt<=(others=>'0');
else
S_saw_cnt<=S_saw_cnt+1;
end if;
end if;
end if;
end if;
end process;
--!comparator duty1 and duty2 should not be the same as the deadzone exits
coe_O_pwm1<='1' when (S_saw_cnt>S_phase1 and S_saw_cnt<S_phase1+S_duty1 and S_saw_en1='1') else
'0' ;
coe_O_pwm2<='1' when (S_saw_cnt<S_phase2+S_duty2 and S_saw_cnt>S_phase2 and S_saw_en2='1') else
'0' ;
--!register
-- process(csi_I_clk,csi_I_rst,I_period)
-- begin
-- if rising_edge(csi_I_clk) then
-- if csi_I_rst=G_reset_polarity then
-- S_period<=(others=>'0');
-- else
-- S_period<=I_period;
-- end if;
-- end if;
-- end process;
-- process(csi_I_clk,csi_I_rst,I_duty1)
-- begin
-- if rising_edge(csi_I_clk) then
-- if csi_I_rst=G_reset_polarity then
-- S_duty1<=(others=>'0');
-- else
-- S_duty1<=I_duty1;
-- end if;
-- end if;
-- end process;
-- process(csi_I_clk,csi_I_rst,I_duty2)
-- begin
-- if rising_edge(csi_I_clk) then
-- if csi_I_rst=G_reset_polarity then
-- S_duty2<=(others=>'0');
-- else
-- S_duty2<=I_duty2;
-- end if;
-- end if;
-- end process;
-- process(csi_I_clk,csi_I_rst,I_saw_en)
-- begin
-- if rising_edge(csi_I_clk) then
-- if csi_I_rst=G_reset_polarity then
-- S_saw_en<='0';
-- else
-- S_saw_en<=I_saw_en;
-- end if;
-- end if;
-- end process;
--avalon interface
process(csi_I_clk,csi_I_rst,avs_address,avs_write,avs_I_cs,avs_I_wr_data)
begin
if rising_edge(csi_I_clk) then
if csi_I_rst='0' then
S_saw_en1<='0';
S_saw_en2<='0';
S_period<=(others=>'0');
S_duty1<=(others=>'0');
S_duty2<=(others=>'0');
S_phase1<=(others=>'0');
S_phase2<=(others=>'0');
else
if avs_write='1' and avs_I_cs='1' then
case avs_address is
when "000"=> --enable register
S_saw_en1<=avs_I_wr_data(0);
S_saw_en2<=avs_I_wr_data(1);
when "001"=> --period register
S_period<=unsigned(avs_I_wr_data);
when "010"=> --duty1 register
S_duty1<=unsigned(avs_I_wr_data);
when "011"=> --duty2 register
S_duty2<=unsigned(avs_I_wr_data);
when "100"=> --phase register
S_phase1<=unsigned(avs_I_wr_data);
when "101"=>
S_phase2<=unsigned(avs_I_wr_data);
when others=> null;
end case;
end if;
end if;
end if;
end process;
end A_rtl;
|
gpl-2.0
|
fef64939183d198fa2031a2678788293
| 0.579504 | 2.835179 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/decoBCD/decoBCD_tb.vhd
| 1 | 1,583 |
library ieee;
use ieee.std_logic_1164.all;
entity decoBCD_tb is
end;
architecture decoBCD_tb_func of decoBCD_tb is
--Contador
signal rst_in: std_logic:='1';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
--Conexiones
signal counter_to_deco: std_logic_vector(3 downto 0) := (others => '0');
--Deco
signal anod_out: std_logic:='1';
signal n_out: std_logic_vector(7 downto 0) := (others => '0');
signal c_out: std_logic:='0';
component contBCD is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
s: out std_logic_vector(3 downto 0);
co: out std_logic
);
end component;
component decoBCD is
port(
ena: in std_logic; --Estara conectado al anodo del BCD para habilitarlo o no
count: in std_logic_vector(3 downto 0); --Bits del contador
a: out std_logic;
b: out std_logic;
c: out std_logic;
d: out std_logic;
e: out std_logic;
f: out std_logic;
g: out std_logic;
dp: out std_logic;
anod: out std_logic
);
end component;
begin
clk_in <= not(clk_in) after 20 ns;
rst_in <= '0' after 50 ns;
enable_in <= '1' after 60 ns;
contadorBCDMap: contBCD port map(
clk => clk_in,
rst => rst_in,
ena => enable_in,
s => counter_to_deco,
co => c_out
);
decoBCDMap: decoBCD port map(
a => n_out(7),
b => n_out(6),
c => n_out(5),
d => n_out(4),
e => n_out(3),
f => n_out(2),
g => n_out(1),
dp => n_out(0),
ena => enable_in,
count => counter_to_deco
);
end architecture;
|
gpl-3.0
|
4d31b6c0f738a27bcf30666070a1d03f
| 0.57928 | 2.669477 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/pipeline_polynomial_calc_v4.vhd
| 1 | 4,857 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Pipeline_Polynomial_Calc_v4
-- Module Name: Pipeline_Polynomial_Calc_v4
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st and 3rd step in Goppa Code Decoding.
--
-- This circuit is to be used inside polynomial_syndrome_computing_n to evaluate polynomials
-- or generate the syndrome.
-- This circuit is the essential for 1 pipeline, therefor all stages are composed in here.
-- For more than 1 pipeline, only in polynomial_syndrome_computing_n with the shared components
-- for all pipelines.
--
-- For the computation this circuit applies the Horner scheme, where at each stage
-- an accumulator is multiplied by respective x and then added accumulated with coefficient.
-- In Horner scheme algorithm, it begin from the most significative coefficient until reaches
-- lesser significative coefficient.
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- size :
--
-- The number of stages the pipeline has. More stages means more values of value_polynomial
-- are tested at once.
--
-- Dependencies:
-- VHDL-93
--
-- stage_polynomial_calc_v4 Rev 1.0
-- register_nbits Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pipeline_polynomial_calc_v4 is
Generic (
gf_2_m : integer range 1 to 20;
size : integer
);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((((gf_2_m)*size) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
reg_x_rst : in STD_LOGIC_VECTOR((size - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((((gf_2_m)*size) - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end pipeline_polynomial_calc_v4;
architecture Behavioral of pipeline_polynomial_calc_v4 is
component stage_polynomial_calc_v4
Generic(gf_2_m : integer range 1 to 20 := 11);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial_coefficient : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component register_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
type array_std_logic_vector is array(integer range <>) of STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal acc_d : array_std_logic_vector((size) downto 0);
signal acc_q : array_std_logic_vector((size) downto 0);
signal x_d : array_std_logic_vector((size) downto 0);
signal x_q : array_std_logic_vector((size - 1) downto 0);
constant reg_x_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(1, gf_2_m));
begin
x_d(0) <= value_x;
acc_d(0) <= value_acc;
pipeline : for I in 0 to (size - 1) generate
reg_x_I : register_rst_nbits
Generic Map(size => gf_2_m)
Port Map(
d => x_d(I),
clk => clk,
ce => '1',
rst => reg_x_rst(I),
rst_value => reg_x_rst_value,
q => x_q(I)
);
reg_acc_I : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => acc_d(I),
clk => clk,
ce => '1',
q => acc_q(I)
);
stage_I : stage_polynomial_calc_v4
Generic Map(gf_2_m => gf_2_m)
Port Map (
value_x => x_q(I),
value_polynomial_coefficient => value_polynomial(((gf_2_m)*(I+1) - 1) downto ((gf_2_m)*(I))),
mode_polynomial_syndrome => mode_polynomial_syndrome,
value_acc => acc_q(I),
new_value_syndrome => new_value_syndrome(((gf_2_m)*(I+1) - 1) downto ((gf_2_m)*(I))),
new_value_acc => acc_d(I+1)
);
x_d(I+1) <= x_q(I);
end generate;
reg_acc_last : register_nbits
Generic Map(size => gf_2_m)
Port Map(
d => acc_d(size),
clk => clk,
ce => '1',
q => acc_q(size)
);
new_value_acc <= acc_q(size);
end Behavioral;
|
bsd-2-clause
|
9402f612fdc69505dd4a35f7e511c1bd
| 0.640107 | 2.922383 | false | false | false | false |
rajvinjamuri/ECE385_VHDL
|
random_gen.vhd
| 1 | 1,777 |
---------------------------------------------------------------------------
-- random_gen.vhd --
-- Raj Vinjamuri --
-- 3-13 --
-- --
-- Purpose/Description: --
-- generates bits based on a counter from the clock --
-- acts as pseudo-random seed --
-- --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
-- --
---------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
----------------------------------------------------
entity random_gen is
port( Clk, toggle, reset: in std_logic;
seed: out std_logic_vector(17 downto 0);
seedLED: out std_logic_vector(17 downto 0));
end random_gen;
----------------------------------------------------
architecture behavioral of random_gen is
signal Pre_Q: std_logic_vector(35 downto 0);
begin
count: process(Clk)
begin
if (reset = '1') then
Pre_Q <= "000000000000000000000000000000000000"; --36 zeros
elsif (Clk='1' and Clk'event) then
Pre_Q <= Pre_Q + 1;
end if;
end process;
setLED: process(toggle)
begin
if (toggle = '1') then
seedLED <= Pre_Q(35 downto 18); --use a switch to see the seed or not
else seedLED <= "000000000000000000"; --18 zeros
end if;
end process;
-- concurrent assignment statement
seed <= Pre_Q(35 downto 18);
end behavioral;
-----------------------------------------------------
|
mit
|
891ac571ad96a249964b23d715e947ab
| 0.409116 | 4.688654 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/UART/uart.vhd
| 1 | 1,609 |
-----------------------------------------------
-- UART core --
-----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.uart_comps.all;
entity uart is
generic (
F : natural := 50000; -- Device clock frequency [KHz].
min_baud : natural := 1200;
num_data_bits : natural := 8
);
port (
Rx : in std_logic;
Tx : out std_logic;
Din : in std_logic_vector(7 downto 0);
StartTx : in std_logic;
TxBusy : out std_logic;
Dout : out std_logic_vector(7 downto 0);
RxRdy : out std_logic;
RxErr : out std_logic;
Divisor : in std_logic_vector;
clk : in std_logic;
rst : in std_logic
);
end;
architecture arch of uart is
signal top16 : std_logic;
signal toprx : std_logic;
signal toptx : std_logic;
signal Sig_ClrDiv : std_logic;
begin
reception_unit: receive
generic map (
NDBits => num_data_bits
)
port map (
CLK => clk,
RST => rst,
Rx => Rx,
Dout => Dout,
RxErr => RxErr,
RxRdy => RxRdy,
ClrDiv => Sig_ClrDiv,
Top16 => top16,
TopRx => toprx
);
transmission_unit: transmit
generic map (
NDBits => num_data_bits
)
port map (
CLK => clk,
RST => rst,
Tx => Tx,
Din => Din,
TxBusy => TxBusy,
TopTx => toptx,
StartTx => StartTx
);
timings_unit: timing
generic map (
F => F,
min_baud => min_baud
)
port map (
CLK => clk,
RST => rst,
divisor => Divisor,
ClrDiv => Sig_ClrDiv,
Top16 => top16,
TopTx => toptx,
TopRx => toprx
);
end;
|
gpl-3.0
|
3f67de4214163cbe2d2fa433afa31fa0
| 0.539466 | 2.759863 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/controller_syndrome_calculator_1.vhd
| 1 | 9,538 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Syndrome_Calculator_1
-- Module Name: Controller_Syndrome_Calculator_1
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st step in Goppa Code Decoding.
--
-- This circuit is the state machine that controls the syndrome_calculator_1
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_syndrome_calculator_1 is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_ctr_codeword_q : in STD_LOGIC;
limit_ctr_syndrome_q : in STD_LOGIC;
reg_first_syndrome_q : in STD_LOGIC_VECTOR(0 downto 0);
reg_codeword_q : in STD_LOGIC_VECTOR(0 downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
reg_L_ce : out STD_LOGIC;
square_h : out STD_LOGIC;
reg_h_ce : out STD_LOGIC;
sel_reg_h : out STD_LOGIC;
reg_syndrome_ce : out STD_LOGIC;
reg_syndrome_rst : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_first_syndrome_ce : out STD_LOGIC;
reg_first_syndrome_rst : out STD_LOGIC;
ctr_syndrome_ce : out STD_LOGIC;
ctr_syndrome_rst : out STD_LOGIC;
ctr_codeword_ce : out STD_LOGIC;
ctr_codeword_rst : out STD_LOGIC
);
end controller_syndrome_calculator_1;
architecture Behavioral of controller_syndrome_calculator_1 is
type State is (reset, load_counters, prepare_values, load_values, jump_codeword, prepare_synd, load_synd, store_synd, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, limit_ctr_codeword_q, limit_ctr_syndrome_q, reg_first_syndrome_q, reg_codeword_q)
begin
case (actual_state) is
when reset =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '0';
sel_reg_h <= '0';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '1';
when load_counters =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '0';
sel_reg_h <= '0';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '1';
when prepare_values =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '0';
square_h <= '0';
reg_h_ce <= '0';
sel_reg_h <= '0';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
when load_values =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '1';
square_h <= '0';
reg_h_ce <= '1';
sel_reg_h <= '0';
reg_syndrome_ce <= '1';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '1';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
when jump_codeword =>
if(reg_codeword_q(0) = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '1';
reg_h_ce <= '1';
sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
elsif(limit_ctr_codeword_q = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '1';
reg_h_ce <= '1';
sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '1';
reg_h_ce <= '1';
sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '1';
ctr_codeword_rst <= '0';
end if;
when prepare_synd =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '0';
sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
when load_synd =>
if(reg_first_syndrome_q(0) = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '0';
sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '0';
sel_reg_h <= '1';
reg_syndrome_ce <= '1';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
end if;
when store_synd =>
if(limit_ctr_syndrome_q = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '1';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '1';
sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '1';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '1';
ctr_codeword_rst <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '1';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '1';
sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '1';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
end if;
when final =>
syndrome_finalized <= '1';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '0';
sel_reg_h <= '0';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '1';
when others =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '0';
sel_reg_h <= '0';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '1';
end case;
end process;
NewState: process (actual_state, limit_ctr_codeword_q, limit_ctr_syndrome_q, reg_first_syndrome_q, reg_codeword_q)
begin
case (actual_state) is
when reset =>
next_state <= load_counters;
when load_counters =>
next_state <= prepare_values;
when prepare_values =>
next_state <= load_values;
when load_values =>
next_state <= jump_codeword;
when jump_codeword =>
if(reg_codeword_q(0) = '1') then
next_state <= prepare_synd;
elsif(limit_ctr_codeword_q = '1') then
next_state <= final;
else
next_state <= prepare_values;
end if;
when prepare_synd =>
next_state <= load_synd;
when load_synd =>
next_state <= store_synd;
when store_synd =>
if(limit_ctr_syndrome_q = '1') then
if(limit_ctr_codeword_q = '1') then
next_state <= final;
else
next_state <= prepare_values;
end if;
else
next_state <= prepare_synd;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
11bb77bd3785562cf722846b49952c8c
| 0.557874 | 2.69055 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/bcd_controller/anod_enabler_decoder.vhd
| 2 | 818 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity anod_enabler_decoder is
port(
binary_in: in std_logic_vector(1 downto 0); --"2 bit vector to switch between the 4 possible anod values"
code_out: out std_logic_vector(3 downto 0) --4 bit output to switch between anod
);
end;
architecture anod_enabler_decoder_arq of anod_enabler_decoder is
begin
process(binary_in)
begin
--Set all values as deactivated
code_out <= (others => not('0'));
CHECK: case to_integer(unsigned(binary_in)) is
when 0 =>
code_out(0) <= not('1');
when 1 =>
code_out(1) <= not('1');
when 2 =>
code_out(2) <= not('1');
when 3 =>
code_out(3) <= not('1');
when others => --redundant
end case CHECK;
end process;
end;
|
gpl-3.0
|
aa7074c49ea9f49a86b02d491d8ca18e
| 0.606357 | 3.06367 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/syndrome_calculator_n_pipe_v3_slave.vhd
| 1 | 16,890 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Syndrome_Calculator_N_Pipe_v3_Slave
-- Module Name: Syndrome_Calculator_N_Pipe_v3_Slave
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st step in Goppa Code Decoding.
--
-- This circuit computes the syndrome from the ciphertext, support elements and
-- inverted evaluation of support elements into polynomial g, aka g(L)^(-1).
-- This circuit works by computing the syndrome of only the positions where the ciphertext
-- has value 1.
--
-- This is circuit version with a variable number of computation units, pipeline and
-- a variable number of pipelines. This is the slave pipeline circuit controlled by the
-- master circuit, where it is repeated on the master circuit.
--
-- The circuits parameters
--
-- initial_address :
--
-- The initial address for this circuit to begin computing the syndrome.
-- This is necessary so different syndrome calculator, do not compute the same ciphertext.
--
-- increment_address :
--
-- How much is incremented in the initial_addres, in each step.
-- This is necessary so different syndrome calculator, do not compute the same ciphertext.
--
-- syndrome_calculator_size :
--
-- The number of units that compute each syndrome at the same time.
-- This number must be bigger than 1.
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword or in this case the ciphertext. Both the codeword
-- and ciphertext has the same size.
--
-- size_codeword :
--
-- The number of bits necessary to hold the ciphertext/codeword.
-- This is ceil(log2(length_codeword)).
--
-- length_syndrome :
--
-- The size of the syndrome array. This parameter depends of the
-- Goppa code used.
--
-- size_syndrome :
--
-- The number of bits necessary to hold the array syndrome.
-- This is ceil(log2(length_syndrome)).
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- syndrome_calculator_n_pipe_v3_slave Rev 1.0
-- controller_syndrome_calculator_2_pipe_v3_master Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_decrement_rst_nbits Rev 1.0
-- shift_register_rst_nbits Rev 1.0
-- mult_gf_2_m Rev 1.0
-- adder_gf_2_m Rev 1.0
-- and_reduce Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity syndrome_calculator_n_pipe_v3_slave is
Generic(
initial_address : integer;
increment_address : integer;
syndrome_calculator_size : integer;
gf_2_m : integer range 1 to 20;
length_codeword : integer;
size_codeword : integer;
length_syndrome : integer;
size_syndrome : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_L : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR(0 downto 0);
start_calculation : in STD_LOGIC;
last_syndrome : in STD_LOGIC;
ready_calculation : out STD_LOGIC;
finished_calculation : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_h : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_L : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0)
);
end syndrome_calculator_n_pipe_v3_slave;
architecture Behavioral of syndrome_calculator_n_pipe_v3_slave is
component controller_syndrome_calculator_2_pipe_v3_slave
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
almost_units_ready : in STD_LOGIC;
empty_units : in STD_LOGIC;
limit_ctr_codeword_q : in STD_LOGIC;
reg_codeword_q : in STD_LOGIC_VECTOR(0 downto 0);
start_calculation : in STD_LOGIC;
last_syndrome : in STD_LOGIC;
ready_calculation : out STD_LOGIC;
finished_calculation : out STD_LOGIC;
control_units_ce : out STD_LOGIC;
control_units_rst : out STD_LOGIC;
int_reg_L_ce : out STD_LOGIC;
square_h : out STD_LOGIC;
int_reg_h_ce : out STD_LOGIC;
int_reg_h_rst : out STD_LOGIC;
int_sel_reg_h : out STD_LOGIC;
reg_load_L_ce : out STD_LOGIC;
reg_load_h_ce : out STD_LOGIC;
reg_load_h_rst : out STD_LOGIC;
reg_new_value_syndrome_ce : out STD_LOGIC;
reg_new_value_syndrome_rst : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
ctr_load_address_codeword_ce : out STD_LOGIC;
ctr_load_address_codeword_rst : out STD_LOGIC;
reg_load_limit_codeword_rst : out STD_LOGIC;
reg_load_limit_codeword_ce : out STD_LOGIC;
reg_calc_limit_codeword_rst : out STD_LOGIC;
reg_calc_limit_codeword_ce : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_decrement_rst_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component shift_register_rst_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component mult_gf_2_m
Generic (gf_2_m : integer range 1 to 20 := 11);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component adder_gf_2_m
Generic(
gf_2_m : integer := 1;
number_of_elements : integer range 2 to integer'high := 2
);
Port(
a : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_elements) - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal reg_L_d : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal reg_L_ce : STD_LOGIC_VECTOR((syndrome_calculator_size - 1) downto 0);
signal reg_L_q : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal reg_h_d :STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal reg_h_ce : STD_LOGIC_VECTOR((syndrome_calculator_size - 1) downto 0);
signal reg_h_rst : STD_LOGIC_VECTOR((syndrome_calculator_size - 1) downto 0);
constant reg_h_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_h_q : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal sel_reg_h : STD_LOGIC_VECTOR((syndrome_calculator_size - 1) downto 0);
signal square_h : STD_LOGIC;
signal reg_load_L_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_load_L_ce : STD_LOGIC;
signal reg_load_L_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_load_h_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_load_h_ce : STD_LOGIC;
signal reg_load_h_rst : STD_LOGIC;
constant reg_load_h_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
signal reg_load_h_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_syndrome_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_syndrome_ce : STD_LOGIC;
signal reg_new_value_syndrome_rst : STD_LOGIC;
constant reg_new_value_syndrome_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
signal reg_new_value_syndrome_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_codeword_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_codeword_ce : STD_LOGIC;
signal reg_codeword_q : STD_LOGIC_VECTOR(0 downto 0);
signal mult_a : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal mult_b : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal mult_o : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal adder_a : STD_LOGIC_VECTOR(((syndrome_calculator_size)*gf_2_m - 1) downto 0);
signal adder_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_load_address_codeword_ce : STD_LOGIC;
signal ctr_load_address_codeword_rst : STD_LOGIC;
constant ctr_load_address_codeword_rst_value : STD_LOGIC_VECTOR((size_codeword - 1) downto 0) := std_logic_vector(to_unsigned(initial_address, size_codeword));
signal ctr_load_address_codeword_q : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal reg_load_limit_codeword_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_load_limit_codeword_ce : STD_LOGIC;
signal reg_load_limit_codeword_rst : STD_LOGIC;
constant reg_load_limit_codeword_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_load_limit_codeword_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_calc_limit_codeword_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_calc_limit_codeword_ce : STD_LOGIC;
signal reg_calc_limit_codeword_rst : STD_LOGIC;
signal reg_calc_limit_codeword_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_calc_limit_codeword_q : STD_LOGIC_VECTOR(0 downto 0);
signal control_units_ce : STD_LOGIC;
signal control_units_rst : STD_LOGIC;
constant control_units_rst_value0 : STD_LOGIC_VECTOR((syndrome_calculator_size - 1) downto 0) := (others => '0');
constant control_units_rst_value1 : STD_LOGIC_VECTOR((syndrome_calculator_size) downto (syndrome_calculator_size)) := "1";
constant control_units_rst_value : STD_LOGIC_VECTOR((syndrome_calculator_size) downto 0) := control_units_rst_value1 & control_units_rst_value0;
signal control_units_q : STD_LOGIC_VECTOR((syndrome_calculator_size) downto 0);
signal control_units_data_out : STD_LOGIC;
signal int_reg_L_ce : STD_LOGIC;
signal int_reg_h_ce : STD_LOGIC;
signal int_reg_h_rst: STD_LOGIC;
signal int_sel_reg_h : STD_LOGIC;
signal almost_units_ready : STD_LOGIC;
signal empty_units : STD_LOGIC;
signal limit_ctr_codeword_q : STD_LOGIC;
begin
controller : controller_syndrome_calculator_2_pipe_v3_slave
Port Map(
clk => clk,
rst => rst,
almost_units_ready => almost_units_ready,
empty_units => empty_units,
limit_ctr_codeword_q => reg_calc_limit_codeword_q(0),
reg_codeword_q => reg_codeword_q,
start_calculation => start_calculation,
last_syndrome => last_syndrome,
ready_calculation => ready_calculation,
finished_calculation => finished_calculation,
control_units_ce => control_units_ce,
control_units_rst => control_units_rst,
int_reg_L_ce => int_reg_L_ce,
square_h => square_h,
int_reg_h_ce => int_reg_h_ce,
int_reg_h_rst => int_reg_h_rst,
int_sel_reg_h => int_sel_reg_h,
reg_load_L_ce => reg_load_L_ce,
reg_load_h_ce => reg_load_h_ce,
reg_load_h_rst => reg_load_h_rst,
reg_new_value_syndrome_ce => reg_new_value_syndrome_ce,
reg_new_value_syndrome_rst => reg_new_value_syndrome_rst,
reg_codeword_ce => reg_codeword_ce,
ctr_load_address_codeword_ce => ctr_load_address_codeword_ce,
ctr_load_address_codeword_rst => ctr_load_address_codeword_rst,
reg_load_limit_codeword_ce => reg_load_limit_codeword_ce,
reg_load_limit_codeword_rst => reg_load_limit_codeword_rst,
reg_calc_limit_codeword_ce => reg_calc_limit_codeword_ce,
reg_calc_limit_codeword_rst => reg_calc_limit_codeword_rst
);
calculator_units : for I in 0 to (syndrome_calculator_size - 1) generate
reg_L_I : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_L_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
clk => clk,
ce => reg_L_ce(I),
q => reg_L_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
reg_h_I : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_h_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
clk => clk,
ce => reg_h_ce(I),
rst => reg_h_rst(I),
rst_value => reg_h_rst_value,
q => reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
mult_I : mult_gf_2_m
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => mult_a(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
b => mult_b(((I + 1)*gf_2_m - 1) downto I*gf_2_m),
o => mult_o(((I + 1)*gf_2_m - 1) downto I*gf_2_m)
);
reg_L_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_load_L_q;
reg_h_d(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= mult_o(((I + 1)*gf_2_m - 1) downto I*gf_2_m) when sel_reg_h(I) = '1' else
reg_load_h_q;
mult_a(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m) when square_h = '1' else
reg_L_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m);
mult_b(((I + 1)*gf_2_m - 1) downto I*gf_2_m) <= reg_h_q(((I + 1)*gf_2_m - 1) downto I*gf_2_m);
reg_L_ce(I) <= int_reg_L_ce and control_units_q(I);
reg_h_ce(I) <= int_reg_h_ce and (control_units_q(I) or int_sel_reg_h);
reg_h_rst(I) <= int_reg_h_rst and control_units_q(I);
sel_reg_h(I) <= int_sel_reg_h;
end generate;
control_units : shift_register_rst_nbits
Generic Map(
size => syndrome_calculator_size+1
)
Port Map(
data_in => control_units_data_out,
clk => clk,
ce => control_units_ce,
rst => control_units_rst,
rst_value => control_units_rst_value,
q => control_units_q,
data_out => control_units_data_out
);
reg_load_L : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_load_L_d,
clk => clk,
ce => reg_load_L_ce,
q => reg_load_L_q
);
reg_load_h : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_load_h_d,
clk => clk,
ce => reg_load_h_ce,
rst => reg_load_h_rst,
rst_value => reg_load_h_rst_value,
q => reg_load_h_q
);
reg_new_value_syndrome : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_syndrome_d,
clk => clk,
ce => reg_new_value_syndrome_ce,
rst => reg_new_value_syndrome_rst,
rst_value => reg_new_value_syndrome_rst_value,
q => reg_new_value_syndrome_q
);
reg_codeword : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_codeword_d,
clk => clk,
ce => reg_codeword_ce,
q => reg_codeword_q
);
ctr_load_address_codeword : counter_rst_nbits
Generic Map(
size => size_codeword,
increment_value => increment_address
)
Port Map(
clk => clk,
ce => ctr_load_address_codeword_ce,
rst => ctr_load_address_codeword_rst,
rst_value => ctr_load_address_codeword_rst_value,
q => ctr_load_address_codeword_q
);
reg_load_limit_codeword : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_load_limit_codeword_d,
clk => clk,
ce => reg_load_limit_codeword_ce,
rst => reg_load_limit_codeword_rst,
rst_value => reg_load_limit_codeword_rst_value,
q => reg_load_limit_codeword_q
);
reg_calc_limit_codeword : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_calc_limit_codeword_d,
clk => clk,
ce => reg_calc_limit_codeword_ce,
rst => reg_calc_limit_codeword_rst,
rst_value => reg_calc_limit_codeword_rst_value,
q => reg_calc_limit_codeword_q
);
calculator_size_1 : if (syndrome_calculator_size = 1) generate
reg_new_value_syndrome_d <= reg_h_q;
end generate;
calculator_size_more_than_1 : if (syndrome_calculator_size > 1) generate
adder : adder_gf_2_m
Generic Map(
gf_2_m => gf_2_m,
number_of_elements => syndrome_calculator_size
)
Port Map(
a => adder_a,
o => adder_o
);
adder_a <= reg_h_q;
reg_new_value_syndrome_d <= adder_o;
end generate;
reg_load_limit_codeword_d(0) <= limit_ctr_codeword_q;
reg_calc_limit_codeword_d <= reg_load_limit_codeword_q;
reg_load_L_d <= value_L;
reg_load_h_d <= value_h;
reg_codeword_d <= value_codeword;
new_value_syndrome <= reg_new_value_syndrome_q;
address_h <= ctr_load_address_codeword_q;
address_L <= ctr_load_address_codeword_q;
address_codeword <= ctr_load_address_codeword_q;
almost_units_ready <= control_units_q(syndrome_calculator_size - 1);
empty_units <= control_units_q(0);
limit_ctr_codeword_q <= '1' when (unsigned(ctr_load_address_codeword_q) >= (to_unsigned(length_codeword - increment_address, ctr_load_address_codeword_q'length))) else '0';
end Behavioral;
|
bsd-2-clause
|
a6929e437521e45ac7b80d9c93151345
| 0.667732 | 2.727273 | false | false | false | false |
pwuertz/digitizer2fw
|
src/rtl/ft2232fifo_2.vhd
| 1 | 9,686 |
-------------------------------------------------------------------------------
-- FT2232H Sync FIFO Interface
--
-- This component is designed to interface an FT2232H USB chip with two
-- dual-port FIFOs in first-word-fall-through (zero read latency) mode. The
-- FIFOs are used for buffering and (de)serializing data words and for
-- crossing the USB and FPGA clock domains.
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ft2232fifo is
port (
-- ftdi interface
usb_clk: in std_logic;
usb_oe_n: out std_logic;
usb_rd_n: out std_logic;
usb_wr_n: out std_logic;
usb_rxf_n: in std_logic;
usb_txe_n: in std_logic;
usb_d: inout std_logic_vector(7 downto 0);
-- application/fifo interface
rst: in std_logic;
fifo_in_wr_en: out std_logic;
fifo_in_full: in std_logic;
fifo_in_data: out std_logic_vector(7 downto 0);
fifo_out_rd_en: out std_logic;
fifo_out_empty: in std_logic;
fifo_out_data: in std_logic_vector(7 downto 0)
);
end ft2232fifo;
architecture ft2232fifo_arch of ft2232fifo is
-- registers for signals from or to ftdi
signal qusb_rxf_n: std_logic := '1';
signal qusb_txe_n: std_logic := '1';
signal usb_rxf, usb_txe: std_logic;
signal usb_rd_en: std_logic := '0';
signal usb_wr_en: std_logic := '0';
signal usb_rd_en_at_ftdi: std_logic := '0';
signal usb_wr_en_at_ftdi: std_logic := '0';
signal usb_d_out, usb_d_in: std_logic_vector(7 downto 0) := (others => '-');
signal int_rd_en, int_wr_en, int_oe: std_logic;
signal int_d_out: std_logic_vector(7 downto 0);
signal drive_usb_d: boolean;
signal fifo_in_wr_en_i, fifo_out_rd_en_i: std_logic;
type byte_array_t is array(integer range <>) of std_logic_vector(7 downto 0);
-- data read buffer
signal rx_data_ring: byte_array_t(3 downto 0) := (others => (others => '-'));
signal rx_index_rd: unsigned(1 downto 0) := (others => '0');
signal rx_index_wr: unsigned(1 downto 0) := (others => '0');
signal rx_count: integer range 0 to rx_data_ring'high := 0;
-- data write buffer
signal tx_data_ring: byte_array_t(3 downto 0) := (others => (others => '-'));
signal tx_index_rd: unsigned(1 downto 0) := (others => '0');
signal tx_index_wr: unsigned(1 downto 0) := (others => '0');
signal tx_count: integer range 0 to tx_data_ring'high := 0;
-- state register
type state_t is (
s_reset, s_idle,
s_switch_to_read, s_read, s_end_read,
s_write
);
signal state, next_state: state_t := s_reset;
attribute iob: string;
--attribute iob of usb_rxf_n: signal is "FORCE";
--attribute iob of usb_txe_n: signal is "FORCE";
attribute iob of usb_wr_n: signal is "FORCE";
attribute iob of usb_rd_n: signal is "FORCE";
attribute iob of usb_oe_n: signal is "FORCE";
--attribute iob of usb_d: signal is "FORCE";
--attribute iob of usb_d_out: signal is "FORCE"; -- TODO: drive_usb_d must be registered for moving usb_d to iob
--attribute iob of usb_d_in: signal is "FORCE";
begin
usb_d <= usb_d_out when drive_usb_d else (others => 'Z');
sync_input: process(usb_clk)
begin
if rising_edge(usb_clk) then
if rst = '1' then
qusb_rxf_n <= '1';
qusb_txe_n <= '1';
usb_d_in <= (others => '-');
else
qusb_rxf_n <= usb_rxf_n;
qusb_txe_n <= usb_txe_n;
usb_d_in <= usb_d;
end if;
end if;
end process;
usb_rxf <= not qusb_rxf_n;
usb_txe <= not qusb_txe_n;
sync_state: process(usb_clk)
begin
if rising_edge(usb_clk) then
if rst = '1' then
state <= s_reset;
else
state <= next_state;
end if;
end if;
end process;
sync_receive_data: process(usb_clk)
variable byte_delta: integer range -1 to 1;
begin
if rising_edge(usb_clk) then
if rst = '1' then
rx_count <= 0;
rx_index_rd <= (others => '0');
rx_index_wr <= (others => '0');
rx_data_ring <= (others => (others => '-'));
else
byte_delta := 0;
-- add byte from usb to ring if valid
if (usb_rd_en_at_ftdi = '1') and (usb_rxf = '1') then
rx_data_ring(to_integer(rx_index_wr)) <= usb_d_in;
rx_index_wr <= rx_index_wr + 1;
byte_delta := byte_delta + 1;
end if;
-- remove byte from ring if read from interface
if (fifo_in_wr_en_i = '1') and (fifo_in_full = '0') then
rx_index_rd <= rx_index_rd + 1;
byte_delta := byte_delta - 1;
end if;
rx_count <= rx_count + byte_delta;
end if;
end if;
end process;
fifo_in_data <= rx_data_ring(to_integer(rx_index_rd)) when rx_count /= 0 else (others => '-');
fifo_in_wr_en_i <= '1' when rx_count /= 0 else '0';
fifo_in_wr_en <= fifo_in_wr_en_i;
sync_transmit_data: process(usb_clk)
variable byte_delta: integer range -1 to 1;
begin
if rising_edge(usb_clk) then
if rst = '1' then
tx_count <= 0;
tx_index_rd <= (others => '0');
tx_index_wr <= (others => '0');
tx_data_ring <= (others => (others => '-'));
else
byte_delta := 0;
-- add byte from interface
if (fifo_out_rd_en_i = '1') and (fifo_out_empty = '0') then
tx_data_ring(to_integer(tx_index_wr)) <= fifo_out_data;
tx_index_wr <= tx_index_wr + 1;
byte_delta := byte_delta + 1;
end if;
-- advance data pointer at each write
if int_wr_en = '1' then
tx_index_rd <= tx_index_rd + 1;
byte_delta := byte_delta - 1;
end if;
-- recover byte from ring if write was not accepted
if (usb_wr_en_at_ftdi = '1') and (usb_txe = '0') then
tx_index_rd <= tx_index_rd - 1;
byte_delta := byte_delta + 1;
end if;
tx_count <= tx_count + byte_delta;
end if;
end if;
end process;
comb_state: process(state,
fifo_in_full, usb_rxf, rx_count,
fifo_out_empty, usb_txe, tx_count)
variable could_wr, could_rd: boolean;
begin
-- next state
next_state <= state;
-- output defaults
drive_usb_d <= false;
int_oe <= '0';
int_rd_en <= '0';
int_wr_en <= '0';
-- internal defaults
fifo_out_rd_en_i <= '0';
could_wr := (usb_txe = '1') and ((tx_count > 0) or (fifo_out_empty = '0'));
could_rd := (fifo_in_full = '0') and (usb_rxf = '1') and (rx_count <= 1);
case state is
when s_reset =>
next_state <= s_idle;
when s_idle =>
-- switch to write or read mode
if could_wr then
next_state <= s_write;
elsif could_rd then
next_state <= s_switch_to_read;
end if;
when s_switch_to_read =>
-- disable our outputs and enable usb outputs
int_oe <= '1';
next_state <= s_read;
when s_read =>
-- read data from usb
int_oe <= '1';
int_rd_en <= '1';
-- end reading if there is nothing to read or interface won't accpet more data
if not could_rd then
int_rd_en <= '0';
next_state <= s_end_read;
end if;
when s_end_read =>
-- wait until last read command passed
if could_wr then
next_state <= s_write;
else
next_state <= s_idle;
end if;
when s_write =>
drive_usb_d <= true;
if could_wr then
-- write valid data to usb
if tx_count > 0 then
int_wr_en <= '1';
end if;
-- fetch data from interface if there is enough space for failed writes
if tx_count <= 1 then
fifo_out_rd_en_i <= '1';
end if;
else
-- end writing if there is nothing to write or usb won't accept more data
if could_rd then
next_state <= s_switch_to_read;
else
next_state <= s_idle;
end if;
end if;
when others =>
null;
end case;
end process;
int_d_out <= tx_data_ring(to_integer(tx_index_rd));
fifo_out_rd_en <= fifo_out_rd_en_i;
sync_output_internal: process(usb_clk)
begin
if rising_edge(usb_clk) then
if rst = '1' then
usb_rd_en <= '0';
usb_wr_en <= '0';
usb_rd_en_at_ftdi <= '0';
usb_wr_en_at_ftdi <= '0';
else
usb_rd_en <= int_rd_en;
usb_wr_en <= int_wr_en;
usb_rd_en_at_ftdi <= usb_rd_en;
usb_wr_en_at_ftdi <= usb_wr_en;
end if;
end if;
end process;
sync_output: process(usb_clk)
begin
if rising_edge(usb_clk) then
if rst = '1' then
usb_d_out <= (others => '-');
usb_oe_n <= '1';
usb_rd_n <= '1';
usb_wr_n <= '1';
else
usb_d_out <= int_d_out;
usb_oe_n <= not int_oe;
usb_rd_n <= not int_rd_en;
usb_wr_n <= not int_wr_en;
end if;
end if;
end process;
end ft2232fifo_arch;
|
gpl-3.0
|
5efdfe09ab94584356fa22eec61bfef9
| 0.508672 | 3.398596 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/backup/controller_syndrome_calculator_2.vhd
| 1 | 13,432 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Syndrome_Calculator_2
-- Module Name: Controller_Syndrome_Calculator_2
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st step in Goppa Code Decoding.
--
-- This circuit is the state machine that controls the syndrome_calculator_n
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_syndrome_calculator_2 is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
almost_units_ready : in STD_LOGIC;
empty_units : in STD_LOGIC;
limit_ctr_codeword_q : in STD_LOGIC;
limit_ctr_syndrome_q : in STD_LOGIC;
reg_first_syndrome_q : in STD_LOGIC_VECTOR(0 downto 0);
reg_codeword_q : in STD_LOGIC_VECTOR(0 downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
control_units_ce : out STD_LOGIC;
control_units_rst : out STD_LOGIC;
int_reg_L_ce : out STD_LOGIC;
int_square_h : out STD_LOGIC;
int_reg_h_ce : out STD_LOGIC;
int_reg_h_rst : out STD_LOGIC;
int_sel_reg_h : out STD_LOGIC;
reg_syndrome_ce : out STD_LOGIC;
reg_syndrome_rst : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_first_syndrome_ce : out STD_LOGIC;
reg_first_syndrome_rst : out STD_LOGIC;
ctr_syndrome_ce : out STD_LOGIC;
ctr_syndrome_rst : out STD_LOGIC;
ctr_codeword_ce : out STD_LOGIC;
ctr_codeword_rst : out STD_LOGIC
);
end controller_syndrome_calculator_2;
architecture Behavioral of controller_syndrome_calculator_2 is
type State is (reset, load_counters, prepare_values, load_values, jump_codeword, clear_remaining_units, prepare_synd, load_synd, store_synd, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, limit_ctr_codeword_q, limit_ctr_syndrome_q, reg_first_syndrome_q, reg_codeword_q, almost_units_ready, empty_units)
begin
case (actual_state) is
when reset =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '1';
when load_counters =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '1';
when prepare_values =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
when load_values =>
if(reg_first_syndrome_q(0) = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '1';
int_square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '1';
reg_codeword_ce <= '1';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '1';
int_square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_syndrome_ce <= '1';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '1';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
end if;
when jump_codeword =>
if(reg_codeword_q(0) = '1') then
if(almost_units_ready = '1' or limit_ctr_codeword_q = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '1';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '1';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '1';
ctr_codeword_rst <= '0';
end if;
elsif(limit_ctr_codeword_q = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '1';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '1';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '1';
ctr_codeword_rst <= '0';
end if;
when clear_remaining_units =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '1';
int_sel_reg_h <= '0';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
when prepare_synd =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
when load_synd =>
if(reg_first_syndrome_q(0) = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_syndrome_ce <= '1';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
end if;
when store_synd =>
if(limit_ctr_syndrome_q = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '1';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '1';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '1';
ctr_codeword_rst <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '1';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '1';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
end if;
when final =>
syndrome_finalized <= '1';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '1';
when others =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
int_square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '1';
end case;
end process;
NewState: process (actual_state, limit_ctr_codeword_q, limit_ctr_syndrome_q, reg_first_syndrome_q, reg_codeword_q, almost_units_ready, empty_units)
begin
case (actual_state) is
when reset =>
next_state <= load_counters;
when load_counters =>
next_state <= prepare_values;
when prepare_values =>
next_state <= load_values;
when load_values =>
next_state <= jump_codeword;
when jump_codeword =>
if(reg_codeword_q(0) = '1') then
if(almost_units_ready = '1') then
next_state <= load_synd;
elsif(limit_ctr_codeword_q = '1') then
next_state <= clear_remaining_units;
else
next_state <= prepare_values;
end if;
elsif(limit_ctr_codeword_q = '1') then
if(empty_units = '1') then
next_state <= final;
else
next_state <= clear_remaining_units;
end if;
else
next_state <= prepare_values;
end if;
when clear_remaining_units =>
if(almost_units_ready = '1') then
next_state <= prepare_synd;
else
next_state <= clear_remaining_units;
end if;
when prepare_synd =>
next_state <= load_synd;
when load_synd =>
next_state <= store_synd;
when store_synd =>
if(limit_ctr_syndrome_q = '1') then
if(limit_ctr_codeword_q = '1') then
next_state <= final;
else
next_state <= prepare_values;
end if;
else
next_state <= prepare_synd;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
4054df8e70d47581d9088f6caa33a05c
| 0.554497 | 2.637863 | false | false | false | false |
laurivosandi/hdl
|
primitives/src/mux.vhd
| 1 | 539 |
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port (
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
s : in std_logic_vector(1 downto 0);
m : out std_logic);
end mux;
architecture behavioral of mux is
begin
process(a,b,c,d,s) begin
case s is
when "00" => m <= a;
when "01" => m <= b;
when "10" => m <= c;
when others => m <= d;
end case;
end process;
end behavioral;
|
mit
|
5d56aae9be48cfdae0c224740d095240
| 0.480519 | 3.227545 | false | false | false | false |
rodrigoazs/-7-5-Reed-Solomon
|
code/error_generator.vhd
| 1 | 2,922 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity ErrorGenerator is
Port ( Clock : in std_logic;
Qout: out std_logic_vector(2 downto 0));
end ErrorGenerator;
architecture Behavioral of ErrorGenerator is
component flipflop is
Port ( D: in std_logic_vector(2 downto 0);
Clock: in std_logic;
Reset: in std_logic;
Q: out std_logic_vector(2 downto 0));
end component;
signal SymbolRandom: std_logic_vector(2 downto 0);
signal ErrorStop: std_logic;
signal Result: std_logic_vector(2 downto 0);
signal Dsa0 : std_logic_vector(2 downto 0);
signal Dsa1 : std_logic_vector(2 downto 0);
signal Dsa2 : std_logic_vector(2 downto 0);
signal Dsa3 : std_logic_vector(2 downto 0);
signal Dsa4 : std_logic_vector(2 downto 0);
signal Dsa5 : std_logic_vector(2 downto 0);
signal Dsa6 : std_logic_vector(2 downto 0);
signal Qsa0 : std_logic_vector(2 downto 0);
signal Qsa1 : std_logic_vector(2 downto 0);
signal Qsa2 : std_logic_vector(2 downto 0);
signal Qsa3 : std_logic_vector(2 downto 0);
signal Qsa4 : std_logic_vector(2 downto 0);
signal Qsa5 : std_logic_vector(2 downto 0);
signal Qsa6 : std_logic_vector(2 downto 0);
signal counter_rnd: std_logic_vector(2 downto 0) := "000";
begin
ffsymbola0 : flipflop Port map (Dsa0,Clock,'0',Qsa0);
ffsymbola1 : flipflop Port map (Dsa1,Clock,'0',Qsa1);
ffsymbola2 : flipflop Port map (Dsa2,Clock,'0',Qsa2);
ffsymbola3 : flipflop Port map (Dsa3,Clock,'0',Qsa3);
ffsymbola4 : flipflop Port map (Dsa4,Clock,'0',Qsa4);
ffsymbola5 : flipflop Port map (Dsa5,Clock,'0',Qsa5);
ffsymbola6 : flipflop Port map (Dsa6,Clock,'0',Qsa6);
Result(0) <= Qsa2(1) xor Qsa4(1) xor Qsa3(1) xor Qsa2(2) xor Qsa0(0) xor Qsa2(0) xor Qsa1(2) xor Qsa5(0);
Result(1) <= Qsa4(0) xor Qsa1(0) xor Qsa5(0) xor Qsa2(0) xor Qsa2(2) xor Qsa1(2) xor Qsa0(2);
Result(2) <= Qsa2(2) xor Qsa0(2) xor Qsa2(2) xor Qsa4(1) xor Qsa1(1) xor Qsa5(1);
SymbolRandom(0) <= Qsa3(0) xor Qsa5(2) xor Qsa1(1) xor Qsa6(1) xor Qsa3(2) xor Qsa1(2) xor Qsa5(2);
SymbolRandom(1) <= Qsa5(1) xor Qsa1(1) xor Qsa2(1) xor Qsa4(0) xor Qsa0(2) xor Qsa6(0);
SymbolRandom(2) <= Qsa1(2) xor Qsa0(2) xor Qsa0(0) xor Qsa3(2) xor Qsa3(1);
Dsa0 <= Qsa1;
Dsa1 <= Qsa2;
Dsa2 <= Qsa3;
Dsa3 <= Qsa4;
Dsa4 <= Qsa5;
Dsa5 <= Qsa6;
Dsa6 <= Result;
process(Clock, Result)
begin
if (Clock'event and Clock='1') then
counter_rnd <= counter_rnd + 1;
if ((Result(0) xor Result(2)
xor Result(1))='1' and ErrorStop/='1')
then
Qout(0) <= SymbolRandom(0);
Qout(1) <= SymbolRandom(1);
Qout(2) <= SymbolRandom(2);
ErrorStop <= '1';
else
Qout <= "000";
end if;
if(counter_rnd = "111") then
counter_rnd <= "001";
ErrorStop <= '0';
end if;
end if;
end process;
end Behavioral;
|
mit
|
0a0ce69f5a32a286864beef145b7f0f1
| 0.685147 | 2.639566 | false | false | false | false |
pwuertz/digitizer2fw
|
src/rtl/rising_edge_detect.vhd
| 1 | 1,293 |
-------------------------------------------------------------------------------
-- Detect rising edges in digital input samples
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sampling_pkg.all;
entity rising_edge_detect is
port (
clk: in std_logic;
samples_d: in din_samples_t(0 to 3);
edges_d: out din_samples_t(0 to 3)
);
end rising_edge_detect;
architecture rising_edge_detect_arch of rising_edge_detect is
signal samples_d_buffered: din_samples_t(0 to 4) := (others => (others => '0'));
begin
buffer_signal: process(clk)
begin
if rising_edge(clk) then
samples_d_buffered(0) <= samples_d_buffered(4);
samples_d_buffered(1 to 4) <= samples_d;
end if;
end process;
find_rising_edges: process(clk)
begin
if rising_edge(clk) then
for I in 0 to 3 loop
for CH in samples_d_buffered(I)'low to samples_d_buffered(I)'high loop
if samples_d_buffered(I)(CH) = '0' and samples_d_buffered(I+1)(CH) = '1' then
edges_d(I)(CH) <= '1';
else
edges_d(I)(CH) <= '0';
end if;
end loop;
end loop;
end if;
end process;
end rising_edge_detect_arch;
|
gpl-3.0
|
e6375ada754ac3a9f0db8c8142620f17
| 0.540603 | 3.485175 | false | false | false | false |
pmassolino/hw-goppa-mceliece
|
mceliece/mceliece_qd_goppa_decrypt_v4_with_mem.vhd
| 1 | 32,233 |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: McEliece_QD-Goppa_Decrypt_With_mem_v4
-- Module Name: McEliece_QD-Goppa_Decrypt_With_mem_v4
-- Project Name: McEliece Goppa Decryption
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit implements a McEliece decryption algorithm for binary Goppa codes with
-- all necessary memories.
-- This circuit only supplies the necessary memories for mceliece_qd_goppa_decrypt_v4.
-- Because of how mceliece_qd_goppa_decrypt_v4 circuit handles the memories, it
-- is possible to implement efficiently for values of
-- number_of_polynomial_evaluator_syndrome_pipelines which are not power of 2.
--
-- The circuits parameters
--
-- number_of_polynomial_evaluator_syndrome_pipelines :
--
-- The number of pipelines in polynomial_syndrome_computing_n_v2 circuit.
-- This number can be 1 or greater, but only power of 2.
--
-- log2_number_of_polynomial_evaluator_syndrome_pipelines :
--
-- This is the log2 of the number_of_polynomial_evaluator_syndrome_pipelines.
-- This is ceil(log2(number_of_polynomial_evaluator_syndrome_pipelines))
--
-- polynomial_evaluator_syndrome_pipeline_size :
--
-- This is the number of stages on polynomial_syndrome_computing_n_v2 circuit.
-- This number can be 2 or greater.
--
-- polynomial_evaluator_syndrome_size_pipeline_size :
--
-- The number of bits necessary to hold the number of stages on the pipeline.
-- This is ceil(log2(polynomial_evaluator_syndrome_pipeline_size))
--
-- gf_2_m :
--
-- The size of the finite field extension used in this circuit.
-- This values depends of the Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword in this Goppa code.
-- This values depends of the Goppa code used.
--
-- size_codeword :
--
-- The number of bits necessary to store an array of codeword lengths.
-- This is ceil(log2(length_codeword))
--
-- number_of_errors :
--
-- The number of errors the Goppa code is able to decode.
-- This values depends of the Goppa code used.
--
-- size_number_of_errors :
--
-- The number of bits necessary to store an array of number of errors + 1 length.
-- This is ceil(log2(number_of_errors+1))
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- mceliece_qd_goppa_decrypt_v4_with_mem Rev 1.0
-- register_nbits Rev 1.0
-- synth_ram Rev 1.0
-- synth_double_ram Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mceliece_qd_goppa_decrypt_v4_with_mem is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
number_of_polynomial_evaluator_syndrome_pipelines : integer := 16;
log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 4;
polynomial_evaluator_syndrome_pipeline_size : integer := 3;
polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
gf_2_m : integer range 1 to 20 := 11;
length_codeword : integer := 2048;
size_codeword : integer := 11;
number_of_errors : integer := 27;
size_number_of_errors : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 50;
-- size_number_of_errors : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3307;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 66;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 32;
-- size_number_of_errors : integer := 6
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 16;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 4;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 3;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- number_of_errors : integer := 128;
-- size_number_of_errors : integer := 8
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
load_address_mem : in STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
load_sel_mem : in STD_LOGIC_VECTOR(1 downto 0);
load_write_value_mem : in STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
load_write_enable_mem : in STD_LOGIC;
load_read_value_mem : out STD_LOGIC_VECTOR((2*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
syndrome_generation_finalized : out STD_LOGIC;
key_equation_finalized : out STD_LOGIC;
decryption_finalized : out STD_LOGIC
);
end mceliece_qd_goppa_decrypt_v4_with_mem;
architecture Behavioral of mceliece_qd_goppa_decrypt_v4_with_mem is
component register_nbits
Generic (
size : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component synth_ram
Generic (
ram_address_size : integer;
ram_word_size : integer
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component synth_double_ram
Generic (
ram_address_size : integer;
ram_word_size : integer
);
Port (
data_in_a : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component mceliece_qd_goppa_decrypt_v4
Generic(
number_of_polynomial_evaluator_syndrome_pipelines : integer;
polynomial_evaluator_syndrome_pipeline_size : integer;
polynomial_evaluator_syndrome_size_pipeline_size : integer;
gf_2_m : integer range 1 to 20;
length_codeword : integer;
size_codeword : integer;
number_of_errors : integer;
size_number_of_errors : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_L : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
value_s : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_v : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma_evaluated : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
syndrome_generation_finalized : out STD_LOGIC;
key_equation_finalized : out STD_LOGIC;
decryption_finalized : out STD_LOGIC;
address_value_h : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_L : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_codeword : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_s : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_v : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_s : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_v : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_sigma : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_error : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_s : out STD_LOGIC;
write_enable_new_value_v : out STD_LOGIC;
write_enable_new_value_sigma : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_new_value_error : out STD_LOGIC;
write_enable_new_value_sigma_evaluated : out STD_LOGIC;
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_s : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_v : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_error : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0)
);
end component;
signal value_h : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal value_L : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_codeword : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal value_s : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_v : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_sigma : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_sigma_evaluated : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal address_value_h : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_value_L : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_value_syndrome : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_codeword : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_value_s : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_v : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_sigma : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_sigma_evaluated : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_s : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_v : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_sigma : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_message : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal new_value_error : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal new_value_sigma_evaluated : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal write_enable_new_value_syndrome : STD_LOGIC;
signal write_enable_new_value_s : STD_LOGIC;
signal write_enable_new_value_v : STD_LOGIC;
signal write_enable_new_value_sigma : STD_LOGIC;
signal write_enable_new_value_message : STD_LOGIC;
signal write_enable_new_value_error : STD_LOGIC;
signal write_enable_new_value_sigma_evaluated : STD_LOGIC;
signal address_new_value_syndrome : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_s : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_v : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_sigma : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_message : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_new_value_error : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_new_value_sigma_evaluated : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal mem_L_data_in : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_L_rw : STD_LOGIC;
signal mem_L_address : STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_L_data_out : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_h_data_in : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_h_rw : STD_LOGIC;
signal mem_h_address : STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_h_data_out : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_codeword_data_in : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_codeword_rw : STD_LOGIC;
signal mem_codeword_address : STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_codeword_data_out : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_sigma_evaluated_data_in_a : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_sigma_evaluated_data_in_b : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_sigma_evaluated_rw_a : STD_LOGIC;
signal mem_sigma_evaluated_rw_b : STD_LOGIC;
signal mem_sigma_evaluated_address_a : STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_sigma_evaluated_address_b : STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_sigma_evaluated_data_out_a : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_sigma_evaluated_data_out_b : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_message_data_in : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_message_rw : STD_LOGIC;
signal mem_message_address : STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_message_data_out : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_error_data_in : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_error_rw : STD_LOGIC;
signal mem_error_address : STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_error_data_out : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal mem_syndrome_data_in_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_syndrome_data_in_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_syndrome_rw_a : STD_LOGIC;
signal mem_syndrome_rw_b : STD_LOGIC;
signal mem_syndrome_address_a : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal mem_syndrome_address_b : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal mem_syndrome_data_out_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_syndrome_data_out_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_F_data_in_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_F_data_in_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_F_rw_a : STD_LOGIC;
signal mem_F_rw_b : STD_LOGIC;
signal mem_F_address_a : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal mem_F_address_b : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal mem_F_data_out_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_F_data_out_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_B_data_in_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_B_data_in_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_B_rw_a : STD_LOGIC;
signal mem_B_rw_b : STD_LOGIC;
signal mem_B_address_a : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal mem_B_address_b : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal mem_B_data_out_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_B_data_out_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_sigma_data_in_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_sigma_data_in_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_sigma_rw_a : STD_LOGIC;
signal mem_sigma_rw_b : STD_LOGIC;
signal mem_sigma_address_a : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal mem_sigma_address_b : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal mem_sigma_data_out_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mem_sigma_data_out_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_rst_q : STD_LOGIC;
signal reg_load_address_mem_q : STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal reg_load_sel_mem_q : STD_LOGIC_VECTOR(1 downto 0);
signal reg_load_write_value_mem_q : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal reg_load_write_enable_mem_q : STD_LOGIC;
signal reg_load_read_value_mem_d : STD_LOGIC_VECTOR((2*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal reg_syndrome_generation_finalized_d : STD_LOGIC;
signal reg_key_equation_finalized_d : STD_LOGIC;
signal reg_decryption_finalized_d : STD_LOGIC;
begin
reg_rst : register_nbits
Generic Map(
size => 1
)
Port Map(
d(0) => rst,
clk => clk,
ce => '1',
q(0) => reg_rst_q
);
reg_load_address_mem : register_nbits
Generic Map(
size => size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
d => load_address_mem,
clk => clk,
ce => '1',
q => reg_load_address_mem_q
);
reg_load_sel_mem : register_nbits
Generic Map(
size => 2
)
Port Map(
d => load_sel_mem,
clk => clk,
ce => '1',
q => reg_load_sel_mem_q
);
reg_load_write_value_mem : register_nbits
Generic Map(
size => gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
d => load_write_value_mem,
clk => clk,
ce => '1',
q => reg_load_write_value_mem_q
);
reg_load_write_enable_mem : register_nbits
Generic Map(
size => 1
)
Port Map(
d(0) => load_write_enable_mem,
clk => clk,
ce => '1',
q(0) => reg_load_write_enable_mem_q
);
reg_load_read_value_mem : register_nbits
Generic Map(
size => 2*number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
d => reg_load_read_value_mem_d,
clk => clk,
ce => '1',
q => load_read_value_mem
);
reg_syndrome_generation_finalized : register_nbits
Generic Map(
size => 1
)
Port Map(
d(0) => reg_syndrome_generation_finalized_d,
clk => clk,
ce => '1',
q(0) => syndrome_generation_finalized
);
reg_key_equation_finalized : register_nbits
Generic Map(
size => 1
)
Port Map(
d(0) => reg_key_equation_finalized_d,
clk => clk,
ce => '1',
q(0) => key_equation_finalized
);
reg_decryption_finalized : register_nbits
Generic Map(
size => 1
)
Port Map(
d(0) => reg_decryption_finalized_d,
clk => clk,
ce => '1',
q(0) => decryption_finalized
);
mceliece : mceliece_qd_goppa_decrypt_v4
Generic Map(
number_of_polynomial_evaluator_syndrome_pipelines => number_of_polynomial_evaluator_syndrome_pipelines,
polynomial_evaluator_syndrome_pipeline_size => polynomial_evaluator_syndrome_pipeline_size,
polynomial_evaluator_syndrome_size_pipeline_size => polynomial_evaluator_syndrome_size_pipeline_size,
gf_2_m => gf_2_m,
length_codeword => length_codeword,
size_codeword => size_codeword,
number_of_errors => number_of_errors,
size_number_of_errors => size_number_of_errors
)
Port Map(
clk => clk,
rst => reg_rst_q,
value_h => value_h,
value_L => value_L,
value_syndrome => value_syndrome,
value_codeword => value_codeword,
value_s => value_s,
value_v => value_v,
value_sigma => value_sigma,
value_sigma_evaluated => value_sigma_evaluated,
syndrome_generation_finalized => reg_syndrome_generation_finalized_d,
key_equation_finalized => reg_key_equation_finalized_d,
decryption_finalized => reg_decryption_finalized_d,
address_value_h => address_value_h,
address_value_L => address_value_L,
address_value_syndrome => address_value_syndrome,
address_value_codeword => address_value_codeword,
address_value_s => address_value_s,
address_value_v => address_value_v,
address_value_sigma => address_value_sigma,
address_value_sigma_evaluated => address_value_sigma_evaluated,
new_value_syndrome => new_value_syndrome,
new_value_s => new_value_s,
new_value_v => new_value_v,
new_value_sigma => new_value_sigma,
new_value_message => new_value_message,
new_value_error => new_value_error,
new_value_sigma_evaluated => new_value_sigma_evaluated,
write_enable_new_value_syndrome => write_enable_new_value_syndrome,
write_enable_new_value_s => write_enable_new_value_s,
write_enable_new_value_v => write_enable_new_value_v,
write_enable_new_value_sigma => write_enable_new_value_sigma,
write_enable_new_value_message => write_enable_new_value_message,
write_enable_new_value_error => write_enable_new_value_error,
write_enable_new_value_sigma_evaluated => write_enable_new_value_sigma_evaluated,
address_new_value_syndrome => address_new_value_syndrome,
address_new_value_s => address_new_value_s,
address_new_value_v => address_new_value_v,
address_new_value_sigma => address_new_value_sigma,
address_new_value_message => address_new_value_message,
address_new_value_error => address_new_value_error,
address_new_value_sigma_evaluated => address_new_value_sigma_evaluated
);
mem_L : synth_ram
Generic Map(
ram_address_size => size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines,
ram_word_size => gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
data_in => mem_L_data_in,
rw => mem_L_rw,
clk => clk,
address => mem_L_address,
data_out => mem_L_data_out
);
mem_h : synth_ram
Generic Map(
ram_address_size => size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines,
ram_word_size => gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
data_in => mem_h_data_in,
rw => mem_h_rw,
clk => clk,
address => mem_h_address,
data_out => mem_h_data_out
);
mem_codeword : synth_ram
Generic Map(
ram_address_size => size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines,
ram_word_size => number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
data_in => mem_codeword_data_in,
rw => mem_codeword_rw,
clk => clk,
address => mem_codeword_address,
data_out => mem_codeword_data_out
);
mem_sigma_evaluated : synth_double_ram
Generic Map(
ram_address_size => size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines,
ram_word_size => gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
data_in_a => mem_sigma_evaluated_data_in_a,
data_in_b => mem_sigma_evaluated_data_in_b,
rw_a => mem_sigma_evaluated_rw_a,
rw_b => mem_sigma_evaluated_rw_b,
clk => clk,
address_a => mem_sigma_evaluated_address_a,
address_b => mem_sigma_evaluated_address_b,
data_out_a => mem_sigma_evaluated_data_out_a,
data_out_b => mem_sigma_evaluated_data_out_b
);
mem_message : synth_ram
Generic Map(
ram_address_size => size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines,
ram_word_size => number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
data_in => mem_message_data_in,
rw => mem_message_rw,
clk => clk,
address => mem_message_address,
data_out => mem_message_data_out
);
mem_error : synth_ram
Generic Map(
ram_address_size => size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines,
ram_word_size => number_of_polynomial_evaluator_syndrome_pipelines
)
Port Map(
data_in => mem_error_data_in,
rw => mem_error_rw,
clk => clk,
address => mem_error_address,
data_out => mem_error_data_out
);
mem_syndrome : synth_double_ram
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m
)
Port Map(
data_in_a => mem_syndrome_data_in_a,
data_in_b => mem_syndrome_data_in_b,
rw_a => mem_syndrome_rw_a,
rw_b => mem_syndrome_rw_b,
clk => clk,
address_a => mem_syndrome_address_a,
address_b => mem_syndrome_address_b,
data_out_a => mem_syndrome_data_out_a,
data_out_b => mem_syndrome_data_out_b
);
mem_F : synth_double_ram
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m
)
Port Map(
data_in_a => mem_F_data_in_a,
data_in_b => mem_F_data_in_b,
rw_a => mem_F_rw_a,
rw_b => mem_F_rw_b,
clk => clk,
address_a => mem_F_address_a,
address_b => mem_F_address_b,
data_out_a => mem_F_data_out_a,
data_out_b => mem_F_data_out_b
);
mem_B : synth_double_ram
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m
)
Port Map(
data_in_a => mem_B_data_in_a,
data_in_b => mem_B_data_in_b,
rw_a => mem_B_rw_a,
rw_b => mem_B_rw_b,
clk => clk,
address_a => mem_B_address_a,
address_b => mem_B_address_b,
data_out_a => mem_B_data_out_a,
data_out_b => mem_B_data_out_b
);
mem_sigma : synth_double_ram
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m
)
Port Map(
data_in_a => mem_sigma_data_in_a,
data_in_b => mem_sigma_data_in_b,
rw_a => mem_sigma_rw_a,
rw_b => mem_sigma_rw_b,
clk => clk,
address_a => mem_sigma_address_a,
address_b => mem_sigma_address_b,
data_out_a => mem_sigma_data_out_a,
data_out_b => mem_sigma_data_out_b
);
value_h <= mem_h_data_out;
value_L <= mem_L_data_out;
value_codeword <= mem_codeword_data_out;
value_syndrome <= mem_syndrome_data_out_a;
value_s <= mem_F_data_out_a;
value_v <= mem_B_data_out_a;
value_sigma <= mem_sigma_data_out_a;
value_sigma_evaluated <= mem_sigma_evaluated_data_out_a;
mem_L_data_in <= reg_load_write_value_mem_q;
mem_L_rw <= reg_load_write_enable_mem_q when(reg_rst_q = '1' and reg_load_sel_mem_q = "00") else
'0';
mem_L_address <= reg_load_address_mem_q when(reg_rst_q = '1' and reg_load_sel_mem_q = "00") else
address_value_L((size_codeword - 1) downto log2_number_of_polynomial_evaluator_syndrome_pipelines);
mem_h_data_in <= reg_load_write_value_mem_q;
mem_h_rw <= reg_load_write_enable_mem_q when(reg_rst_q = '1' and reg_load_sel_mem_q = "01") else
'0';
mem_h_address <= reg_load_address_mem_q when(reg_rst_q = '1' and reg_load_sel_mem_q = "01") else
address_value_h((size_codeword - 1) downto log2_number_of_polynomial_evaluator_syndrome_pipelines);
mem_codeword_data_in <= reg_load_write_value_mem_q((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
mem_codeword_rw <= reg_load_write_enable_mem_q when(reg_rst_q = '1' and reg_load_sel_mem_q = "10") else
'0';
mem_codeword_address <= reg_load_address_mem_q when(reg_rst_q = '1' and reg_load_sel_mem_q = "10") else
address_value_codeword((size_codeword - 1) downto log2_number_of_polynomial_evaluator_syndrome_pipelines);
mem_sigma_evaluated_data_in_a <= (others => '0');
mem_sigma_evaluated_data_in_b <= new_value_sigma_evaluated;
mem_sigma_evaluated_rw_a <= '0';
mem_sigma_evaluated_rw_b <= write_enable_new_value_sigma_evaluated;
mem_sigma_evaluated_address_a <= address_value_sigma_evaluated((size_codeword - 1) downto log2_number_of_polynomial_evaluator_syndrome_pipelines);
mem_sigma_evaluated_address_b <= address_new_value_sigma_evaluated((size_codeword - 1) downto log2_number_of_polynomial_evaluator_syndrome_pipelines);
mem_message_data_in <= new_value_message;
mem_message_rw <= '0' when reg_rst_q = '1' else
write_enable_new_value_message;
mem_message_address <= reg_load_address_mem_q when reg_rst_q = '1' else
address_new_value_message((size_codeword - 1) downto log2_number_of_polynomial_evaluator_syndrome_pipelines);
mem_error_data_in <= new_value_error;
mem_error_rw <= '0' when reg_rst_q = '1' else
write_enable_new_value_error;
mem_error_address <= reg_load_address_mem_q when reg_rst_q = '1' else
address_new_value_error((size_codeword - 1) downto log2_number_of_polynomial_evaluator_syndrome_pipelines);
mem_syndrome_data_in_a <= (others => '0');
mem_syndrome_data_in_b <= new_value_syndrome;
mem_syndrome_rw_a <= '0';
mem_syndrome_rw_b <= write_enable_new_value_syndrome;
mem_syndrome_address_a <= address_value_syndrome;
mem_syndrome_address_b <= address_new_value_syndrome;
mem_F_data_in_a <= (others => '0');
mem_F_data_in_b <= new_value_s;
mem_F_rw_a <= '0';
mem_F_rw_b <= write_enable_new_value_s;
mem_F_address_a <= address_value_s;
mem_F_address_b <= address_new_value_s;
mem_B_data_in_a <= (others => '0');
mem_B_data_in_b <= new_value_v;
mem_B_rw_a <= '0';
mem_B_rw_b <= write_enable_new_value_v;
mem_B_address_a <= address_value_v;
mem_B_address_b <= address_new_value_v;
mem_sigma_data_in_a <= (others => '0');
mem_sigma_data_in_b <= new_value_sigma;
mem_sigma_rw_a <= '0';
mem_sigma_rw_b <= write_enable_new_value_sigma;
mem_sigma_address_a <= address_value_sigma;
mem_sigma_address_b <= address_new_value_sigma;
reg_load_read_value_mem_d <= mem_error_data_out & mem_message_data_out;
end Behavioral;
|
bsd-2-clause
|
515e56953d06d08852e7ee0d99f38b83
| 0.696615 | 2.87256 | false | false | false | false |
hitomi2500/wasca
|
fpga_firmware/wasca_toplevel.vhd
| 1 | 11,699 |
-- wasca.vhd
-- Generated using ACDS version 14.1 186 at 2015.05.28.08:37:08
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_toplevel is
port (
clk_clk : in std_logic := '0'; -- clk.clk
sdram_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
sdram_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_cas_n : out std_logic; -- .cas_n
sdram_cke : out std_logic; -- .cke
sdram_cs_n : out std_logic; -- .cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_dqm : out std_logic_vector(1 downto 0); -- .dqm
sdram_ras_n : out std_logic; -- .ras_n
sdram_we_n : out std_logic; -- .we_n
sdram_clk : out std_logic; -- .clk
reset_reset_n : in std_logic := '0'; -- reset.reset_n
abus_address : in std_logic_vector(24 downto 1) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address
abus_data : inout std_logic_vector(15 downto 0) := (others => '0'); -- .data
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_interrupt_disable_out : out std_logic := '1'; --
abus_direction : out std_logic := '0'; -- .direction
heartbeat : out std_logic := '0' ;
spi_stm32_MISO : in std_logic; -- MISO
spi_stm32_MOSI : out std_logic := '0'; -- MOSI
spi_stm32_SCLK : out std_logic := '0'; -- SCLK
spi_stm32_sync_miso : in std_logic; -- SPI synchronization
spi_stm32_sync_mosi : out std_logic := '0'; -- SS_n
uart_0_external_connection_txd : out std_logic := '0'
);
end entity wasca_toplevel;
architecture rtl of wasca_toplevel is
component wasca is
port (
abus_avalon_sdram_bridge_0_abus_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
abus_avalon_sdram_bridge_0_abus_read : in std_logic := 'X'; -- read
abus_avalon_sdram_bridge_0_abus_data : inout std_logic_vector(15 downto 0) := (others => 'X'); -- data
abus_avalon_sdram_bridge_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
abus_avalon_sdram_bridge_0_abus_direction : out std_logic; -- direction
abus_avalon_sdram_bridge_0_abus_interrupt_disable_out : out std_logic; -- interrupt_disable_out
abus_avalon_sdram_bridge_0_abus_interrupt : out std_logic; -- interrupt
abus_avalon_sdram_bridge_0_abus_writebyteenable_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- writebyteenable_n
abus_avalon_sdram_bridge_0_abus_reset : in std_logic := 'X'; -- reset
abus_avalon_sdram_bridge_0_sdram_addr : out std_logic_vector(12 downto 0); -- addr
abus_avalon_sdram_bridge_0_sdram_ba : out std_logic_vector(1 downto 0); -- ba
abus_avalon_sdram_bridge_0_sdram_cas_n : out std_logic; -- cas_n
abus_avalon_sdram_bridge_0_sdram_cke : out std_logic; -- cke
abus_avalon_sdram_bridge_0_sdram_cs_n : out std_logic; -- cs_n
abus_avalon_sdram_bridge_0_sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
abus_avalon_sdram_bridge_0_sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
abus_avalon_sdram_bridge_0_sdram_ras_n : out std_logic; -- ras_n
abus_avalon_sdram_bridge_0_sdram_we_n : out std_logic; -- we_n
abus_avalon_sdram_bridge_0_sdram_clk : out std_logic; -- clk
buffered_spi_sync_miso : in std_logic; -- SPI synchronization
buffered_spi_sync_mosi : out std_logic; -- cs
buffered_spi_mosi : out std_logic; -- mosi
buffered_spi_clk : out std_logic; -- clk
buffered_spi_miso : in std_logic := 'X'; -- miso
buffered_spi_cs : out std_logic; -- cs
clk_clk : in std_logic := 'X'; -- clk
clock_116_mhz_clk : out std_logic; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
reset_controller_0_reset_in1_reset : in std_logic := 'X'; -- reset
heartbeat_heartbeat_out : out std_logic; -- txd
uart_0_external_connection_rxd : in std_logic := 'Z'; -- rxd
uart_0_external_connection_txd : out std_logic -- txd
);
end component wasca;
--signal sega_saturn_abus_slave_0_abus_address_demuxed : std_logic_vector(25 downto 0) := (others => '0');
--signal sega_saturn_abus_slave_0_abus_data_demuxed : std_logic_vector(15 downto 0) := (others => '0');
signal clock_116_mhz : std_logic := '0';
signal por_counter : unsigned(31 downto 0) := (others => '0');
signal por_reset : std_logic := '0';
signal por_reset_n : std_logic := '0';
signal abus_address_with_a0 : std_logic_vector(24 downto 0) := (others => '0');
begin
sdram_clk <= not clock_116_mhz;
abus_address_with_a0 <= abus_address&"0";
my_little_wasca : component wasca
port map (
clk_clk => clk_clk,
clock_116_mhz_clk => clock_116_mhz,
abus_avalon_sdram_bridge_0_sdram_addr => sdram_addr,
abus_avalon_sdram_bridge_0_sdram_ba => sdram_ba,
abus_avalon_sdram_bridge_0_sdram_cas_n => sdram_cas_n,
abus_avalon_sdram_bridge_0_sdram_cke => sdram_cke,
abus_avalon_sdram_bridge_0_sdram_cs_n => sdram_cs_n,
abus_avalon_sdram_bridge_0_sdram_dq => sdram_dq,
abus_avalon_sdram_bridge_0_sdram_dqm => sdram_dqm,
abus_avalon_sdram_bridge_0_sdram_ras_n => sdram_ras_n,
abus_avalon_sdram_bridge_0_sdram_we_n => sdram_we_n,
abus_avalon_sdram_bridge_0_abus_address => abus_address_with_a0,
abus_avalon_sdram_bridge_0_abus_chipselect => "1"&abus_chipselect(1 downto 0),--work only with CS1 and CS0 for now
abus_avalon_sdram_bridge_0_abus_read => abus_read,
abus_avalon_sdram_bridge_0_abus_writebyteenable_n => abus_write,
abus_avalon_sdram_bridge_0_abus_interrupt => abus_interrupt,
abus_avalon_sdram_bridge_0_abus_data => abus_data,
abus_avalon_sdram_bridge_0_abus_direction => abus_direction,
abus_avalon_sdram_bridge_0_abus_interrupt_disable_out => open,--abus_interrupt_disable_out,
abus_avalon_sdram_bridge_0_abus_reset => reset_reset_n,
heartbeat_heartbeat_out => heartbeat,
buffered_spi_sync_miso => spi_stm32_sync_miso,
buffered_spi_sync_mosi => spi_stm32_sync_mosi,
buffered_spi_miso => spi_stm32_MISO,
buffered_spi_mosi => spi_stm32_MOSI,
buffered_spi_clk => spi_stm32_SCLK,
buffered_spi_cs => open,
reset_reset_n => por_reset_n,
reset_controller_0_reset_in1_reset => por_reset,
uart_0_external_connection_rxd => '0',
uart_0_external_connection_txd => uart_0_external_connection_txd
);
--empty subsystem
-- external_sdram_controller_wire_addr <= (others => 'Z');
-- external_sdram_controller_wire_ba <= (others => 'Z');
-- external_sdram_controller_wire_cas_n <= (others => 'Z');
-- external_sdram_controller_wire_cke <= (others => 'Z');
-- external_sdram_controller_wire_cs_n <= (others => 'Z');
-- external_sdram_controller_wire_dq <= (others => 'Z');
-- external_sdram_controller_wire_dqm <= (others => 'Z');
-- external_sdram_controller_wire_ras_n <= (others => 'Z');
-- external_sdram_controller_wire_we_n <= (others => 'Z');
-- external_sdram_controller_wire_clk <= (others => 'Z');
-- sega_saturn_abus_slave_0_abus_data <= (others => 'Z');
-- sega_saturn_abus_slave_0_abus_interrupt <= (others => 'Z');
-- sega_saturn_abus_slave_0_abus_disableout <= '1';
-- sega_saturn_abus_slave_0_abus_direction <= '0';
-- spi_sd_card_MOSI <= 'Z';
-- spi_sd_card_SCLK <= 'Z';
-- spi_sd_card_SS_n <= 'Z';
-- uart_0_external_connection_txd <= 'Z';
-- spi_stm32_MISO <= 'Z';
-- audio_out_DACDAT <= 'Z';
--sega_saturn_abus_slave_0_abus_direction <= '0';
abus_interrupt_disable_out <= '1';
--por
process (clock_116_mhz)
begin
if std_logic(por_counter(24)) = '0' then
por_counter <= por_counter + 1;
end if;
end process;
por_reset <= (std_logic(por_counter(22)));
por_reset_n <= not (std_logic(por_counter(22)));
end architecture rtl; -- of wasca_toplevel
|
gpl-2.0
|
fa524436533bc7f67e87244939a84326
| 0.438841 | 3.936406 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Gaston/TP1-Contador/bcd_multiplexer.vhd
| 1 | 1,034 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd_multiplexer is
port(
bcd0_input : in std_logic_vector(3 downto 0);
bcd1_input : in std_logic_vector(3 downto 0);
bcd2_input : in std_logic_vector(3 downto 0);
bcd3_input : in std_logic_vector(3 downto 0);
mux_selector : in std_logic_vector (1 downto 0);
mux_output : out std_logic_vector (3 downto 0)
);
end bcd_multiplexer;
architecture bcd_multiplexer_arq of bcd_multiplexer is
begin
process (mux_selector,bcd0_input,bcd1_input,bcd2_input,bcd3_input) is
begin
case mux_selector is
when "00" => mux_output <= bcd0_input;
when "01" => mux_output <= bcd1_input;
when "10" => mux_output <= bcd2_input;
when "11" => mux_output <= bcd3_input;
when others => mux_output <= (others => '0');
end case;
end process;
end bcd_multiplexer_arq;
|
gpl-3.0
|
12b56245d9baef4dfd14dfa73c2cf029
| 0.566731 | 3.435216 | false | false | false | false |
pwuertz/digitizer2fw
|
sim/sampling_tb.vhd
| 1 | 2,592 |
-------------------------------------------------------------------------------
-- Sampling module test bench
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
entity sampling_tb is
end sampling_tb;
architecture sampling_tb_arch of sampling_tb is
component sampling
port (
-- data in from pins
DIN_P: in std_logic_vector(1 downto 0);
DIN_N: in std_logic_vector(1 downto 0);
ADC_DA_P: in std_logic_vector(12 downto 0);
ADC_DA_N: in std_logic_vector(12 downto 0);
ADC_DACLK_P: in std_logic;
ADC_DACLK_N: in std_logic;
-- data in to device
app_clk: out std_logic;
samples_d: out std_logic_vector(7 downto 0);
samples_a: out std_logic_vector(25 downto 0);
-- control
rst: in std_logic
);
end component;
signal clk_samples: std_logic := '0';
signal samples_d: std_logic_vector(7 downto 0 ) := (others => '0');
signal samples_a: std_logic_vector(25 downto 0 ) := (others => '0');
signal sampling_rst: std_logic := '0';
signal DIN_P: std_logic_vector(1 downto 0) := (others => '1');
signal DIN_N: std_logic_vector(1 downto 0) := (others => '0');
signal ADC_DA_P: std_logic_vector(12 downto 0) := (others => '0');
signal ADC_DA_N: std_logic_vector(12 downto 0) := (others => '1');
signal ADC_DACLK_P: std_logic := '0';
signal ADC_DACLK_N: std_logic := '0';
constant daclk_period : time := 4 ns;
signal app_clk: std_logic;
begin
sampling_inst: sampling
port map (
DIN_P => DIN_P,
DIN_N => DIN_N,
ADC_DA_P => ADC_DA_P,
ADC_DA_N => ADC_DA_N,
ADC_DACLK_P => ADC_DACLK_P,
ADC_DACLK_N => ADC_DACLK_N,
app_clk => app_clk,
samples_d => samples_d,
samples_a => samples_a,
rst => sampling_rst
);
clk_process: process
begin
ADC_DACLK_P <= '0';
ADC_DACLK_N <= '1';
wait for daclk_period/2;
ADC_DACLK_P <= '1';
ADC_DACLK_N <= '0';
wait for daclk_period/2;
end process;
stimulus: process
begin
sampling_rst <= '1';
for I in 0 to 20 loop
wait until rising_edge(app_clk);
end loop;
sampling_rst <= '0';
wait for 32 ns;
DIN_P(0) <= '0';
DIN_N(0) <= '1';
wait;
end process;
end sampling_tb_arch;
|
gpl-3.0
|
aea37c63c28040140d1017f298e9d977
| 0.568892 | 3.218634 | false | false | false | false |
Xero-Hige/LuGus-VHDL
|
TP4/preprocessor/preprocessor_tb.vhd
| 1 | 3,826 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity preprocessor_tb is
end entity;
architecture preprocessor_tb_arq of preprocessor_tb is
signal x_in : std_logic_vector(31 downto 0) := (others => '0');
signal y_in : std_logic_vector(31 downto 0) := (others => '0');
signal angle_in : std_logic_vector(31 downto 0) := (others => '0');
signal x_out : std_logic_vector(31 downto 0) := (others => '0');
signal y_out : std_logic_vector(31 downto 0) := (others => '0');
signal angle_out : std_logic_vector(31 downto 0) := (others => '0');
component preprocessor is
generic(TOTAL_BITS: integer := 32);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
angle_in : in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
angle_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
begin
preprocessor_0 : preprocessor
generic map(TOTAL_BITS => 32)
port map(
x_in => x_in,
y_in => y_in,
angle_in => angle_in,
x_out => x_out,
y_out => y_out,
angle_out => angle_out
);
process
type pattern_type is record
xi : std_logic_vector(31 downto 0);
yi : std_logic_vector(31 downto 0);
ai : std_logic_vector(31 downto 0);
xo : std_logic_vector(31 downto 0);
yo : std_logic_vector(31 downto 0);
ao : std_logic_vector(31 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000"),
("00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000000"),
("00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000001000101",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000001000101"),
("00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000001100000",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000110"),
("00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000001100000",
"11111111111111111111111111111111",
"00000000000000000000000000000000",
"00000000000000000000000000000110"),
("00000000000000000000000000000001",
"00000000000000000000000000000000",
"11111111111111111111111110100000",
"00000000000000000000000000000000",
"11111111111111111111111111111111",
"11111111111111111111111111111010")
);
begin
for i in patterns'range loop
-- Set the inputs.
x_in <= patterns(i).xi;
y_in <= patterns(i).yi;
angle_in <= patterns(i).ai;
wait for 1 ns;
assert patterns(i).xo = x_out report "BAD X, GOT: " & integer'image(to_integer(signed(x_out)));
assert patterns(i).yo = y_out report "BAD Y, GOT: " & integer'image(to_integer(signed(y_out)));
assert patterns(i).ao = angle_out report "BAD ANGLE, GOT: " & integer'image(to_integer(signed(angle_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
14b660bcbcef2ce6621c086e15b511b2
| 0.6908 | 3.928131 | false | false | false | false |
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